diff --git a/Makefile b/Makefile index 61bc634..ffc9a20 100644 --- a/Makefile +++ b/Makefile @@ -9,4 +9,4 @@ clean: fmt: @cd os && cargo fmt @cd os/src/algorithm && cargo fmt - @cd user && cargo fmt \ No newline at end of file + @cd user && cargo fmt diff --git a/README.md b/README.md index 59ef56e..1213461 100644 --- a/README.md +++ b/README.md @@ -1,53 +1,3 @@ -# rCore-Tutorial V3（开发中） +这是实验三题目**页面置换**需要用到的代码框架，基于全部六部分完成后的操作系统。 -[![Actions Status](https://github.com/rcore-os/rCore-Tutorial/workflows/CI/badge.svg?branch=master)](https://github.com/rcore-os/rCore-Tutorial/actions) - -本教学仓库是继 [rCore_tutorial V2](https://rcore-os.github.io/rCore_tutorial_doc/) 后重构的 V3 版本。 - -本文档的目标主要针对「做实验的同学」，我们会对每章结束后提供完成的代码，你的练习题只需要基于我们给出的版本上增量实现即可，不需要重新按照教程写一遍。 - -而对想完整实现一个 rCore 的同学来说，我们的文档可能不太友好。因为在开发过程中，我们需要对清晰和全面做很多的权衡和考虑、需要省略掉大量语法层面而 OS 无关的代码来带来更多的可读性和精简性，所以想参考本文档并完整实现同学可能不会有从头复制到尾的流畅（这样的做法也不是学习的初衷），可能需要自己有一些完整的认识和思考。 - -另外，如果你觉得字体大小和样式不舒服，可以通过 GitBook 上方的按钮调节。 - -## 仓库目录 - -- `docs/`：教学实验指导分实验内容和开发规范 -- `notes/`：开题报告和若干讨论 -- `os/`：操作系统代码 -- `user/`：用户态代码 -- `SUMMARY.md`：GitBook 目录页 -- `book.json`：GitBook 配置文件 -- `rust-toolchain`：限定 Rust 工具链版本 -- `deploy.sh`：自动部署脚本 - - -## 实验指导 - -基于 GitBook，目前已经部署到了 [GitHub Pages](https://rcore-os.github.io/rCore-Tutorial-deploy/) 上面。 - -### 文档本地使用方法 - - -```bash -npm install -g gitbook-cli -gitbook install -gitbook serve -``` - -## 代码 - -### 操作系统代码 -本项目基于 cargo 和 make 等工具，在根目录通过 `make run` 命令即可运行代码，更具体的细节请参见 `Makefile`、`os/Makefile` 以及 `user/Makefile`。 - -### 参考和感谢 - -本文档和代码部分参考了： -- [rCore](https://github.com/rcore-os/rCore) -- [zCore](https://github.com/rcore-os/zCore) -- [rCore_tutorial V2](https://rcore-os.github.io/rCore_tutorial_doc/) -- [使用Rust编写操作系统](https://github.com/rustcc/writing-an-os-in-rust) - -在此对仓库的开发和维护者表示感谢，同时也感谢很多在本项目开发中一起讨论和勘误的老师和同学们。 - - +你只需要在 `os/src/memory/mapping/swapper.rs` 中实现替代的页面置换算法，并（可选）在 `os/src/main.rs` 中修改测试线程。 diff --git a/SUMMARY.md b/SUMMARY.md deleted file mode 100644 index f29a77a..0000000 --- a/SUMMARY.md +++ /dev/null @@ -1,84 +0,0 @@ -# rCore 教学实验文档 - -* [实验简介](README.md) - -## 实验之前 - - -* [环境部署](docs/pre-lab/env.md) -* [GDB 调试方法*](docs/pre-lab/gdb.md) - -## 实验指导 -* 实验指导零 - * [摘要](docs/lab-0/guide/intro.md) - * [创建项目](docs/lab-0/guide/part-1.md) - * [移除标准库依赖](docs/lab-0/guide/part-2.md) - * [移除运行时环境依赖](docs/lab-0/guide/part-3.md) - * [编译为裸机目标](docs/lab-0/guide/part-4.md) - * [生成内核镜像](docs/lab-0/guide/part-5.md) - * [调整内存布局](docs/lab-0/guide/part-6.md) - * [重写程序入口点](docs/lab-0/guide/part-7.md) - * [使用 QEMU 运行](docs/lab-0/guide/part-8.md) - * [接口封装和代码整理](docs/lab-0/guide/part-9.md) - * [小结](docs/lab-0/guide/summary.md) -* 实验指导一 - * [摘要](docs/lab-1/guide/intro.md) - * [什么是中断](docs/lab-1/guide/part-1.md) - * [RISC-V 中的中断](docs/lab-1/guide/part-2.md) - * [程序运行状态](docs/lab-1/guide/part-3.md) - * [状态的保存与恢复](docs/lab-1/guide/part-4.md) - * [进入中断处理流程](docs/lab-1/guide/part-5.md) - * [时钟中断](docs/lab-1/guide/part-6.md) - * [小结](docs/lab-1/guide/summary.md) -* 实验指导二 - * [摘要](docs/lab-2/guide/intro.md) - * [动态内存分配](docs/lab-2/guide/part-1.md) - * [物理内存探测](docs/lab-2/guide/part-2.md) - * [物理内存管理](docs/lab-2/guide/part-3.md) - * [小结](docs/lab-2/guide/summary.md) -* 实验指导三 - * [摘要](docs/lab-3/guide/intro.md) - * [从虚拟地址到物理地址](docs/lab-3/guide/part-1.md) - * [修改内核](docs/lab-3/guide/part-2.md) - * [实现页表](docs/lab-3/guide/part-3.md) - * [实现内核重映射](docs/lab-3/guide/part-4.md) - * [页面置换*](docs/lab-3/guide/part-5.md) - * [小结](docs/lab-3/guide/summary.md) -* 实验指导四 - * [摘要](docs/lab-4/guide/intro.md) - * [线程和进程](docs/lab-4/guide/part-1.md) - * [线程的创建](docs/lab-4/guide/part-2.md) - * [线程的切换](docs/lab-4/guide/part-3.md) - * [线程的结束](docs/lab-4/guide/part-4.md) - * [内核栈](docs/lab-4/guide/part-5.md) - * [线程调度](docs/lab-4/guide/part-6.md) - * [小结](docs/lab-4/guide/summary.md) -* 实验指导五 - * [摘要](docs/lab-5/guide/intro.md) - * [设备树](docs/lab-5/guide/part-1.md) - * [virtio](docs/lab-5/guide/part-2.md) - * [驱动和块设备驱动](docs/lab-5/guide/part-3.md) - * [文件系统](docs/lab-5/guide/part-4.md) - * [小结](docs/lab-5/guide/summary.md) -* 实验指导六 - * [摘要](docs/lab-6/guide/intro.md) - * [构建用户程序框架](docs/lab-6/guide/part-1.md) - * [打包为磁盘镜像](docs/lab-6/guide/part-2.md) - * [解析 ELF 文件并创建线程](docs/lab-6/guide/part-3.md) - * [实现系统调用](docs/lab-6/guide/part-4.md) - * [处理文件描述符](docs/lab-6/guide/part-5.md) - * [条件变量](docs/lab-6/guide/part-6.md) - * [小结](docs/lab-6/guide/summary.md) - -## 实验题 -* [实验一：中断](docs/lab-1/practice.md) -* [实验二：内存分配](docs/lab-2/practice.md) -* [实验三：虚实地址转换](docs/lab-3/practice.md) -* [实验四（上）：线程](docs/lab-4/practice-1.md) -* [实验四（下）：线程调度](docs/lab-4/practice-2.md) -* [实验六：系统调用](docs/lab-6/practice.md) - -## 开发笔记 -* [文档代码划分](docs/format/partition.md) -* [文档格式规范](docs/format/doc.md) -* [代码格式规范](docs/format/code.md) \ No newline at end of file diff --git a/book.json b/book.json deleted file mode 100644 index f086e18..0000000 --- a/book.json +++ /dev/null @@ -1,26 +0,0 @@ -{ - "plugins": [ - "hide-element", - "chapter-fold", - "katex", - "alerts", - "emphasize", - "mermaid-gb3", - "codeblock-label", - "code", - "search-pro", - "click-reveal", - "expandable-chapters-interactive", - "localized-footer" - ], - "pluginsConfig": { - "fontsettings": { - "theme": "white", - "family": "sans", - "size": 1 - }, - "localized-footer": { - "filename": "gitalk.html" - } - } -} \ No newline at end of file diff --git a/bootloader/rustsbi-k210.bin b/bootloader/rustsbi-k210.bin new file mode 100755 index 0000000..f6c8028 Binary files /dev/null and b/bootloader/rustsbi-k210.bin differ diff --git a/bootloader/rustsbi-qemu.bin b/bootloader/rustsbi-qemu.bin new file mode 100755 index 0000000..4aa16e2 Binary files /dev/null and b/bootloader/rustsbi-qemu.bin differ diff --git a/deploy.sh b/deploy.sh deleted file mode 100755 index 446853b..0000000 --- a/deploy.sh +++ /dev/null @@ -1,17 +0,0 @@ -#!/bin/sh -# 下面的 DEPLOY_DIR 目录需要关联到 https://github.com/rcore-os/rCore-Tutorial-deploy 远程仓库 -# 随后可以通过 https://rcore-os.github.io/rCore-Tutorial-deploy 来访问 -DEPLOY_DIR=../rCore-Tutorial-deploy/ - -# Build and copy -gitbook build -cp -r _book/* $DEPLOY_DIR -cd $DEPLOY_DIR || exit - -CURRENT_TIME=$(date +"%Y-%m-%d %H:%m:%S") -# Commit and push -git add * -git commit -m "[Auto-deploy] Build $CURRENT_TIME" -git push origin master - -cd - || exit \ No newline at end of file diff --git a/docs/format/code.md b/docs/format/code.md deleted file mode 100644 index 197b3a7..0000000 --- a/docs/format/code.md +++ /dev/null @@ -1,30 +0,0 @@ -## 代码规范 - -### 代码风格 -- 以 cargo 输出没有 warning 为准 -- 可以通过根目录的 `make fmt` 来自动调用 `cargo fmt` 规范全部的代码 - -### 注释规范 -- 用 `//!` 注释外层内容，例如在文件开始注释整个模块 -- 用 `///` 为函数添加 doc 注释，其内部使用 Markdown 语法 -- 可以使用 markdown 格式的链接，链接内容使用 Rust 可以直接链上，例如 - ```rust - /// 样例注释 - /// [`link`]: crate::xxx::xxx - fn some_func() {} - ``` - -- 对于地址 literal，使用小写，使用 `_` 每隔四位进行标记，例如 `0x8000_0000` `0xffff_ffff_c000_0000` - -- 实现一个 trait 时，doc 是可选的，而如果有，应当写在 impl 上面，而不是具体的方法上面 - ```rust - /// doc here (optional) - impl Default for Type { - /// not here - fn default() -> Self { ... } - } - ``` - -### 参考 -- https://doc.rust-lang.org/1.26.2/book/first-edition/comments.html -- https://doc.rust-lang.org/1.26.2/book/second-edition/ch14-02-publishing-to-crates-io.html \ No newline at end of file diff --git a/docs/format/doc.md b/docs/format/doc.md deleted file mode 100644 index bc9f306..0000000 --- a/docs/format/doc.md +++ /dev/null @@ -1,100 +0,0 @@ -## 文档规范 - -### 一些标准的架构、软件名词写法 -- 语言相关 - - Rust - - C - - C++ - - Markdown -- 教程 - - rCore-Tutorial -- 操作系统相关 - - uCore - - rCore - - Linux - - macOS - - Windows - - Ubuntu -- 操作系统技术相关 - - 物理页（而不是物理页帧） - - 虚拟页（而不是物理页帧） -- 架构相关 - - x86_64 - - RISC-V 64 -- 其他一些名词 - - ABI - - GitHub - - virtio -- Rust 相关 - - rustup - - cargo - - rustc -- 其他软件 - - QEMU - - Homebrew - -### 内容控制 -- 我们的目标针对于「做实验的同学」，对想完整实现一个 rCore 的同学来说可能不太友好； -- 但是我们也相信，这部分想完整实现的同学也不会因为我们在文档中少些了一部分非常细节的诸如模块调用的内容就放弃，而且从头复制到尾也不是一个好的做法，这不会让你对操作系统有更深刻的理解； -- 所以，在文档开发过程中，我们需要对清晰和全面做很多的权衡和考虑，需要省略掉大量语法层面而 OS 无关的代码来带来更多的可读性和精简性； -- 所以，在文档中引用的代码，只需要写主体的函数，不需要把一系列调用、头部注释全部加入进去。在最后，可能会再利用代码折叠的方式对这个问题进一步权衡。 - -### 书写格式 -- 在数字、英文、独立的标点或记号两侧的中文之间要加空格，如： - - 安装 QEMU - - 分为 2 个部分 -- 命令、宏名、寄存器、类型名、函数名、变量名、行间输出、编译选项、路径和文件名需要使用 \`\` 记号 - - 寄存器 `a0` 这样的也需要使用 \`\` 记号，而不是 $$a_0$$，这是为了和 `sepc` 统一 -- 行内命令或运行输出引用使用 \`\` 记号，并在两侧加入空格，如： - - `cargo run` - - 出现 `ERROR: pkg-config binary 'pkg-config' not found` 时 -- 行间命令使用 \`\`\` 记号并加入语言记号： - - 命令使用 bash 记号 - - Rust 语言使用 rust 记号 - - cargo 的配置使用 toml 记号 - - 如何命令只是命令，则不需要 $ 记号（方便同学复制），如： - ```bash - echo "Hello, world." - ``` - - 如果在展示一个命令带来的输出效果，需要加入 $ 记号表示一个命令的开始，如： - ```bash - $ echo "Hello, world." - Hello, world. - ``` -- 粗体使用 \*\* **粗体** \*\* 记号 - - 一些重要的概念最好进行加粗 -- 斜体使用 \* *斜体* \* 记号，而不要混合使用 \_ _Italic_ \_ 记号 -- 在正式的段落中要加入标点符号，在 - 记号开始的列表中的单独名词表项不加入标点符号（但是如果是段落需要加），如： - - 操作系统有（名词罗列）： - - macOS - - Windows - - 我们需要（连贯段落）： - - 先打开 QEMU； - - 再关闭 QEMU。 -- 在 / 记号两侧添加空格，如： - - Linux / Windows WSL -- 中文名词的英文解释多用大写，如： - - 裸机（Bare Metal） - - `sepc` （Supervisor Exception Program Counter） -- 只要是主体是中文的段落，括号统一使用中文括号（），如果主体是英文则使用英文括号 () - - 值得注意的是中文括号两侧本来就会又留白，这里不会在括号两侧加入空格 - - 英文空格两侧最好加上空格 -- 在文档中引用成段的代码时，需要填写上文件的路径，如： - - {% label %}os/src/sbi.rs{% endlabel %} - ```rust - /// 向控制台输出一个字符 - /// - /// 需要注意我们不能直接使用 Rust 中的 char 类型 - pub fn console_putchar(c: usize) { - sbi_call(SBI_CONSOLE_PUTCHAR, c, 0, 0); - } - ``` -- 在使用伪代码时，不使用 `$` `%` 等符号描述寄存器，使用 `:=` 表示赋值，例如 `pc := sepc` -- 代码过长或会让文档显得很长时，需要进行折叠 -- 强调请使用「强调」，而不是『强调』 - -### 小节格式 - -- 章节的标题为使用 `#` 一级标题，后面的子标题依次加级别 -- 小节的标题统一使用 `##` 二级标题，后面的子标题依次加级别 \ No newline at end of file diff --git a/docs/format/partition.md b/docs/format/partition.md deleted file mode 100644 index 2455fd1..0000000 --- a/docs/format/partition.md +++ /dev/null @@ -1,8 +0,0 @@ -## 文档代码划分 - -### 文档和代码功能划分和注意事项 - -- 文档专注于 OS 的原理和同时涉及 OS 和 Rust 特性的 Rust 语言特性，不会花篇幅来讲解 Rust 语言本身； -- 文档中引用的代码和代码目录中代码保持一致； -- 代码中书写的注释专注于功能性，不会有流程性和原理性的介绍； -- 文档应有全面的包括流程性、原理性和功能性的介绍。 \ No newline at end of file diff --git a/docs/lab-0/guide/intro.md b/docs/lab-0/guide/intro.md deleted file mode 100644 index b06f798..0000000 --- a/docs/lab-0/guide/intro.md +++ /dev/null @@ -1,11 +0,0 @@ -# 实验指导零 - -## 实验概要 - -这一章的实验指导中，你将会学到： - -- 使用 Rust 包管理器 cargo 创建一个 Rust 项目 -- 移除 Rust 程序对操作系统的依赖，构建一个独立化可执行的程序 -- 我们将程序的目标平台设置为 RISC-V，这样我们的代码将可以在 RISC-V 指令集的裸机（Bare Metal）上执行 Rust 代码 -- 生成内核镜像、调整代码的内存布局并在 QEMU 模拟器中启动 -- 封装如输出、关机等一些 SBI 的接口，方便后续开发 \ No newline at end of file diff --git a/docs/lab-0/guide/part-1.md b/docs/lab-0/guide/part-1.md deleted file mode 100644 index ef205aa..0000000 --- a/docs/lab-0/guide/part-1.md +++ /dev/null @@ -1,45 +0,0 @@ -## 创建 Rust 项目 - -### 创建项目 -我们首先创建一个整个项目的目录，并在工作目录中首先创建一个名为 `rust-toolchain` 的文件，并在其中写入所需要的工具链版本： - -{% label %}rust-toolchain{% endlabel %} -``` -nightly-2020-06-27 -``` - -之后在目录内部使用 `cargo new` 命令在我们的项目目录内创建一个新的 Rust 项目 os，命令如下： - -{% label %}运行命令{% endlabel %} -```bash -cargo new os -``` - -这里我们把项目命名为 os。同时，cargo 默认为我们添加了 `--bin` 选项，说明我们将要创建一个可执行文件而非一个库。 - -### 目录结构 - -创建完成后，整个项目的目录结构如下： - -{% label %}目录结构{% endlabel %} -```bash -Project 项目目录 -├── rust-toolchain Rust 工具链版本 -└── os - ├── Cargo.toml 项目配置文件 - └── src 源代码路径 - └── main.rs 源程序 -``` - -### 构建和运行 - -接下来我们进入 os 文件夹，并尝试构建、运行项目： - -{% label %}运行输出{% endlabel %} -```bash -$ cargo run - ... -Hello, world! -``` - -打开 `os/src/main.rs` 发现里面确实只是输出了一行 `Hello, world!`。这个应用可以正常运行，但是即使只是这么一个简单的功能，也离不开所在操作系统的帮助。我们既然要写一个新的操作系统，就不能依赖于任何已有操作系统，接下来我们尝试移除该项目对于操作系统的依赖。 \ No newline at end of file diff --git a/docs/lab-0/guide/part-2.md b/docs/lab-0/guide/part-2.md deleted file mode 100644 index a074192..0000000 --- a/docs/lab-0/guide/part-2.md +++ /dev/null @@ -1,98 +0,0 @@ -## 移除标准库依赖 - -### 禁用标准库 -项目默认是链接 Rust 标准库 std 的，它依赖于操作系统，因此我们需要显式通过 `#![no_std]` 将其禁用： - -{% label %}os/src/main.rs{% endlabel %} -```rust -//! # 全局属性 -//! - `#![no_std]` -//! 禁用标准库 -#![no_std] - -fn main() { - println!("Hello, rCore-Tutorial!"); -} -``` - -我们使用 `cargo build` 构建项目，会出现下面的错误： - -{% label %}运行输出{% endlabel %} -```rust -error: cannot find macro `println` in this scope - --> src/main.rs:3:5 - | -7 | println!("Hello, rCore-Tutorial!"); - | ^^^^^^^ -error: `#[panic_handler]` function required, but not found -error: language item required, but not found: `eh_personality` -``` - -接下来，我们依次解决这些问题。 - -### 宏 println! - -第一个错误是说 `println!` 宏未找到，实际上这个宏属于 Rust 标准库 std，它会依赖操作系统标准输出等一系列功能。由于它被我们禁用了当然就找不到了。我们暂时将该输出语句删除，之后给出不依赖操作系统的实现。 - -### panic 处理函数 - -第二个错误是说需要一个函数作为 `panic_handler` ，这个函数负责在程序发生 panic 时调用。它默认使用标准库 std 中实现的函数并依赖于操作系统特殊的文件描述符，由于我们禁用了标准库，因此只能自己实现它： - -{% label %}os/src/main.rs{% endlabel %} -```rust -use core::panic::PanicInfo; - -/// 当 panic 发生时会调用该函数 -/// 我们暂时将它的实现为一个死循环 -#[panic_handler] -fn panic(_info: &PanicInfo) -> ! { - loop {} -} -``` - -> **[info] Rust Panic** -> -> Panic 在 Rust 中表明程序遇到了错误，需要被迫停止运行或者通过捕获的机制来处理。 - -类型为 `PanicInfo` 的参数包含了 panic 发生的文件名、代码行数和可选的错误信息。这个函数从不返回，所以他被标记为发散函数（Diverging Function）。发散函数的返回类型称作 Never 类型（"never" type），记为 `!`。对这个函数，我们目前能做的很少，所以我们只需编写一个死循环 `loop {}`。 - -这里我们用到了核心库 core，与标准库 std 不同，这个库不需要操作系统的支持，下面我们还会与它打交道。 - -### eh_personality 语义项 - -第三个错误提到了语义项（Language Item） ，它是编译器内部所需的特殊函数或类型。刚才的 `panic_handler` 也是一个语义项，我们要用它告诉编译器当程序发生 panic 之后如何处理。 - -而这个错误相关语义项 `eh_personality` ，其中 eh 是 Exception Handling 的缩写，它是一个标记某函数用来实现**堆栈展开**处理功能的语义项。这个语义项也与 panic 有关。 - -> **[info] 堆栈展开 (Stack Unwinding) ** -> -> 通常当程序出现了异常时，从异常点开始会沿着 caller 调用栈一层一层回溯，直到找到某个函数能够捕获这个异常或终止程序。这个过程称为堆栈展开。 -> -> 当程序出现异常时，我们需要沿着调用栈一层层回溯上去回收每个 caller 中定义的局部变量（这里的回收包括 C++ 的 RAII 的析构以及 Rust 的 drop 等）避免造成捕获异常并恢复后的内存溢出。 -> -> 而在 Rust 中，panic 证明程序出现了错误，我们则会对于每个 caller 函数调用依次这个被标记为堆栈展开处理函数的函数进行清理。 -> -> 这个处理函数是一个依赖于操作系统的复杂过程，在标准库中实现。但是我们禁用了标准库使得编译器找不到该过程的实现函数了。 - -简单起见，我们这里不会进一步捕获异常也不需要清理现场，我们设置为直接退出程序即可。这样堆栈展开处理函数不会被调用，编译器也就不会去寻找它的实现了。 - -因此，我们在项目配置文件中直接将 dev 配置和 release 配置的 panic 的处理策略设为直接终止，也就是直接调用我们的 `panic_handler` 而不是先进行堆栈展开等处理再调用。 - -{% label %}os/Cargo.toml{% endlabel %} -```toml -... - -# panic 时直接终止，因为我们没有实现堆栈展开的功能 -[profile.dev] -panic = "abort" - -[profile.release] -panic = "abort" -``` - -此时，我们 `cargo build` ，但是又出现了新的错误，我们将在后面的部分解决： - -{% label %}运行输出{% endlabel %} -```bash -error: requires `start` lang_item -``` \ No newline at end of file diff --git a/docs/lab-0/guide/part-3.md b/docs/lab-0/guide/part-3.md deleted file mode 100644 index c24e96d..0000000 --- a/docs/lab-0/guide/part-3.md +++ /dev/null @@ -1,54 +0,0 @@ -## 移除运行时环境依赖 - -### 运行时系统 -对于大多数语言，他们都使用了**运行时系统**（Runtime System），这可能导致 `main` 函数并不是实际执行的第一个函数。 - -以 Rust 语言为例，一个典型的链接了标准库的 Rust 程序会首先跳转到 C 语言运行时环境中的 `crt0`（C Runtime Zero）进入 C 语言运行时环境设置 C 程序运行所需要的环境（如创建堆栈或设置寄存器参数等）。 - -然后 C 语言运行时环境会跳转到 Rust 运行时环境的入口点（Entry Point）进入 Rust 运行时入口函数继续设置 Rust 运行环境，而这个 Rust 的运行时入口点就是被 `start` 语义项标记的。Rust 运行时环境的入口点结束之后才会调用 `main` 函数进入主程序。 - -C 语言运行时环境和 Rust 运行时环境都需要标准库支持，我们的程序无法访问。如果覆盖了 `start` 语义项，仍然需要 `crt0`，并不能解决问题。所以需要重写覆盖整个 `crt0` 入口点： - -{% label %}os/src/main.rs{% endlabel %} -```rust -//! # 全局属性 -//! - `#![no_std]` -//! 禁用标准库 -#![no_std] -//! -//! - `#![no_main]` -//! 不使用 `main` 函数等全部 Rust-level 入口点来作为程序入口 -#![no_main] - -use core::panic::PanicInfo; - -/// 当 panic 发生时会调用该函数 -/// 我们暂时将它的实现为一个死循环 -#[panic_handler] -fn panic(_info: &PanicInfo) -> ! { - loop {} -} - -/// 覆盖 crt0 中的 _start 函数 -/// 我们暂时将它的实现为一个死循环 -#[no_mangle] -pub extern "C" fn _start() -> ! { - loop {} -} -``` - -我们加上 `#![no_main]` 告诉编译器我们不用常规的入口点。 - -同时我们实现一个 `_start` 函数来代替 `crt0`，并加上 `#[no_mangle]` 告诉编译器对于此函数禁用编译期间的名称重整（Name Mangling），即确保编译器生成一个名为 `_start` 的函数，而非为了实现函数重载等而生成的形如 `_ZN3blog_os4_start7hb173fedf945531caE` 散列化后的函数名。由于 `_start` 是大多数系统的默认入口点名字，所以我们要确保它不会发生变化。 - -接着，我们使用 `extern "C"` 描述 `_start` 函数，这是 Rust 中的 FFI （Foreign Function Interface, 语言交互接口）语法，表示此函数是一个 C 函数而非 Rust 函数。由于 `_start` 是作为 C 语言运行时的入口点，看起来合情合理。 - -由于程序会一直停在 `crt0` 的入口点，我们可以移除没用的 `main` 函数。 - -### 链接错误 - -再次 `cargo build` ，我们会看到一大段链接错误。 - -链接器（Linker）是一个程序，它将生成的目标文件组合为一个可执行文件。不同的操作系统如 Windows、macOS 或 Linux，规定了不同的可执行文件格式，因此也各有自己的链接器，抛出不同的错误；但这些错误的根本原因还是相同的：链接器的默认配置假定程序依赖于 C 语言的运行时环境，但我们的程序并不依赖于它。 - -为了解决这个错误，我们需要告诉链接器，它不应该包含 C 语言运行时环境。我们可以选择提供特定的链接器参数（Linker Argument），也可以选择编译为裸机目标（Bare Metal Target），我们将沿着后者的思路在后面解决这个问题，即直接编译为裸机目标不链接任何运行时环境。 \ No newline at end of file diff --git a/docs/lab-0/guide/part-4.md b/docs/lab-0/guide/part-4.md deleted file mode 100644 index a6fe4be..0000000 --- a/docs/lab-0/guide/part-4.md +++ /dev/null @@ -1,51 +0,0 @@ -## 编译为裸机目标 - -在默认情况下，Rust 尝试适配当前的系统环境，编译可执行程序。举个例子，如果你使用 x86_64 平台的 Windows 系统，Rust 将尝试编译一个扩展名为 `.exe` 的 Windows 可执行程序，并使用 `x86_64` 指令集。这个环境又被称作为你的宿主系统（Host System）。 - -为了描述不同的环境，Rust 使用一个称为目标三元组（Target Triple）的字符串 `---`。要查看当前系统的目标三元组，我们可以运行 `rustc --version --verbose`： - -{% label %}运行输出{% endlabel %} -```bash -rustc 1.46.0-nightly (7750c3d46 2020-06-26) -binary: rustc -commit-hash: 7750c3d46bc19784adb1ee6e37a5ec7e4cd7e772 -commit-date: 2020-06-26 -host: x86_64-unknown-linux-gnu -release: 1.46.0-nightly -LLVM version: 10.0 -``` - -上面这段输出来自一个 x86_64 平台下的 Linux 系统。我们能看到，host 字段的值为三元组 x86_64-unknown-linux-gnu，它包含了 CPU 架构 x86_64、供应商 unknown、操作系统 linux 和二进制接口 gnu。 - -Rust 编译器尝试为当前系统的三元组编译，并假定底层有一个类似于 Windows 或 Linux 的操作系统提供 C 语言运行环境，然而这将导致链接器错误。所以，为了避免这个错误，我们可以另选一个底层没有操作系统的运行环境。 - -这样的运行环境被称作裸机环境，例如目标三元组 riscv64imac-unknown-none-elf 描述了一个 RISC-V 64 位指令集的系统。我们暂时不需要了解它的细节，只需要知道这个环境底层没有操作系统，这是由三元组中的 none 描述的。要为这个目标编译，我们需要使用 rustup 添加它： - -{% label %}运行命令{% endlabel %} -```bash -rustup target add riscv64imac-unknown-none-elf -``` - -这行命令将为目标下载一个标准库和 core 库。这之后，我们就能为这个目标成功构建独立式可执行程序了： - -{% label %}运行命令{% endlabel %} -```bash -cargo build --target riscv64imac-unknown-none-elf -``` - -编译出的结果被放在了 `os/target/riscv64imac-unknown-none-elf/debug` 文件夹中。可以看到其中有一个名为 `os` 的可执行文件。不过由于它的目标平台是 RISC-V 64，我们暂时还不能通过我们的开发环境执行它。 - -由于我们之后都会使用 RISC-V 作为编译目标，为了避免每次都要加 `--target` 参数，我们可以使用 [cargo 配置文件](https://doc.rust-lang.org/cargo/reference/config.html)为项目配置默认的编译选项。 - -在 `os` 文件夹中创建一个 `.cargo` 文件夹，并在其中创建一个名为 `config` 的文件，在其中填入以下内容： - -{% label %}os/.cargo/config{% endlabel %} -```toml -# 编译的目标平台 -[build] -target = "riscv64imac-unknown-none-elf" -``` - -这指定了此项目编译时默认的目标。以后我们就可以直接使用 `cargo build` 来编译了。 - -至此，我们完成了在 RISC-V 64 位平台的二进制程序编译，后面我们将通过布局和代码的简单调整实现一个最简单的内核。 diff --git a/docs/lab-0/guide/part-5.md b/docs/lab-0/guide/part-5.md deleted file mode 100644 index 454ddf8..0000000 --- a/docs/lab-0/guide/part-5.md +++ /dev/null @@ -1,139 +0,0 @@ -## 生成内核镜像 - -### 安装 binutils 工具集 - -为了查看和分析生成的可执行文件，我们首先需要安装一套名为 binutils 的命令行工具集，其中包含了 objdump 和 objcopy 等常用工具。 - -Rust 社区提供了一个 cargo-binutils 项目，可以帮助我们方便地调用 Rust 内置的 LLVM binutils。我们用以下命令安装它： - -{% label %}运行命令{% endlabel %} -```bash -cargo install cargo-binutils -rustup component add llvm-tools-preview -``` - -之后尝试使用 `rust-objdump --version` 命令看看是否安装成功。 - -> **[info] rust-objdump 找不到？** -> -> `cargo install` 会默认将二进制文件添加到 `${HOME}/.cargo/bin` 中，我们将这个路径加入到 `$PATH` 环境变量中之后就能找到需要的 rust-objdump 命令了。 - -> **[info] 其它选择：GNU 工具链** -> -> 除了内置的 LLVM 工具链以外，我们也可以使用 GNU 工具链，其中还包含了 GCC 等 C 语言工具链。 -> -> 我们可以在 https://www.sifive.com/boards#software 上去下载最新的适合自己操作系统的预编译版本。 - -### 查看生成的可执行文件 - -我们编译之后的产物为 `os/target/riscv64imac-unknown-none-elf/debug/os`，让我们先看看它的文件类型： - -{% label %}运行输出{% endlabel %} -```bash -$ file target/riscv64imac-unknown-none-elf/debug/os -target/riscv64imac-unknown-none-elf/debug/os: ELF 64-bit LSB executable, UCB RISC-V, version 1 (SYSV), statically linked, with debug_info, not stripped -``` - -从中，我们可以看出它是一个 64 位的 elf 格式的可执行文件，架构是 RISC-V；链接方式为静态链接；not stripped 指的是里面符号表的信息未被剔除，而这些信息在调试程序时会用到，程序正常执行时通常不会使用。 - -接下来使用刚刚安装的工具链中的 rust-objdump 工具看看它的具体信息： - -{% label %}运行输出{% endlabel %} -```clike -$ rust-objdump target/riscv64imac-unknown-none-elf/debug/os -x --arch-name=riscv64 - -target/riscv64imac-unknown-none-elf/debug/os: file format ELF64-riscv - -architecture: riscv64 -start address: 0x0000000000011000 - -Sections: -Idx Name Size VMA Type - 0 00000000 0000000000000000 - 1 .text 0000000c 0000000000011000 TEXT - 2 .debug_str 000004f6 0000000000000000 - 3 .debug_abbrev 0000010e 0000000000000000 - 4 .debug_info 00000633 0000000000000000 - 5 .debug_aranges 00000040 0000000000000000 - 6 .debug_ranges 00000030 0000000000000000 - 7 .debug_macinfo 00000001 0000000000000000 - 8 .debug_pubnames 000000ce 0000000000000000 - 9 .debug_pubtypes 000003a2 0000000000000000 - 10 .debug_frame 00000068 0000000000000000 - 11 .debug_line 00000059 0000000000000000 - 12 .comment 00000012 0000000000000000 - 13 .symtab 00000108 0000000000000000 - 14 .shstrtab 000000b4 0000000000000000 - 15 .strtab 0000002d 0000000000000000 - -SYMBOL TABLE: -0000000000000000 l df *ABS* 00000000 3k1zkxjipadm3tm5 -0000000000000000 .debug_frame 00000000 -0000000000011000 .text 00000000 -0000000000011000 .text 00000000 -0000000000011000 .text 00000000 -000000000001100c .text 00000000 -0000000000000000 .debug_ranges 00000000 -0000000000000000 .debug_info 00000000 -0000000000000000 .debug_line 00000000 .Lline_table_start0 -0000000000011000 g F .text 0000000c _start -Program Header: - PHDR off 0x0000000000000040 vaddr 0x0000000000010040 paddr 0x0000000000010040 align 2**3 - filesz 0x00000000000000e0 memsz 0x00000000000000e0 flags r-- - LOAD off 0x0000000000000000 vaddr 0x0000000000010000 paddr 0x0000000000010000 align 2**12 - filesz 0x0000000000000120 memsz 0x0000000000000120 flags r-- - LOAD off 0x0000000000001000 vaddr 0x0000000000011000 paddr 0x0000000000011000 align 2**12 - filesz 0x0000000000001000 memsz 0x0000000000001000 flags r-x - STACK off 0x0000000000000000 vaddr 0x0000000000000000 paddr 0x0000000000000000 align 2**64 - filesz 0x0000000000000000 memsz 0x0000000000000000 flags rw- - -Dynamic Section: - -``` - -我们按顺序逐个查看： - -- start address：程序的入口地址 -- Sections：从这里我们可以看到程序各段的各种信息。后面以 debug 开头的段是调试信息 -- SYMBOL TABLE：符号表，从中我们可以看到程序中所有符号的地址。例如 `_start` 函数就位于入口地址上 -- Program Header：程序加载时所需的段信息 - - 其中的 off 是它在文件中的位置，vaddr 和 paddr 是要加载到的虚拟地址和物理地址，align 规定了地址的对齐，filesz 和 memsz 分别表示它在文件和内存中的大小，flags 描述了相关权限（r 表示可读，w 表示可写，x 表示可执行） - -在这里我们使用的是 `-x` 来查看程序的元信息，下面我们用 `-d` 来对代码进行反汇编： - -{% label %}运行输出{% endlabel %} -```bash -$ rust-objdump target/riscv64imac-unknown-none-elf/debug/os -d --arch-name=riscv64 - -target/riscv64imac-unknown-none-elf/debug/os: file format ELF64-riscv - -Disassembly of section .text: - -0000000000011000 _start: - 11000: 41 11 addi sp, sp, -16 - 11002: 06 e4 sd ra, 8(sp) - 11004: 22 e0 sd s0, 0(sp) - 11006: 00 08 addi s0, sp, 16 - 11008: 09 a0 j 2 - 1100a: 01 a0 j 0 -``` - -可以看到其中只有一个 `_start` 函数，里面什么都不做，就一个死循环。 - -### 生成镜像 - -我们之前生成的 elf 格式可执行文件有以下特点： - -- 含有冗余的调试信息，使得程序体积较大 -- 需要对 Program Header 部分进行手动解析才能知道各段的信息，而这需要我们了解 Program Header 的二进制格式，并以字节为单位进行解析 - -由于我们目前没有调试的手段，不需要调试信息；同时也不会解析 elf 格式文件，所以我们可以使用工具 rust-objcopy 从 elf 格式可执行文件生成内核镜像： - -{% label %}运行命令{% endlabel %} -```bash -rust-objcopy target/riscv64imac-unknown-none-elf/debug/os --strip-all -O binary target/riscv64imac-unknown-none-elf/debug/kernel.bin -``` - -这里 `--strip-all` 表明丢弃所有符号表及调试信息，`-O binary` 表示输出为二进制文件。 - -至此，我们编译并生成了内核镜像 `kernel.bin` 文件。接下来，我们将使用 QEMU 模拟器真正将我们的内核镜像跑起来。不过在此之前还需要完成两个工作：**调整内存布局**和**重写入口函数**。 diff --git a/docs/lab-0/guide/part-6.md b/docs/lab-0/guide/part-6.md deleted file mode 100644 index 7aea69d..0000000 --- a/docs/lab-0/guide/part-6.md +++ /dev/null @@ -1,167 +0,0 @@ -## 调整内存布局 - -上一节中我们看到，编译出的程序默认被放到了从 0x11000 开始的位置上： - -{% label %}运行输出{% endlabel %} -```clike -start address: 0x0000000000011000 -... -Program Header: - PHDR off 0x0000000000000040 vaddr 0x0000000000010040 ... - LOAD off 0x0000000000000000 vaddr 0x0000000000010000 ... - LOAD off 0x0000000000001000 vaddr 0x0000000000011000 ... - STACK off 0x0000000000000000 vaddr 0x0000000000000000 ... -``` - -这是因为对于普通用户程序来说，代码和数据一般放在低地址空间上的。 - -对于 OS 内核，一般都将其地址空间放在高地址上。并且在 QEMU 模拟的 RISC-V 中，DRAM 内存的物理地址是从 0x80000000 开始，有 128MB 大小（如想进一步了解，可参看 `qemu/hw/riscv/virt.c` 中的 `VIRT_DRAM` 的赋值，以及[实验指导二中物理内存探测](../../lab-2/guide/part-2.md)小节）。因此接下来我们需要调整程序的内存布局，改变它的链接地址。 - -> **[info] 程序的内存布局** -> -> 一般来说，一个程序按照功能不同会分为下面这些段： -> -> - .text 段：代码段，存放汇编代码 -> - .rodata 段：只读数据段，顾名思义里面存放只读数据，通常是程序中的常量 -> - .data 段：存放被初始化的可读写数据，通常保存程序中的全局变量 -> - .bss 段：存放被初始化为 0 的可读写数据，与 .data 段的不同之处在于我们知道它要被初始化为 0，因此在可执行文件中只需记录这个段的大小以及所在位置即可，而不用记录里面的数据，也不会实际占用二进制文件的空间 -> - Stack：栈，用来存储程序运行过程中的局部变量，以及负责函数调用时的各种机制。它从高地址向低地址增长 -> - Heap：堆，用来支持程序**运行过程中**内存的**动态分配**，比如说你要读进来一个字符串，在你写程序的时候你也不知道它的长度究竟为多少，于是你只能在运行过程中，知道了字符串的长度之后，再在堆中给这个字符串分配内存 -> -> 内存布局，也就是指这些段各自所放的位置。一种典型的内存布局如下： ->
- -### 编写链接脚本 - -我们使用**链接脚本（Linker Script）**来指定程序的内存布局。创建文件 `os/src/linker.ld`： - -{% label %}os/src/linker.ld{% endlabel %} -```cpp -/* 有关 Linker Script 可以参考：https://sourceware.org/binutils/docs/ld/Scripts.html */ - -/* 目标架构 */ -OUTPUT_ARCH(riscv) - -/* 执行入口 */ -ENTRY(_start) - -/* 数据存放起始地址 */ -BASE_ADDRESS = 0x80200000; - -SECTIONS -{ - /* . 表示当前地址（location counter） */ - . = BASE_ADDRESS; - - /* start 符号表示全部的开始位置 */ - kernel_start = .; - - text_start = .; - - /* .text 字段 */ - .text : { - /* 把 entry 函数放在最前面 */ - *(.text.entry) - /* 要链接的文件的 .text 字段集中放在这里 */ - *(.text .text.*) - } - - rodata_start = .; - - /* .rodata 字段 */ - .rodata : { - /* 要链接的文件的 .rodata 字段集中放在这里 */ - *(.rodata .rodata.*) - } - - data_start = .; - - /* .data 字段 */ - .data : { - /* 要链接的文件的 .data 字段集中放在这里 */ - *(.data .data.*) - } - - bss_start = .; - - /* .bss 字段 */ - .bss : { - /* 要链接的文件的 .bss 字段集中放在这里 */ - *(.sbss .bss .bss.*) - } - - /* 结束地址 */ - kernel_end = .; -} -``` - -时至今日我们已经不太可能将所有代码都写在一个文件里面。在编译过程中，我们的编译器和链接器已经给每个文件都自动生成了一个内存布局。这里，我们的链接工具所要做的是最终将各个文件的内存布局装配起来生成整个内核的内存布局。 - -我们首先使用 OUTPUT_ARCH 指定了架构，随后使用 ENTRY 指定了入口点为 `_start` 函数，即程序第一条被执行的指令所在之处。在这个链接脚本中我们并未看到 `_start` ，回忆上一章，我们为了移除运行时环境依赖，重写了入口 `_start` 。所以，链接脚本宣布整个程序会从那里开始运行。 - -链接脚本的整体写在 `SECTION{ }` 中，里面有多个形如 `output section: { input section list }` 的语句，每个都描述了整个程序内存布局中的一个输出段 output section 是由各个文件中的哪些输入段 input section 组成的。 - -我们可以用 `*( )` 来表示将各个文件中所有符合括号内要求的输入段放在当前的位置。而括号内，你可以直接使用段的名字，也可以包含通配符 `*`。 - -单独的一个 `.` 为**当前地址（Location Counter）**，可以对其赋值来从设置的地址继续向高地址放置各个段。如果不进行赋值的话，则默认各个段会紧挨着向高地址放置。将一个符号赋值为 `.` 则会记录下这个符号的地址。 - -到这里我们大概看懂了这个链接脚本在做些什么事情。首先是从 BASE_ADDRESS 即 0x80200000 开始向下放置各个段，依次是 .text，.rodata，.data，.stack 和 .bss。同时我们还记录下了每个段的开头和结尾地址，如 .text 段的开头、结尾地址分别就是符号 stext 和 etext 的值，我们接下来会用到。 - -> **[info] 为什么是 0x80200000 ** -> -> [OpenSBI](https://github.com/riscv/opensbi)（如想进一步了解，可参看本章的[重写程序入口点](part7.md)小节相关的介绍）将自身放在 0x80000000，完成初始化后会跳转到 0x80200000，因此 `_start` 必须位于这个地址。.text 为代码段标识，其第一个放置的就是 `_start`（即 `.text.entry`）。 - -这里面有一个输入段与其他的不太一样，即 .text.entry，似乎编译器不会自动生成这样名字的段。事实上，它是我们在后面自己定义的。 - -### 使用链接脚本 - -为了在编译时使用上面自定义的链接脚本，我们在 `.cargo/config` 文件中加入以下配置： - -{% label %}os/.cargo/config{% endlabel %} -```toml -# 使用我们的 linker script 来进行链接 -[target.riscv64imac-unknown-none-elf] -rustflags = [ - "-C", "link-arg=-Tsrc/linker.ld", -] -``` - -它的作用是在链接时传入一个参数 `-T` 来指定使用哪个链接脚本。 - -我们重新编译一下，然后再次查看生成的可执行文件： - -{% label %}运行输出{% endlabel %} -```bash -$ cargo build -... - Finished dev [unoptimized + debuginfo] target(s) in 0.23s -$ rust-objdump target/riscv64imac-unknown-none-elf/debug/os -h --arch-name=riscv64 - -target/riscv64imac-unknown-none-elf/debug/os: file format ELF64-riscv - -Sections: -Idx Name Size VMA Type - 0 00000000 0000000000000000 - 1 .text 0000000c 0000000080200000 TEXT - 2 .rodata 00000000 000000008020000c TEXT - 3 .data 00000000 000000008020000c TEXT - 4 .bss 00000000 000000008020000c BSS -... -$ rust-objdump target/riscv64imac-unknown-none-elf/debug/os -d --arch-name=riscv64 - -target/riscv64imac-unknown-none-elf/debug/os: file format ELF64-riscv - -Disassembly of section .text: - -0000000080200000 stext: -80200000: 41 11 addi sp, sp, -16 -80200002: 06 e4 sd ra, 8(sp) -80200004: 22 e0 sd s0, 0(sp) -80200006: 00 08 addi s0, sp, 16 -80200008: 09 a0 j 2 -8020000a: 01 a0 j 0 -``` - -程序已经被正确地放在了指定的地址上。 - -到这里，我们清楚了最终程序的内存布局会长成什么样子。下一节我们来补充这个链接脚本中未定义的段，并完成编译。 diff --git a/docs/lab-0/guide/part-7.md b/docs/lab-0/guide/part-7.md deleted file mode 100644 index 7d6ba2f..0000000 --- a/docs/lab-0/guide/part-7.md +++ /dev/null @@ -1,111 +0,0 @@ -## 重写程序入口点 `_start` - -我们在第一章中，曾自己重写了一个入口点 `_start`，在那里我们仅仅只是让它死循环。但是现在，类似 C 语言运行时环境，我们希望这个函数可以为我们设置内核的运行环境。随后，我们才真正开始执行内核的代码。 - -但是具体而言我们需要设置怎样的运行环境呢？ - -> **[info] 第一条指令** -> -> 在 CPU 加电或 Reset 后，它首先会进行自检（POST, Power-On Self-Test），通过自检后会跳转到**启动代码（Bootloader）**的入口。在 bootloader 中，我们进行外设探测，并对内核的运行环境进行初步设置。随后，bootloader 会将内核代码从硬盘加载到内存中，并跳转到内核入口，正式进入内核。也就是说，CPU 所执行的第一条指令其实是指 bootloader 的第一条指令。 - -幸运的是， 我们已经有现成的 bootloader 实现 [OpenSBI](https://github.com/riscv/opensbi) 固件（Firmware）。 - -> **[info] Firmware 固件** -> -> 在计算中，固件是一种特定的计算机软件，它为设备的特定硬件提供低级控制进一步加载其他软件的功能。固件可以为设备更复杂的软件（如操作系统）提供标准化的操作环境，或者，对于不太复杂的设备，充当设备的完整操作系统，执行所有控制、监视和数据操作功能。在基于 x86 的计算机系统中, BIOS 或 UEFI 是一种固件；在基于 RISC-V 的计算机系统中，OpenSBI 是一种固件。 - -OpenSBI 固件运行在特权级别很高的计算机硬件环境中，即 RISC-V 64 的 M Mode（CPU 加电后也就运行在 M Mode），我们将要实现的 OS 内核运行在 S Mode，而我们要支持的用户程序运行在 U Mode。在开发过程中我们重点关注 S Mode。 - -> **[info] RISC-V 64 的特权级** -> -> RISC-V 共有 3 种特权级，分别是 U Mode（User / Application 模式）、S Mode（Supervisor 模式）和 M Mode（Machine 模式）。 -> -> 从 U 到 S 再到 M，权限不断提高，这意味着你可以使用更多的特权指令，访需求权限更高的寄存器等等。我们可以使用一些指令来修改 CPU 的**当前特权级**。而当当前特权级不足以执行特权指令或访问一些寄存器时，CPU 会通过某种方式告诉我们。 - -OpenSBI 所做的一件事情就是把 CPU 从 M Mode 切换到 S Mode，接着跳转到一个固定地址 0x80200000，开始执行内核代码。 - -> **[info] RISC-V 的 M Mode** -> -> Machine 模式是 RISC-V 中可以执行的最高权限模式。在机器态下运行的代码对内存、I/O 和一些对于启动和配置系统来说必要的底层功能有着完全的使用权。 -> -> **RISC-V 的 S Mode** -> -> Supervisor 模式是支持现代类 Unix 操作系统的权限模式，支持现代类 Unix 操作系统所需要的基于页面的虚拟内存机制是其核心。 -> - -接着我们要在 `_start` 中设置内核的运行环境了，我们直接来看代码： - -{% label %}os/src/entry.asm{% endlabel %} -```assembly -# 操作系统启动时所需的指令以及字段 -# -# 我们在 linker.ld 中将程序入口设置为了 _start，因此在这里我们将填充这个标签 -# 它将会执行一些必要操作，然后跳转至我们用 rust 编写的入口函数 -# -# 关于 RISC-V 下的汇编语言，可以参考 https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md - - .section .text.entry - .globl _start -# 目前 _start 的功能：将预留的栈空间写入 $sp，然后跳转至 rust_main -_start: - la sp, boot_stack_top - call rust_main - - # 回忆：bss 段是 ELF 文件中只记录长度，而全部初始化为 0 的一段内存空间 - # 这里声明字段 .bss.stack 作为操作系统启动时的栈 - .section .bss.stack - .global boot_stack -boot_stack: - # 16K 启动栈大小 - .space 4096 * 16 - .global boot_stack_top -boot_stack_top: - # 栈结尾 -``` - -可以看到我们在 .bss 中加入了 .stack 段，并在这里分配了一块 $$4096\times{4}\text{\ Bytes}=16 \text{\ KBytes}$$ 的内存作为启动时内核的栈。之前的 .text.entry 也出现了，也就是我们将 `_start` 函数放在了 .text 段的开头。 - -我们看看 `_start` 里面做了什么： - -1. 修改栈指针寄存器 `sp` 为 .bss.stack 段的结束地址，由于栈是从高地址往低地址增长，所以高地址是初始的栈顶； -2. 使用 `call` 指令跳转到 `rust_main` 。这意味着我们的内核运行环境设置完成了，正式进入内核。 - -我们将 `os/src/main.rs` 里面的 `_start` 函数删除，并换成 `rust_main` ： - -{% label %}os/src/main.rs{% endlabel %} -```rust -//! # 全局属性 -//! - `#![no_std]` -//! 禁用标准库 -#![no_std] -//! -//! - `#![no_main]` -//! 不使用 `main` 函数等全部 Rust-level 入口点来作为程序入口 -#![no_main] -//! -//! - `#![feature(global_asm)]` -//! 内嵌整个汇编文件 -#![feature(global_asm)] - -// 汇编编写的程序入口，具体见该文件 -global_asm!(include_str!("entry.asm")); - -use core::panic::PanicInfo; - -/// 当 panic 发生时会调用该函数 -/// 我们暂时将它的实现为一个死循环 -#[panic_handler] -fn panic(_info: &PanicInfo) -> ! { - loop {} -} - -/// Rust 的入口函数 -/// -/// 在 `_start` 为我们进行了一系列准备之后，这是第一个被调用的 Rust 函数 -#[no_mangle] -pub extern "C" fn rust_main() -> ! { - loop {} -} -``` - -到现在为止我们终于将一切都准备好了，接下来就要配合 OpenSBI 运行我们的内核！ \ No newline at end of file diff --git a/docs/lab-0/guide/part-8.md b/docs/lab-0/guide/part-8.md deleted file mode 100644 index 01b565a..0000000 --- a/docs/lab-0/guide/part-8.md +++ /dev/null @@ -1,162 +0,0 @@ -## 使用 QEMU 运行内核 - -### 使用 OpenSBI - -新版 QEMU 中内置了 OpenSBI 固件，它主要负责在操作系统运行前的硬件初始化和加载操作系统的功能。我们使用以下命令尝试运行一下： - -{% label %}运行输出{% endlabel %} -```bash -$ qemu-system-riscv64 \ - --machine virt \ - --nographic \ - --bios default - -OpenSBI v0.4 (Jul 2 2019 11:53:53) - ____ _____ ____ _____ - / __ \ / ____| _ \_ _| - | | | |_ __ ___ _ __ | (___ | |_) || | - | | | | '_ \ / _ \ '_ \ \___ \| _ < | | - | |__| | |_) | __/ | | |____) | |_) || |_ - \____/| .__/ \___|_| |_|_____/|____/_____| - | | - |_| - -Platform Name : QEMU Virt Machine -Platform HART Features : RV64ACDFIMSU -Platform Max HARTs : 8 -Current Hart : 0 -Firmware Base : 0x80000000 -Firmware Size : 112 KB -Runtime SBI Version : 0.1 - -PMP0: 0x0000000080000000-0x000000008001ffff (A) -PMP1: 0x0000000000000000-0xffffffffffffffff (A,R,W,X) -``` - -可以看到我们已经在 qemu-system-riscv64 模拟的 QEMU Virt Machine 硬件上将 OpenSBI 这个固件跑起来了。QEMU 可以使用 `ctrl+a` （macOS 为 `control+a`） 再按下 `x` 键退出。 - -### 加载内核镜像 - -为了确信我们已经跑起来了内核里面的代码，我们最好在 `rust_main` 里面加上简单的输出： - -{% label %}os/src/main.rs{% endlabel %} -```rust -//! # 全局属性 -//! - `#![no_std]` -//! 禁用标准库 -#![no_std] -//! -//! - `#![no_main]` -//! 不使用 `main` 函数等全部 Rust-level 入口点来作为程序入口 -#![no_main] -//! # 一些 unstable 的功能需要在 crate 层级声明后才可以使用 -//! - `#![feature(llvm_asm)]` -//! 内嵌汇编 -#![feature(llvm_asm)] -//! -//! - `#![feature(global_asm)]` -//! 内嵌整个汇编文件 -#![feature(global_asm)] - -// 汇编编写的程序入口，具体见该文件 -global_asm!(include_str!("entry.asm")); - -use core::panic::PanicInfo; - -/// 当 panic 发生时会调用该函数 -/// 我们暂时将它的实现为一个死循环 -#[panic_handler] -fn panic(_info: &PanicInfo) -> ! { - loop {} -} - -/// 在屏幕上输出一个字符，目前我们先不用了解其实现原理 -pub fn console_putchar(ch: u8) { - let _ret: usize; - let arg0: usize = ch as usize; - let arg1: usize = 0; - let arg2: usize = 0; - let which: usize = 1; - unsafe { - llvm_asm!("ecall" - : "={x10}" (_ret) - : "{x10}" (arg0), "{x11}" (arg1), "{x12}" (arg2), "{x17}" (which) - : "memory" - : "volatile" - ); - } -} - -/// Rust 的入口函数 -/// -/// 在 `_start` 为我们进行了一系列准备之后，这是第一个被调用的 Rust 函数 -#[no_mangle] -pub extern "C" fn rust_main() -> ! { - // 在屏幕上输出 "OK\n" ，随后进入死循环 - console_putchar(b'O'); - console_putchar(b'K'); - console_putchar(b'\n'); - - loop {} -} -``` - -这样，如果我们将内核镜像加载完成后，屏幕上出现了 OK ，就说明我们之前做的事情没有问题。 - - - -现在我们生成内核镜像要通过多条命令来完成，我们可以通过在 os 目录下建立一个 Makefile 来简化这一过程： - -{% label %}os/Makefile{% endlabel %} -```makefile -TARGET := riscv64imac-unknown-none-elf -MODE := debug -KERNEL_FILE := target/$(TARGET)/$(MODE)/os -BIN_FILE := target/$(TARGET)/$(MODE)/kernel.bin - -OBJDUMP := rust-objdump --arch-name=riscv64 -OBJCOPY := rust-objcopy --binary-architecture=riscv64 - -.PHONY: doc kernel build clean qemu run - -# 默认 build 为输出二进制文件 -build: $(BIN_FILE) - -# 通过 Rust 文件中的注释生成 os 的文档 -doc: - @cargo doc --document-private-items - -# 编译 kernel -kernel: - @cargo build - -# 生成 kernel 的二进制文件 -$(BIN_FILE): kernel - @$(OBJCOPY) $(KERNEL_FILE) --strip-all -O binary $@ - -# 查看反汇编结果 -asm: - @$(OBJDUMP) -d $(KERNEL_FILE) | less - -# 清理编译出的文件 -clean: - @cargo clean - -# 运行 QEMU -qemu: build - @qemu-system-riscv64 \ - -machine virt \ - -nographic \ - -bios default \ - -device loader,file=$(BIN_FILE),addr=0x80200000 - -# 一键运行 -run: build qemu - -``` - -这里我们通过参数 `-device` 来将内核镜像加载到 QEMU 中，我们指定了内核镜像文件，并告诉 OpenSBI 最后跳转到 0x80200000 这个入口地址。 - -最后，我们可以使用 `make run` 来用 Qemu 加载内核镜像并运行。匆匆翻过一串长长的 OpenSBI 输出，我们看到了 OK！于是历经了千辛万苦我们终于将我们的内核跑起来了！ - -下一节我们实现格式化输出来使得我们后续能够更加方便的通过输出来进行内核调试。 \ No newline at end of file diff --git a/docs/lab-0/guide/part-9.md b/docs/lab-0/guide/part-9.md deleted file mode 100644 index ded3f83..0000000 --- a/docs/lab-0/guide/part-9.md +++ /dev/null @@ -1,270 +0,0 @@ -## 接口封装和代码整理 - -### 使用 OpenSBI 提供的服务 - -OpenSBI 实际上不仅起到了 bootloader 的作用，还为我们提供了一些底层系统服务供我们在编写内核时使用，以简化内核实现并提高内核跨硬件细节的能力。这层底层系统服务接口称为 SBI（Supervisor Binary Interface），是 S Mode 的 OS 和 M Mode 执行环境之间的标准接口约定。 - -参考 [OpenSBI 文档](https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc#legacy-sbi-extension-extension-ids-0x00-through-0x0f) ，我们会发现里面包含了一些以 C 函数格式给出的我们可以调用的接口。 - -上一节中我们的 `console_putchar` 函数类似于调用下面的接口来实现的： -```int -void sbi_console_putchar(int ch) -``` - -而实际的过程是这样的：运行在 S 态的 OS 通过 ecall 发起 SBI 调用请求，RISC-V CPU 会从 S 态跳转到 M 态的 OpenSBI 固件，OpenSBI 会检查 OS 发起的 SBI 调用的编号，如果编号在 0-8 之间，则进行处理，否则交由我们自己的中断处理程序处理（暂未实现）。想进一步了解编号在 0-8 之间的系统调用，请参考看 [OpenSBI 文档](https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc#function-listing-1)。 - -执行 `ecall` 前需要指定 SBI 调用的编号，传递参数。一般而言，`a7(x17)` 为 SBI 调用编号，`a0(x10)`、`a1(x11)` 和 `a2(x12)` 寄存器为 SBI 调用参数： - -{% label %}os/src/sbi.rs{% endlabel %} -```rust -//! 调用 Machine 层的操作 -// 目前还不会用到全部的 SBI 调用，暂时允许未使用的变量或函数 -#![allow(unused)] - -/// SBI 调用 -#[inline(always)] -fn sbi_call(which: usize, arg0: usize, arg1: usize, arg2: usize) -> usize { - let ret; - unsafe { - llvm_asm!("ecall" - : "={x10}" (ret) - : "{x10}" (arg0), "{x11}" (arg1), "{x12}" (arg2), "{x17}" (which) - : "memory" // 如果汇编可能改变内存，则需要加入 memory 选项 - : "volatile"); // 防止编译器做激进的优化（如调换指令顺序等破坏 SBI 调用行为的优化） - } - ret -} -``` - -> **[info] 函数调用与 Calling Convention ** -> -> 我们知道，编译器将高级语言源代码翻译成汇编代码。对于汇编语言而言，在最简单的编程模型中，所能够利用的只有指令集中提供的指令、各通用寄存器、 CPU 的状态、内存资源。那么，在高级语言中，我们进行一次函数调用，编译器要做哪些工作利用汇编语言来实现这一功能呢？ -> -> 显然并不是仅用一条指令跳转到被调用函数开头地址就行了。我们还需要考虑： -> -> - 如何传递参数？ -> - 如何传递返回值？ -> - 如何保证函数返回后能从我们期望的位置继续执行？ -> -> 等更多事项。通常编译器按照某种规范去翻译所有的函数调用，这种规范被称为 [Calling Convention](https://en.wikipedia.org/wiki/Calling_convention) 。值得一提的是，为了确保被调用函数能正确执行，我们需要预先分配一块内存作为**调用栈** ，后面会看到调用栈在函数调用过程中极其重要。你也可以理解为什么第一章刚开始我们就要分配栈了。 - -对于参数比较少且是基本数据类型的时候，我们从左到右使用寄存器 `a0` 到 `a7` 就可以完成参数的传递。具体规范可参考 [RISC-V Calling Convention](https://riscv.org/wp-content/uploads/2015/01/riscv-calling.pdf)。 - -对于设置寄存器并执行汇编指令的代码编写，已经超出了 Rust 语言的基本描述能力。之前采用的 `global_asm!` 方式在Rust代码中插入汇编代码，还不太方便实现Rust代码与汇编代码的互操作。为有效编写 Rust代码与汇编代码的互操作，我们还有另外一种**内联汇编（Inline Assembly）**方式， 可相对简单地完成诸如把 `u8` 类型的单个字符传给 `a0` 作为输入参数的编码需求。**内联汇编（Inline Assembly）**的具体规范请参考书籍[《Rust 编程》](https://kaisery.gitbooks.io/rust-book-chinese/content/content/Inline%20Assembly%20%E5%86%85%E8%81%94%E6%B1%87%E7%BC%96.html)。 - -输出部分，我们将结果保存到变量 `ret` 中，限制条件 `{x10}` 告诉编译器使用寄存器 `x10`（即 `a0` 寄存器），前面的 `=` 表明汇编代码会修改该寄存器并作为最后的返回值。 - -输入部分，我们分别通过寄存器 `x10`、`x11`、`x12` 和 `x17`（这四个寄存器又名 `a0`、`a1`、`a2` 和 `a7`） 传入参数 `arg0`、`arg1`、`arg2` 和 `which` ，其中前三个参数分别代表接口可能所需的三个输入参数，最后一个 `which` 用来区分我们调用的是哪个接口（SBI Extension ID）。这里之所以提供三个输入参数是为了将所有接口囊括进去，对于某些接口有的输入参数是冗余的，比如 `sbi_console_putchar` 由于只需一个输入参数，它就只关心寄存器 `a0` 的值。 - -接着利用 `sbi_call` 函数参考 OpenSBI 文档实现对应的接口，顺带也可以把关机函数通过 SBI 接口一并实现： - -{% label %}os/src/sbi.rs{% endlabel %} -```rust -const SBI_SET_TIMER: usize = 0; -const SBI_CONSOLE_PUTCHAR: usize = 1; -const SBI_CONSOLE_GETCHAR: usize = 2; -const SBI_CLEAR_IPI: usize = 3; -const SBI_SEND_IPI: usize = 4; -const SBI_REMOTE_FENCE_I: usize = 5; -const SBI_REMOTE_SFENCE_VMA: usize = 6; -const SBI_REMOTE_SFENCE_VMA_ASID: usize = 7; -const SBI_SHUTDOWN: usize = 8; - -/// 向控制台输出一个字符 -/// -/// 需要注意我们不能直接使用 Rust 中的 char 类型 -pub fn console_putchar(c: usize) { - sbi_call(SBI_CONSOLE_PUTCHAR, c, 0, 0); -} - -/// 从控制台中读取一个字符 -/// -/// 没有读取到字符则返回 -1 -pub fn console_getchar() -> usize { - sbi_call(SBI_CONSOLE_GETCHAR, 0, 0, 0) -} - -/// 调用 SBI_SHUTDOWN 来关闭操作系统（直接退出 QEMU） -pub fn shutdown() -> ! { - sbi_call(SBI_SHUTDOWN, 0, 0, 0); - unreachable!() -} -``` - -现在我们比较深入的理解了 `console_putchar` 到底是怎么一回事。下面我们使用 `console_putchar` 实现格式化输出，为后面的调试提供方便。 - -### 实现格式化输出 - -只能使用 `console_putchar` 这种苍白无力的输出手段让人头皮发麻。如果我们能使用 `println!` 宏的话该有多好啊！于是我们就来实现自己的 `print!`宏和 `println!`宏！ - -我们将这一部分放在 `os/src/conosle.rs` 中，关于格式化输出，Rust 中提供了一个接口 `core::fmt::Write`，你需要实现函数： - -```rust -fn write_str(&mut self, s: &str) -> Result -``` - -随后我们就可以调用如下函数（会进一步调用`write_str` 实现函数）来进行显示： - -```rust -fn write_fmt(mut self: &mut Self, args: Arguments<'_>) -> Result -``` - -`write_fmt` 函数需要处理 `Arguments` 类封装的输出字符串。而我们已经有现成的 `format_args!` 宏，它可以将模式字符串和参数列表的输入转化为 `Arguments` 类，比如 `format_args!("{} {}", 1, 2)` 。 - -因此，我们宏的实现思路便为： - -- 解析传入参数，转化为 `format_args!` 可接受的输入（事实上原封不动就行了），并通过 `format_args!` 宏得到 `Arguments` 类 -- 调用 `write_fmt` 函数输出这个类 - -而为了调用 `write_fmt` 函数，我们必须实现 `write_str` 函数，而它可用 `console_putchar` 函数来实现。 - -最后，我们把整个 `print` 和 `println` 宏按照逻辑写出即可，整体逻辑的代码如下： - -{% label %}os/src/console.rs{% endlabel %} -```rust -//! 实现控制台的字符输入和输出 -//! -//! # 格式化输出 -//! -//! [`core::fmt::Write`] trait 包含 -//! - 需要实现的 [`write_str`] 方法 -//! - 自带实现，但依赖于 [`write_str`] 的 [`write_fmt`] 方法 -//! -//! 我们声明一个类型，为其实现 [`write_str`] 方法后，就可以使用 [`write_fmt`] 来进行格式化输出 -//! -//! [`write_str`]: core::fmt::Write::write_str -//! [`write_fmt`]: core::fmt::Write::write_fmt - -use crate::sbi::*; -use core::fmt::{self, Write}; - -/// 一个 [Zero-Sized Type]，实现 [`core::fmt::Write`] trait 来进行格式化输出 -/// -/// ZST 只可能有一个值（即为空），因此它本身就是一个单件 -struct Stdout; - -impl Write for Stdout { - /// 打印一个字符串 - /// - /// [`console_putchar`] sbi 调用每次接受一个 `usize`，但实际上会把它作为 `u8` 来打印字符。 - /// 因此，如果字符串中存在非 ASCII 字符，需要在 utf-8 编码下，对于每一个 `u8` 调用一次 [`console_putchar`] - fn write_str(&mut self, s: &str) -> fmt::Result { - let mut buffer = [0u8; 4]; - for c in s.chars() { - for code_point in c.encode_utf8(&mut buffer).as_bytes().iter() { - console_putchar(*code_point as usize); - } - } - Ok(()) - } -} - -/// 打印由 [`core::format_args!`] 格式化后的数据 -/// -/// [`print!`] 和 [`println!`] 宏都将展开成此函数 -/// -/// [`core::format_args!`]: https://doc.rust-lang.org/nightly/core/macro.format_args.html -pub fn print(args: fmt::Arguments) { - Stdout.write_fmt(args).unwrap(); -} - -/// 实现类似于标准库中的 `print!` 宏 -/// -/// 使用实现了 [`core::fmt::Write`] trait 的 [`console::Stdout`] -#[macro_export] -macro_rules! print { - ($fmt: literal $(, $($arg: tt)+)?) => { - $crate::console::print(format_args!($fmt $(, $($arg)+)?)); - } -} - -/// 实现类似于标准库中的 `println!` 宏 -/// -/// 使用实现了 [`core::fmt::Write`] trait 的 [`console::Stdout`] -#[macro_export] -macro_rules! println { - ($fmt: literal $(, $($arg: tt)+)?) => { - $crate::console::print(format_args!(concat!($fmt, "\n") $(, $($arg)+)?)); - } -} -``` - -### 整理 panic 处理模块 -最后，我们用刚刚实现的格式化输出和关机的函数，将 `main.rs` 中处理 panic 的语义项抽取并完善到 `panic.rs` 中： - -{% label %}os/src/panic.rs{% endlabel %} -```rust -//! 代替 std 库，实现 panic 和 abort 的功能 - -use core::panic::PanicInfo; -use crate::sbi::shutdown; - -/// 打印 panic 的信息并 [`shutdown`] -/// -/// ### `#[panic_handler]` 属性 -/// 声明此函数是 panic 的回调 -#[panic_handler] -fn panic_handler(info: &PanicInfo) -> ! { - // `\x1b[??m` 是控制终端字符输出格式的指令，在支持的平台上可以改变文字颜色等等，这里使用红色 - // 参考：https://misc.flogisoft.com/bash/tip_colors_and_formatting - // - // 需要全局开启 feature(panic_info_message) 才可以调用 .message() 函数 - println!("\x1b[1;31mpanic: '{}'\x1b[0m", info.message().unwrap()); - shutdown() -} - -/// 终止程序 -/// -/// 调用 [`panic_handler`] -#[no_mangle] -extern "C" fn abort() -> ! { - panic!("abort()") -} -``` - -### 检验我们的成果 - -最后，我们可以 `os/src/main.rs` 中去掉之前写的 `console_putchar`并调用我们新写的一系列函数，并在 Rust 入口处加入一些简单的输出看一看我们的逻辑是否正确： - -{% label %}os/src/main.rs{% endlabel %} -```rust -//! # 全局属性 -//! - `#![no_std]` -//! 禁用标准库 -#![no_std] -//! -//! - `#![no_main]` -//! 不使用 `main` 函数等全部 Rust-level 入口点来作为程序入口 -#![no_main] -//! # 一些 unstable 的功能需要在 crate 层级声明后才可以使用 -//! - `#![feature(llvm_asm)]` -//! 内嵌汇编 -#![feature(llvm_asm)] -//! -//! - `#![feature(global_asm)]` -//! 内嵌整个汇编文件 -#![feature(global_asm)] -//! -//! - `#![feature(panic_info_message)]` -//! panic! 时，获取其中的信息并打印 -#![feature(panic_info_message)] - -#[macro_use] -mod console; -mod panic; -mod sbi; - -// 汇编编写的程序入口，具体见该文件 -global_asm!(include_str!("entry.asm")); - -/// Rust 的入口函数 -/// -/// 在 `_start` 为我们进行了一系列准备之后，这是第一个被调用的 Rust 函数 -#[no_mangle] -pub extern "C" fn rust_main() -> ! { - println!("Hello rCore-Tutorial!"); - panic!("end of rust_main") -} -``` - -在命令行中输入 `make run`，我们成功看到了 `println` 宏输出的 `Hello rCore-Tutorial!` 和一行红色的 `panic: 'end of rust_main'`！ diff --git a/docs/lab-0/guide/summary.md b/docs/lab-0/guide/summary.md deleted file mode 100644 index 63d2e45..0000000 --- a/docs/lab-0/guide/summary.md +++ /dev/null @@ -1,3 +0,0 @@ -## 小结 - -本章作为一个预备实验，用 Rust 实现了一个最小化的内核，并成功通过 QEMU 中的 OpenSBI 启动了我们的内核。在下一章中，我们会和硬件进一步打交道，实现中断机制。 \ No newline at end of file diff --git a/docs/lab-0/pics/painter.key b/docs/lab-0/pics/painter.key deleted file mode 100644 index 0810978..0000000 Binary files a/docs/lab-0/pics/painter.key and /dev/null differ diff --git a/docs/lab-0/pics/typical-layout.png b/docs/lab-0/pics/typical-layout.png deleted file mode 100644 index f5b9c26..0000000 Binary files a/docs/lab-0/pics/typical-layout.png and /dev/null differ diff --git a/docs/lab-1/guide/intro.md b/docs/lab-1/guide/intro.md deleted file mode 100644 index 5665d06..0000000 --- a/docs/lab-1/guide/intro.md +++ /dev/null @@ -1,9 +0,0 @@ -# 实验指导一 - -## 实验概要 - -这一章的实验指导中，我们将会学习 - -- RISC-V 中有关中断处理的寄存器和相关流程 -- 如何保存上下文，使得中断处理流程前后，原本正在执行的程序感知不到发生了中断 -- 处理最简单的断点中断和时钟中断 \ No newline at end of file diff --git a/docs/lab-1/guide/part-1.md b/docs/lab-1/guide/part-1.md deleted file mode 100644 index c90f422..0000000 --- a/docs/lab-1/guide/part-1.md +++ /dev/null @@ -1,23 +0,0 @@ -## 什么是中断 - -中断是我们在操作系统上首先实现的功能，因为它是操作系统所有功能的基础。假如没有中断，操作系统在唤起一个用户程序之后，就只能等到用户程序执行完成之后才能继续执行，那操作系统完全无法进行资源调度。 - -### 一个比喻 - -操作系统就像家长，他将孩子（用户程序）送到学校（开始运行）之后便不再管。 -- 但是如果孩子闯了祸，老师（硬件）就找到家长，这便是**异常** -- 孩子的作业可能需要家长来签字（系统调用），他就会主动找家长，这便是**陷阱** -- 放学时间（时钟中断）到，那么不管孩子想不想回家，家长都会把他接走，这便是**硬件中断** - -### 中断的种类 - -#### 异常（Exception） -执行指令时产生的，通常无法预料的错误。例如：访问无效内存地址、执行非法指令（除以零）等。 - -有的异常可以恢复，例如缺页异常；有的异常会导致用户程序被终止，例如非法访问。 - -#### 陷阱（Trap） -陷阱是一系列强行导致中断的指令，例如：**系统调用（Syscall）**等。 - -#### 硬件中断（Hardware Interrupt） -前两种都是指令导致的异常，而硬件中断是由 CPU 之外的硬件产生的异步中断，例如：时钟中断、外设发来数据等。 \ No newline at end of file diff --git a/docs/lab-1/guide/part-2.md b/docs/lab-1/guide/part-2.md deleted file mode 100644 index d675a51..0000000 --- a/docs/lab-1/guide/part-2.md +++ /dev/null @@ -1,104 +0,0 @@ -## RISC-V 与中断相关的寄存器和指令 - -> **[info] 回顾：RISC-V 中的机器态（Machine Mode，机器模式，M 模式）** -> - 是 RISC-V 中的最高权限模式，一些底层操作的指令只能由机器态进行使用。 -> - 是所有标准 RISC-V 处理器都必须实现的模式。 -> - 默认所有中断实际上是交给机器态处理的，但是为了实现更多功能，机器态会将某些中断交由内核态处理。这些异常也正是我们编写操作系统所需要实现的。 -> -> **回顾：RISC-V 中的内核态（Supervisor Mode，内核模式，S 模式）** -> - 通常为操作系统使用，可以访问一些 supervisor 级别的寄存器，通过这些寄存器对中断和虚拟内存映射进行管理。 -> - Unix 系统中，大部分的中断都是内核态的系统调用。机器态可以通过异常委托机制（Machine Interrupt Delegation）将一部分中断设置为不经过机器态，直接由内核态处理 - -在实验中，我们主要关心的就是内核态可以使用的一些特权指令和寄存器。其中关于中断的会在本章用到，而关于内存映射的部分将会在第三部分用到。 - -### 与中断相关的寄存器 - -在内核态和机器态中，RISC-V 设计了一些 CSR（Control and Status Registers）寄存器用来保存控制信息。目前我们关心的是其中涉及到控制中断的寄存器。 - -#### 发生中断时，硬件自动填写的寄存器 - -- `sepc` -即 Exception Program Counter，用来记录触发中断的指令的地址。 - - > 和我们之前学的 MIPS 32 系统不同，RISC-V 中不需要考虑延迟槽的问题。但是 RISC-V 中的指令不定长，如果中断处理需要恢复到异常指令后一条指令进行执行，就需要正确判断将 `pc` 寄存器加上多少字节。 - -- `scause` -记录中断是否是硬件中断，以及具体的中断原因。 - -- `stval` -`scause` 不足以存下中断所有的必须信息。例如缺页异常，就会将 `stval` 设置成需要访问但是不在内存中的地址，以便于操作系统将这个地址所在的页面加载进来。 - -#### 指导硬件处理中断的寄存器 - -- `stvec` -设置内核态中断处理流程的入口地址。存储了一个基址 BASE 和模式 MODE： - - - MODE 为 0 表示 Direct 模式，即遇到中断便跳转至 BASE 进行执行。 - - - MODE 为 1 表示 Vectored 模式，此时 BASE 应当指向一个向量，存有不同处理流程的地址，遇到中断会跳转至 `BASE + 4 * cause` 进行处理流程。 - -- `sstatus` -具有许多状态位，控制全局中断使能等。 - -- `sie` -即 Supervisor Interrupt Enable，用来控制具体类型中断的使能，例如其中的 STIE 控制时钟中断使能。 - -- `sip` -即 Supervisor Interrupt Pending，和 `sie` 相对应，记录每种中断是否被触发。仅当 `sie` 和 `sip` 的对应位都为 1 时，意味着开中断且已发生中断，这时中断最终触发。 - -#### `sscratch` - -（这个寄存器的用处会在实现线程时起到作用，目前仅了解即可） - -在用户态，`sscratch` 保存内核栈的地址；在内核态，`sscratch` 的值为 0。 - -为了能够执行内核态的中断处理流程，仅有一个入口地址是不够的。中断处理流程很可能需要使用栈，而程序当前的用户栈是不安全的。因此，我们还需要一个预设的安全的栈空间，存放在这里。 - -在内核态中，`sp` 可以认为是一个安全的栈空间，`sscratch` 便不需要保存任何值。此时将其设为 0，可以在遇到中断时通过 `sscratch` 中的值判断中断前程序是否处于内核态。 - -### 与中断相关的指令 - -#### 进入和退出中断 - -- `ecall` -触发中断，进入更高一层的中断处理流程之中。用户态进行系统调用进入内核态中断处理流程，内核态进行 SBI 调用进入机器态中断处理流程，使用的都是这条指令。 - -- `sret` -从内核态返回用户态，同时将 `pc` 的值设置为 `sepc`。（如果需要返回到 `sepc` 后一条指令，就需要在 `sret` 之前修改 `sepc` 的值） - -- `ebreak` -触发一个断点。 - -- `mret` -从机器态返回内核态，同时将 `pc` 的值设置为 `mepc`。 - -#### 操作 CSR - -只有一系列特殊的指令（CSR Instruction）可以读写 CSR。尽管所有模式都可以使用这些指令，用户态只能只读的访问某几个寄存器。 - -为了让操作 CSR 的指令不被干扰，许多 CSR 指令都是结合了读写的原子操作。不过在实验中，我们只用到几个简单的指令。 - -- `csrrw dst, csr, src`（CSR Read Write） -同时读写的原子操作，将指定 CSR 的值写入 `dst`，同时将 `src` 的值写入 CSR。 - -- `csrr dst, csr`（CSR Read） -仅读取一个 CSR 寄存器。 - -- `csrw csr, src`（CSR Write） -仅写入一个 CSR 寄存器。 - -- `csrc(i) csr, rs1`（CSR Clear） -将 CSR 寄存器中指定的位清零，`csrc` 使用通用寄存器作为 mask，`csrci` 则使用立即数。 - -- `csrs(i) csr, rs1`（CSR Set） -将 CSR 寄存器中指定的位置 1，`csrc` 使用通用寄存器作为 mask，`csrci` 则使用立即数。 - -### 了解更多 - -RISC-V 官方文档： - -- CSR 寄存器（Chapter 4，p59） -https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf - -- CSR 指令（Section 2.8，p33） -https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf diff --git a/docs/lab-1/guide/part-3.md b/docs/lab-1/guide/part-3.md deleted file mode 100644 index 41c24ea..0000000 --- a/docs/lab-1/guide/part-3.md +++ /dev/null @@ -1,27 +0,0 @@ -## 程序运行状态 - -对于用户程序而言，中断的处理应当是不留任何痕迹的：只要中断处理改动了一个寄存器，都可能导致原本正在运行的线程出现错误。因此，在处理中断之前，必须要保存所有可能被修改的寄存器，并且在处理完成后恢复。因此，我们需要保存所有通用寄存器，`sepc`、`scause` 和 `stval` 这三个会被硬件自动写入的 CSR 寄存器，以及 `sstatus`。因为中断可能会涉及到权限的切换，以及中断的开关，这些都会修改 `sstatus`。 - -### Context - -我们把在中断时保存了各种寄存器的结构体叫做 `Context`，他表示原来程序正在执行所在的上下文（这个概念在后面线程的部分还会用到），这里我们和 `scause` 以及 `stval` 作为一个区分，后两者将不会放在 `Context` 而仅仅被看做一个临时的变量（在后面会被用到），`Context` 的定义如下： - -{% label %}os/src/interrupt/context.rs{% endlabel %} -```rust -use riscv::register::{sstatus::Sstatus, scause::Scause}; - -#[repr(C)] -pub struct Context { - pub x: [usize; 32], // 32 个通用寄存器 - pub sstatus: Sstatus, - pub sepc: usize -} -``` - -这里我们使用了 rCore 中的库 riscv 封装的一些寄存器操作，需要在 `os/Cargo.toml` 中添加依赖。 - -{% label %}os/Cargo.toml{% endlabel %} -```toml -[dependencies] -riscv = { git = "https://github.com/rcore-os/riscv", features = ["inline-asm"] } -``` \ No newline at end of file diff --git a/docs/lab-1/guide/part-4.md b/docs/lab-1/guide/part-4.md deleted file mode 100644 index 2dcdf04..0000000 --- a/docs/lab-1/guide/part-4.md +++ /dev/null @@ -1,100 +0,0 @@ -## 状态的保存与恢复 - -### 操作流程 - -为了状态的保存与恢复，我们可以先用栈上的一小段空间来把需要保存的全部通用寄存器和 CSR 寄存器保存在栈上，保存完之后在跳转到 Rust 编写的中断处理函数；而对于恢复，则直接把备份在栈上的内容写回寄存器。由于涉及到了寄存器级别的操作，我们需要用汇编来实现。 - -而对于如何保存在栈上，我们可以直接令 `sp` 栈寄存器直接减去相应需要开辟的大小，然后依次放在栈上。需要注意的是，`sp` 寄存器又名 `x2`，我们需要不断用到这个寄存器告诉 CPU 其他寄存器放在哪个地址，所以处理这个 `sp` 寄存器本身的保存时也需要格外小心。 - -### 编写汇编 - -因为汇编代码较长，这里我们新建一个 `os/src/interrupt/interrupt.asm` 文件来编写这段操作： - -{% label %}os/src/interrupt/interrupt.asm{% endlabel %} -```asm -# 我们将会用一个宏来用循环保存寄存器。这是必要的设置 -.altmacro -# 寄存器宽度对应的字节数 -.set REG_SIZE, 8 -# Context 的大小 -.set CONTEXT_SIZE, 34 - -# 宏：将寄存器存到栈上 -.macro SAVE reg, offset - sd \reg, \offset*8(sp) -.endm - -.macro SAVE_N n - SAVE x\n, \n -.endm - - -# 宏：将寄存器从栈中取出 -.macro LOAD reg, offset - ld \reg, \offset*8(sp) -.endm - -.macro LOAD_N n - LOAD x\n, \n -.endm - - .section .text - .globl __interrupt -# 进入中断 -# 保存 Context 并且进入 Rust 中的中断处理函数 interrupt::handler::handle_interrupt() -__interrupt: - # 在栈上开辟 Context 所需的空间 - addi sp, sp, -34*8 - - # 保存通用寄存器，除了 x0（固定为 0） - SAVE x1, 1 - # 将原来的 sp（sp 又名 x2）写入 2 位置 - addi x1, sp, 34*8 - SAVE x1, 2 - # 保存 x3 至 x31 - .set n, 3 - .rept 29 - SAVE_N %n - .set n, n + 1 - .endr - - # 取出 CSR 并保存 - csrr s1, sstatus - csrr s2, sepc - SAVE s1, 32 - SAVE s2, 33 - - # 调用 handle_interrupt，传入参数 - # context: &mut Context - mv a0, sp - # scause: Scause - csrr a1, scause - # stval: usize - csrr a2, stval - jal handle_interrupt - - .globl __restore -# 离开中断 -# 从 Context 中恢复所有寄存器，并跳转至 Context 中 sepc 的位置 -__restore: - # 恢复 CSR - LOAD s1, 32 - LOAD s2, 33 - csrw sstatus, s1 - csrw sepc, s2 - - # 恢复通用寄存器 - LOAD x1, 1 - # 恢复 x3 至 x31 - .set n, 3 - .rept 29 - LOAD_N %n - .set n, n + 1 - .endr - - # 恢复 sp（又名 x2）这里最后恢复是为了上面可以正常使用 LOAD 宏 - LOAD x2, 2 - sret -``` - -这样的话我们就完成了对当前执行现场保存，我们把 `Context` 以及 `scause` 和 `stval` 作为参数传入了 `handle_interrupt` 函数中，这是一个 Rust 编写的函数，后面我们将会实现它。 diff --git a/docs/lab-1/guide/part-5.md b/docs/lab-1/guide/part-5.md deleted file mode 100644 index 6114b6d..0000000 --- a/docs/lab-1/guide/part-5.md +++ /dev/null @@ -1,100 +0,0 @@ -## 进入中断处理流程 - -接下来，我们将要手动触发一个 Trap（`ebreak`），并且进入中断处理流程。 - -### 开启中断 - -为了让硬件能够找到我们编写的 `__interrupt` 入口，在操作系统初始化时，需要将其写入 `stvec` 寄存器中： - -{% label %}os/src/interrupt/handler.rs{% endlabel %} -```rust -use super::context::Context; -use riscv::register::stvec; - -global_asm!(include_str!("./interrupt.asm")); - -/// 初始化中断处理 -/// -/// 把中断入口 `__interrupt` 写入 `stvec` 中，并且开启中断使能 -pub fn init() { - unsafe { - extern "C" { - /// `interrupt.asm` 中的中断入口 - fn __interrupt(); - } - // 使用 Direct 模式，将中断入口设置为 `__interrupt` - stvec::write(__interrupt as usize, stvec::TrapMode::Direct); - } -} -``` - -### 处理中断 - -然后，我们再补上 `__interrupt` 后跳转的中断处理流程 `handle_interrupt()`： - -{% label %}os/src/interrupt/handler.rs{% endlabel %} -```rust -/// 中断的处理入口 -/// -/// `interrupt.asm` 首先保存寄存器至 Context，其作为参数和 scause 以及 stval 一并传入此函数 -/// 具体的中断类型需要根据 scause 来推断，然后分别处理 -#[no_mangle] -pub fn handle_interrupt(context: &mut Context, scause: Scause, stval: usize) { - panic!("Interrupted: {:?}", scause.cause()); -} -``` - -### 触发中断 - -最后，我们把刚刚写的函数封装一下： - -{% label %}os/src/interrupt/mod.rs{% endlabel %} -```rust -//! 中断模块 -//! -//! - -mod handler; -mod context; - -/// 初始化中断相关的子模块 -/// -/// - [`handler::init`] -/// - [`timer::init`] -pub fn init() { - handler::init(); - println!("mod interrupt initialized"); -} -``` - -同时，我们在 main 函数中主动使用 `ebreak` 来触发一个中断。 - -{% label %}os/src/main.rs{% endlabel %} -```rust -... -mod interrupt; -... - -/// Rust 的入口函数 -/// -/// 在 `_start` 为我们进行了一系列准备之后，这是第一个被调用的 Rust 函数 -pub extern "C" fn rust_main() -> ! { - // 初始化各种模块 - interrupt::init(); - - unsafe { - llvm_asm!("ebreak"::::"volatile"); - }; - - unreachable!(); -} -``` - -运行一下，可以看到 `ebreak` 导致程序进入了中断处理并退出，而没有执行到后面的 `unreachable!()`： - -{% label %}运行输出{% endlabel %} -``` -Hello rCore-Tutorial! -mod interrupt initialized -panic: 'Interrupted: Exception(Breakpoint)' -``` \ No newline at end of file diff --git a/docs/lab-1/guide/part-6.md b/docs/lab-1/guide/part-6.md deleted file mode 100644 index 2e06589..0000000 --- a/docs/lab-1/guide/part-6.md +++ /dev/null @@ -1,142 +0,0 @@ -## 时钟中断 - -本章的最后，我们来实现操作系统中极其重要的时钟中断。时钟中断是操作系统能够进行线程调度的基础，操作系统会在每次时钟中断时被唤醒，暂停正在执行的线程，并根据调度算法选择下一个应当运行的线程。 - -> **[info] RISC-V 中断寄存器的细分** -> -> 在[前面](part-2.md#指导硬件处理中断的寄存器)提到，`sie` 和 `sip` 寄存器分别保存不同中断种类的使能和触发记录。例如，软件中断的使能是 `sie` 中的 SSIE 位，触发记录是 `sip` 中的 SSIP 位。 -> -> RISC-V 中将中断分为三种： -> - 软件中断（Software Interrupt），对应 SSIE 和 SSIP -> - 时钟中断（Timer Interrupt），对应 STIE 和 STIP -> - 外部中断（External Interrupt），对应 SEIE 和 SEIP - -### 开启时钟中断 - -时钟中断也需要我们在初始化操作系统时开启，我们同样只需使用 riscv 库中提供的接口即可。 - -{% label %}os/src/interrupt/timer.rs{% endlabel %} -```rust -//! 预约和处理时钟中断 - -use crate::sbi::set_timer; -use riscv::register::{time, sie, sstatus}; - -/// 初始化时钟中断 -/// -/// 开启时钟中断使能，并且预约第一次时钟中断 -pub fn init() { - unsafe { - // 开启 STIE，允许时钟中断 - sie::set_stimer(); - // 开启 SIE（不是 sie 寄存器），允许内核态被中断打断 - sstatus::set_sie(); - } - // 设置下一次时钟中断 - set_next_timeout(); -} -``` - -这里可能引起误解的是 `sstatus::set_sie()`，它的作用是开启 `sstatus` 寄存器中的 SIE 位，与 `sie` 寄存器无关。SIE 位决定中断是否能够打断 supervisor 线程。在这里我们需要允许时钟中断打断 内核态线程，因此置 SIE 位为 1。 -另外，无论 SIE 位为什么值，中断都可以打断用户态的线程。 - -### 设置时钟中断 - -每一次的时钟中断都需要操作系统设置一个下一次中断的时间，这样硬件会在指定的时间发出时钟中断。为简化操作系统实现，操作系统可请求（`sbi_call` 调用 `ecall` 指令）SBI 服务来完成时钟中断的设置。OpenSBI 固件在接到 SBI 服务请求后，会帮助 OS 设置下一次要触发时钟中断的时间，CPU 在执行过程中会检查当前的时间间隔是否已经超过设置的时钟中断时间间隔，如果超时则会触发时钟中断。 -{% label %}os/src/sbi.rs{% endlabel %} -```rust -/// 设置下一次时钟中断的时间 -pub fn set_timer(time: usize) { - sbi_call(SBI_SET_TIMER, time, 0, 0); -} -``` - -为了便于后续处理，我们设置时钟间隔为 100000 个 CPU 周期。越短的间隔可以让 CPU 调度资源更加细致，但同时也会导致更多资源浪费在操作系统上。 - -{% label %}os/src/interrupt/timer.rs{% endlabel %} -```rust -/// 时钟中断的间隔，单位是 CPU 指令 -static INTERVAL: usize = 100000; - -/// 设置下一次时钟中断 -/// -/// 获取当前时间，加上中断间隔，通过 SBI 调用预约下一次中断 -fn set_next_timeout() { - set_timer(time::read() + INTERVAL); -} -``` - -由于没有一个接口来设置固定重复的时间中断间隔，因此我们需要在每一次时钟中断时，设置再下一次的时钟中断。 - -{% label %}os/src/interrupt/timer.rs{% endlabel %} -```rust -/// 触发时钟中断计数 -pub static mut TICKS: usize = 0; - -/// 每一次时钟中断时调用 -/// -/// 设置下一次时钟中断，同时计数 +1 -pub fn tick() { - set_next_timeout(); - unsafe { - TICKS += 1; - if TICKS % 100 == 0 { - println!("{} tick", TICKS); - } - } -} -``` - -### 实现时钟中断的处理流程 - -接下来，我们在 `handle_interrupt()` 根据不同中断种类进行不同的处理流程。 - -{% label %}os/src/interrupt/handler.rs{% endlabel %} -```rust -/// 中断的处理入口 -/// -/// `interrupt.asm` 首先保存寄存器至 Context，其作为参数和 scause 以及 stval 一并传入此函数 -/// 具体的中断类型需要根据 scause 来推断，然后分别处理 -#[no_mangle] -pub fn handle_interrupt(context: &mut Context, scause: Scause, stval: usize) { - // 可以通过 Debug 来查看发生了什么中断 - // println!("{:x?}", context.scause.cause()); - match scause.cause() { - // 断点中断（ebreak） - Trap::Exception(Exception::Breakpoint) => breakpoint(context), - // 时钟中断 - Trap::Interrupt(Interrupt::SupervisorTimer) => supervisor_timer(context), - // 其他情况，终止当前线程 - _ => fault(context, scause, stval), - } -} - -/// 处理 ebreak 断点 -/// -/// 继续执行，其中 `sepc` 增加 2 字节，以跳过当前这条 `ebreak` 指令 -fn breakpoint(context: &mut Context) { - println!("Breakpoint at 0x{:x}", context.sepc); - context.sepc += 2; -} - -/// 处理时钟中断 -/// -/// 目前只会在 [`timer`] 模块中进行计数 -fn supervisor_timer(_: &Context) { - timer::tick(); -} - -/// 出现未能解决的异常 -fn fault(context: &mut Context, scause: Scause, stval: usize) { - panic!( - "Unresolved interrupt: {:?}\n{:x?}\nstval: {:x}", - scause.cause(), - context, - stval - ); -} -``` - -至此，时钟中断就可以正常工作了。我们在 `os/interrupt/mod.rs` 中引入 `mod timer` 并在 初始化 `handler::init()` 语句的后面加入 `timer::init()` 就成功加载了模块。 - -最后我们在 main 函数中去掉 `unreachable!()`，然后观察时钟中断。应当可以看到程序每隔一秒左右进行一次输出 `100 ticks` `200 ticks`…… diff --git a/docs/lab-1/guide/summary.md b/docs/lab-1/guide/summary.md deleted file mode 100644 index 4f91c12..0000000 --- a/docs/lab-1/guide/summary.md +++ /dev/null @@ -1,7 +0,0 @@ -## 小结 - -本章完成了 RISC-V 中有关中断处理的部分，我们实现了中断相关的上下文保存和切换，使得原来正在的运行的程序不需要做任何处理就可以让操作系统处理好中断或异常。我们进一步完成了简单的断点中断和时钟中断，展示了中断处理的执行过程，为后面的章节（包括系统调用的处理）打下了一定的基础。 - -在下一章节中，我们将从物理内存的管理出发，让操作系统真正可以去管理我们的可以使用的内存。 - -截至目前的所有代码在 `lab-1` 分支中。 \ No newline at end of file diff --git a/docs/lab-1/practice.md b/docs/lab-1/practice.md deleted file mode 100644 index 79764e7..0000000 --- a/docs/lab-1/practice.md +++ /dev/null @@ -1,61 +0,0 @@ -## 实验一：中断 - -### 实验之前 - -- 阅读实验指导零和一，最好一步步跟着实现一遍。 -- checkout 到仓库中的 `lab-1` 分支，实验题将以此展开。 - -> 我们的实验题会提供一个基础的代码框架，以便于进行实验。如果你选择参考教程，自己编写操作系统，这个代码框架也可以用来进行对照。 - -### 实验题 - - - -1. 原理：在 `rust_main` 函数中，执行 `ebreak` 命令后至函数结束前，`sp` 寄存器的值是怎样变化的？ - - {% reveal %} -> - `sp` 首先减去一个 `Context` 的大小（入栈），然后原 `sp` 的值被保存到这个入栈的 `Context` 中。 -> -> - 执行 `handle_interrupt` 的过程中，随着局部变量的使用，编译器可能会自动加入一些出入栈操作。但无论如何，`handle_interrupt` 前后 `sp` 的值是一样的。 -> -> - 从 `handle_interrupt` 返回后，执行 `__restore`，在最后将保存的原 `sp` 值恢复。 - {% endreveal %} - -
-2. 分析：如果去掉 `rust_main` 后的 `panic` 会发生什么，为什么？ - - {% reveal %} -> `rust_main` 返回后，程序并没有停止。`rust_main` 是在 `entry.asm` 中通过 `jal` 指令调用的，因此其执行完后会回到 `entry.asm` 中。但是，`entry.asm` 并没有在后面写任何指令，这意味着程序将接着向后执行内存中的任何指令。 -> -> 我们可以通过 `rust-objdump -d -S os/target/riscv64imac-unknown-none-elf/debug/os | less` 来查看汇编代码，其中就能看到：`_start` 只有短短三条指令，而后面则放着许多 Rust 库中的函数。这些指令可能导致程序进入循环，或崩溃退出。 - {% endreveal %} - -
-3. 实验 - 1. 如果程序访问不存在的地址，会得到 `Exception::LoadFault`。模仿捕获 `ebreak` 和时钟中断的方法，捕获 `LoadFault`（之后 `panic` 即可）。 - - {% reveal %} -> 直接在 `match` 中添加一个 arm 即可。例如 `Trap::Exception(Exception::LoadFault) => panic!()` - {% endreveal %} - -
- 2. 在处理异常的过程中，如果程序想要非法访问的地址是 `0x0`，则打印 `SUCCESS!`。 - - {% reveal %} -> 如果程序因无效访问内存造成异常，这个访问的地址会被存放在 `stval` 中，而它已经被我们作为参数传入 `handle_interrupt` 了，因此直接判断即可 - {% endreveal %} - -
- 3. 添加或修改少量代码，使得运行时触发这个异常，并且打印出 `SUCCESS!`。 - - 要求：不允许添加或修改任何 unsafe 代码 - -
- - {% reveal %} -> - 解法 1：在 `interrupt/handler.rs` 的 `breakpoint` 函数中，将 `context.sepc += 2` 修改为 `context.sepc = 0`（则 `sret` 时程序会跳转到 `0x0`） -> - 解法 2：去除 `rust_main` 中的 `panic` 语句，并在 `entry.asm` 的 `jal rust_main` 之后，添加一行读取 `0x0` 地址的指令（例如 `jr x0` 或 `ld x1, (x0)`） - - {% endreveal %} diff --git a/docs/lab-2/guide/intro.md b/docs/lab-2/guide/intro.md deleted file mode 100644 index ce99a1e..0000000 --- a/docs/lab-2/guide/intro.md +++ /dev/null @@ -1,9 +0,0 @@ -# 实验指导二 - -## 实验概要 - -这一章的实验指导中，你将会学到： - -- 实现动态内存的分配 -- 了解 QEMU 模拟的 RISC-V Virt 计算机的物理内存 -- 通过页的方式对物理内存进行管理 \ No newline at end of file diff --git a/docs/lab-2/guide/part-1.md b/docs/lab-2/guide/part-1.md deleted file mode 100644 index c6d496d..0000000 --- a/docs/lab-2/guide/part-1.md +++ /dev/null @@ -1,137 +0,0 @@ -## 动态内存分配 - -我们之前在 C/C++ 语言等中使用过 `malloc/free` 等动态内存分配方法，与在编译期就已完成的静态内存分配相比，动态内存分配可以根据程序运行时状态修改内存申请的时机及大小，显得更为灵活，但是这是需要操作系统的支持的，同时也会带来一些开销。 - -我们的内核中也需要动态内存分配。典型的应用场景有： - -- `Box` ，你可以理解为它和 `malloc` 有着相同的功能； -- 引用计数 `Rc`，原子引用计数 `Arc`，主要用于在引用计数清零，即某对象不再被引用时，对该对象进行自动回收； -- 一些 Rust std 标准库中的数据结构，如 `Vec` 和 `HashMap` 等。 - -我们编写的操作系统不能直接使用 Rust std 标准库提供的动态内存分配功能，因为这些功能需要底层操作系统的支持，这就形成了递归依赖的矛盾了。为了在我们的内核中支持动态内存分配，在 Rust 语言中，我们需要实现 `Trait GlobalAlloc`，将这个类实例化，并使用语义项 `#[global_allocator]` 进行标记。这样的话，编译器就会知道如何使用我们提供的内存分配函数进行动态内存分配。 - -为了实现 `Trait GlobalAlloc`，我们需要支持这么两个函数： - -```rust -unsafe fn alloc(&self, layout: Layout) -> *mut u8; -unsafe fn dealloc(&self, ptr: *mut u8, layout: Layout); -``` - -可见我们要分配/回收一块虚拟内存。 - -那么这里面的 `Layout` 又是什么呢？从文档中可以找到，它有两个字段：`size` 表示要分配的字节数，`align` 则表示分配的虚拟地址的最小对齐要求，即分配的地址要求是 `align` 的倍数。这里的 `align` 必须是 2 的幂次。 - -也就表示，我们的需求是分配一块连续的、大小至少为 `size` 字节的虚拟内存，且对齐要求为 `align` 。 - -### 连续内存分配算法 - -假设我们已经有一整块虚拟内存用来分配，那么如何进行分配呢？ - -我们可能会想到一些简单粗暴的方法，比如对于一个分配任务，贪心地将其分配到可行的最小地址去。这样一直分配下去的话，我们分配出去的内存都是连续的，看上去很合理的利用了内存。 - -但是一旦涉及到回收的话，设想我们在连续分配出去的很多块内存中间突然回收掉一块，它虽然是可用的，但是由于上下两边都已经被分配出去，它就只有这么大而不能再被拓展了，这种可用的内存我们称之为**外碎片**。 - -随着不断回收会产生越来越多的碎片，某个时刻我们可能会发现，需要分配一块较大的内存，几个碎片加起来大小是足够的，但是单个碎片是不够的。我们会想到通过**碎片整理**将几个碎片合并起来。但是这个过程的开销极大。 - -在操作系统课程上，我们了解到还有若干更有效的内存分配算法，包括伙伴系统（Buddy System）和 SLAB 分配器等算法，我们在这里使用 Buddy System 来实现这件事情。 - -### 支持动态内存分配 - -为了避免重复造轮子，我们可以直接开一个静态的 8M 数组作为堆的空间，然后调用 [@jiege](https://github.com/jiegec/) 开发的 Buddy System Allocator。 - -{% label %}os/src/memory/config.rs{% endlabel %} -```rust -/// 操作系统动态分配内存所用的堆大小（8M） -pub const KERNEL_HEAP_SIZE: usize = 0x80_0000; -``` - -{% label %}os/src/memory/heap.rs{% endlabel %} -```rust -/// 进行动态内存分配所用的堆空间 -/// -/// 大小为 [`KERNEL_HEAP_SIZE`] -/// 这段空间编译后会被放在操作系统执行程序的 bss 段 -static mut HEAP_SPACE: [u8; KERNEL_HEAP_SIZE] = [0; KERNEL_HEAP_SIZE]; - -/// 堆，动态内存分配器 -/// -/// ### `#[global_allocator]` -/// [`LockedHeap`] 实现了 [`alloc::alloc::GlobalAlloc`] trait， -/// 可以为全局需要用到堆的地方分配空间。例如 `Box` `Arc` 等 -#[global_allocator] -static HEAP: LockedHeap = LockedHeap::empty(); - -/// 初始化操作系统运行时堆空间 -pub fn init() { - // 告诉分配器使用这一段预留的空间作为堆 - unsafe { - HEAP.lock().init( - HEAP_SPACE.as_ptr() as usize, KERNEL_HEAP_SIZE - ) - } -} - -/// 空间分配错误的回调，直接 panic 退出 -#[alloc_error_handler] -fn alloc_error_handler(_: alloc::alloc::Layout) -> ! { - panic!("alloc error") -} -``` - -同时还有一些模块调用等细节代码，这里不再贴出，请参考完成本章后的仓库中的代码。 - - -{% reveal %} -> 提示： -> -> 1. 在 `os/Cargo.toml` 中添加相关的依赖； -> 2. 在 `os/main.rs` 中添加对 Rust 新特性 `alloc_error_handler` 的引用。 -{% endreveal %} - - -### 动态内存分配测试 - -现在我们来测试一下动态内存分配是否有效，分配一个动态数组： - -{% label %}os/src/main.rs{% endlabel %} -```rust -/// Rust 的入口函数 -/// -/// 在 `_start` 为我们进行了一系列准备之后，这是第一个被调用的 Rust 函数 -#[no_mangle] -pub extern "C" fn rust_main() -> ! { - // 初始化各种模块 - interrupt::init(); - memory::init(); - - // 动态内存分配测试 - use alloc::boxed::Box; - use alloc::vec::Vec; - let v = Box::new(5); - assert_eq!(*v, 5); - core::mem::drop(v); - - let mut vec = Vec::new(); - for i in 0..10000 { - vec.push(i); - } - assert_eq!(vec.len(), 10000); - for (i, value) in vec.into_iter().enumerate() { - assert_eq!(value, i); - } - println!("heap test passed"); - - panic!() -} -``` - -最后，运行一下会看到 `heap test passed` 类似的输出。有了这个工具之后，后面我们就可以使用一系列诸如 `Vec` 等基于动态分配实现的库中的结构了。 - -### 思考 - -动态分配的内存地址在哪个范围里？ - -{% reveal %} -> 在 .bss 段中，因为我们用来存放动态分配的这段是一个静态的没有初始化的数组，算是内核代码的一部分。 -{% endreveal %} - diff --git a/docs/lab-2/guide/part-2.md b/docs/lab-2/guide/part-2.md deleted file mode 100644 index 28537a6..0000000 --- a/docs/lab-2/guide/part-2.md +++ /dev/null @@ -1,89 +0,0 @@ -## 物理内存探测 - -### 物理内存的相关概念 - -我们知道，物理地址访问的通常是一片 DRAM，我们可以把它看成一个以字节为单位的大数组，通过物理地址找到对应的位置进行读写。但是，物理地址并不仅仅只能访问 DRAM，也可以用来访问其他的外设，因此你也可以认为 DRAM 也算是一种外设，物理地址则是一个对可以存储的介质的一种抽象。 - -而如果访问其他外设要使用不同的指令（如 x86 单独提供了 `in` 和 `out` 等指令来访问不同于内存的 IO 地址空间），会比较麻烦；于是，很多指令集架构（如 RISC-V、ARM 和 MIPS 等）通过 MMIO（Memory Mapped I/O）技术将外设映射到一段物理地址，这样我们访问其他外设就和访问物理内存一样了。 - -我们先不管那些外设，来看物理内存。 - -### 物理内存探测 - -操作系统怎样知道物理内存所在的那段物理地址呢？在 RISC-V 中，这个一般是由 bootloader，即 OpenSBI 固件来完成的。它来完成对于包括物理内存在内的各外设的扫描，将扫描结果以 DTB（Device Tree Blob）的格式保存在物理内存中的某个地方。随后 OpenSBI 固件会将其地址保存在 `a1` 寄存器中，给我们使用。 - -这个扫描结果描述了所有外设的信息，当中也包括 QEMU 模拟的 RISC-V Virt 计算机中的物理内存。 - -> **[info] QEMU 模拟的 RISC-V Virt 计算机中的物理内存** -> -> 通过查看 QEMU 代码中 [`hw/riscv/virt.c`](https://github.com/qemu/qemu/blob/master/hw/riscv/virt.c) 的 `virt_memmap[]` 的定义，可以了解到 QEMU 模拟的 RISC-V Virt 计算机的详细物理内存布局。可以看到，整个物理内存中有不少内存空洞（即含义为 unmapped 的地址空间），也有很多外设特定的地址空间，现在我们看不懂没有关系，后面会慢慢涉及到。目前只需关心最后一块含义为 DRAM 的地址空间，这就是 OS 将要管理的 128 MB 的内存空间。 -> -> | 起始地址 | 终止地址 | 含义 | -> | :--------: | :--------: | :---------------------------------------------------- | -> | 0x0 | 0x100 | QEMU VIRT_DEBUG | -> | 0x100 | 0x1000 | unmapped | -> | 0x1000 | 0x12000 | QEMU MROM | -> | 0x12000 | 0x100000 | unmapped | -> | 0x100000 | 0x101000 | QEMU VIRT_TEST | -> | 0x101000 | 0x2000000 | unmapped | -> | 0x2000000 | 0x2010000 | QEMU VIRT_CLINT | -> | 0x2010000 | 0x3000000 | unmapped | -> | 0x3000000 | 0x3010000 | QEMU VIRT_PCIE_PIO | -> | 0x3010000 | 0xc000000 | unmapped | -> | 0xc000000 | 0x10000000 | QEMU VIRT_PLIC | -> | 0x10000000 | 0x10000100 | QEMU VIRT_UART0 | -> | 0x10000100 | 0x10001000 | unmapped | -> | 0x10001000 | 0x10002000 | QEMU VIRT_VIRTIO | -> | 0x10002000 | 0x20000000 | unmapped | -> | 0x20000000 | 0x24000000 | QEMU VIRT_FLASH | -> | 0x24000000 | 0x30000000 | unmapped | -> | 0x30000000 | 0x40000000 | QEMU VIRT_PCIE_ECAM | -> | 0x40000000 | 0x80000000 | QEMU VIRT_PCIE_MMIO | -> | 0x80000000 | 0x88000000 | DRAM 缺省 128MB，大小可配置 | - -不过为了简单起见，我们并不打算自己去解析这个结果。因为我们知道，QEMU 规定的 DRAM 物理内存的起始物理地址为 0x80000000 。而在 QEMU 中，可以使用 `-m` 指定 RAM 的大小，默认是 128 MB 。因此，默认的 DRAM 物理内存地址范围就是 [0x80000000, 0x88000000)。 - -因为后面还会涉及到虚拟地址、物理页和虚拟页面的概念，为了进一步区分而不是简单的只是使用 `usize` 类型来存储，我们首先建立一个 `PhysicalAddress` 的类，然后对其实现一系列的 `usize` 的加、减和输出等等操作，由于这部分实现偏向于 Rust 语法而非 OS，这里不贴出代码，请参考 `os/src/memory/address.rs` 文件。 - -然后，我们直接将 DRAM 物理内存结束地址硬编码到内核中，同时因为我们操作系统本身也用了一部分空间，我们也记录下操作系统用到的地址结尾（即 linker script 中的 `kernel_end`）。 - -{% label %}os/src/memory/config.rs{% endlabel %} -```rust -lazy_static! { - /// 内核代码结束的地址，即可以用来分配的内存起始地址 - /// - /// 因为 Rust 语言限制，我们只能将其作为一个运行时求值的 static 变量，而不能作为 const - pub static ref KERNEL_END_ADDRESS: PhysicalAddress = PhysicalAddress(kernel_end as usize); -} - -extern "C" { - /// 由 `linker.ld` 指定的内核代码结束位置 - /// - /// 作为变量存在 [`KERNEL_END_ADDRESS`] - fn kernel_end(); -} -``` - -这里使用了 `lazy_static` 库，由于 Rust 语言的限制，我们能对编译时 `kernel_end` 做一个求值然后赋值到 `KERNEL_END_ADDRESS` 中；所以，`lazy_static!` 宏帮助我们在第一次使用 `lazy_static!` 宏包裹的变量时自动完成这些求值工作。 - -最后，我们在各级文件中加入模块调用，并在 `os/src/main.rs` 尝试输出。 - -{% label %}os/src/main.rs{% endlabel %} -```rust -/// Rust 的入口函数 -/// -/// 在 `_start` 为我们进行了一系列准备之后，这是第一个被调用的 Rust 函数 -#[no_mangle] -pub extern "C" fn rust_main() -> ! { - // 初始化各种模块 - interrupt::init(); - memory::init(); - - // 注意这里的 KERNEL_END_ADDRESS 为 ref 类型，需要加 * - println!("{}", *memory::config::KERNEL_END_ADDRESS); - - panic!() -} -``` - -最后运行，可以看到成功显示了我们内核使用的结尾地址 `PhysicalAddress(0x8020b220)`；注意到这里，你的输出可能因为实现上的细节并不完全一样。 \ No newline at end of file diff --git a/docs/lab-2/guide/part-3.md b/docs/lab-2/guide/part-3.md deleted file mode 100644 index c5ed37b..0000000 --- a/docs/lab-2/guide/part-3.md +++ /dev/null @@ -1,213 +0,0 @@ -## 物理内存管理 - -### 物理页 - -通常，我们在分配物理内存时并不是以字节为单位，而是以一**物理页（Frame）**，即连续的 4 KB 字节为单位分配。我们希望用物理页号（Physical Page Number，PPN）来代表一物理页，实际上代表物理地址范围在 $$[\text{PPN}\times 4\text{KB},(\text{PPN}+1)\times 4\text{KB})$$ 的一物理页。 - -不难看出，物理页号与物理页形成一一映射。为了能够使用物理页号这种表达方式，每个物理页的开头地址必须是 4 KB 的倍数。但这也给了我们一个方便：对于一个物理地址，其除以 4096（或者说右移 12 位）的商即为这个物理地址所在的物理页号。 - -同样的，我们还是用一个新的结构来封装一下物理页，一是为了和其他类型地址作区分；二是我们可以同时实现一些页帧和地址相互转换的功能。为了后面的方便，我们也把虚拟地址和虚拟页（概念还没有涉及，后面的指导会进一步讲解）一并实现出来，这部分代码请参考 `os/src/memory/address.rs`。 - -同时，我们也需要在 `os/src/memory/config.rs` 中加入相关的设置： - -{% label %}os/src/memory/config.rs{% endlabel %} -```rust -/// 页 / 帧大小，必须是 2^n -pub const PAGE_SIZE: usize = 4096; - -/// 可以访问的内存区域起始地址 -pub const MEMORY_START_ADDRESS: PhysicalAddress = PhysicalAddress(0x8000_0000); -/// 可以访问的内存区域结束地址 -pub const MEMORY_END_ADDRESS: PhysicalAddress = PhysicalAddress(0x8800_0000); -``` - -### 分配和回收 - -为了方便管理所有的物理页，我们需要实现一个分配器可以进行分配和回收的操作，在这之前，我们需要先把物理页的概念进行封装。注意到，物理页实际上是一块连续的内存区域，这里我们只是把内存区域的起始物理地址封装到了一个 `FrameTracker` 里面。 - -{% label %}os/src/memory/frame/frame_tracker.rs{% endlabel %} -```rust -/// 分配出的物理页 -/// -/// # `Tracker` 是什么？ -/// 太长不看 -/// > 可以理解为 [`Box`](alloc::boxed::Box)，而区别在于，其空间不是分配在堆上， -/// > 而是直接在内存中划一片（一个物理页）。 -/// -/// 在我们实现操作系统的过程中，会经常遇到「指定一块内存区域作为某种用处」的情况。 -/// 此时，我们说这块内存可以用，但是因为它不在堆栈上，Rust 编译器并不知道它是什么，所以 -/// 我们需要 unsafe 地将其转换为 `&'static mut T` 的形式（`'static` 一般可以省略）。 -/// -/// 但是，比如我们用一块内存来作为页表，而当这个页表我们不再需要的时候，就应当释放空间。 -/// 我们其实更需要一个像「创建一个有生命期的对象」一样的模式来使用这块内存。因此， -/// 我们不妨用 `Tracker` 类型来封装这样一个 `&'static mut` 引用。 -/// -/// 使用 `Tracker` 其实就很像使用一个 smart pointer。如果需要引用计数， -/// 就在外面再套一层 [`Arc`](alloc::sync::Arc) 就好 -pub struct FrameTracker(pub(super) PhysicalPageNumber); - -impl FrameTracker { - /// 帧的物理地址 - pub fn address(&self) -> PhysicalAddress { - self.0.into() - } - /// 帧的物理页号 - pub fn page_number(&self) -> PhysicalPageNumber { - self.0 - } -} - -/// 帧在释放时会放回 [`static@FRAME_ALLOCATOR`] 的空闲链表中 -impl Drop for FrameTracker { - fn drop(&mut self) { - FRAME_ALLOCATOR.lock().dealloc(self); - } -} -``` - -这里，我们实现了 `FrameTracker` 这个结构，而区分于实际在内存中的 4KB 大小的 "Frame"，我们设计的初衷是分配器分配给我们 `FrameTracker` 作为一个帧的标识，而随着不再需要这个物理页，我们需要回收，我们利用 Rust 的 drop 机制在析构的时候自动实现回收。 - -最后，我们封装一个物理页分配器，为了符合更 Rust 规范的设计，这个分配器将不涉及任何的具体算法，具体的算法将用一个名为 `Allocator` 的 Rust trait 封装起来，而我们的 `FrameAllocator` 会依赖于具体的 trait 实现例化。 - -{% label %}os/src/memory/frame/allocator.rs{% endlabel %} -```rust -lazy_static! { - /// 帧分配器 - pub static ref FRAME_ALLOCATOR: Mutex> = Mutex::new(FrameAllocator::new(Range::from( - PhysicalPageNumber::ceil(PhysicalAddress::from(*KERNEL_END_ADDRESS))..PhysicalPageNumber::floor(MEMORY_END_ADDRESS), - ) - )); -} - -/// 基于线段树的帧分配 / 回收 -pub struct FrameAllocator { - /// 可用区间的起始 - start_ppn: PhysicalPageNumber, - /// 分配器 - allocator: T, -} - -impl FrameAllocator { - /// 创建对象 - pub fn new(range: impl Into> + Copy) -> Self { - FrameAllocator { - start_ppn: range.into().start, - allocator: T::new(range.into().len()), - } - } - - /// 分配帧，如果没有剩余则返回 `Err` - pub fn alloc(&mut self) -> MemoryResult { - self.allocator - .alloc() - .ok_or("no available frame to allocate") - .map(|offset| FrameTracker(self.start_ppn + offset)) - } - - /// 将被释放的帧添加到空闲列表的尾部 - /// - /// 这个函数会在 [`FrameTracker`] 被 drop 时自动调用，不应在其他地方调用 - pub(super) fn dealloc(&mut self, frame: &FrameTracker) { - self.allocator.dealloc(frame.page_number() - self.start_ppn); - } -} - -``` - -这个分配器会以一个 `PhysicalPageNumber` 的 `Range` 初始化，然后把起始地址记录下来，把整个区间的长度告诉具体的分配器算法，当分配的时候就从算法中取得一个可用的位置作为 `offset`，再加上起始地址返回回去。 - -有关具体的算法，我们封装了一个分配器需要的 Rust trait： - -{% label %}os/src/algorithm/src/allocator/mod.rs{% endlabel %} -```rust -/// 分配器：固定容量，每次分配 / 回收一个元素 -pub trait Allocator { - /// 给定容量，创建分配器 - fn new(capacity: usize) -> Self; - /// 分配一个元素，无法分配则返回 `None` - fn alloc(&mut self) -> Option; - /// 回收一个元素 - fn dealloc(&mut self, index: usize); -} -``` - -并在 `os/src/algorithm/src/allocator/` 中分别实现了链表和线段树算法，具体内容可以参考代码。 - -需要注意，我们使用了 `lazy_static!` 和 `Mutex` 来包装分配器，且对于 `static mut` 类型的修改操作是 unsafe 的。对于静态全局数据，所有的线程都能访问。当一个线程正在访问这段数据的时候，如果另一个线程也来访问，就可能会产生冲突，并带来难以预测的结果。我们在后面的章节会进一步介绍线程和 Mutex 等概念。 - -所以我们的方法是使用 `spin::Mutex` 给这段数据加一把锁，一个线程试图通过 `lock()` 打开锁来获取内部数据的可变引用，如果钥匙被别的线程所占用，那么这个线程就会一直卡在这里；直到那个占用了钥匙的线程对内部数据的访问结束，锁被释放，将钥匙交还出来，被卡住的那个线程拿到了钥匙，就可打开锁获取内部引用，访问内部数据。 - -这里使用的是 `spin::Mutex`，我们需要在 `os/Cargo.toml` 中添加依赖。幸运的是，它也无需任何操作系统支持（即支持 `no_std`），我们可以放心使用。 - -最后，我们把新写的模块加载进来，并在 main 函数中进行简单的测试： - -{% label %}os/src/main.rs{% endlabel %} -```rust -/// Rust 的入口函数 -/// -/// 在 `_start` 为我们进行了一系列准备之后，这是第一个被调用的 Rust 函数 -#[no_mangle] -pub extern "C" fn rust_main() -> ! { - // 初始化各种模块 - interrupt::init(); - memory::init(); - - // 物理页分配 - for _ in 0..2 { - let frame_0 = match memory::frame::FRAME_ALLOCATOR.lock().alloc() { - Result::Ok(frame_tracker) => frame_tracker, - Result::Err(err) => panic!("{}", err) - }; - let frame_1 = match memory::frame::FRAME_ALLOCATOR.lock().alloc() { - Result::Ok(frame_tracker) => frame_tracker, - Result::Err(err) => panic!("{}", err) - }; - println!("{} and {}", frame_0.address(), frame_1.address()); - } - - panic!() -} -``` - -可以看到类似这样的输出： - -{% label %}运行输出{% endlabel %} -``` -PhysicalAddress(0x80a14000) and PhysicalAddress(0x80a15000) -PhysicalAddress(0x80a14000) and PhysicalAddress(0x80a15000) -``` - -我们可以看到 `frame_0` 和 `frame_1` 会被自动析构然后回收，第二次又分配同样的地址。 - -### 思考 - -运行下面的代码： - -{% label %}os/src/main.rs{% endlabel %} -```rust -/// Rust 的入口函数 -/// -/// 在 `_start` 为我们进行了一系列准备之后，这是第一个被调用的 Rust 函数 -#[no_mangle] -pub extern "C" fn rust_main() -> ! { - // 初始化各种模块 - interrupt::init(); - memory::init(); - - // 物理页分配 - match memory::frame::FRAME_ALLOCATOR.lock().alloc() { - Result::Ok(frame_tracker) => frame_tracker, - Result::Err(err) => panic!("{}", err) - }; - - panic!() -``` - -思考，和上面的代码有何不同，我们的设计是否存在一些语法上的设计缺陷？ - -{% reveal %} -> 这里的 `frame_tracker` 变量会在 `match` 语法里面析构。但是析构的时候，外层的 `lock()` 函数还没有释放锁，这样写会导致死锁。 -> -{% endreveal %} - - \ No newline at end of file diff --git a/docs/lab-2/guide/summary.md b/docs/lab-2/guide/summary.md deleted file mode 100644 index 5c9eb4c..0000000 --- a/docs/lab-2/guide/summary.md +++ /dev/null @@ -1,7 +0,0 @@ -## 小结 - -本章完成了动态分配内存的管理和物理内存的管理，我们通过划分出一段静态内存为操作系统实现了动态内存的分配；通过页的管理模式，实现了物理页的分配器。 - -本章还只是物理内存的管理，后面为了进一步支持多线程的内存管理，我们将在下一章实现内存的虚拟化。 - -截至目前的所有代码在 `lab-2` 分支中 \ No newline at end of file diff --git a/docs/lab-2/practice.md b/docs/lab-2/practice.md deleted file mode 100644 index 27cd291..0000000 --- a/docs/lab-2/practice.md +++ /dev/null @@ -1,60 +0,0 @@ -## 实验二：内存分配 - -### 实验之前 - -- 阅读实验指导二。 -- checkout 到仓库中的 `lab-2` 分支，实验题将以此展开。 - -### 实验题 - -1. 原理：.bss 字段是什么含义？为什么我们要将动态分配的内存（堆）空间放在 .bss 字段？ - - {% reveal %} -> 对于一个 ELF 程序文件而言，.bss 字段一般包含全局变量的名称和长度，在执行时由操作系统分配空间并初始化为零。 -> -> *不过，在我们执行 `rust-objcopy` 时，不同的字段会相应地被处理而形成一段连续的二进制数据，这段二进制数据会直接写入到 QEMU 所模拟的机器的 `0x80200000` 位置。这是因为我们写的操作系统是直接运行在机器上的，而不是一个被操作系统加载的程序。* -> -> 我们一般遇到应用程序的动态内存分配（堆）是由其操作系统提供的。例如在 C 语言中的 `malloc()`，glibc 运行库会维护一个堆空间，而这个空间是通过 `brk()` 等系统调用向内核索要的。由于我们编写操作系统，自然就无法像这样获取空间。但是此时我们具有随意使用内存空间的权力，因此我们可以在内存中随意划一段空间，然后用相应的算法来实现一个堆。 -> -> 至于为何堆在 .bss 字段，实际上这也不是必须的——我们完全可以随意指定一段可以访问的内存空间。不过，在代码中用全局变量来表示堆并将其放在 .bss 字段，是一个很简单的实现：这样堆空间就包含在内核的二进制数据之中了，而自 `KERNEL_END_ADDRESS` 以后的空间就都可以给进程使用。 - {% endreveal %} - -
-2. 分析：我们在动态内存分配中实现了一个堆，它允许我们在内核代码中使用动态分配的内存，例如 `Vec` `Box` 等。那么，如果我们在实现这个堆的过程中使用 `Vec` 而不是 `[u8]`，会出现什么结果？ - - - 无法编译？ - - - 运行时错误？ - - - 正常运行？ -
- - {% reveal %} -> **都不会！**程序会陷入一个循环：它需要在堆上分配空间，但是分配器又需要在堆上分配空间…… - {% endreveal %} - -
-3. 实验 - 1. 回答：`algorithm/src/allocator` 下有一个 `Allocator` trait，我们之前用它实现了物理页面分配。这个算法的时间和空间复杂度是什么？ - - {% reveal %} -> 时间复杂度是 O(1)，空间复杂度是 O(n) - {% endreveal %} - -
- 2. 二选一：实现基于线段树的物理页面分配算法（不需要考虑合并分配）；或尝试修改 `FrameAllocator`，令其使用未被分配的页面空间（而不是全局变量）来存放页面使用状态。 - -
-4. 挑战实验（选做） - 1. 在 `memory/heap2.rs` 中，提供了一个手动实现堆的方法。它使用 `algorithm::VectorAllocator` 作为其根本分配算法，而我们目前提供了一个非常简单的 bitmap 算法（而且只开了很小的空间）。请在 `algorithm` crate 中利用伙伴算法实现 `VectorAllocator` trait。 - -
- 2. 前面说到，堆的实现本身不能完全使用动态内存分配。但有没有可能让堆能够利用动态分配的空间，这样做会带来什么好处？ - - {% reveal %} -> 我们以一个朴素的分配器算法为例：将每一次内存分配记录用链表存起来。 -> -> 分配器最初必须具有一个节点的静态空间。而每当它仅剩一个节点空间时，都可以用它来为自己分配一块更大的空间。如此，就实现了分配器动态分配自己。 -> -> 再考虑到，每次分配 1KB 或 1MB 都需要额外保存一份元信息。如果只用静态分配，就必须按最坏情况（每次都只分配最小单元）来预先留好空间。使用动态分配就可以减少空间浪费。 - {% endreveal %} diff --git a/docs/lab-3/guide/intro.md b/docs/lab-3/guide/intro.md deleted file mode 100644 index 8103a35..0000000 --- a/docs/lab-3/guide/intro.md +++ /dev/null @@ -1,9 +0,0 @@ -# 实验指导三 - -## 实验概要 - -这一章的实验指导中，你将会学到： - -- 虚拟地址和物理地址的概念和关系 -- 利用页表完成虚拟地址到物理地址的映射 -- 实现内核的重映射 \ No newline at end of file diff --git a/docs/lab-3/guide/part-1.md b/docs/lab-3/guide/part-1.md deleted file mode 100644 index 1502f22..0000000 --- a/docs/lab-3/guide/part-1.md +++ /dev/null @@ -1,106 +0,0 @@ -## 从虚拟内存到物理内存 - -### 虚拟地址和物理地址 - -到目前为止，我们简易的操作系统还只是一个内核在执行，还没有多任务的概念。在现代的操作系统中，为了让其他的程序能方便的运行在操作系统上，需要完成的一个很重要的抽象是「每个程序有自己的地址空间，且地址空间范围是一样的」，这将会减少了上层程序的大量麻烦，否则程序本身要维护自己需要的物理内存，这也会导致极大程度的不安全。 - -这个执行上看到的地址空间，就是虚拟内存。而访问虚拟内存的地址就是**虚拟地址（Virtual Address）**，与之对应的是**物理地址（Physical Address）**。这样的设计会导致上层的应用程序可能会访问同一个值相等的虚拟地址，所以操作系统需要做的就是替这些程序维护这个虚拟地址到物理地址的映射。甚者，为了统一和连贯，内核自己本身访问内存也将会通过虚拟地址。 - -我们可以说这个映射的**维护**是操作系统在做，但是大量频繁的访存不可能全部通过调用操作系统的接口来获取真实的物理地址。所以，这里硬件也会参与，帮我们快速**查询**操作系统维护的映射，而这个机制就是页表。 - -![](../pics/rcore_memory_layout.png) - -如上图所示，这里的图表示了非教学版 rCore 的虚拟地址和物理地址的映射关系。可以看到内核的数据放在了一段高虚拟地址空间，然后会映射到 0x80200000 开始的一段低物理地址空间；而所有的用户程序，将通过操作系统维护的页表映射到不同的物理空间。当然，这只是非教学版 rCore 的设计，在本教程中 kernel layout 和 user layout 会和图有些出入，具体细节可以翻看 linker script。 - -### Sv39 - -![](../pics/sv39_address.png) - -页表的设计和接口会有很多种，这里我们选择 RISC-V 本身硬件支持的 Sv39 模式作为页表的实现。 - -在 Sv39 模式中，定义物理地址有 56 位，而虚拟地址有 64 位。虽然虚拟地址有 64 位，只有低 39 位有效。不过这不是说高 25 位可以随意取值，规定 63-39 位的值必须等于第 38 位的值，否则会认为该虚拟地址不合法，在访问时会产生异常。 - -Sv39 模式同样是基于页的，在物理内存那一节曾经提到**物理页（Frame）**与**物理页号（PPN，Physical Page Number）**。在这里物理页号为 44 位，每个物理页大小为 4KB。同理，我们对于虚拟内存定义**虚拟页（Page）**以及**虚拟页号（VPN, Virtual Page Number)** 。在这里虚拟页号为 27 位，每个虚拟页大小也为 4KB。物理地址和虚拟地址的最后 12 位都表示页内偏移，即表示该地址在所在物理页（虚拟页）上的什么位置。 - -虚拟地址到物理地址的映射以页为单位，也就是说把虚拟地址所在的虚拟页映射到一个物理页，然后再在这个物理页上根据页内偏移找到物理地址，从而完成映射。我们要实现虚拟页到物理页的映射，由于虚拟页与虚拟页号一一对应，物理页帧与物理页号一一对应，本质上我们要实现虚拟页号到物理页号的映射，而这就是页表所做的事情。 - -### 页表项 - -![](../pics/sv39_pte.jpg) - -一个**页表项（PTE，Page Table Entry）**是用来描述一个虚拟页号如何映射到物理页号的。如果一个虚拟页号通过某种手段找到了一个页表项，并通过读取上面的物理页号完成映射，我们称这个虚拟页号通过该页表项完成映射的。 - -我们可以看到 Sv39 模式里面的一个页表项大小为 64 位（即 8 字节）。其中第 53-10 共 44 位为一个物理页号，表示这个虚拟页号映射到的物理页号。后面的第 9-0 位则描述页的相关状态信息。 - -- `V` 表示这个页表项是否合法。如果为 0 表示不合法，此时页表项其他位的值都会被忽略。 - -- `R,W,X` 分别表示是否可读（Readable）、可写（Writable）和可执行（Executable）。 - - - 以 `W` 这一位为例，如果为零表示不可写，那么如果一条 `store` 的指令，它通过这个页表项完成了虚拟页号到物理页号的映射，找到了物理地址。但是仍然会报出异常，是因为这个页表项规定如果物理地址是通过它映射得到的，执行的行为和页表描述的状态并不一致。 - - - 同时，根据 `R,W,X` 取值的不同，我们还有一些特别表示和约定： - - ![](../pics/sv39_rwx.jpg) - - - 也就是说，如果 `R,W,X` 均为 0，文档上说这表示这个页表项指向下一级页表，我们先暂时记住就好。 - -- `U` 为 1 表示用户态运行的程序可以通过该页表项完成地址映射。事实上用户态运行的程序也只能够通过 `U` 为 1 的页表项进行虚实地址映射。 - - - 然而，我们所处在的 S 态也并不是理所当然的可以访问通过这些 `U` 为 1 的页表项进行映射的用户态内存空间。我们需要将 S 态的状态寄存器 `sstatus` 上的 `SUM (permit Supervisor User Memory access)` 位手动设置为 1 才可以做到这一点。否则 S 态通过的 `load/store` 等指令在访问`U` 为 1 的页表项映射的用合同内存空间时，CPU 会报出异常。 - -- `A` 表示 Accessed，如果为 1 则表示自从上次 `A` 被清零后，有虚拟地址通过这个页表项进行读写。 - -- `D` 表示 Dirty，如果为 1 表示自从上次 `D` 被清零后，有虚拟地址通过这个页表项进行写入。 - -- `RSW` 两位留给 S 态的程序来进行拓展功能实现。 - -### 多级页表 - -一个虚拟页号要通过某种手段找到页表项，那么要怎么才能找到呢？ - -想一种最为简单粗暴的方法，在物理内存中开一个大数组作为页表，把所有虚拟页号对应的页表项都存下来。在找的时候根据虚拟页号来索引页表项。即，假设大数组开头的物理地址为 a，虚拟页号为 $$\text{VPN}$$，则该虚拟页号对应的页表项的物理地址为 $$a+\text{VPN}\times8$$（每个页表项 8 字节）。 - -但是这样会花掉我们大量的内存空间。我们目前只有可怜的 128MB 内存，即使我们有足够的内存也不应该这样去浪费。这是由于有很多虚拟地址我们根本没有用到，因此他们对应的虚拟页号不需要映射，我们浪费了很多无用的内存。 - -事实上，在 Sv39 模式中我们采用三级页表，即将 27 位的虚拟页号分为三个等长的部分，第 26-18 位为三级索引 $$\text{VPN}_2$$，第 17-9 位为二级索引 $$\text{VPN}_1$$，第 8-0 位为一级索引 $$\text{VPN}_0$$。 - -我们也将页表分为三级页表，二级页表，一级页表。每个页表都用 9 位索引的，因此有 $$2^{9}=512$$ 个页表项，而每个页表项都是 8 字节，因此每个页表大小都为 $$512\times 8=4\text{KB}$$。正好是一个物理页的大小。我们可以把一个页表放到一个物理页中，并用一个物理页号来描述它。事实上，三级页表的每个页表项中的物理页号可描述一个二级页表；二级页表的每个页表项中的物理页号可描述一个一级页表；一级页表中的页表项内容则和我们刚才提到的页表项一样，其内容包含物理页号，即描述一个要映射到的物理页。 - -具体来说，假设我们有虚拟地址 $$(\text{VPN}_2, \text{VPN}_1, \text{VPN}_0, \text{offset})$$： - -- 我们首先会记录装载「当前所用的三级页表的物理页」的页号到 `satp` 寄存器中； -- 把 $$\text{VPN}_2$$ 作为偏移在三级页表的物理页中找到第二级页表的物理页号； -- 把 $$\text{VPN}_1$$ 作为偏移在二级页表的物理页中找到第一级页表的物理页号； -- 把 $$\text{VPN}_0$$ 作为偏移在一级页表的物理页中找到要访问位置的物理页号； -- 物理页号对应的物理页基址加上 $$\text{offset}$$ 就是虚拟地址对应的物理地址。 - -上述流程也可以用下图表（来源于 MIT 6.828 课程）示： -![](../pics/sv39_pagetable.jpg) - -我们通过这种复杂的手段，终于从虚拟页号找到了一级页表项，从而得出了物理页号。刚才我们提到若页表项满足 `R,W,X` 都为 0，表明这个页表项指向下一级页表。在这里三级和二级页表项的 `R,W,X` 为 0 应该成立，因为它们指向了下一级页表。 - -然而三级和二级页表项不一定要指向下一级页表。我们知道每个一级页表项控制一个虚拟页号，即控制 4KB 虚拟内存；每个二级页表项则控制 9 位虚拟页号，总计控制 $$4\text{KB}\times 2^9=2\text{MB}$$ 虚拟内存；每个三级页表项控制 18 位虚拟页号，总计控制 $$2\text{MB}\times 2^9=1\text{GB}$$ 虚拟内存。我们可以将二级页表项的 `R,W,X` 设置为不是全 0 的，那么它将与一级页表项类似，只不过可以映射一个 2MB 的**大页（Huge Page）**。同理，也可以将三级页表项看作一个叶子，来映射一个 1GB 的大页。这样在 RISC-V 中，可以很方便地建立起大页机制。 - -### 页表基址 - -页表的基址（起始地址）一般会保存在一个特殊的寄存器中。在 RISC-V 中，这个特殊的寄存器就是页表寄存器 satp。 - -![](../pics/sv39_satp.jpg) - -我们使用寄存器 `satp` 来控制 CPU 进行页表映射。 - -- `MODE` 控制 CPU 使用哪种页表实现，我们只需将 `MODE` 设置为 8 即表示 CPU 使用 Sv39 。 -- `ASID` 表示地址空间标识符，这里还没有涉及到进程的概念，我们不需要管这个地方。 -- `PPN` 存的是三级页表所在的物理页号。这样，给定一个虚拟页号，CPU 就可以从三级页表开始一步步的将其映射到一个物理页号。 - -于是，OS 可以在内存中为不同的应用分别建立不同虚实映射的页表，并通过修改寄存器 `satp` 的值指向不同的页表，从而可以修改 CPU 虚实地址映射关系及内存保护的行为。 - -### 快表（TLB） - -我们知道，物理内存的访问速度要比 CPU 的运行速度慢很多。如果我们按照页表机制循规蹈矩的一步步走，将一个虚拟地址转化为物理地址需要访问 3 次物理内存，得到物理地址后还需要再访问一次物理内存，才能完成访存。这无疑很大程度上降低了效率。 - -事实上，实践表明虚拟地址的访问具有时间局部性和空间局部性。因此，在 CPU 内部，我们使用**快表（TLB, Translation Lookaside Buffer）**来作为虚拟页号到物理页号的映射的缓存。这部分知识在计算机组成原理课程中有所体现，当我们要做一个映射时，会有很大可能这个映射在近期被完成过，所以我们可以先到 TLB 里面去查一下，如果有的话我们就可以直接完成映射，而不用访问那么多次内存了。 - -但如果修改了 `satp` 寄存器，说明 OS 切换到了一个与先前映射方式完全不同的页表。此时快表里面存储的映射已经失效了，这种情况下 OS 要在修改 `satp` 的指令后面马上使用 `sfence.vma` 指令刷新整个 TLB。 - -同样，我们手动修改一个页表项之后，也修改了映射，但 TLB 并不会自动刷新，我们也需要使用 `sfence.vma` 指令刷新 TLB。如果不加参数的，`sfence.vma` 会刷新整个 TLB。你可以在后面加上一个虚拟地址，这样 `sfence.vma` 只会刷新这个虚拟地址的映射。 diff --git a/docs/lab-3/guide/part-2.md b/docs/lab-3/guide/part-2.md deleted file mode 100644 index 0afb0c2..0000000 --- a/docs/lab-3/guide/part-2.md +++ /dev/null @@ -1,186 +0,0 @@ -## 修改内核 - -之前的内核实现并未使能页表机制，实际上内核是直接在物理地址空间上运行的。这样虽然比较简单，但是为了后续能够支持多个用户进程能够在内核中并发运行，满足隔离等性质，我们要先运用学过的页表知识，把内核的运行环境从物理地址空间转移到虚拟地址空间，为之后的功能打好铺垫。 - -更具体的，我们现在想将内核代码放在虚拟地址空间中以 0xffffffff80200000 开头的一段高地址空间中。这意味着原来放在 0x80200000 起始地址的全部内核结构被平移到了 0xffffffff80200000 的地址上，即映射关系为：虚拟地址减去偏移量 0xffffffff00000000 为原来的物理地址。当然，这种线性平移并不是唯一的映射方式，但是至少现在，内核的全部代码和数据所在的虚拟空间和物理空间是这样的线性映射。 - -所以需要把原来的 linker script 和之前在物理内存管理上的一些参数修改一下。 - -{% label %}os/src/linker.ld{% endlabel %} -```clike -/* Linker Script 语法可以参见：http://www.scoberlin.de/content/media/http/informatik/gcc_docs/ld_3.html */ - -/* 目标架构 */ -OUTPUT_ARCH(riscv) - -/* 执行入口 */ -ENTRY(_start) - -/* 数据存放起始地址 */ -BASE_ADDRESS = 0xffffffff80200000; /* 修改为虚拟地址 */ - -SECTIONS -{ - /* . 表示当前地址（location counter） */ - . = BASE_ADDRESS; - - /* start 符号表示全部的开始位置 */ - kernel_start = .; - - /* 加入对齐 */ - . = ALIGN(4K); - text_start = .; - - /* .text 字段 */ - .text : { - /* 把 entry 函数放在最前面 */ - *(.text.entry) - /* 要链接的文件的 .text 字段集中放在这里 */ - *(.text .text.*) - } - - /* 加入对齐 */ - . = ALIGN(4K); - rodata_start = .; - - /* .rodata 字段 */ - .rodata : { - /* 要链接的文件的 .rodata 字段集中放在这里 */ - *(.rodata .rodata.*) - } - - /* 加入对齐 */ - . = ALIGN(4K); - data_start = .; - - /* .data 字段 */ - .data : { - /* 要链接的文件的 .data 字段集中放在这里 */ - *(.data .data.*) - } - - /* 加入对齐 */ - . = ALIGN(4K); - bss_start = .; - - /* .bss 字段 */ - .bss : { - /* 要链接的文件的 .bss 字段集中放在这里 */ - *(.sbss .bss .bss.*) - } - - /* 结束地址 */ - /* 加入对齐 */ - . = ALIGN(4K); - kernel_end = .; -} -``` - -首先，对于 linker script，我们把放置的基地址修改为了虚拟地址，另外还有一些修改是我们把每个数据段都对齐到了 4KB，一个 4KB 的虚拟页中不会包含两个段，这意味着这个页的属性是可以确定的。举个例子，如果不对齐的话，只读的 .rodata 和 .data 段可能放在一个页中，但是页表中需要写上诸如是否可写的属性，这时候就必须分开才可以标注属性。 - -对应修改 `os/src/memory/config.rs` 中的 `KERNEL_END_ADDRESS` 修改为虚拟地址并加入偏移量： - -{% label %}os/src/memory/config.rs{% endlabel %} -```rust -lazy_static! { - /// 内核代码结束的地址，即可以用来分配的内存起始地址 - /// - /// 因为 Rust 语言限制，我们只能将其作为一个运行时求值的 static 变量，而不能作为 const - pub static ref KERNEL_END_ADDRESS: VirtualAddress = VirtualAddress(kernel_end as usize); -} - -/// 内核使用线性映射的偏移量 -pub const KERNEL_MAP_OFFSET: usize = 0xffff_ffff_0000_0000; -``` - -和上一章类似，我们也对虚拟地址和虚拟页号这两个类进行了封装，同时也支持了一些诸如 `VirtualAddress::from(PhysicalAddress)` 的转换 trait（即一些加减偏移量等操作），这部分实现更偏向于 Rust 语法，这里不再赘述实现方法，想去了解实现时可以参考 `os/src/memory/address.rs`。 - -最后一步，我们需要告诉 RISC-V CPU 我们做了这些修改，也就是需要在启动时、在进入 `rust_main` 之前我们要完成一个从物理地址访存模式到虚拟访存模式的转换，同时这也意味着，我们要写一个简单的页表，完成这个线性映射： - -{% label %}os/src/entry.asm{% endlabel %} -```assembly -# 操作系统启动时所需的指令以及字段 -# -# 我们在 linker.ld 中将程序入口设置为了 _start，因此在这里我们将填充这个标签 -# 它将会执行一些必要操作，然后跳转至我们用 rust 编写的入口函数 -# -# 关于 RISC-V 下的汇编语言，可以参考 https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md -# %hi 表示取 [12,32) 位，%lo 表示取 [0,12) 位 - - .section .text.entry - .globl _start -# 目前 _start 的功能：将预留的栈空间写入 $sp，然后跳转至 rust_main -_start: - # 计算 boot_page_table 的物理页号 - lui t0, %hi(boot_page_table) - li t1, 0xffffffff00000000 - sub t0, t0, t1 - srli t0, t0, 12 - # 8 << 60 是 satp 中使用 Sv39 模式的记号 - li t1, (8 << 60) - or t0, t0, t1 - # 写入 satp 并更新 TLB - csrw satp, t0 - sfence.vma - - # 加载栈地址 - lui sp, %hi(boot_stack_top) - addi sp, sp, %lo(boot_stack_top) - # 跳转至 rust_main - lui t0, %hi(rust_main) - addi t0, t0, %lo(rust_main) - jr t0 - - # 回忆：bss 段是 ELF 文件中只记录长度，而全部初始化为 0 的一段内存空间 - # 这里声明字段 .bss.stack 作为操作系统启动时的栈 - .section .bss.stack - .global boot_stack -boot_stack: - # 16K 启动栈大小 - .space 4096 * 16 - .global boot_stack_top -boot_stack_top: - # 栈结尾 - - # 初始内核映射所用的页表 - .section .data - .align 12 -boot_page_table: - .quad 0 - .quad 0 - # 第 2 项：0x8000_0000 -> 0x8000_0000，0xcf 表示 VRWXAD 均为 1 - .quad (0x80000 << 10) | 0xcf - .zero 507 * 8 - # 第 510 项：0xffff_ffff_8000_0000 -> 0x8000_0000，0xcf 表示 VRWXAD 均为 1 - .quad (0x80000 << 10) | 0xcf - .quad 0 -``` - -回顾一下，当 OpenSBI 启动完成之后，我们面对的是一个怎样的局面： -- 物理内存状态中 OpenSBI 代码放在 [0x80000000,0x80200000) 中，内核代码放在以 0x80200000 开头的一块连续物理内存中； -- CPU 状态：处于 S Mode ，寄存器 `satp` 的 `MODE` 字段被设置为 Bare 模式，即无论取指还是访存我们通过物理地址直接访问物理内存。PC 即为 0x80200000 指向内核的第一条指令； -- 栈指针寄存器 `sp` 还没有初始化，还没有指向 `boot_stack_top`； -- 代码中 `boot_stack_top` 等符号的地址都是虚拟地址（高地址）。 - -而我们需要做的就是，把 CPU 的访问模式改为 Sv39，这里需要做的就是把一个页表的物理页号和 Sv39 模式写入 `satp` 寄存器，然后刷新 TLB。 - -我们先使用一种最简单的页表构造方法，还记得上一节中所讲的大页吗？那时我们提到，将一个三级页表项的标志位 `R,W,X` 不设为全 0，可以将它变为表示 1GB 的一个大页。 - -那么，页表里面需要放什么数据呢？第二个 `.quad` （表中第 510 项，510 的二进制是要索引虚拟地址的 $$VPN_3$$）显然是从 0xffffffff80000000 到 0x80000000 这样的线性映射，同时 `0xcf` 表示了 `VRWXAD` 均为 1 的属性。 - -观察一下，除了上面这个映射，我们的 `boot_page_table` 里面为什么还有一个从 0x80000000 到 0x80000000 的映射？ - -{% reveal %} -> 这是因为，在跳转到 `rust_main` 之前（即 `jr t0`）之前，PC 的值都还是 0x802xxxxx 这样的地址，即使是写入了 `satp` 寄存器，但是 PC 的地址不会变。为了执行这段中间的尴尬的代码，我们在页表里面也需要加入这段代码的地址的映射。 -> -> 那为什么跳转之后就没有问题了呢？这是因为 `rust_main` 这个符号本身是高虚拟地址（这点在 linker script 里面已经体现了）。 -> -> 为什么我把这个映射删了，代码还是可以运行？因为 QEMU 有指令缓存，实际上这样的删去的写法是错误的。 -> -> 这个尴尬的映射会对后面产生错误的影响吗？不会，因为在后面，我们将使用 Rust 而不是汇编把新的页表加载到 `satp` 里面，这个页表只是启动时的一个简单页表，或者我们可以叫它“内核初始映射”，后面我们会加入更细致的映射，把不同的段根据属性放在不同的页面里面。 -> -{% endreveal %} - -
- -刷新之后，我们加载完栈地址，就可以跳转到 Rust 编写的函数中了。至此，我可以在主函数中做些简单的输出，我们重新编译（cargo 不会感知 linker script 的变化，可能需要 `cargo clean`）并运行，正确的结果应该是我们可以看到这些输出，虽然这和上一个章节的结果看上去没什么两样，但是现在内核的运行已经在虚拟地址空间了。 \ No newline at end of file diff --git a/docs/lab-3/guide/part-3.md b/docs/lab-3/guide/part-3.md deleted file mode 100644 index d18f6d7..0000000 --- a/docs/lab-3/guide/part-3.md +++ /dev/null @@ -1,169 +0,0 @@ -## 实现页表 - -为了实现 Sv39 页表，我们的思路是把一个分配好的物理页（即会自动销毁的 `FrameTracker`）拿来把数据填充作为页表，而页表中的每一项是一个 8 字节的页表项。 - -对于页表项的位级别的操作，首先需要加入两个关于位操作的 crate： - -{% label %}os/Cargo.toml{% endlabel %} -```toml -bitflags = "1.2.1" -bit_field = "0.10.0" -``` - -然后，首先了构建了通过虚拟页号获得三级 VPN 的函数： -{% label %}os/src/memory/address.rs{% endlabel %} -```rust -impl VirtualPageNumber { - /// 得到一、二、三级页号 - pub fn levels(self) -> [usize; 3] { - [ - self.0.get_bits(18..27), - self.0.get_bits(9..18), - self.0.get_bits(0..9), - ] - } -} -``` - -### 页表项 - -后面，我们来实现页表项，其实就是对一个 `usize`（8 字节）的封装，同时我们可以用刚刚加入的 bit 级别操作的 crate 对其实现一些取出特定段的方便后续实现的函数： - -{% label %}os/src/memory/mapping/page_table_entry.rs{% endlabel %} -```rust -/// Sv39 结构的页表项 -#[derive(Copy, Clone, Default)] -pub struct PageTableEntry(usize); - -/// Sv39 页表项中标志位的位置 -const FLAG_RANGE: core::ops::Range = 0..8; -/// Sv39 页表项中物理页号的位置 -const PAGE_NUMBER_RANGE: core::ops::Range = 10..54; - -impl PageTableEntry { - /// 将相应页号和标志写入一个页表项 - pub fn new(page_number: Option, mut flags: Flags) -> Self { - // 标志位中是否包含 Valid 取决于 page_number 是否为 Some - flags.set(Flags::VALID, page_number.is_some()); - Self( - *0usize - .set_bits(FLAG_RANGE, flags.bits() as usize) - .set_bits(PAGE_NUMBER_RANGE, page_number.unwrap_or_default().into()), - ) - } - /// 设置物理页号，同时根据 ppn 是否为 Some 来设置 Valid 位 - pub fn update_page_number(&mut self, ppn: Option) { - if let Some(ppn) = ppn { - self.0 - .set_bits(FLAG_RANGE, (self.flags() | Flags::VALID).bits() as usize) - .set_bits(PAGE_NUMBER_RANGE, ppn.into()); - } else { - self.0 - .set_bits(FLAG_RANGE, (self.flags() - Flags::VALID).bits() as usize) - .set_bits(PAGE_NUMBER_RANGE, 0); - } - } - /// 获取页号 - pub fn page_number(&self) -> PhysicalPageNumber { - PhysicalPageNumber::from(self.0.get_bits(10..54)) - } - /// 获取地址 - pub fn address(&self) -> PhysicalAddress { - PhysicalAddress::from(self.page_number()) - } - /// 获取标志位 - pub fn flags(&self) -> Flags { - unsafe { Flags::from_bits_unchecked(self.0.get_bits(..8) as u8) } - } - /// 是否为空（可能非空也非 Valid） - pub fn is_empty(&self) -> bool { - self.0 == 0 - } -} - -impl core::fmt::Debug for PageTableEntry { - fn fmt(&self, formatter: &mut core::fmt::Formatter) -> core::fmt::Result { - formatter - .debug_struct("PageTableEntry") - .field("value", &self.0) - .field("page_number", &self.page_number()) - .field("flags", &self.flags()) - .finish() - } -} - -bitflags! { - /// 页表项中的 8 个标志位 - #[derive(Default)] - pub struct Flags: u8 { - /// 有效位 - const VALID = 1 << 0; - /// 可读位 - const READABLE = 1 << 1; - /// 可写位 - const WRITABLE = 1 << 2; - /// 可执行位 - const EXECUTABLE = 1 << 3; - /// 用户位 - const USER = 1 << 4; - /// 全局位，我们不会使用 - const GLOBAL = 1 << 5; - /// 已使用位，用于替换算法 - const ACCESSED = 1 << 6; - /// 已修改位，用于替换算法 - const DIRTY = 1 << 7; - } -} -``` - -### 页表 - -有了页表项，512 个连续的页表项组成的 4KB 物理页，同时再加上一些诸如多级添加映射的功能，就可以封装为页表。 - -{% label %}os/src/memory/mapping/page_table.rs{% endlabel %} -```rust -/// 存有 512 个页表项的页表 -/// -/// 注意我们不会使用常规的 Rust 语法来创建 `PageTable`。相反，我们会分配一个物理页， -/// 其对应了一段物理内存，然后直接把其当做页表进行读写。我们会在操作系统中用一个「指针」 -/// [`PageTableTracker`] 来记录这个页表。 -#[repr(C)] -pub struct PageTable { - pub entries: [PageTableEntry; PAGE_SIZE / 8], -} - -impl PageTable { - /// 将页表清零 - pub fn zero_init(&mut self) { - self.entries = [Default::default(); PAGE_SIZE / 8]; - } -} -``` - -然而，我们不会把这个巨大的数组在函数之间不停传递，我们这里的思路也同样更多利用 Rust 的特性，所以做法是利用一个 `PageTableTracker` 的结构对 `FrameTracker` 封装，但是里面的行为是对 `FrameTracker` 记录的物理页当成 `PageTable` 进行操作。同时，这个 `PageTableTracker` 和 `PageTableEntry` 也通过一些 Rust 中的自动解引用的特性为后面的实现铺平了道路，比如我们可以直接把 `PageTableTracker` 当成 `PageTable` 对待，同时，如果一个 `PageTableEntry` 指向的是另一个 `PageTable` 我们可以直接方便的让编译器自动完成这些工作。 - -{% label %}os/src/memory/mapping/page_table.rs{% endlabel %} -```rust -/// 类似于 [`FrameTracker`]，用于记录某一个内存中页表 -/// -/// 注意到，「真正的页表」会放在我们分配出来的物理页当中，而不应放在操作系统的运行栈或堆中。 -/// 而 `PageTableTracker` 会保存在某个线程的元数据中（也就是在操作系统的堆上），指向其真正的页表。 -/// -/// 当 `PageTableTracker` 被 drop 时，会自动 drop `FrameTracker`，进而释放帧。 -pub struct PageTableTracker(pub FrameTracker); - -impl PageTableTracker { - /// 将一个分配的帧清零，形成空的页表 - pub fn new(frame: FrameTracker) -> Self { - let mut page_table = Self(frame); - page_table.zero_init(); - page_table - } - /// 获取物理页号 - pub fn page_number(&self) -> PhysicalPageNumber { - self.0.page_number() - } -} -``` - -至此，我们完成了物理页中的页表。后面，我们将把内核中各个段做一个更精细的映射，把之前的那个粗糙的初始映射页表替换掉。 \ No newline at end of file diff --git a/docs/lab-3/guide/part-4.md b/docs/lab-3/guide/part-4.md deleted file mode 100644 index b689d3d..0000000 --- a/docs/lab-3/guide/part-4.md +++ /dev/null @@ -1,340 +0,0 @@ -## 实现内核重映射 - -在上文中，我们虽然构造了一个简单映射使得内核能够运行在虚拟空间上，但是这个映射是比较粗糙的。 - -我们知道一个程序通常含有下面几段： - -- .text 段：存放代码，需要可读、可执行的，但不可写； -- .rodata 段：存放只读数据，顾名思义，需要可读，但不可写亦不可执行； -- .data 段：存放经过初始化的数据，需要可读、可写； -- .bss 段：存放零初始化的数据，需要可读、可写。 - -我们看到各个段之间的访问权限是不同的。在现在的映射下，我们甚至可以修改内核 .text 段的代码。因为我们通过一个标志位 `W` 为 1 的页表项完成映射。 - -因此，我们考虑对这些段分别进行重映射，使得他们的访问权限被正确设置。 - -这个需求可以抽象为一段内存（可能是很多个虚拟页）通过一个方式映射到很多个物理页上，同时这个内存段将会有一个统一的属性和进一步高层次的管理。 - -举个例子，在内核的代码段中 .bss 段可能不止会占用一个页面，而是很多页面，我们需要把全部的这些页面以线性的形式映射到一个位置。同时整个这些页面构成的内存段将会有统一的属性交由内核来管理。 - -下面，我们首先来封装内存段的概念。 - -### 内存段 Segment - -正如上面说的，内存段是一篇连续的虚拟页范围，其中的每一页通过线性映射（直接偏移到一个物理页）或者分配（其中的每个虚拟页调用物理页分配器分配一个物理页）。线性映射出现在内核空间中；而为了支持每个用户进程看到的虚拟空间是一样的，我们不能全都用线性映射，所以基于页分配的方式会出现在用户这种情景下。如果你还是不明白，可以去翻看一下本章的「虚拟地址到物理地址」一个小节中非教学版 rCore 的映射图。 - -下面，我们用 enum 和 struct 来封装内存段映射的类型和内存段本身： - -{% label %}os/src/memory/mapping/segment.rs{% endlabel %} -```rust -/// 映射的类型 -#[derive(Debug)] -pub enum MapType { - /// 线性映射，操作系统使用 - Linear, - /// 按帧分配映射 - Framed, -} - -/// 一个映射片段（对应旧 tutorial 的 `MemoryArea`） -#[derive(Copy, Clone, Debug, Eq, PartialEq)] -pub struct Segment { - /// 映射类型 - pub map_type: MapType, - /// 所映射的虚拟地址 - pub range: Range, - /// 权限标志 - pub flags: Flags, -} -``` - -后面，上层需要做的是把一个 Segment 中没有建立物理页映射关系的全部虚拟页，都申请到物理页并建立映射关系（或者说线性映射没有这样的虚拟页，而分配映射需要把每个虚拟页都申请一个对应的物理页）。 - -于是我们可以实现这样一个需要具体分配的迭代器： - -{% label %}os/src/memory/mapping/segment.rs{% endlabel %} -```rust -impl Segment { - /// 遍历对应的物理地址（如果可能） - pub fn iter_mapped(&self) -> Option> { - match self.map_type { - // 线性映射可以直接将虚拟地址转换 - MapType::Linear => Some(self.page_range().into().iter()), - // 按帧映射无法直接获得物理地址，需要分配 - MapType::Framed => None, - } - } -} -``` - -### Mapping - -有了页表、内存段，我们对这两个进行组合和封装，借助其中对页表的操作实现对内存段的映射，或者也可以说这里的结构是对上一小节的页表的进一步的从单级到三级的封装，需要记录根页表和对其中申请的页表进行追踪来控制何时释放空间。 - -{% label %}os/src/memory/mapping/mapping.rs{% endlabel %} -```rust -#[derive(Default)] -/// 某个线程的内存映射关系 -pub struct Mapping { - /// 保存所有使用到的页表 - page_tables: Vec, - /// 根页表的物理页号 - root_ppn: PhysicalPageNumber, - /// 所有分配的物理页面映射信息 - mapped_pairs: VecDeque<(VirtualPageNumber, FrameTracker)>, -} - -impl Mapping { - /// 创建一个有根节点的映射 - pub fn new() -> MemoryResult { - let root_table = PageTableTracker::new(FRAME_ALLOCATOR.lock().alloc()?); - let root_ppn = root_table.page_number(); - Ok(Mapping { - page_tables: vec![root_table], - root_ppn, - mapped_pairs: VecDeque::new(), - }) - } -} -``` - -后面，实现对页表的查找，并利用该函数实现对虚拟页号到物理页号的映射： - -{% label %}os/src/memory/mapping/mapping.rs: impl Mapping{% endlabel %} -```rust -/// 找到给定虚拟页号的三级页表项 -/// -/// 如果找不到对应的页表项，则会相应创建页表 -pub fn find_entry(&mut self, vpn: VirtualPageNumber) -> MemoryResult<&mut PageTableEntry> { - // 从根页表开始向下查询 - // 这里不用 self.page_tables[0] 避免后面产生 borrow-check 冲突（我太菜了） - let root_table: &mut PageTable = PhysicalAddress::from(self.root_ppn).deref_kernel(); - let mut entry = &mut root_table.entries[vpn.levels()[0]]; - for vpn_slice in &vpn.levels()[1..] { - if entry.is_empty() { - // 如果页表不存在，则需要分配一个新的页表 - let new_table = PageTableTracker::new(FRAME_ALLOCATOR.lock().alloc()?); - let new_ppn = new_table.page_number(); - // 将新页表的页号写入当前的页表项 - *entry = PageTableEntry::new(Some(new_ppn), Flags::VALID); - // 保存页表 - self.page_tables.push(new_table); - } - // 进入下一级页表（使用偏移量来访问物理地址） - entry = &mut entry.get_next_table().entries[*vpn_slice]; - } - // 此时 entry 位于第三级页表 - Ok(entry) -} - -/// 为给定的虚拟 / 物理页号建立映射关系 -fn map_one( - &mut self, - vpn: VirtualPageNumber, - ppn: Option, - flags: Flags, -) -> MemoryResult<()> { - // 定位到页表项 - let entry = self.find_entry(vpn)?; - assert!(entry.is_empty(), "virtual address is already mapped"); - // 页表项为空，则写入内容 - *entry = PageTableEntry::new(ppn, flags); - Ok(()) -} -``` - -有了 `map_one` 来实现一个虚拟页对物理页的映射，我们就可以实现对一个连续的 Segment 的映射： - -{% label %}os/src/memory/mapping/mapping.rs: impl Mapping{% endlabel %} -```rust -/// 加入一段映射，可能会相应地分配物理页面 -/// -/// 未被分配物理页面的虚拟页号暂时不会写入页表当中，它们会在发生 PageFault 后再建立页表项。 -pub fn map(&mut self, segment: &Segment, init_data: Option<&[u8]>) -> MemoryResult<()> { - match segment.map_type { - // 线性映射，直接对虚拟地址进行转换 - MapType::Linear => { - for vpn in segment.page_range().iter() { - self.map_one(vpn, Some(vpn.into()), segment.flags)?; - } - // 拷贝数据 - if let Some(data) = init_data { - unsafe { - (&mut *slice_from_raw_parts_mut(segment.range.start.deref(), data.len())) - .copy_from_slice(data); - } - } - } - // 需要分配帧进行映射 - MapType::Framed => { - for vpn in segment.page_range().iter() { - // 页面的数据，默认为全零 - let mut page_data = [0u8; PAGE_SIZE]; - // 如果提供了数据，则使用这些数据来填充 page_data - if let Some(init_data) = init_data { - if !init_data.is_empty() { - // 这里必须进行一些调整，因为传入的数据可能并非按照整页对齐 - - // 拷贝时必须考虑区间与整页不对齐的情况 - // start（仅第一页时非零） - // | stop（仅最后一页时非零） - // 0 |---data---| 4096 - // |------------page------------| - let page_address = VirtualAddress::from(vpn); - let start = if segment.range.start > page_address { - segment.range.start - page_address - } else { - 0 - }; - let stop = min(PAGE_SIZE, segment.range.end - page_address); - // 计算来源和目标区间并进行拷贝 - let dst_slice = &mut page_data[start..stop]; - let src_slice = &init_data[(page_address + start - segment.range.start) - ..(page_address + stop - segment.range.start)]; - dst_slice.copy_from_slice(src_slice); - } - }; - - // 建立映射 - let mut frame = FRAME_ALLOCATOR.lock().alloc()?; - // 更新页表 - self.map_one(vpn, Some(frame.page_number()), segment.flags)?; - // 写入数据 - (*frame).copy_from_slice(&page_data); - // 保存 - self.mapped_pairs.push_back((vpn, frame)); - } - } - } - Ok(()) -} -``` - -最后，我们实现一个函数实现页表的激活，也就是把 `satp` 寄存器更新并刷新 TLB： - -{% label %}os/src/memory/mapping/mapping.rs: impl Mapping{% endlabel %} -```rust -/// 将当前的映射加载到 `satp` 寄存器 -pub fn activate(&self) { - // satp 低 27 位为页号，高 4 位为模式，8 表示 Sv39 - let new_satp = self.root_ppn.0 | (8 << 60); - unsafe { - // 将 new_satp 的值写到 satp 寄存器 - llvm_asm!("csrw satp, $0" :: "r"(new_satp) :: "volatile"); - // 刷新 TLB - llvm_asm!("sfence.vma" :::: "volatile"); - } -} -``` - -### MemorySet - -最后，我们需要把内核的每个段根据不同的属性写入上面的封装的 `Mapping` 中，并把它作为一个新的结构 `MemorySet` 给后面的线程的概念使用，这意味着：每个线程（到目前为止你可以大致理解为自己电脑中的同时工作的应用程序们）将会拥有一个 `MemorySet`，其中存的将会是「它看到的虚拟内存空间分成的内存段」和「这些段中包含的虚拟页到物理页的映射」： - -{% label %}os/src/memory/mapping/memory_set.rs{% endlabel %} -```rust -/// 一个进程所有关于内存空间管理的信息 -pub struct MemorySet { - /// 维护页表和映射关系 - pub mapping: Mapping, - /// 每个字段 - pub segments: Vec, -} -``` - -到目前为止，我们还只有内核这个概念，所以我们只是实现一个内核的精细映射来代替开始的时候粗糙的权限管理（一并把页表激活实现）： - -{% label %}os/src/memory/mapping/memory_set.rs{% endlabel %} -```rust -impl MemorySet { - /// 创建内核重映射 - pub fn new_kernel() -> MemoryResult { - // 在 linker.ld 里面标记的各个字段的起始点，均为 4K 对齐 - extern "C" { - fn text_start(); - fn rodata_start(); - fn data_start(); - fn bss_start(); - } - - // 建立字段 - let segments = vec![ - // .text 段，r-x - Segment { - map_type: MapType::Linear, - range: Range::from((text_start as usize)..(rodata_start as usize)), - flags: Flags::READABLE | Flags::EXECUTABLE, - }, - // .rodata 段，r-- - Segment { - map_type: MapType::Linear, - range: Range::from((rodata_start as usize)..(data_start as usize)), - flags: Flags::READABLE, - }, - // .data 段，rw- - Segment { - map_type: MapType::Linear, - range: Range::from((data_start as usize)..(bss_start as usize)), - flags: Flags::READABLE | Flags::WRITABLE, - }, - // .bss 段，rw- - Segment { - map_type: MapType::Linear, - range: Range::from(VirtualAddress::from(bss_start as usize)..*KERNEL_END_ADDRESS), - flags: Flags::READABLE | Flags::WRITABLE, - }, - // 剩余内存空间，rw- - Segment { - map_type: MapType::Linear, - range: Range::from(*KERNEL_END_ADDRESS..VirtualAddress::from(MEMORY_END_ADDRESS)), - flags: Flags::READABLE | Flags::WRITABLE, - }, - ]; - let mut mapping = Mapping::new()?; - // 准备保存所有新分配的物理页面 - let mut allocated_pairs = Vec::new(); - - // 每个字段在页表中进行映射 - for segment in segments.iter() { - // 同时将新分配的映射关系保存到 allocated_pairs 中 - mapping.map(segment, None)?; - } - Ok(MemorySet { mapping, segments }) - } - - /// 替换 `satp` 以激活页表 - /// - /// 如果当前页表就是自身，则不会替换，但仍然会刷新 TLB。 - pub fn activate(&self) { - self.mapping.activate() - } -} -``` - -到这里，我们完整实现了内核的重映射，最后可以在主函数中测试一下： - -{% label %}os/src/main.rs{% endlabel %} -```rust -/// Rust 的入口函数 -/// -/// 在 `_start` 为我们进行了一系列准备之后，这是第一个被调用的 Rust 函数 -#[no_mangle] -pub extern "C" fn rust_main() -> ! { - // 初始化各种模块 - interrupt::init(); - memory::init(); - - let remap = memory::mapping::MemorySet::new_kernel().unwrap(); - remap.activate(); - - println!("kernel remapped"); - - panic!() -} -``` - -在这里我们申请了一个内核的重映射，然后对页表进行激活，后面运行了一句输出，虽然看起来没有什么不同，只是输出了一句话，但是需要注意到这句话所用的所有逻辑已经建立在了新构建的页表上，而不是那个粗糙的 `boot_page_table` 了。`boot_page_table` 并非没有用，它为我们构建重映射提供了支持，但终究我们会用更精细的页表和映射代替了它，实现了更细致的管理和安全性。 - -至此，我们实现了重映射，而在上面我们也只是用一个局部变量来调用了简单测试了这个映射，而实际上，后面我们会把全部运行的逻辑都封装为线程，每个线程将会有一个 `MemorySet` 并存在于一个线程的结构中而不是一个简单的局部变量。当线程销毁的时候，线程中全部使用的逻辑（包括页表所在的物理页和其他申请的物理页等）将会被之前设计的 Tracker 机制自动释放。 - -不得不说，用 Rust 写这些内容是痛苦的（可能后面一两个章节还会痛苦一段时间），但是为了充分发挥 Rust 的特性，这些挣扎是必要的，一旦我们铺平了这些基础设施，后面的流程会大大简化。对于这两章的内容我们也经历过大量讨论，也做了大量的设计性和教学性权衡，如果你阅读文档还是一头雾水，可以去完整的阅读代码和对应的注释并尝试运行。 diff --git a/docs/lab-3/guide/part-5.md b/docs/lab-3/guide/part-5.md deleted file mode 100644 index 5e99dcd..0000000 --- a/docs/lab-3/guide/part-5.md +++ /dev/null @@ -1,177 +0,0 @@ -## 页面置换\* - -> **[info] 注意** -> 本小节涉及内容繁杂，实现也可能有考虑不周之处，具体的代码仅供有兴趣的同学阅读。 -> -> 由于需要操作“页面置换文件”，页面置换的具体实现会用到文件系统（实验五）的框架。不过，实验五会提供非常抽象的接口，我们暂时不需要完全了解后面实验的实现方法。 -> -> 如果你选择对照我们的实验指导，自行实现一个操作系统，你可以阅读本小节但暂时跳过这部分的实现。它不会影响任何后续实验的功能。 - -### 原理 - -虚拟内存的一大优势是可以用有限的物理内存空间虚拟出近乎无限的虚拟内存空间，其原理就是只将一部分虚拟内存所对应的数据存放在物理内存中，而剩余的则存放在磁盘（外设）中。当一个线程操作到那些不在物理内存中的虚拟地址时，就会产生**缺页异常（Page Fault）**。此时操作系统会介入，交换一部分物理内存和磁盘中的数据，使得需要访问的内存数据被放入物理内存之中。 - -在页表中，页表项的 Valid 位就表示对应的页面是否在物理内存中。因此，操作系统还必须更新页表，并刷新缓存。 - -### 置换算法 - -我们可以很自然地认为，操作系统需要将那些“经常被使用”的内存空间放在物理内存中，而“不那么经常被使用”的放在外部存储中。但是，计算机不可能预言哪些地址会在以后被访问。我们只能通过一些置换算法，根据前一段时间的内存使用情况，来估计未来哪些地址会被使用，从而将这部分数据保留在物理内存中。 - -朴素地考虑，我们可以假设如果程序刚刚访问了一部分内存，那么他就很有可能重复地访问它。因此，每次出现缺页时，就将物理内存中最后访问时间最靠前的页面替换出去。这就是**LRU (Least Recently Used) 算法**。但这种算法需要维护一个优先队列，而且在每一次访问内存时都要更新。很显然这是不现实的，它带来的开销太大。 - -目前存在着大量的置换算法，我们可以在[维基百科](https://en.wikipedia.org/wiki/Page_replacement_algorithm)上初步了解。 - -### 我们的实现 - -首先，我们要在磁盘中建立一个页面置换文件，来保存所有换出的页面。为了简化实现，我们直接在镜像中打包一个全是 0 的文件 `SWAP_FILE` 进去。 - -{% label %}user/Makefile{% endlabel %} -```makefile -# 编译、打包、格式转换、预留空间 -build: dependency - @cargo build - @echo Targets: $(patsubst $(SRC_DIR)/%.rs, %, $(SRC_FILES)) - @rm -rf $(OUT_DIR) - @mkdir -p $(OUT_DIR) - @cp $(BIN_FILES) $(OUT_DIR) ---> @dd if=/dev/zero of=$(OUT_DIR)/SWAP_FILE bs=1M count=16 - @rcore-fs-fuse --fs sfs $(IMG_FILE) $(OUT_DIR) zip - @qemu-img convert -f raw $(IMG_FILE) -O qcow2 $(QCOW_FILE) - @qemu-img resize $(QCOW_FILE) +1G -``` - -我们希望每个进程的 `Mapping` 都能够像管理物理页面一样管理这些置换页面（在销毁时也能够释放它们），因此我们实现了一个类似于 `FrameTracker` 的 `SwapTracker`。它的具体实现会用到一些文件系统的操作，如果感兴趣可以参考源码。但简概括之：**`SwapTracker` 记录了一个被置换出物理内存的页面，并提供一些便捷的操作接口**。 - -{% label %}os/src/fs/swap.rs{% endlabel %} -```rust -/// 类似于 [`FrameTracker`]，相当于 `Box<置换文件中的一个页面>` -/// -/// 内部保存该置换页面在文件中保存的 index -/// -/// [`FrameTracker`]: crate::memory::frame::FrameTracker -#[derive(Debug, Ord, PartialOrd, Eq, PartialEq, Hash)] -pub struct SwapTracker(pub(super) usize); - -impl SwapTracker { - /// 从置换文件分配一个页面空间 - pub fn new() -> MemoryResult { - ... - } - - /// 读取页面数据 - pub fn read(&self) -> [u8; PAGE_SIZE] { - ... - } - - /// 写入页面数据 - pub fn write(&self, data: &[u8; PAGE_SIZE]) { - ... - } -} - -impl Drop for SwapTracker { - fn drop(&mut self) { - ... - } -} -``` - -然后，我们定义了一个置换算法的接口，并且实现了一个非常简单的置换算法，具体算法就不呈现了。 - -{% label %}os/src/memory/mapping/swapper.rs{% endlabel %} -```rust -/// 管理一个线程所映射的页面的置换操作 -pub trait Swapper { - /// 新建带有一个分配数量上限的置换器 - fn new(quota: usize) -> Self; - - /// 是否已达到上限 - fn full(&self) -> bool; - - /// 取出一组映射 - fn pop(&mut self) -> Option<(VirtualPageNumber, FrameTracker)>; - - /// 添加一组映射（不会在以达到分配上限时调用） - fn push(&mut self, vpn: VirtualPageNumber, frame: FrameTracker); - - /// 只保留符合某种条件的条目（用于移除一段虚拟地址） - fn retain(&mut self, predicate: impl Fn(&VirtualPageNumber) -> bool); -} -``` - -这里，`Swapper` 就替代了 `Mapping` 中的 `mapped_pairs: Vec<(VirtualPageNumber, FrameTracker)>` 的作用。因此，我们替换 `Mapping` 中的成员： - -{% label %}os/src/memory/mapping/mapping.rs{% endlabel %} -```rust -/// 某个进程的内存映射关系 -pub struct Mapping { - /// 保存所有使用到的页表 - page_tables: Vec, - /// 根页表的物理页号 - root_ppn: PhysicalPageNumber, - /// 所有分配的物理页面映射信息 - mapped_pairs: SwapperImpl, - /// 被换出的页面存储在虚拟内存文件中的 Tracker - swapped_pages: HashMap, -} -``` - -最后，让我们实现内存置换：遇到缺页异常，找到需要访问的页号、需要访问的页面数据，并置换出一个物理内存中的页号、页面数据，将二者进行交换 - -{% label %}os/src/memory/mapping/mapping.rs{% endlabel %} -```rust -impl Mapping { - /// 处理缺页异常 - pub fn handle_page_fault(&mut self, stval: usize) -> MemoryResult<()> { - let vpn = VirtualPageNumber::floor(stval.into()); - let swap_tracker = self - .swapped_pages - .remove(&vpn) - .ok_or("stval page is not mapped")?; - let page_data = swap_tracker.read(); - - if self.mapped_pairs.full() { - // 取出一个映射 - let (popped_vpn, mut popped_frame) = self.mapped_pairs.pop().unwrap(); - // print!("{:x?} -> {:x?}", popped_vpn, vpn); - // 交换数据 - swap_tracker.write(&*popped_frame); - (*popped_frame).copy_from_slice(&page_data); - // 修改页表映射 - self.invalidate_one(popped_vpn)?; - self.remap_one(vpn, popped_frame.page_number())?; - // 更新记录 - self.mapped_pairs.push(vpn, popped_frame); - self.swapped_pages.insert(popped_vpn, swap_tracker); - } else { - // 如果当前还没有达到配额，则可以继续分配物理页面。这种情况目前还不会出现 - // 添加新的映射 - let mut frame = FRAME_ALLOCATOR.lock().alloc()?; - // 复制数据 - (*frame).copy_from_slice(&page_data); - // 更新映射 - self.remap_one(vpn, frame.page_number())?; - // 更新记录 - self.mapped_pairs.push(vpn, frame); - } - Ok(()) - } -} -``` - -然后，令缺页异常调用上面的函数，就完成了页面置换的实现 - -{% label %}os/src/interrupt/handler.rs{% endlabel %} -```rust -/// 处理缺页异常 -/// -/// todo: 理论上这里需要判断访问类型，并与页表中的标志位进行比对 -fn page_fault(context: &mut Context, stval: usize) -> Result<*mut Context, String> { - println!("page_fault"); - let current_thread = PROCESSOR.lock().current_thread(); - let memory_set = &mut current_thread.process.write().memory_set; - memory_set.mapping.handle_page_fault(stval)?; - memory_set.activate(); - Ok(context) -} -``` diff --git a/docs/lab-3/guide/summary.md b/docs/lab-3/guide/summary.md deleted file mode 100644 index b7901a4..0000000 --- a/docs/lab-3/guide/summary.md +++ /dev/null @@ -1,5 +0,0 @@ -## 小结 - -回顾本章，我们理清了虚拟地址和物理地址的概念和关系；并利用页表完成虚拟地址到物理地址的映射；最后实现了内核空间段的重映射。 - -如果说本章和前一个章节是对空间的划分和管理，那么在下一个小节中，我们将实现对时间的划分和管理，也就是线程。 \ No newline at end of file diff --git a/docs/lab-3/pics/rcore_memory_layout.png b/docs/lab-3/pics/rcore_memory_layout.png deleted file mode 100644 index 4d38c75..0000000 Binary files a/docs/lab-3/pics/rcore_memory_layout.png and /dev/null differ diff --git a/docs/lab-3/pics/sv39_address.png b/docs/lab-3/pics/sv39_address.png deleted file mode 100644 index deedb2a..0000000 Binary files a/docs/lab-3/pics/sv39_address.png and /dev/null differ diff --git a/docs/lab-3/pics/sv39_pagetable.jpg b/docs/lab-3/pics/sv39_pagetable.jpg deleted file mode 100644 index 5678542..0000000 Binary files a/docs/lab-3/pics/sv39_pagetable.jpg and /dev/null differ diff --git a/docs/lab-3/pics/sv39_pte.jpg b/docs/lab-3/pics/sv39_pte.jpg deleted file mode 100644 index 22f1529..0000000 Binary files a/docs/lab-3/pics/sv39_pte.jpg and /dev/null differ diff --git a/docs/lab-3/pics/sv39_rwx.jpg b/docs/lab-3/pics/sv39_rwx.jpg deleted file mode 100644 index bbc8fb3..0000000 Binary files a/docs/lab-3/pics/sv39_rwx.jpg and /dev/null differ diff --git a/docs/lab-3/pics/sv39_satp.jpg b/docs/lab-3/pics/sv39_satp.jpg deleted file mode 100644 index 7b0f214..0000000 Binary files a/docs/lab-3/pics/sv39_satp.jpg and /dev/null differ diff --git a/docs/lab-3/practice.md b/docs/lab-3/practice.md deleted file mode 100644 index e932445..0000000 --- a/docs/lab-3/practice.md +++ /dev/null @@ -1,46 +0,0 @@ -## 实验三：虚实地址转换 - -### 实验之前 - -- 阅读实验指导三，可以结合 `lab-3` 分支的代码来理解。 -- **（验框架尚未准备完善）**本次的实验题将使用 `lab-3+` 分支，它包含了后面章节的内容，而我们不需要管那些部分。 - -### 实验题 - -1. 原理：在 `os/src/entry.asm` 中，`boot_page_table` 的意义是什么？当跳转执行 `rust_main` 时，不考虑缓存，硬件通过哪些地址找到了 `rust_main` 的第一条指令？ - - {% reveal %} -> 1. `boot_page_table` 是一个用二进制表示的根页表，其中包含两个 1GB 大页，分别是将虚拟地址 `0x8000_0000` 至 `0xc000_0000` 映射到物理地址 `0x8000_0000` 至 `0xc000_0000`，以及将虚拟地址 `0xffff_ffff_8000_0000` 至 `0xffff_ffff_c000_0000` 映射到物理地址 `0x8000_0000` 至 `0xc000_0000`。 -> -> 由于我们在 `linker.ld` 中指定了起始地址为 `0xffff_ffff_8020_0000`，操作系统执行文件会认为所有的符号都是在这个高地址上的。但是我们在硬件上只能将内核加载到 `0x8020_0000` 开始的内存空间上，此时的 `pc` 也会调转到这里。 -> -> 为了让程序能够正确跳转至高地址的 `rust_main`，我们需要在 `entry.asm` 中先应用内核重映射，即将高地址映射到低地址。但我们不可能在替换页表的同时修改 `pc`，此时 `pc` 仍然处于低地址。所以，页表中的另一项（低地址的恒等映射）则保证程序替换页表后的短暂时间内，`pc` 仍然可以顺着低地址去执行内存中的指令。 -> -> *注：如果 `boot_page_table` 中不包含低地址恒等映射，程序可能仍然可以正常运行。这可能和硬件的缓存设计有关。但保险起见，应当保留这两个映射。* -> -> 2. 执行 `jal rust_main` 时，硬件需要加载 `rust_main` 对应的地址，大概是 `0xffff_ffff_802x_xxxx`。 -> - 页表已经启用，硬件先从 `satp` 高位置读取内存映射模式，再从 `satp` 低位置读取根页表页号，即 `boot_page_table` 的物理页号 -> - 对于 Sv39 模式，页号有三级共 27 位。对于 `rust_main` 而言，一级页号是其 [30:38] 位，即 510。硬件此时定位到根页表的第 510 项 -> - 这一项的标志为 XWR，说明它指向一个大页而不是指向下一级页表；目标的页号为 `0x8_0000`，即物理地址 `0x8000_0000` 开始的区间；这一项的 V 位为 1，说明目标在内存中。因此，硬件寻址到页基址 + 页内偏移，即 `0x8000_0000 + 0x2x_xxxx`，找到 `rust_main` - {% endreveal %} - -
-2. 分析：为什么 `Mapping` 中的 `page_tables` 和 `mapped_pairs` 都保存了一些 `FrameTracker`？二者有何不同？ - - {% reveal %} -> 页表也是需要我们去分配页面来存储的。因此，`page_tables` 存放了所有页表所用到的页面，而 `mapped_pairs` 则存放了进程所用到的页面。 - {% endreveal %} - -
-3. 分析：假设某进程需要虚拟地址 A 到物理地址 B 的映射，这需要操作系统来完成。那么操作系统在建立映射时有没有访问 B？如果有，它是怎么在还没有映射的情况下访问 B 的呢？ - - {% reveal %} -> 建立映射不需要访问 B，而只需要操作页表即可。不过，通常程序都会需要操作系统建立映射的同时向页面中加载一些数据。此时，尽管 A→B 的映射尚不存在，因为我们将整个可用物理内存都建立了内核映射，所以操作系统仍然可以通过线性偏移量来访问到 B。 - {% endreveal %} - -
-4. **（实验框架尚未准备完善）**实验：了解并实现时钟页面置换算法（或任何你感兴趣的算法），可以自行设计样例来比较性能 - - - 置换算法只需要修改 `os/src/memory/mapping/swapper.rs`，你可能需要在其中访问页表项 - - - 在 `main.rs` 中调用 `start_kernel_thread` 来创建线程，你可以任意修改其中运行的函数，以达到测试效果 diff --git a/docs/lab-4/guide/intro.md b/docs/lab-4/guide/intro.md deleted file mode 100644 index 2954351..0000000 --- a/docs/lab-4/guide/intro.md +++ /dev/null @@ -1,9 +0,0 @@ -# 实验指导四 - -## 实验概要 - -这一章的实验指导中，你将会学到： - -- 线程和进程的概念以及运行状态的表示 -- 线程的切换 -- 对 CPU 进行抽象在上面完成对线程的调度 \ No newline at end of file diff --git a/docs/lab-4/guide/part-1.md b/docs/lab-4/guide/part-1.md deleted file mode 100644 index c04a44b..0000000 --- a/docs/lab-4/guide/part-1.md +++ /dev/null @@ -1,110 +0,0 @@ -## 线程和进程 - -### 基本概念 - -从**源代码**经过编译器一系列处理（编译、链接、优化等）得到的可执行文件，我们称为**程序（Program）**。而通俗地说，**进程（Process）**就是**正在运行**并**使用计算机资源**的程序，与放在磁盘中一动不动的程序不同：首先，进程得到了操作系统提供的**资源**：程序的代码、数据段被加载到**内存**中，程序所需的虚拟内存空间被真正构建出来。同时操作系统还给进程分配了程序所要求的各种**其他资源**，如我们上面几个章节中提到过的页表、文件的资源。 - -然而如果仅此而已，进程还尚未体现出其“**正在运行**”的动态特性。而正在运行意味着 **CPU** 要去执行程序代码段中的代码，为了能够进行函数调用，我们还需要**运行栈（Stack）**。 - -出于OS对计算机系统精细管理的目的，我们通常将“正在运行”的动态特性从进程中剥离出来，这样的一个借助 CPU 和栈的执行流，我们称之为**线程 (Thread)** 。一个进程可以有多个线程，也可以如传统进程一样只有一个线程。 - -这样，进程虽然仍是代表一个正在运行的程序，但是其主要功能是作为**资源的分配单位**，管理页表、文件、网络等资源。而一个进程的多个线程则共享这些资源，专注于执行，从而作为**执行的调度单位**。举一个例子，为了分配给进程一段内存，我们把一整个页表交给进程，而出于某些目的（比如为了加速需要两个线程放在两个 CPU 的核上），我们需要线程的概念来进一步细化执行的方式，这时进程内部的全部这些线程看到的就是同样的页表，看到的也是相同的地址。但是需要注意的是，这些线程为了可以独立运行，有自己的栈（会放在相同地址空间的不同位置），CPU 也会以它们这些线程为一个基本调度单位。 - -### 线程的表示 - -在不同操作系统中，为每个线程所保存的信息都不同。在这里，我们提供一种基础的实现，每个线程会包括： - -- **线程 ID**：用于唯一确认一个线程，它会在系统调用等时刻用到。 -- **运行栈**：每个线程都必须有一个独立的运行栈，保存运行时数据。 -- **线程执行上下文**：当线程不在执行时，我们需要保存其上下文（其实就是一堆**寄存器**的值），这样之后才能够将其恢复，继续运行。和之前实现的中断一样，上下文由 `Context` 类型保存。（注：这里的**线程执行上下文**与前面提到的**中断上下文**是不同的概念） -- **所属进程的记号**：同一个进程中的多个线程，会共享页表、打开文件等信息。因此，我们将它们提取出来放到线程中。 -- ***内核栈***：除了线程运行必须有的运行栈，中断处理也必须有一个单独的栈。之前，我们的中断处理是直接在原来的栈上进行（我们直接将 `Context` 压入栈）。但是在后面我们会引入用户线程，这时就只有上帝才知道发生了什么——栈指针、程序指针都可能在跨国（**国 == 特权态**）旅游。为了确保中断处理能够进行（让操作系统能够接管这样的线程），中断处理必须运行在一个准备好的、安全的栈上。这就是内核栈。不过，内核栈并没有存储在线程信息中。（注：**它的使用方法会有些复杂，我们会在后面讲解**。） - -{% label %}os/src/process/thread.rs{% endlabel %} -```rust -/// 线程的信息 -pub struct Thread { - /// 线程 ID - pub id: ThreadID, - /// 线程的栈 - pub stack: Range, - /// 所属的进程 - pub process: Arc, - /// 用 `Mutex` 包装一些可变的变量 - pub inner: Mutex, -} - -/// 线程中需要可变的部分 -pub struct ThreadInner { - /// 线程执行上下文 - /// - /// 当且仅当线程被暂停执行时，`context` 为 `Some` - pub context: Option, - /// 是否进入休眠 - pub sleeping: bool, - /// 是否已经结束 - pub dead: bool, -} -``` - -注意到，因为线程一般使用 `Arc` 来保存，它是不可变的，所以其中再用 `Mutex` 来包装一部分，让这部分可以修改。 - -### 进程的表示 - -在我们实现的简单操作系统中，进程只需要维护页面映射，并且存储一点额外信息： - -- **用户态标识**：我们会在后面进行区分内核态线程和用户态线程。 -- **访存空间 `MemorySet`**：进程中的线程会共享同一个页表，即可以访问的虚拟内存空间（简称：访存空间）。 - -{% label %}os/src/process/process.rs{% endlabel %} -```rust -/// 进程的信息 -pub struct Process { - /// 是否属于用户态 - pub is_user: bool, - /// 用 `Mutex` 包装一些可变的变量 - pub inner: Mutex, -} - -pub struct ProcessInner { - /// 进程中的线程公用页表 / 内存映射 - pub memory_set: MemorySet, -// /// 打开的文件描述符（实验五） -// pub descriptors: Vec>, -} -``` - -同样地，线程也需要一部分是可变的。 - -### 处理器 - -有了线程和进程，现在，我们再抽象出「处理器」来存放和管理线程池。同时，也需要存放和管理目前正在执行的线程（即中断前执行的线程，因为操作系统在工作时是处于中断、异常或系统调用服务之中）。 - -{% label %}os/src/process/processor.rs{% endlabel %} -```rust -/// 线程调度和管理 -/// -/// 休眠线程会从调度器中移除，单独保存。在它们被唤醒之前，不会被调度器安排。 -pub struct Processor { - /// 当前正在执行的线程 - current_thread: Option>, - /// 线程调度器，记录活跃线程 - scheduler: SchedulerImpl>, - /// 保存休眠线程 - sleeping_threads: HashSet>, -} -``` - -- `current_thread` 需要保存当前正在运行的线程，这样当出现系统调用的时候，操作系统便可以方便地知道是哪个线程在举手。 -- `scheduler` 会负责调度线程，其接口就是简单的“添加”“移除”“获取下一个”，我们会在[后面](part-6.md)详细讲到。 -- 休眠线程是指等待一些外部资源（例如硬盘读取、外设读取等）的线程，这时 CPU 如果给其时间片运行是没有意义的，因此它们也就需要移出调度器而单独保存。 - -{% label %}os/src/process/processor.rs{% endlabel %} -```rust -lazy_static! { - /// 全局的 [`Processor`] - pub static ref PROCESSOR: Lock = Lock::new(Processor::default()); -} -``` - -注意到这里我们用了一个 `Lock`（`os/process/lock.rs`），它封装了 `spin::Mutex`，而在其基础上进一步关闭了中断。这是因为我们（以后）在内核线程中也有可能访问 `PROCESSOR`，但是此时我们不希望它被时钟打断，这样在中断处理中就无法访问 `PROCESSOR` 了，因为它已经被锁住。 diff --git a/docs/lab-4/guide/part-2.md b/docs/lab-4/guide/part-2.md deleted file mode 100644 index 45bfd5c..0000000 --- a/docs/lab-4/guide/part-2.md +++ /dev/null @@ -1,117 +0,0 @@ -## 线程的创建 - -接下来，我们的第一个目标就是创建一个线程并且让他运行起来。一个线程要开始运行，需要这些准备工作： - -- 建立页表映射，需要包括以下映射空间： - - 线程所执行的一段指令 - - 线程执行栈 - - *操作系统的部分内存空间* -- 设置起始执行的地址 -- 初始化各种寄存器，比如 `sp` -- 可选：设置一些执行参数（例如 `argc` 和 `argv`等 ） - -思考：为什么线程即便与操作系统无关，也需要在内存中映射操作系统的内存空间呢？ - -{% reveal %} -> 当发生中断时，需要跳转到 `stvec` 所指向的中断处理过程。如果操作系统的内存不在页表之中，将无法处理中断。 -> -> 当然，也不是所有操作系统的代码都需要被映射，但是为了实现简便，我们会为每个进程的页表映射全部操作系统的内存。而由于这些页表都标记为**内核权限**（即 `U` 位为 0），也不必担心用户线程可以随意访问。 -{% endreveal %} - -### 执行第一个线程 - -因为启动线程需要修改各种寄存器的值，所以我们又要使用汇编了。不过，这一次我们只需要对 `interrupt.asm` 稍作修改就可以了。 - -在 `interrupt.asm` 中的 `__restore` 标签现在就能派上用途了。原本这段汇编代码的作用是将之前所保存的 `Context` 恢复到寄存器中，而现在我们让它使用一个精心设计的 `Context`，就可以让程序在恢复后直接进入我们的新线程。 - -首先我们稍作修改，添加一行 `mv sp, a0`。原本这里是读取之前存好的 `Context`，现在我们让其从 `a0` 中读取我们设计好的 `Context`。这样，我们可以直接在 Rust 代码中调用 `__restore(context)`。 - -{% label %}os/src/interrupt/interrupt.asm{% endlabel %} -```asm -__restore: - mv sp, a0 # 加入这一行 - # ... -``` - -#### 那么我们需要如何设计 `Context` 呢？ - -- 通用寄存器 - - `sp`：应当指向该线程的栈顶 - - `a0`-`a7`：按照函数调用规则，用来传递参数 - - `ra`：线程执行完应该跳转到哪里呢？在后续**系统调用**章节我们会介绍正确的处理方式。现在，我们先将其设为一个不可执行的地址，这样线程一结束就会触发页面异常 -- `sepc` - - 执行 `sret` 指令后会跳转到这里，所以 `sepc` 应当存储线程的入口地址（执行的函数地址） -- `sstatus` - - `spp` 位按照用户态或内核态有所不同 - - `spie` 位为 1 - -> **[info] `sstatus` 标志位的具体意义** -> -> - `spp`：中断前系统处于内核态（1）还是用户态（0） -> - `sie`：内核态是否允许中断。对用户态而言，无论 `sie` 取何值都开启中断 -> - `spie`：中断前是否开中断（用户态中断时可能 `sie` 为 0） -> -> **硬件处理流程** -> -> - 在中断发生时，系统要切换到内核态。此时，**切换前的状态**会被保存在 **`spp`** 位中（1 表示切换前处于内核态）。同时，**切换前是否开中断**会被保存在 **`spie`** 位中，而 `sie` 位会被置 0，表示关闭中断。 -> - 在中断结束，执行 `sret` 指令时，会根据 `spp` 位的值决定 `sret` 执行后是处于内核态还是用户态。与此同时，`spie` 位的值会被写入 `sie` 位，而 `spie` 位置 1。这样，特权状态和中断状态就全部恢复了。 -> -> **为何如此繁琐？** -> -> - 特权状态： -> 中断处理流程必须切换到内核态，所以中断时需要用 `spp` 来保存之前的状态。 -> 回忆计算机组成原理的知识，`sret` 指令必须同时完成跳转并切换状态的工作。 -> - 中断状态： -> 中断刚发生时，必须关闭中断，以保证现场保存的过程不会被干扰。同理，现场恢复的过程也必须关中断。因此，需要有以上两个硬件自动执行的操作。 -> 由于中断可能嵌套，在保存现场后，根据中断的种类，可能会再开启部分中断的使能。 - -设计好 `Context` 之后，我们只需要将它应用到所有的寄存器上（即执行 `__restore`），就可以切换到第一个线程了。 - -{% label %}os/src/main.rs: rust_main(){% endlabel %} -```rust -extern "C" { - fn __restore(context: usize); -} -// 获取第一个线程的 Context，具体原理后面讲解 -let context = PROCESSOR.lock().prepare_next_thread(); -// 启动第一个线程 -unsafe { __restore(context as usize) }; -unreachable!() -``` - -#### 为什么 `unreachable` - -我们直接调用的 `__restore` 并没有 `ret` 指令，甚至 `ra` 都会被 `Context` 中的数值直接覆盖。这意味着，一旦我们执行了 `__restore(context)`，程序就无法返回到调用它的位置了。**注：直接 jump 是一个非常危险的操作**。 - -但是没有关系，我们也不需要这个函数返回。因为开始执行第一个线程，意味着操作系统的初始化已经完成，再回到 `rust_main()` 也没有意义了。甚至原本我们使用的栈 `bootstack`，也可以被回收（不过我们现在就丢掉不管吧）。 - -#### 在启动时不打开中断 - -现在，我们会在线程开始运行时开启中断，而在操作系统初始化的过程中是不应该有中断的。所以，我们删去之前设置「开启中断」的代码。 - -{% label %}os/interrupt/timer.rs{% endlabel %} -```rust -/// 初始化时钟中断 -/// -/// 开启时钟中断使能，并且预约第一次时钟中断 -pub fn init() { - unsafe { - // 开启 STIE，允许时钟中断 - sie::set_stimer(); - // （删除）开启 SIE（不是 sie 寄存器），允许内核态被中断打断 - // sstatus::set_sie(); - } - // 设置下一次时钟中断 - set_next_timeout(); -} -``` - -### 小结 - -为了执行一个线程，我们需要初始化所有寄存器的值。为此，我们选择构建一个 `Context` 然后跳转至 `interrupt.asm` 中的 `__restore` 来执行，用这个 `Context` 来写入所有寄存器。 - -#### 思考 - -`__restore` 现在会将 `a0` 寄存器视为一个 `*mut Context` 来读取，因此我们在执行第一个线程时只需调用 `__restore(context)`。 - -那么，如果是程序发生了中断，执行到 `__restore` 的时候，`a0` 的值又是谁赋予的呢？ diff --git a/docs/lab-4/guide/part-3.md b/docs/lab-4/guide/part-3.md deleted file mode 100644 index aaf7773..0000000 --- a/docs/lab-4/guide/part-3.md +++ /dev/null @@ -1,112 +0,0 @@ -## 线程的切换 - -回答一下前一节的思考题：当发生中断时，在 `__restore` 时，`a0` 寄存器的值是 `handle_interrupt` 函数的返回值。也就是说，如果我们令 `handle_interrupt` 函数返回另一个线程的 `*mut Context`，就可以在时钟中断后跳转到这个线程来执行。 - -### 修改中断处理 - -在线程切换时（即时钟中断时），`handle_interrupt` 函数需要将上一个线程的 `Context` 保存起来，然后将下一个线程的 `Context` 恢复并返回。 - -> 注 1：为什么不直接 in-place 修改 `Context` 呢？这是因为 `handle_interrupt` 函数返回的 `Context` 指针除了存储上下文以外，还提供了内核栈的地址。这个会在后面详细阐述。 -> -> 注 2：在 Rust 中，引用 `&mut` 和指针 `*mut` 只是编译器的理解不同，其本质都是一个存储对象地址的寄存器。这里返回值使用指针而不是引用，是因为其指向的位置十分特殊，其生命周期在这里没有意义。 - -{% label %}os/src/interrupt/handler.rs{% endlabel %} -```rust -/// 中断的处理入口 -#[no_mangle] -pub fn handle_interrupt(context: &mut Context, scause: Scause, stval: usize) -> *mut Context { - /* ... */ -} - -/// 处理 ebreak 断点 -fn breakpoint(context: &mut Context) -> *mut Context { - println!("Breakpoint at 0x{:x}", context.sepc); - context.sepc += 2; - context -} - -/// 处理时钟中断 -fn supervisor_timer(context: &mut Context) -> *mut Context { - timer::tick(); - PROCESSOR.lock().park_current_thread(context); - PROCESSOR.lock().prepare_next_thread() -} -``` - -可以看到，当发生断点中断时，直接返回原来的上下文（修改一下 `sepc`）；而如果是时钟中断的时候，我们执行了两个函数得到的返回值作为上下文，那它又是怎么工作的呢？ - -### 线程切换 - -让我们看一下 `Processor` 中的这两个方法是如何实现的。 - -（调度器 `scheduler` 会在后面的小节中讲解，我们只需要知道它能够返回下一个等待执行的线程。） - -{% label %}os/src/process/processor.rs: impl Processor{% endlabel %} -```rust -/// 保存当前线程的 `Context` -pub fn park_current_thread(&mut self, context: &Context) { - self.current_thread().park(*context); -} - -/// 在一个时钟中断时，替换掉 context -pub fn prepare_next_thread(&mut self) -> *mut Context { - // 向调度器询问下一个线程 - if let Some(next_thread) = self.scheduler.get_next() { - // 准备下一个线程 - let context = next_thread.prepare(); - self.current_thread = Some(next_thread); - context - } else { - // 没有活跃线程 - if self.sleeping_threads.is_empty() { - // 也没有休眠线程，则退出 - panic!("all threads terminated, shutting down"); - } else { - // 有休眠线程，则等待中断 - /* ... */ - } - } -} -``` - -#### 上下文 `Context` 的保存和取出 - -在线程切换时，我们需要保存前一个线程的 `Context`，为此我们实现 `Thread::park` 函数。 - -{% label %}os/src/process/thread.rs: impl Thread{% endlabel %} -```rust -/// 发生时钟中断后暂停线程，保存状态 -pub fn park(&self, context: Context) { - // 检查目前线程内的 context 应当为 None - assert!(self.inner().context.is_none()); - // 将 Context 保存到线程中 - self.inner().context.replace(context); -} -``` - -然后，我们需要取出下一个线程的 `Context`，为此我们实现 `Thread::prepare`。不过这次需要注意的是，启动一个线程除了需要 `Context`，还需要切换页表。这个操作我们也在这个方法中完成。 - -{% label %}os/src/process/thread.rs: impl Thread{% endlabel %} -```rust -/// 准备执行一个线程 -/// -/// 激活对应进程的页表，并返回其 Context -pub fn prepare(&self) -> *mut Context { - // 激活页表 - self.process.inner().memory_set.activate(); - // 取出 Context - let parked_frame = self.inner().context.take().unwrap(); - // 将 Context 放至内核栈顶 - unsafe { KERNEL_STACK.push_context(parked_frame) } -} -``` - -思考：在 `run` 函数中，我们在一开始就激活了页表，会不会导致后续流程无法正常执行？ - -#### 内核栈？ - -现在，线程保存 `Context` 都是根据 `sp` 指针，在栈上压入一个 `Context` 来存储。但是，对于一个用户线程而言，它在用户态运行时用的是位于用户空间的用户栈。而它在用户态运行中如果触发中断，`sp` 指针指向的是用户空间的某地址，但此时 RISC-V CPU 会切换到内核态继续执行，就不能再用这个 `sp` 指针指向的用户空间地址了。这样，我们需要为 sp 指针准备好一个专门用于在内核态执行函数的内核栈。所以，为了不让一个线程的崩溃导致操作系统的崩溃，我们需要提前准备好内核栈，当线程发生中断时可用来存储线程的 `Context`。在下一节我们将具体讲解该如何做。 - -### 小结 - -为了实现线程的切换，我们让 `handle_interrupt` 返回一个 `*mut Context`。如果需要切换线程，就将前一个线程的 `Context` 保存起来换上新的线程的 `Context`。而如果不需要切换，那么直接返回原本的 `Context` 即可。 diff --git a/docs/lab-4/guide/part-4.md b/docs/lab-4/guide/part-4.md deleted file mode 100644 index 9ce55a7..0000000 --- a/docs/lab-4/guide/part-4.md +++ /dev/null @@ -1,43 +0,0 @@ -## 线程的结束 - -### 现有问题 - -当内核线程终止时，会发生什么？如果就按目前的实现，我们会发现线程所执行的函数末尾会触发 `Exception::InstructionPageFault` 而终止，其中访问的的地址 `stval = 0`。 - -这是因为内核线程在执行完 `entry_point` 所指向的函数后会返回到 `ra` 指向的地址，而我们没有为其赋初值（初值为 0）。此时，程序就会尝试跳转到 `0x0` 地址，而显然它是不存在的。 - -### 解决办法 - -很自然的，我们希望能够让内核线程在结束时触发一个友善的中断（而不是一个看上去像是错误的缺页异常），然后被操作系统释放。我们可能会想到系统调用，但很可惜我们无法使用它，因为系统调用的本质是一个环境调用 `ecall`，而在内核线程（内核态）中进行的环境调用是用来与 M 态通信的。我们之前实现的 SBI 调用就是使用的 S 态 `ecall`。 - -因此，我们设计一个折衷的解决办法：内核线程将自己标记为“已结束”，同时触发一个普通的异常 `ebreak`。此时操作系统观察到线程的标记，便将其终止。 - -{% label %}os/src/main.rs{% endlabel %} -```rust -/// 内核线程需要调用这个函数来退出 -fn kernel_thread_exit() { - // 当前线程标记为结束 - PROCESSOR.lock().current_thread().as_ref().inner().dead = true; - // 制造一个中断来交给操作系统处理 - unsafe { llvm_asm!("ebreak" :::: "volatile") }; -} -``` - -然后，我们将这个函数作为内核线程的 `ra`，使得它执行的函数完成后便执行 `kernel_thread_exit()` - -{% label %}os/src/main.rs{% endlabel %} -```rust -/// 创建一个内核进程 -pub fn create_kernel_thread( - process: Arc, - entry_point: usize, - arguments: Option<&[usize]>, -) -> Arc { - // 创建线程 - let thread = Thread::new(process, entry_point, arguments).unwrap(); - // 设置线程的返回地址为 kernel_thread_exit - thread.as_ref().inner().context.as_mut().unwrap() - .set_ra(kernel_thread_exit as usize); - thread -} -``` diff --git a/docs/lab-4/guide/part-5.md b/docs/lab-4/guide/part-5.md deleted file mode 100644 index 0605852..0000000 --- a/docs/lab-4/guide/part-5.md +++ /dev/null @@ -1,109 +0,0 @@ -## 内核栈 - -### 为什么 / 怎么做 - -在实现内核栈之前，让我们先检查一下需求和我们的解决办法。 - -- **不是每个线程都需要一个独立的内核栈**，因为内核栈只会在中断时使用，而中断结束后就不再使用。在只有一个 CPU 的情况下，不会有两个线程同时出现中断，**所以我们只需要实现一个共用的内核栈就可以了**。 -- **每个线程都需要能够在中断时第一时间找到内核栈的地址**。这时，所有通用寄存器的值都无法预知，也无法从某个变量来加载地址。为此，**我们将内核栈的地址存放到内核态使用的特权寄存器 `sscratch` 中**。这个寄存器只能在内核态访问，这样在中断发生时，就可以安全地找到内核栈了。 - -因此，我们的做法就是： - -- 预留一段空间作为内核栈 -- 运行线程时，在 `sscratch` 寄存器中保存内核栈指针 -- 如果线程遇到中断，则从将 `Context` 压入 `sscratch` 指向的栈中（`Context` 的地址为 `sscratch - size_of::()`），同时用新的栈地址来替换 `sp`（此时 `sp` 也会被复制到 `a0` 作为 `handle_interrupt` 的参数） -- 从中断中返回时（`__restore` 时），`a0` 应指向**被压在内核栈中的 `Context`**。此时出栈 `Context` 并且将栈顶保存到 `sscratch` 中 - -### 实现 - -#### 为内核栈预留空间 - -我们直接使用一个 `static mut` 来指定一段空间作为栈。 - -{% label %}os/src/process/kernel_stack.rs{% endlabel %} -```rust -/// 内核栈 -#[repr(align(16))] -#[repr(C)] -pub struct KernelStack([u8; KERNEL_STACK_SIZE]); - -/// 公用的内核栈 -pub static mut KERNEL_STACK: KernelStack = KernelStack([0; STACK_SIZE]); -``` - -在我们创建线程时，需要使用的操作就是在内核栈顶压入一个初始状态 `Context`： - -{% label %}os/src/process/kernel_stack.rs{% endlabel %} -```rust -impl KernelStack { - /// 在栈顶加入 Context 并且返回新的栈顶指针 - pub fn push_context(&mut self, context: Context) -> *mut Context { - // 栈顶 - let stack_top = &self.0 as *const _ as usize + size_of::(); - // Context 的位置 - let push_address = (stack_top - size_of::()) as *mut Context; - unsafe { - *push_address = context; - } - push_address - } -} -``` - -#### 修改 `interrupt.asm` - -在这个汇编代码中，我们需要加入对 `sscratch` 的判断和使用。 - -{% label %}os/src/interrput/interrupt.asm{% endlabel %} -```asm -__interrupt: - # 因为线程当前的栈不一定可用，必须切换到内核栈来保存 Context 并进行中断流程 - # 因此，我们使用 sscratch 寄存器保存内核栈地址 - # 思考：sscratch 的值最初是在什么地方写入的？ - - # 交换 sp 和 sscratch（切换到内核栈） - csrrw sp, sscratch, sp - # 在内核栈开辟 Context 的空间 - addi sp, sp, -36*8 - - # 保存通用寄存器，除了 x0（固定为 0） - SAVE x1, 1 - # 将本来的栈地址 sp（即 x2）保存 - csrr x1, sscratch - SAVE x1, 2 - - # ... -``` - -以及事后的恢复： - -{% label %}os/src/interrupt/interrupt.asm{% endlabel %} -```asm -# 离开中断 -# 此时内核栈顶被推入了一个 Context，而 a0 指向它 -# 接下来从 Context 中恢复所有寄存器，并将 Context 出栈（用 sscratch 记录内核栈地址） -# 最后跳转至恢复的 sepc 的位置 -__restore: - # 从 a0 中读取 sp - # 思考：a0 是在哪里被赋值的？（有两种情况） - mv sp, a0 - # 恢复 CSR - LOAD t0, 32 - LOAD t1, 33 - csrw sstatus, t0 - csrw sepc, t1 - # 将内核栈地址写入 sscratch - addi t0, sp, 36*8 - csrw sscratch, t0 - - # 恢复通用寄存器 - # ... -``` - -### 小结 - -为了能够鲁棒地处理用户线程产生的异常，我们为线程准备好一个内核栈，发生中断时会切换到这里继续处理。 - -#### 思考 - -在栈的切换过程中，会不会导致一些栈空间没有被释放，或者被错误释放的情况？ diff --git a/docs/lab-4/guide/part-6.md b/docs/lab-4/guide/part-6.md deleted file mode 100644 index ccfd07b..0000000 --- a/docs/lab-4/guide/part-6.md +++ /dev/null @@ -1,86 +0,0 @@ -## 调度器 - -调度器的算法有许多种，我们将它提取出一个 trait 作为接口 - -{% label %}os/src/algorithm/src/scheduler/mod.rs{% endlabel %} -```rust -/// 线程调度器 -/// -/// 这里 `ThreadType` 就是 `Arc` -pub trait Scheduler: Default { - /// 优先级的类型 - type Priority; - /// 向线程池中添加一个线程 - fn add_thread(&mut self, thread: ThreadType); - /// 获取下一个时间段应当执行的线程 - fn get_next(&mut self) -> Option; - /// 移除一个线程 - fn remove_thread(&mut self, thread: &ThreadType); - /// 设置线程的优先级 - fn set_priority(&mut self, thread: ThreadType, priority: Self::Priority); -} -``` - -具体的算法就不在此展开了，我们可以参照目录 `os/src/algorithm/src/scheduler` 下的一些样例。 - -### 运行！ - -修改 `main.rs`，我们就可以跑起来多线程了。 - -{% label %}os/src/main.rs{% endlabel %} -```rust -pub extern "C" fn rust_main() -> ! { - memory::init(); - interrupt::init(); - - { - let mut processor = PROCESSOR.lock(); - // 创建一个内核进程 - let kernel_process = Process::new_kernel().unwrap(); - // 为这个进程创建多个线程，并设置入口均为 sample_process，而参数不同 - for i in 1..9usize { - processor.add_thread(create_kernel_thread( - kernel_process.clone(), - sample_process as usize, - Some(&[i]), - )); - } - } - - extern "C" { - fn __restore(context: usize); - } - // 获取第一个线程的 Context - let context = PROCESSOR.lock().prepare_next_thread(); - // 启动第一个线程 - unsafe { __restore(context as usize) }; - unreachable!() -} - -fn sample_process(message: usize) { - println!("hello from kernel thread {}", id); -} -``` - -运行一下，我们会得到类似的输出： - -{% label %}运行输出{% endlabel %} -``` -hello from kernel thread 7 -thread 7 exit -hello from kernel thread 6 -thread 6 exit -hello from kernel thread 5 -thread 5 exit -hello from kernel thread 4 -thread 4 exit -hello from kernel thread 3 -thread 3 exit -hello from kernel thread 2 -thread 2 exit -hello from kernel thread 1 -thread 1 exit -hello from kernel thread 8 -thread 8 exit -src/process/processor.rs:87: 'all threads terminated, shutting down' -``` diff --git a/docs/lab-4/guide/summary.md b/docs/lab-4/guide/summary.md deleted file mode 100644 index fdef69a..0000000 --- a/docs/lab-4/guide/summary.md +++ /dev/null @@ -1,25 +0,0 @@ -## 小结 - -本章我们的工作有： - -- 理清线程和进程的概念 -- 通过设置 `Context`，可以构造一个线程的初始状态 -- 通过 `__restore` 标签，直接进入第一个线程之中 -- 用 `Context` 来保存进程的状态，从而实现在时钟中断时切换线程 -- 实现内核栈，提供安全的中断处理空间 -- 实现调度器，完成线程的调度 - -同时，可以发现我们这一章的内容集中在内核线程上面，对用户进程还没有过多的提及。而为了让用户进程可以在我们的系统上运行起来，一个优美的做法将会是隔开用户程序和内核。需要注意到现在的内核还直接放在了内存上，在下一个章节，我们暂时跳过用户进程，实现可以放置用户数据的文件系统。 - -### 思考 - -可以看到我们的设计中用了大量的锁结构，很多都是为了让 Rust 知道我们是安全的，而且大部分情况下我们**仅仅**会在中断发生的时候来使用这些逻辑，这意味着，只要内核线程里面不用，就不会发生死锁，但是真的是这样吗？即使我们不在内核中使用各种 `Processor` 和 `Thread` 等等的逻辑，仅仅完成一些简单的运算，真的没有死锁吗？ - -{% reveal %} -> 会有死锁，比如我们在内核线程中构造一个 `Vec`，然后在里面 push 几个元素，这个时候就可能产生死锁。 -> -> 需要注意到，我们的动态分配器是一个 `LockedHeap`，是外面加了锁的一个分配器，如果在线程里面 push 的过程中需要动态分配，然后正好在上完锁而且没有释放锁的时候产生了中断，而中断中我们的 `Scheduler` 也用到了 `Vec`，这个时候会再去锁住，但是又拿不到，同时需要注意的是在处理中断本身时，我们的时钟中断是关掉的，这意味着我们的锁会一直去申请，就形成了类似死锁的死循环。 -> -> 解决这个问题需要把申请到锁之后加上关闭中断，通过这种抢占式的方法彻底执行完分配逻辑之后再关闭锁同时打开中断。这个问题是一个设计上的取舍，如果我们不支持内核抢占，就需要很多精妙的设计来绕开这个问题。在这里，我们先不会理会这个问题。 -> -{% endreveal %} \ No newline at end of file diff --git a/docs/lab-4/practice-1.md b/docs/lab-4/practice-1.md deleted file mode 100644 index 76d1e95..0000000 --- a/docs/lab-4/practice-1.md +++ /dev/null @@ -1,37 +0,0 @@ -## 实验四（上）：线程 - -### 实验之前 - -- 阅读实验指导四。 -- 从本次实验起，我们将不再提供“截至当前章节的代码框架”。你可以直接在 `master` 分支上查看代码，因为后面章节基本只会添加代码而鲜有修改。 -- 实验用到的代码在 `lab-4` 分支上，与 `master` 稍有修改。 - -### 实验题目 - -1. 原理：线程切换之中，页表是何时切换的？页表的切换会不会影响程序 / 操作系统的运行？为什么？ - - {% reveal %} -> 页表是在 `Process::prepare_next_thread()` 中调用 `Thread::prepare()`，其中换入了新线程的页表。 -> -> 它不会影响执行，因为在中断期间是操作系统正在执行，而操作系统所用到的内核线性映射是存在于每个页表中的。 - {% endreveal %} - -
-2. 设计：如果不使用 `sscratch` 提供内核栈，而是像原来一样，遇到中断就直接将上下文压栈，请举出（思路即可，无需代码）： - - 一种情况不会出现问题 - - 一种情况导致异常无法处理（指无法进入 `handle_interrupt`） - - 一种情况导致产生嵌套异常（指第二个异常能够进行到调用 `handle_interrupt`，不考虑后续执行情况） - - 一种情况导致一个用户进程（先不考虑是怎么来的）可以将自己变为内核进程，或以内核态执行自己的代码 - - {% reveal %} -> - 只运行一个非常善意的线程，比如 `loop {}` -> - 线程把自己的 `sp` 搞丢了，比如 `mv sp, x0`。此时无法保存寄存器，也没有能够支持操作系统正常运行的栈 -> - 运行两个线程。在两个线程切换的时候，会需要切换页表。但是此时操作系统运行在前一个线程的栈上，一旦切换，再访问栈就会导致缺页，因为每个线程的栈只在自己的页表中 -> - 用户进程巧妙地设计 `sp`，使得它恰好落在内核的某些变量附近，于是在保存寄存器时就修改了变量的值。这相当于任意修改操作系统的控制信息 - {% endreveal %} - -
-3. 实验：当键盘按下 Ctrl + C 时，操作系统应该能够捕捉到中断。实现操作系统捕获该信号并结束当前运行的线程（你可能需要阅读一点在实验指导中没有提到的代码） - -
-4. 实验：实现线程的 `clone()`。目前的内核线程不能进行系统调用，所以我们先简化地实现为“按 C 进行 clone”。clone 后应当为目前的线程复制一份几乎一样的拷贝，新线程与旧线程同属一个进程，公用页表和大部分内存空间，而新线程的栈是一份拷贝。 diff --git a/docs/lab-4/practice-2.md b/docs/lab-4/practice-2.md deleted file mode 100644 index 6ed2d21..0000000 --- a/docs/lab-4/practice-2.md +++ /dev/null @@ -1,10 +0,0 @@ -## 实验四（下）：线程调度 - -### 实验题目 - -1. 实验：了解并实现 Stride Scheduling 调度算法，为不同线程设置不同优先级，使得其获得与优先级成正比的运行时间。 - -2. 分析： - - 在 Stride Scheduling 算法下，如果一个线程进入了一段时间的等待（例如等待输入，此时它不会被运行），会发生什么？ - - 对于两个优先级分别为 9 和 1 的线程，连续 10 个时间片中，前者的运行次数一定更多吗？ - - 你认为 Stride Scheduling 算法有什么不合理之处？可以怎样改进？ diff --git a/docs/lab-5/files/rcore-fs-analysis.pdf b/docs/lab-5/files/rcore-fs-analysis.pdf deleted file mode 100644 index 10bb570..0000000 Binary files a/docs/lab-5/files/rcore-fs-analysis.pdf and /dev/null differ diff --git a/docs/lab-5/guide/intro.md b/docs/lab-5/guide/intro.md deleted file mode 100644 index ea79597..0000000 --- a/docs/lab-5/guide/intro.md +++ /dev/null @@ -1,10 +0,0 @@ -# 实验指导五 - -## 实验概要 - -这一章的实验指导中，你将会学到： - -- 设备树的概念和读取 -- virtio 总线协议 -- 块设备驱动的实现 -- 将块设备托管给文件系统 \ No newline at end of file diff --git a/docs/lab-5/guide/part-1.md b/docs/lab-5/guide/part-1.md deleted file mode 100644 index 1fb933f..0000000 --- a/docs/lab-5/guide/part-1.md +++ /dev/null @@ -1,85 +0,0 @@ -## 设备树 - -### 从哪里读取设备信息 - -既然我们要实现把数据放在某个存储设备上并让操作系统来读取，首先操作系统就要有一个读取全部已接入设备信息的能力，而设备信息放在哪里又是谁帮我们来做的呢？这个问题其实在[物理内存探测](../../lab-2/guide/part-2.md)中就提到过，在 RISC-V 中，这个一般是由 bootloader，即 OpenSBI 固件完成的。它来完成对于包括物理内存在内的各外设的扫描，将扫描结果以**设备树二进制对象（DTB，Device Tree Blob）**的格式保存在物理内存中的某个地方。而这个放置的物理地址将放在 `a1` 寄存器中，而将会把 HART ID （**HART，Hardware Thread，硬件线程，可以理解为执行的 CPU 核**）放在 `a0` 寄存器上。 - -在我们之前的函数中并没有使用过这两个参数，如果要使用，我们不需要修改任何入口汇编的代码，只需要给 `rust_main` 函数增加两个参数即可： - -{% label %}os/src/main.rs{% endlabel %} -```rust -/// Rust 的入口函数 -/// -/// 在 `_start` 为我们进行了一系列准备之后，这是第一个被调用的 Rust 函数 -#[no_mangle] -pub extern "C" fn rust_main(_hart_id: usize, dtb_pa: PhysicalAddress) -> ! { - memory::init(); - interrupt::init(); - drivers::init(dtb_pa); - ... -} -``` - -打印输出一下，`dtb_pa` 变量约在 0x82200000 附近，而内核结束的地址约为 0x80b17000，也就是在我们内核的后面放着，这意味着当我们内核代码超过 32MB 的时候就会出现问题，在更好的实现中，其实 OpenSBI 固件启动的应该是第二级小巧的 Bootloader，而我们现在全部内核内容都在内存中且也没 32MB 那么大，我们暂时不理会这个问题。 - -### 设备树 - -上面提到 OpenSBI 固件会把设备信息以设备树的格式放在某个地址上，哪设备树格式究竟是怎样的呢？在各种操作系统中，我们打开设备管理器（Windows）和系统报告（macOS）等内置的系统软件就可以看到我们使用的电脑的设备树，一个典型的设备树如下图所示： - -
- -每个设备在物理上连接到了父设备上最后再通过总线等连接起来构成一整个设备树，在每个节点上都描述了对应设备的信息，如支持的协议是什么类型等等。而操作系统就是通过这些节点上的信息来实现对设备的识别的。 - -> **[info] 设备节点属性** -> -> 具体而言，一个设备节点上会有几个标准属性，这里简要介绍我们需要用到的几个： -> -> - compatible：该属性指的是该设备的编程模型，一般格式为 "manufacturer,model"，分别指一个出厂标签和具体模型。如 "virtio,mmio" 指的是这个设备通过 virtio 协议、MMIO（内存映射 I/O）方式来驱动 -> - model：指的是设备生产商给设备的型号 -> - reg：当一些很长的信息或者数据无法用其他标准属性来定义时，可以用 reg 段来自定义存储一些信息 -> -> 设备树是一个比较复杂的标准，更多细节可以参考 [Device Tree Reference](https://elinux.org/Device_Tree_Reference)。 - -### 解析设备树 - -对于上面的属性，我们不需要自己来实现这件事情，可以直接调用 rCore 中 device_tree 库，然后遍历树上节点即可： - -{% label %}os/src/drivers/device_tree.rs{% endlabel %} -```rust -/// 递归遍历设备树 -fn walk(node: &Node) { - // 检查设备的协议支持并初始化 - if let Ok(compatible) = node.prop_str("compatible") { - if compatible == "virtio,mmio" { - virtio_probe(node); - } - } - // 遍历子树 - for child in node.children.iter() { - walk(child); - } -} - -/// 整个设备树的 Headers（用于验证和读取） -struct DtbHeader { - magic: u32, - size: u32, -} - -/// 遍历设备树并初始化设备 -pub fn init(dtb_va: VirtualAddress) { - let header = unsafe { &*(dtb_va.0 as *const DtbHeader) }; - // from_be 是大小端序的转换（from big endian） - let magic = u32::from_be(header.magic); - if magic == DEVICE_TREE_MAGIC { - let size = u32::from_be(header.size); - // 拷贝数据，加载并遍历 - let data = unsafe { slice::from_raw_parts(dtb_va.0 as *const u8, size as usize) }; - if let Ok(dt) = DeviceTree::load(data) { - walk(&dt.root); - } - } -} -``` - -注：在开始的时候，有一步来验证 Magic Number，这一步是一个保证系统可靠性的要求，是为了验证这段内存到底是不是设备树。在遍历过程中，一旦发现了一个支持 "virtio,mmio" 的设备（其实就是 QEMU 模拟的存储设备），就进入下一步加载驱动的逻辑。 diff --git a/docs/lab-5/guide/part-2.md b/docs/lab-5/guide/part-2.md deleted file mode 100644 index a07415a..0000000 --- a/docs/lab-5/guide/part-2.md +++ /dev/null @@ -1,148 +0,0 @@ -## virtio - -### 挂载到 QEMU - -为了让 QEMU 挂载上我们虚拟的存储设备，我们这里选了 QEMU 支持的 virtio 协议，需要在 QEMU 运行的时候加入选项： - -{% label %}os/Makefile{% endlabel %} -```Makefile -# 运行 QEMU -qemu: build - @qemu-system-riscv64 \ - -machine virt \ - -nographic \ - -bios default \ - -device loader,file=$(BIN_FILE),addr=0x80200000 \ - -drive file=$(TEST_IMG),format=raw,id=sfs \ # 模拟存储设备 - -device virtio-blk-device,drive=sfs # 以 virtio Block Device 的形式挂载到 virtio 总线上 -``` - -其中的 `TEST_IMG` 是特定文件系统格式的磁盘镜像，我们在本小节还不会提及到这个概念，这里可以直接用目录下的测试镜像。 - -### 什么是 virtio - -virtio 起源于 [virtio: Towards a De-Facto Standard For Virtual I/O Devices](https://www.ozlabs.org/~rusty/virtio-spec/virtio-paper.pdf) 这篇论文，主要针对于半虚拟化技术中对通用设备的抽象。 - -> **[info] 完全虚拟化和半虚拟化** -> -> 在完全虚拟化中，被虚拟的操作系统运行在位于物理机器上的 Hypervisor 之上。被虚拟的操作系统并不知道它已被虚拟化，并且不需要任何更改就可以在该配置下工作。相反，在半虚拟化中，被虚拟的操作系统不仅知道它运行在 Hypervisor 之上，还包含让被虚拟的操作系统更高效地过渡到 Hypervisor 的代码。 -> -> 在完全虚拟化模式中，Hypervisor 必须模拟设备硬件，它是在会话的最低级别进行模拟的（例如，网络驱动程序）。尽管在该抽象中模拟很干净，但它同时也是最低效、最复杂的。在半虚拟化模式中，被虚拟的操作系统和 Hypervisor 能够共同合作，让模拟更加高效。半虚拟化方法的缺点是操作系统知道它被虚拟化，并且需要修改才能工作。 - -具体来说，virtio 的架构如图所示： - -
- -以 virtio 为中心的总线下又挂载了 virtio-blk（块设备）总线、virtio-net（网络设备）总线、virtio-pci（PCI 设备）总线等，本身就构成一个设备树。 - -### virtio 节点探测 - -在上一节中，我们实现了对 "virtio,mmio" 的节点的判断，下面我们进一步来区分上面提到的那些 virtio 设备： - -{% label %}os/src/drivers/bus/virtio_mmio.rs{% endlabel %} -```rust -/// 从设备树的某个节点探测 virtio 协议具体类型 -pub fn virtio_probe(node: &Node) { - // reg 属性中包含了描述设备的 Header 的位置 - let reg = match node.prop_raw("reg") { - Some(reg) => reg, - _ => return, - }; - let pa = PhysicalAddress(reg.as_slice().read_be_u64(0).unwrap() as usize); - let va = VirtualAddress::from(pa); - let header = unsafe { &mut *(va.0 as *mut VirtIOHeader) }; - // 目前只支持某个特定版本的 virtio 协议 - if !header.verify() { - return; - } - // 判断设备类型 - match header.device_type() { - DeviceType::Block => virtio_blk::add_driver(header), - device => println!("unrecognized virtio device: {:?}", device), - } -} -``` - -从设备树节点的 reg 信息中可以读出设备更详细信息的放置位置（如：在 0x10000000 - 0x10010000 ），这段区间虽然算是内存区间，但是还记得的吗？我们的物理内存只分布在 0x80000000 到 0x88000000 的空间中，那这段空间哪里来的呢？这就是所谓的**内存映射读写 MMIO（Memory Mapped I/O）**，也就是总线把对设备操作信息传递也映射成了内存的一部分，CPU 操作设备和访问内存的形式没有任何的区别，但读写效果是不同的。大家可以回忆一下计算机组成原理中对串口的访问，这里是一个道理。 - -所以，为了访问这段地址，我们也需要把它加到页表里面，分别对应在 `os/src/entry.asm` 中的 `boot_page_table` 以及 `os/src/memory/mapping/memory_set.rs` 的新建内核线程中加入了这段地址，使得我们的内核线程可以访问他们。 - -### virtio_drivers 库 - -我们在这里不会自己来实现驱动的每一个细节，同样的，我们使用 rCore 中的 virtio_drivers 库，这个库会帮我们通过 MMIO 的方式对设备进行交互，同时我们也需要给这个库提供一些诸如申请物理内存、物理地址虚拟转换等接口。 - -{% label %}os/src/drivers/bus/virtio_mmio.rs{% endlabel %} -```rust -lazy_static! { - /// 用于放置给设备 DMA 所用的物理页（[`FrameTracker`]） - pub static ref TRACKERS: RwLock> = - RwLock::new(BTreeMap::new()); -} - -/// 为 DMA 操作申请连续 pages 个物理页（为 [`virtio_drivers`] 库提供） -/// -/// 为什么要求连续的物理内存？设备的 DMA 操作只涉及到内存和对应设备 -/// 这个过程不会涉及到 CPU 的 MMU 机制，我们只能给设备传递物理地址 -/// 而陷于我们之前每次只能分配一个物理页的设计，这里我们假设我们连续分配的地址是连续的 -#[no_mangle] -extern "C" fn virtio_dma_alloc(pages: usize) -> PhysicalAddress { - let mut pa: PhysicalAddress = Default::default(); - let mut last: PhysicalAddress = Default::default(); - for i in 0..pages { - let tracker: FrameTracker = FRAME_ALLOCATOR.lock().alloc().unwrap(); - if i == 0 { - pa = tracker.address(); - } else { - assert_eq!(last + PAGE_SIZE, tracker.address()); - } - last = tracker.address(); - TRACKERS.write().insert(last, tracker); - } - return pa; -} - -/// 为 DMA 操作释放对应的之前申请的连续的物理页（为 [`virtio_drivers`] 库提供） -#[no_mangle] -extern "C" fn virtio_dma_dealloc(pa: PhysicalAddress, pages: usize) -> i32 { - for i in 0..pages { - TRACKERS.write().remove(&(pa + i * PAGE_SIZE)); - } - 0 -} - -/// 将物理地址转为虚拟地址（为 [`virtio_drivers`] 库提供） -/// -/// 需要注意，我们在 0xffffffff80200000 到 0xffffffff88000000 是都有对应的物理地址映射的 -/// 因为在内核重映射的时候，我们已经把全部的段放进去了 -/// 所以物理地址直接加上 Offset 得到的虚拟地址是可以通过任何内核进程的页表来访问的 -#[no_mangle] -extern "C" fn virtio_phys_to_virt(pa: PhysicalAddress) -> VirtualAddress { - VirtualAddress::from(pa) -} - -/// 将虚拟地址转为物理地址（为 [`virtio_drivers`] 库提供） -/// -/// 需要注意，实现这个函数的目的是告诉 DMA 具体的请求，请求在实现中会放在栈上面 -/// 而在我们的实现中，栈是以 Framed 的形式分配的，并不是高地址的线性映射 Linear -/// 为了得到正确的物理地址并告诉 DMA 设备，我们只能查页表 -#[no_mangle] -extern "C" fn virtio_virt_to_phys(va: VirtualAddress) -> PhysicalAddress { - Mapping::lookup(va).unwrap() -} -``` - -至于为什么要实现这些操作，是因为本身设备是通过**直接内存访问DMA（Direct Memory Access）**技术来实现数据传输的，CPU 只需要给出要传输哪些内容，放在哪段物理内存上面，把请求告诉设备，设备后面的操作就会利用 DMA 而不经过 CPU 直接传输，在传输结束之后，会通过**中断请求 IRQ（Interrupt ReQuest）**技术沿着设备树把"我做完了"这个信息告诉 CPU，CPU 会作为一个中断进一步处理。而为了实现 DMA，我们需要一些请求和内存空间，比如让磁盘把数据传到某个内存段，我们需要告诉设备内存的物理地址（之所以不是虚拟地址是因为 DMA 不会经过 CPU 的 MMU 技术），而且这个物理地址最好是连续的。同时，我们在栈上申请一个请求的结构，这个结构的物理地址也要告诉设备，所以也需要一些虚实地址转换的接口。 - -现在，我们的 `FRAME_ALLOCATOR` 还只能分配一个帧出来，我们连续调用，暂时先假设他是连续的。同时注意到，为了实现虚实物理转换，我们需要查找页表，很不幸的是 RISC-V 并没有给我提供一个很方便的根据当前页表找到物理地址的指令，所以这里我们在 `os/src/memory/mapping/mapping.rs` 中实现了一个类似的功能。 - -### 思考 - -为什么物理地址到虚拟地址转换直接线性映射，而虚拟地址到物理地址却要查表？ - -{% reveal %} -> 我们拿到地址的究极目的是访问地址上的内容，需要注意到在 0x80000000 到 0x88000000 的区间的物理页有可能对应着两个虚拟页，我们在启动或是新建内核线程的时候都包含诸如 0xffffffff80000000 到 0x80000000 这样的线性映射，这意味着，在内核线程里面，只要一个物理地址加上偏移得到的虚拟地址肯定是可以访问对应的物理地址的。所以，把物理地址转为虚拟地址加个偏移既可。 -> -> 也需要注意到，内核线程虽然代码和数据都是线性映射的，但是内核栈是以 Frame 为单位分配的（除了 boot 线程是直接放在 .bss 中），而以 Frame 为单位分配意味着，虚拟地址可能从 0 开始，这个时候要转为物理地址，显然不是减去偏移量的线性映射，而必须查当前的表。 -> -> 这个时候，你可能问了：为什么 RISC-V 处理器可以通过虚拟地址来访问，但是我还要手写查表来做这件事呢？这是因为 RISC-V 还真没有直接用 MMU 得到地址的指令，我们只能手写。 -{% endreveal %} diff --git a/docs/lab-5/guide/part-3.md b/docs/lab-5/guide/part-3.md deleted file mode 100644 index 016b6fc..0000000 --- a/docs/lab-5/guide/part-3.md +++ /dev/null @@ -1,137 +0,0 @@ -## 驱动和块设备驱动 - -### 什么是块设备 - -注意到我们在介绍 virtio 时提到了 virtio-blk 设备，这种设备提供了以整块为粒度的读和写操作，一般对应到真实的物理设备是那种硬盘。而之所以是以块为单位是为了加快读写的速度，毕竟硬盘等设备还需要寻道等等操作，一次性读取很大的一块将会节约很多时间。 - -### 抽象驱动 - -在写块设备驱动之前，我们先抽象驱动的概念，也方便后面网络设备等的介入。 - -{% label %}os/src/drivers/driver.rs{% endlabel %} -```rust -/// 驱动类型 -/// -/// 目前只有块设备，可能还有网络、GPU 设备等 -#[derive(Debug, Eq, PartialEq)] -pub enum DeviceType { - Block, -} - -/// 驱动的接口 -pub trait Driver: Send + Sync { - /// 设备类型 - fn device_type(&self) -> DeviceType; - - /// 读取某个块到 buf 中（块设备接口） - fn read_block(&self, _block_id: usize, _buf: &mut [u8]) -> bool { - unimplemented!("not a block driver") - } - - /// 将 buf 中的数据写入块中（块设备接口） - fn write_block(&self, _block_id: usize, _buf: &[u8]) -> bool { - unimplemented!("not a block driver") - } -} - -lazy_static! { - /// 所有驱动 - pub static ref DRIVERS: RwLock>> = RwLock::new(Vec::new()); -} -``` - -这里暂时只有块设备这个种类，不过这样写还是为了方便未来的扩展。 - -### 抽象块设备 - -有了驱动的概念，我们进一步抽象块设备： - -{% label %}os/src/drivers/block/mod.rs{% endlabel %} -```rust -/// 块设备抽象（驱动的引用） -pub struct BlockDevice(pub Arc); - -/// 为 [`BlockDevice`] 实现 [`rcore-fs`] 中 [`BlockDevice`] trait -/// -/// 使得文件系统可以通过调用块设备的该接口来读写 -impl dev::BlockDevice for BlockDevice { - /// 每个块的大小（取 2 的对数） - /// - /// 这里取 512B 是因为 virtio 驱动对设备的操作粒度为 512B - const BLOCK_SIZE_LOG2: u8 = 9; - - /// 读取某个块到 buf 中 - fn read_at(&self, block_id: usize, buf: &mut [u8]) -> dev::Result<()> { - match self.0.read_block(block_id, buf) { - true => Ok(()), - false => Err(dev::DevError), - } - } - - /// 将 buf 中的数据写入块中 - fn write_at(&self, block_id: usize, buf: &[u8]) -> dev::Result<()> { - match self.0.write_block(block_id, buf) { - true => Ok(()), - false => Err(dev::DevError), - } - } - - /// 执行和设备的同步 - /// - /// 因为我们这里全部为阻塞 I/O 所以不存在同步的问题 - fn sync(&self) -> dev::Result<()> { - Ok(()) - } -} -``` - -这里所谓的 `BlockDevice` 其实就是一个 `Driver` 的引用。而且利用 rcore-fs 中提供的 `BlockDevice` trait 实现了为文件系统的接口，实际上是对上传文件系统的连接。 - -### virtio-blk 块设备驱动 - -最后，我们来实现 virtio-blk 的驱动（主要通过调用现成的库完成）： - -{% label %}os/src/drivers/block/virtio_blk.rs{% endlabel %} -```rust -/// virtio 协议的块设备驱动 -struct VirtIOBlkDriver(Mutex>); - -/// 为 [`VirtIOBlkDriver`] 实现 [`Driver`] trait -/// -/// 调用了 [`virtio_drivers`] 库，其中规定的块大小为 512B -impl Driver for VirtIOBlkDriver { - /// 设备类型 - fn device_type(&self) -> DeviceType { - DeviceType::Block - } - - /// 读取某个块到 buf 中 - fn read_block(&self, block_id: usize, buf: &mut [u8]) -> bool { - self.0.lock().read_block(block_id, buf).is_ok() - } - - /// 将 buf 中的数据写入块中 - fn write_block(&self, block_id: usize, buf: &[u8]) -> bool { - self.0.lock().write_block(block_id, buf).is_ok() - } -} - -/// 将从设备树中读取出的设备信息放到 [`static@DRIVERS`] 中 -pub fn add_driver(header: &'static mut VirtIOHeader) { - let virtio_blk = VirtIOBlk::new(header).expect("failed to init blk driver"); - let driver = Arc::new(VirtIOBlkDriver(Mutex::new(virtio_blk))); - DRIVERS.write().push(driver.clone()); -} -``` - -需要注意的是，现在的逻辑怎么看都不像是之前提到的**异步 DMA + IRQ 中断**的高级 I/O 操作技术，而更像是阻塞的读取。实际上的确是阻塞的读取，目前 virtio-drivers 库中的代码虽然调用了 DMA，但是返回时还是阻塞的逻辑，我们这里为了简化也没有设计 IRQ 的响应机制。 - - - -### 小结 - -至此，我们完成了全部的驱动逻辑，我们总结一下目前的设计模式如下所示： - -
- -其中 `Driver` 作为一个核心 trait 为上提供实现，上层也就是 `Driver` 的使用侧（设备的抽象），而下层则是 `Driver` 的实现侧（设备的实现）。而下一个小节，我们将利用这些驱动来实现文件系统。 diff --git a/docs/lab-5/guide/part-4.md b/docs/lab-5/guide/part-4.md deleted file mode 100644 index d52a8af..0000000 --- a/docs/lab-5/guide/part-4.md +++ /dev/null @@ -1,121 +0,0 @@ -## 文件系统 - -之前我们在加载 QEMU 的时候引入了一个磁盘镜像文件，这个文件的打包是由 [rcore-fs-fuse 工具](https://github.com/rcore-os/rcore-fs/tree/master/rcore-fs-fuse) 来完成的，它会根据不同的格式把目录的文件封装成到一个文件系统中，并把文件系统封装为一个磁盘镜像文件。然后我们把这个镜像文件像设备一样挂载在 QEMU 上，QEMU 就把它模拟为一个块设备了。接下来我们需要让操作系统理解块设备里面的文件系统。 - -### Simple File System - -因为文件系统本身比较庞大，我们这里还是用了 rCore 中的文件系统模块 [rcore-fs](https://github.com/rcore-os/rcore-fs)，其中实现了很多格式的文件系统，我们这里选择最简单的 Simple File System（这也是为什么 QEMU 中的设备 id 为 `sfs`），关于文件系统的细节，这里将不展开描述，可以参考[前人的分析](../files/rcore-fs-analysis.pdf)。 - -不过，为了使用这个模块，一个自然的想法是存取根目录的 `INode`（一个 `INode` 是对一个文件的位置抽象，目录也是文件的一种），后面对于文件系统的操作都可以通过根目录来实现。 - -### 实现 - -这里我们用到了我们的老朋友 `lazy_static` 宏，将会在我们第一次使用 `ROOT_INODE` 时进行初始化，而初始化的方式是找到全部设备驱动中的第一个存储设备作为根目录。 - -{% label %}os/src/fs/mod.rs{% endlabel %} -```rust -lazy_static! { - /// 根文件系统的根目录的 INode - pub static ref ROOT_INODE: Arc = { - // 选择第一个块设备 - for driver in DRIVERS.read().iter() { - if driver.device_type() == DeviceType::Block { - let device = BlockDevice(driver.clone()); - // 动态分配一段内存空间作为设备 Cache - let device_with_cache = Arc::new(BlockCache::new(device, BLOCK_CACHE_CAPACITY)); - return SimpleFileSystem::open(device_with_cache) - .expect("failed to open SFS") - .root_inode(); - } - } - panic!("failed to load fs") - }; -} -``` - -同时，还可以注意到我们也加入了一个 `BlockCache`，该模块也是 rcore-fs 提供的，提供了一个存储设备在内存 Cache 的抽象，通过调用 `BlockCache::new(device, BLOCK_CACHE_CAPACITY)` 就可以把 `device` 自动变为一个有 Cache 的设备。最后我们用 `SimpleFileSystem::open` 打开并返回根节点即可。 - -### 测试 - -终于到了激动人心的测试环节了！我们首先在触发一下 `ROOT_INODE` 的初始化，然后尝试输出一下根目录的内容： - -{% label %}os/src/fs/mod.rs{% endlabel %} -```rust -/// 打印某个目录的全部文件 -pub fn ls(path: &str) { - let mut id = 0; - let dir = ROOT_INODE.lookup(path).unwrap(); - print!("files in {}: \n ", path); - while let Ok(name) = dir.get_entry(id) { - id += 1; - print!("{} ", name); - } - print!("\n"); -} - -/// 触发 [`static@ROOT_INODE`] 的初始化并打印根目录内容 -pub fn init() { - ls("/"); - println!("mod fs initialized"); -} -``` - -最后在主函数中测试初始化，然后测试在另一个内核线程中创建个文件夹，而之所以在另一个线程中做是为了验证我们之前写驱动涉及到的页表的那些操作： - -{% label %}os/src/fs/mod.rs{% endlabel %} -```rust -/// Rust 的入口函数 -/// -/// 在 `_start` 为我们进行了一系列准备之后，这是第一个被调用的 Rust 函数 -#[no_mangle] -pub extern "C" fn rust_main(_hart_id: usize, dtb_pa: PhysicalAddress) -> ! { - memory::init(); - interrupt::init(); - drivers::init(dtb_pa); - fs::init(); - - let process = Process::new_kernel().unwrap(); - - PROCESSOR - .lock() - .add_thread(Thread::new(process.clone(), simple as usize, Some(&[0])).unwrap()); - - // 把多余的 process 引用丢弃掉 - drop(process); - - PROCESSOR.lock().run() -} - -/// 测试任何内核线程都可以操作文件系统和驱动 -fn simple(id: usize) { - println!("hello from thread id {}", id); - // 新建一个目录 - fs::ROOT_INODE - .create("tmp", rcore_fs::vfs::FileType::Dir, 0o666) - .expect("failed to mkdir /tmp"); - // 输出根文件目录内容 - fs::ls("/"); - - loop {} -} -``` - -`make run` 一下，你会得到类似的输出： - -{% label %}运行输出{% endlabel %} -``` -mod memory initialized -mod interrupt initialized -mod driver initialized -files in /: - . .. temp rust -mod fs initialized -hello from thread id 0 -files in /: - . .. temp rust tmp -100 tick -200 tick -... -``` - -成功了！我们可以看到系统正确的读出了文件，而且也正确地创建了文件，这为后面用户进程数据的放置提供了很好的保障。 diff --git a/docs/lab-5/guide/summary.md b/docs/lab-5/guide/summary.md deleted file mode 100644 index 8172d6b..0000000 --- a/docs/lab-5/guide/summary.md +++ /dev/null @@ -1,11 +0,0 @@ -## 小结 - -本章我们的工作有： - -- 在 QEMU 上挂载了存储设备 -- 通过读取设备树找到了挂载的设备 -- 实现了 virtio 驱动，把物理设备抽象为了驱动 -- 进一步把驱动抽象给上层文件系统使用 -- 调用 rcore-fs 的文件系统实现对文件的管理 - -现在，我们再也不会担心用户数据没有地方放置了，在下一个章节中，我们将实现用户进程，并让内核把用户进程加载和运行，实现和用户进程的交互。 diff --git a/docs/lab-5/pics/design.key b/docs/lab-5/pics/design.key deleted file mode 100755 index 3062fb8..0000000 Binary files a/docs/lab-5/pics/design.key and /dev/null differ diff --git a/docs/lab-5/pics/design.png b/docs/lab-5/pics/design.png deleted file mode 100644 index 44c128d..0000000 Binary files a/docs/lab-5/pics/design.png and /dev/null differ diff --git a/docs/lab-5/pics/device-tree.png b/docs/lab-5/pics/device-tree.png deleted file mode 100644 index b4a9a74..0000000 Binary files a/docs/lab-5/pics/device-tree.png and /dev/null differ diff --git a/docs/lab-5/pics/virtio.gif b/docs/lab-5/pics/virtio.gif deleted file mode 100644 index 629d35b..0000000 Binary files a/docs/lab-5/pics/virtio.gif and /dev/null differ diff --git a/docs/lab-6/guide/intro.md b/docs/lab-6/guide/intro.md deleted file mode 100644 index b175b7a..0000000 --- a/docs/lab-6/guide/intro.md +++ /dev/null @@ -1,9 +0,0 @@ -# 实验指导六 - -## 实验概要 - -这一章的实验指导中，你将会学到： - -- 单独生成 ELF 格式的用户程序，并打包进文件系统中 -- 创建并运行用户进程 -- 使用系统调用为用户程序提供服务 diff --git a/docs/lab-6/guide/part-1.md b/docs/lab-6/guide/part-1.md deleted file mode 100644 index 74ef6a9..0000000 --- a/docs/lab-6/guide/part-1.md +++ /dev/null @@ -1,40 +0,0 @@ -## 构建用户程序框架 - -接下来我们要做的工作，和实验准备中为操作系统「去除依赖」的工作十分类似：我们需要为用户程序提供一个类似的没有Rust std标准运行时依赖的极简运行时环境。这里我们会快速梳理一遍我们为用户程序进行的流程。 - -### 建立 crate - -我们在 `os` 的旁边建立一个 `user` crate。此时，我们移除默认的 `main.rs`，而是在 `src` 目录下建立 `lib` 和 `bin` 子目录， 在 `lib` 中存放的是极简运行时环境，在 `bin` 中存放的源文件会被编译成多个单独的执行文件。 - -{% label %}运行命令{% endlabel %} -```bash -cargo new --bin user -``` - -{% label %}目录结构{% endlabel %} -``` -rCore-Tutorial - - os - - user - - src - - bin - - hello_world.rs - - lib.rs - - Cargo.toml -``` - -### 基础框架搭建 - -和操作系统一样，我们需要为用户程序移除 std 依赖，并且补充一些必要的功能。 - -#### `lib.rs` - -- `#![no_std]` 移除标准库 -- `#![feature(...)]` 开启一些不稳定的功能 -- `#[global_allocator]` 使用库来实现动态内存分配 -- `#[panic_handler]` panic 时终止 - -#### 其他文件 - -- `.cargo/config` 设置编译目标为 RISC-V 64 -- `console.rs` 实现 `print!` `println!` 宏 diff --git a/docs/lab-6/guide/part-2.md b/docs/lab-6/guide/part-2.md deleted file mode 100644 index 22b9975..0000000 --- a/docs/lab-6/guide/part-2.md +++ /dev/null @@ -1,37 +0,0 @@ -## 打包为磁盘镜像 - -在上一章我们已经实现了文件系统，并且可以让操作系统加载磁盘镜像。现在，我们只需要利用工具将编译后的用户程序打包为镜像，就可以使用了。 - -### 工具安装 - -通过 cargo 来安装 `rcore-fs-fuse` 工具： - -{% label %}运行命令{% endlabel %} -```bash -cargo install rcore-fs-fuse --git https://github.com/rcore-os/rcore-fs -``` - -### 打包 - -这个工具可以将一个目录打包成 SimpleFileSystem 格式的磁盘镜像。为此，我们需要将编译得到的 ELF 文件单独放在一个导出目录中，即 `user/build/disk`。 - -{% label %}user/Makefile{% endlabel %} -```makefile -build: dependency - # 编译 - @cargo build - @echo Targets: $(patsubst $(SRC_DIR)/%.rs, %, $(SRC_FILES)) - # 移除原有的所有文件 - @rm -rf $(OUT_DIR) - @mkdir -p $(OUT_DIR) - # 复制编译生成的 ELF 至目标目录 - @cp $(BIN_FILES) $(OUT_DIR) - # 使用 rcore-fs-fuse 工具进行打包 - @rcore-fs-fuse --fs sfs $(IMG_FILE) $(OUT_DIR) zip - # 将镜像文件的格式转换为 QEMU 使用的高级格式 - @qemu-img convert -f raw $(IMG_FILE) -O qcow2 $(QCOW_FILE) - # 提升镜像文件的容量（并非实际大小），来允许更多数据写入 - @qemu-img resize $(QCOW_FILE) +1G -``` - -在 `os/Makefile` 中指定我们新生成的 `QCOW_FILE` 为加载镜像，就可以在操作系统中看到打包好的目录了。 diff --git a/docs/lab-6/guide/part-3.md b/docs/lab-6/guide/part-3.md deleted file mode 100644 index 1e7665e..0000000 --- a/docs/lab-6/guide/part-3.md +++ /dev/null @@ -1,123 +0,0 @@ -## 解析 ELF 文件并创建线程 - -在之前实现内核线程时，我们只需要为线程指定一个起始位置就够了，因为所有的代码都在操作系统之中。但是现在，我们需要从 ELF 文件中加载用户程序的代码和数据信息，并且映射到内存中。 - -当然，我们不需要自己实现 ELF 文件解析器，因为有 `xmas-elf` 这个 crate 替我们实现了 ELF 的解析。 - -### `xmas-elf` 解析器 - -tips：如果 IDE 无法对其中的类型进行推断，可以在 rustdoc 中找到该 crate 进行查阅。 - -#### 读取文件内容 - -`xmas-elf` 需要将 ELF 文件首先读取到内存中。在上一章文件系统的基础上，我们很容易为 `INode` 添加一个将整个文件作为 `[u8]` 读取出来的方法： - -{% label %}os/src/fs/inode_ext.rs{% endlabel %} -```rust -fn readall(&self) -> Result> { - // 从文件头读取长度 - let size = self.metadata()?.size; - // 构建 Vec 并读取 - let mut buffer = Vec::with_capacity(size); - unsafe { buffer.set_len(size) }; - self.read_at(0, buffer.as_mut_slice())?; - Ok(buffer) -} -``` - -### 解析各个字段 - -对于 ELF 中的不同字段，其存放的地址通常是不连续的，同时其权限也会有所不同。我们利用 `xmas-elf` 库中的接口，便可以从读出的 ELF 文件中对应建立 `MemorySet`。 - -注意到，用户程序也会首先映射所有内核态的空间，否则将无法进行中断处理。 - -{% label %}os/src/memory/mapping/memory_set.rs{% endlabel %} -```rust -/// 通过 elf 文件创建内存映射（不包括栈） -pub fn from_elf(file: &ElfFile, is_user: bool) -> MemoryResult { - // 建立带有内核映射的 MemorySet - let mut memory_set = MemorySet::new_kernel()?; - - // 遍历 elf 文件的所有部分 - for program_header in file.program_iter() { - if program_header.get_type() != Ok(Type::Load) { - continue; - } - // 从每个字段读取「起始地址」「大小」和「数据」 - let start = VirtualAddress(program_header.virtual_addr() as usize); - let size = program_header.mem_size() as usize; - let data: &[u8] = - if let SegmentData::Undefined(data) = program_header.get_data(file).unwrap() { - data - } else { - return Err("unsupported elf format"); - }; - - // 将每一部分作为 Segment 进行映射 - let segment = Segment { - map_type: MapType::Framed, - range: Range::from(start..(start + size)), - flags: Flags::user(is_user) - | Flags::readable(program_header.flags().is_read()) - | Flags::writable(program_header.flags().is_write()) - | Flags::executable(program_header.flags().is_execute()), - }; - - // 建立映射并复制数据 - memory_set.add_segment(segment, Some(data))?; - } - - Ok(memory_set) -} -``` - -### 加载数据到内存中 - -思考：我们在为用户程序建立映射时，虚拟地址是 ELF 文件中写明的，那物理地址是程序在磁盘中存储的地址吗？这样做有什么问题吗？ - -{% reveal %} -> 我们在模拟器上运行可能不觉得，但是如果直接映射磁盘空间，使用时会带来巨大的延迟，所以需要在程序准备运行时，将其磁盘中的数据复制到内存中。如果程序较大，操作系统可能只会复制少量数据，而更多的则在需要时再加载。当然，我们实现的简单操作系统就一次性全都加载到内存中了。 -> -> 而且，就算是想要直接映射磁盘空间，也不一定可行。这是因为虚实地址转换时，页内偏移是不变的。这是就无法保证在 ELF 中指定的地址和其在磁盘中的地址满足这样的关系。 -{% endreveal %} - -
- -我们将修改 `Mapping::map` 函数，为其增加一个参数表示用于初始化的数据。在实现时，有一些重要的细节需要考虑。 - -- 因为用户程序的内存分配是动态的，其分配到的物理页面不一定连续，所以必须单独考虑每一个页面 -- 每一个字段的长度不一定是页大小的倍数，所以需要考虑不足一个页时的复制情况 -- 程序有一个 bss 段，它在 ELF 中不保存数据，而其在加载到内存是需要零初始化 -- 对于一个页面，有其**物理地址**、**虚拟地址**和**待加载数据的地址**。此时，是不是直接从**待加载数据的地址**拷贝到页面的**虚拟地址**，如同 `memcpy` 一样就可以呢？ - -{% reveal %} -> 在目前的框架中，只有当线程将要运行时，才会加载其页表。因此，除非我们额外的在每映射一个页面之后，就更新一次页表并且刷新 TLB，否则此时的**虚拟地址**是无法访问的。 -> -> 但是，我们通过分配器得到了页面的**物理地址**，而这个物理地址实际上已经在内核的线性映射当中了。所以，这里实际上用的是**物理地址**来写入数据。 -{% endreveal %} - -
- -具体的实现，可以查看 `os/src/memory/mapping/mapping.rs` 中的 `Mapping::map` 函数。 - -### 运行 Hello World？ - -现在，我们就可以在操作系统中运行磁盘镜像中的用户程序了，代码示例如下： - -{% label %}os/src/main.rs{% endlabel %} -```rust -// 从文件系统中找到程序 -let app = fs::ROOT_INODE.find("hello_world").unwrap(); -// 读取数据 -let data = app.readall().unwrap(); -// 解析 ELF 文件 -let elf = ElfFile::new(data.as_slice()).unwrap(); -// 利用 ELF 文件创建线程，映射空间并加载数据 -let process = Process::from_elf(&elf, true).unwrap(); -// 再从 ELF 中读出程序入口地址 -let thread = Thread::new(process, elf.header.pt2.entry_point() as usize, None).unwrap(); -// 添加线程 -PROCESSOR.lock().add_thread(thread); -``` - -可惜的是，我们不能像内核线程一样在用户程序中直接使用 `print`。前者是基于 OpenSBI 的机器态 SBI 调用，而为了让用户程序能够打印字符，我们还需要在操作系统中实现系统调用来给用户进程提供服务。 diff --git a/docs/lab-6/guide/part-4.md b/docs/lab-6/guide/part-4.md deleted file mode 100644 index f7a6e04..0000000 --- a/docs/lab-6/guide/part-4.md +++ /dev/null @@ -1,59 +0,0 @@ -## 实现系统调用 - -目前，我们实现 `sys_read` `sys_write` 和 `sys_exit` 三个简单的系统调用。通过学习它们的实现，更多的系统调用也并没有多难。 - -### 用户程序中调用系统调用 - -在用户程序中实现系统调用比较容易，就像我们之前在操作系统中使用 `sbi_call` 一样，只需要符合规则传递参数即可。而且这一次我们甚至不需要参考任何标准，每个人都可以为自己的操作系统实现自己的标准。 - -例如，在实验指导中，系统调用的编号使用了 musl 中的编码和参数格式。但实际上，在实现操作系统的时候，编码和参数格式都可以随意调整，只要在用户程序中的调用和操作系统中的解释相符即可。 - -{% label %}代码示例{% endlabel %} -```rust -// musl 中的 sys_read 调用格式 -llvm_asm!("ecall" : - "={x10}" (/* 返回读取长度 */) : - "{x10}" (/* 文件描述符 */), - "{x11}" (/* 读取缓冲区 */), - "{x12}" (/* 缓冲区长度 */), - "{x17}" (/* sys_read 编号 63 */) :: -); -// 一种可能的 sys_read 调用格式 -llvm_asm!("ecall" : - "={x10}" (/* 现在的时间 */), - "={x11}" (/* 今天的天气 */), - "={x12}" (/* 读取一个字符 */) : - "{x20}" (/* sys_read 编号 0x595_7ead */) :: -); -``` - -实验指导提供了第一种无趣的系统调用格式。 - -### 避免忙等待 - -在常见操作系统中，一些延迟非常大的操作，例如文件读写、网络通讯，都可以使用异步接口来进行。但是为了实现更加简便，我们的读写系统调用都是阻塞的。在 `sys_read` 中，使用了 `loop` 来保证仅当成功读取字符时才返回。 - -此时，如果用户程序需要获取从控制台输入的字符，但是此时并没有任何字符到来。那么，程序将被阻塞，而操作系统的职责就是尽量减少线程执行无用阻塞占用 CPU 的时间，而是将这段时间分配给其他可以执行的线程。具体的做法，将会在后面**条件变量**的章节讲述。 - -### 操作系统中实现系统调用 - -在操作系统中，系统调用的实现和中断处理一样，有同样的入口，而针对不同的参数设置不同的处理流程。为了简化流程，我们不妨把系统调用的处理结果分为三类： - -- 返回一个数值，程序继续执行 -- 程序进入等待 -- 程序将被终止 - -#### 系统调用的处理流程 - -- 首先，从相应的寄存器中取出调用代号和参数 -- 根据调用代号，进入不同的处理流程，得到处理结果 - - 返回数值并继续执行： - - 返回值存放在 `x10` 寄存器，`sepc += 4`，继续此 `context` 的执行 - - 程序进入等待 - - 同样需要更新 `x10` 和 `sepc`，但是需要将当前线程标记为等待，切换其他线程来执行 - - 程序终止 - - 不需要考虑系统调用的返回，直接删除线程 - -#### 具体的调用实现 - -那么具体该如何实现读 / 写系统调用呢？这里我们会利用文件的统一接口 `INode`，使用其中的 `read_at()` 和 `write_at()` 接口即可。下一节就将讲解如何处理文件描述符。 diff --git a/docs/lab-6/guide/part-5.md b/docs/lab-6/guide/part-5.md deleted file mode 100644 index 0c4f751..0000000 --- a/docs/lab-6/guide/part-5.md +++ /dev/null @@ -1,57 +0,0 @@ -## 处理文件描述符 - -尽管很不像，但是在大多操作系统中，标准输入输出流 `stdin` 和 `stdout` 虽然叫做「流」，但它们都有文件的接口。我们同样也会将它们实现成为文件。 - -但是不用担心，作为文件的许多功能，`stdin` 和 `stdout` 都不会支持。我们只需要为其实现最简单的读写接口。 - -### 进程打开的文件 - -操作系统需要为进程维护一个进程打开的文件清单。其中，一定存在的是 `stdin` `stdout` 和 `stderr`。为了简便，我们只实现 `stdin` 和 `stdout`，它们的文件描述符数值分别为 0 和 1。 - -### `stdout` - -输出流最为简单：每当遇到系统调用时，直接将缓冲区中的字符通过 SBI 调用打印出去。 - -### `stdin` - -输入流较为复杂：每当遇到系统调用时，通过中断或轮询方式获取字符：如果有，就进一步获取；如果没有就等待。直到收到约定长度的字符串才返回。 - -#### 外部中断 - -对于用户程序而言，外部输入是随时主动读取的数据。但是事实上外部输入通常时间短暂且不会等待，需要操作系统立即处理并缓冲下来，再等待程序进行读取。所以，每一个键盘按键对于操作系统而言都是一次短暂的中断。 - -而在之前的实验中操作系统不会因为一个按键就崩溃，是因为 OpenSBI 默认会关闭各种外部中断。但是现在我们需要将其打开，来接受按键信息。 - -{% label %}os/src/interrupt/handler.rs{% endlabel %} -```rust -/// 初始化中断处理 -/// -/// 把中断入口 `__interrupt` 写入 `stvec` 中，并且开启中断使能 -pub fn init() { - unsafe { - extern "C" { - /// `interrupt.asm` 中的中断入口 - fn __interrupt(); - } - // 使用 Direct 模式，将中断入口设置为 `__interrupt` - stvec::write(__interrupt as usize, stvec::TrapMode::Direct); - - // 开启外部中断使能 - sie::set_sext(); - - // 在 OpenSBI 中开启外部中断 - *PhysicalAddress(0x0c00_2080).deref_kernel() = 1 << 10; - // 在 OpenSBI 中开启串口 - *PhysicalAddress(0x1000_0004).deref_kernel() = 0x0bu8; - *PhysicalAddress(0x1000_0001).deref_kernel() = 0x01u8; - } -} -``` - -这里，我们需要按照 OpenSBI 的接口在指定的地址进行配置。好在这些地址都在文件系统映射的空间内，就不需要再为其单独建立内存映射了。开启中断使能后，任何一个按键都会导致程序进入 `unimplemented!` 的区域。 - -#### 实现输入流 - -输入流则需要配有一个缓冲区，我们可以用 `alloc::collections::VecDeque` 来实现。在遇到键盘中断时，调用 `sbi_call` 来获取字符并加入到缓冲区中。当遇到系统调用 `sys_read` 时，再相应从缓冲区中取出一定数量的字符。 - -那么，如果遇到了 `sys_read` 系统调用，而缓冲区并没有数据可以读取，应该如何让线程进行等待，而又不浪费 CPU 资源呢？ diff --git a/docs/lab-6/guide/part-6.md b/docs/lab-6/guide/part-6.md deleted file mode 100644 index e484de1..0000000 --- a/docs/lab-6/guide/part-6.md +++ /dev/null @@ -1,44 +0,0 @@ -## 条件变量 - -条件变量（conditional variable）的常见接口是这样的： - -- wait：当前线程开始等待这个条件变量 -- notify_one：让某一个等待此条件变量的线程继续运行 -- notify_all：让所有等待此变量的线程继续运行 - -条件变量和互斥锁的区别在于，互斥锁解铃还须系铃人，但条件变量可以由任何来源发出 notify 信号。同时，互斥锁的一次 lock 一定对应一次 unlock，但条件变量多次 notify 只能保证 wait 的线程执行次数不超过 notify 次数。 - -为输入流加入条件变量后，就可以使得调用 `sys_read` 的线程在等待期间保持休眠，不被调度器选中，消耗 CPU 资源。 - -### 调整调度器 - -为了继续沿用调度算法，不带来太多修改，我们为线程池单独设立一个「休眠区」，其中保存的线程与调度器互斥。当线程进入等待，就将它从调度器中取出，避免之后再被无用唤起。 - -{% label %}os/src/process/processor.rs{% endlabel %} -```rust -pub struct Processor { - /// 当前正在执行的线程 - current_thread: Option>, - /// 线程调度器，记录活跃线程 - scheduler: SchedulerImpl>, - /// 保存休眠线程 - sleeping_threads: HashSet>, -} -``` - -### 实现条件变量 - -条件变量会被包含在输入流等涉及等待和唤起的结构中，而一个条件变量保存的就是所有等待它的线程。 - -{% label %}os/src/kernel/condvar.rs{% endlabel %} -```rust -#[derive(Default)] -pub struct Condvar { - /// 所有等待此条件变量的线程 - watchers: Mutex>>, -} -``` - -当一个线程调用 `sys_read` 而缓冲区为空时，就会将其加入条件变量的 `watcher` 中，同时在 `Processor` 中移出活跃线程。而当键盘中断到来，读取到字符时，就会将线程重新放回调度器中，准备下一次调用。 - -开放思考：如果多个线程同时等待输入流会怎么样？有什么解决方案吗？ diff --git a/docs/lab-6/guide/summary.md b/docs/lab-6/guide/summary.md deleted file mode 100644 index 7c3555a..0000000 --- a/docs/lab-6/guide/summary.md +++ /dev/null @@ -1,3 +0,0 @@ -## 总结 - -这一章的实验指导中，我们成功单独生成 ELF 格式的用户程序，并打包进文件系统中；同时，从中读取，创建并运行用户进程；而为了可以让用户程序享受到操作系统的功能，我们使用系统调用为用户程序提供服务。 \ No newline at end of file diff --git a/docs/lab-6/practice.md b/docs/lab-6/practice.md deleted file mode 100644 index 9d2493c..0000000 --- a/docs/lab-6/practice.md +++ /dev/null @@ -1,24 +0,0 @@ -## 实验六：系统调用 - -### 实验之前 - -- 阅读实验指导五、六。 - -### 实验题目 - -1. 原理：使用条件变量之后，分别从线程和操作系统的角度而言读取字符的系统调用是阻塞的还是非阻塞的？ - - {% reveal %} -> 对于线程而言，是阻塞的，因为在等待有效输入之前线程都会暂停。但对于操作系统而言，等待输入的时间完全分配给了其他线程，所以对于操作系统来说是非阻塞的。 - {% endreveal %} - -
-2. 设计：如果要让用户线程能够使用 `Vec` 等，需要做哪些工作？如果要让用户线程能够使用大于其栈大小的动态分配空间，需要做哪些工作？ - -3. 实验：实现 `get_tid` 系统调用，使得用户线程可以获取自身的线程 ID。 - -4. 实验：将你在实验四（上）实现的 `clone` 改进成为 `sys_clone` 系统调用，使得该系统调用为父进程返回自身的线程 ID，而为子线程返回 0。 - -5. 实验：将一个文件打包进用户镜像，并让一个用户进程读取它并打印其内容。需要实现 `sys_open`，将文件描述符加入进程的 `descriptors` 中，然后通过 `sys_read` 来读取。 - -6. 挑战实验：实现 `sys_pipe`，返回两个文件描述符，分别为一个管道的读和写端。用户线程调用完 `sys_pipe` 后调用 `sys_fork`，父线程写入管道，子线程可以读取。读取时尽量避免忙等待。 diff --git a/docs/pre-lab/env.md b/docs/pre-lab/env.md deleted file mode 100644 index 84ff594..0000000 --- a/docs/pre-lab/env.md +++ /dev/null @@ -1,180 +0,0 @@ -# 环境部署 - -在开展实验之前，我们需要根据不同的平台提前安装相关依赖的软件包，具体需要的软件包如下： -- Rust 工具链 - - Rust 版本管理工具：rustup - - Rust 软件包管理工具：cargo - - Rust 编译器：rustc - - 等等 -- 虚拟机软件：QEMU （版本至少支持 RISC-V 64） - -具体安装的方法在不同平台上安装方式类似，但也有细微差别，后面会有具体说明。 - - - -## 安装 QEMU -根据不同平台，我们分为下面 3 个部分来介绍。 - -### macOS -在 macOS 中，我们可以直接打开命令行用 Homebrew 软件包管理器来安装最新版 QEMU 和其依赖： - -{% label %}运行命令{% endlabel %} -```bash -brew install qemu -``` - -### Linux -在 Linux 中，由于很多软件包管理器的默认软件源中包含的 QEMU 版本过低，这里**推荐**的方式是我们自己手动从源码编译安装： - -{% label %}运行命令{% endlabel %} -```bash -# 下载源码包 （如果下载速度过慢可以把地址替换为我们提供的地址：TODO） -wget https://download.qemu.org/qemu-4.2.0.tar.xz -# 解压 -tar xvJf qemu-4.2.0.tar.xz -# 编译安装并配置 RISC-V 支持 -cd qemu-4.2.0 -./configure --target-list=riscv32-softmmu,riscv64-softmmu -make -j$(nproc) -sudo make install -``` - -如果在运行 `configure` 时遇到软件包依赖的问题（以 Ubuntu 系统举例）： -- 出现 `ERROR: pkg-config binary 'pkg-config' not found` 时，可以通过 `sudo apt-get install pkg-config` 安装； -- 出现 `ERROR: glib-2.48 gthread-2.0 is required to compile QEMU` 时，可以通过 `sudo apt-get install libglib2.0-dev` 安装； -- 出现 `ERROR: pixman >= 0.21.8 not present` 时，可以通过 `sudo apt-get install libpixman-1-dev` 安装。 - -如果有其他问题，请针对不同操作系统在软件包管理器中查找并安装依赖。 - -当然如果你可以找到包含较新版本的 QEMU 的软件包源，**也可以**通过软件包管理器直接安装： - -{% label %}运行命令{% endlabel %} -```bash -# Ubuntu / Debian / Windows WSL -sudo apt-get install qemu - -# CentOS / Fedora / RedHat / SUSE -sudo yum install qemu -``` - -### Windows WSL 2 - -[WSL](https://docs.microsoft.com/zh-cn/windows/wsl/)（Windows Subsystem for Linux）是指 Windows 下构建 Linux 环境。你可以在使用 Windows 的同时，方便地进行 Linux 下的开发，并且 Linux 子系统上可以访问 Windows 的文件系统。但是，WSL 在安装 Rust 时会出现环境配置方面的问题，因此这里我们采用新版的 WSL，即 WSL 2。 - -WSL 2 和 Ubuntu 环境安装步骤： - -- 升级 Windows 10 到最新版（Windows 10 版本 18917 或以后的内部版本） - - 如果不是 Windows 10 专业版，可能需要手动更新，在微软官网上下载。否则，WSL 功能可能不能启动 - - 在 PowerShell 中输入 `winver` 查看**内部版本**号 -- 「Windows 设置 > 更新和安全 > Windows 预览体验计划」处选择加入，Dev 开发者模式 -- 打开 PowerShell 终端（**管理员身份**），输入： - -{% label %}运行命令{% endlabel %} -```powershell -# 启用 Windows 功能：“适用于 Linux 的 Windows 子系统” -dism.exe /online /enable-feature /featurename:Microsoft-Windows-Subsystem-Linux /all /norestart - -# 启用 Windows 功能：“已安装的虚拟机平台” -dism.exe /online /enable-feature /featurename:VirtualMachinePlatform /all /norestart - -# 改为对应从微软应用商店安装的 Linux 版本名，比如：`wsl --set-version Ubuntu 2` -# 如果你没有提前从微软应用商店安装任何 Linux 版本，请跳过此步骤 -wsl --set-version 2 - -# 设置默认为 WSL 2，如果 Windows 版本不够，这条命令会出错 -wsl --set-default-version 2 -``` - -- 在微软商店（Microsoft Store）中搜索 Ubuntu，安装第一个（或者你想要的版本） - - 在[此处](https://docs.microsoft.com/zh-cn/windows/wsl/wsl2-kernel)下载 WSL 2 的 Linux 内核更新包 - - 安装完成后，打开 Ubuntu，进行初始化 -- 回到 PowerShell 终端，输入： - -{% label %}运行命令{% endlabel %} -```powershell -# 查看 WSL 的版本是否为 2 -# 可简写为 `wsl -l -v` -wsl --list --verbose -``` - -- 若得到的版本信息正确，结束。WSL 2 和 Ubuntu 环境安装完毕。 - -在构建完成 WSL 2 + Ubuntu 环境后，可以在 Windows 的 Linux 子系统下便捷地部署 Linux 环境。请查看上文 Linux 环境搭建步骤。 - -### 完成后 - -安装完成后可以用 `qemu-system-riscv64 --version` 命令检查是否成功安装我们需要的 RISC-V 64 虚拟器。 - -## 安装 Rust 工具链 -首先安装 Rust 版本管理器 rustup 和 Rust 包管理器 cargo，这里我们用官方的安装脚本来安装： - -{% label %}运行命令{% endlabel %} -```bash -curl https://sh.rustup.rs -sSf | sh -``` - -如果通过官方的脚本下载失败了，可以在浏览器的地址栏中输入 https://sh.rustup.rs 来下载脚本，在本地运行即可。 - -如果官方的脚本在运行时出现了网络速度较慢的问题，**可选地**可以通过修改 rustup 的镜像地址（修改为中国科学技术大学的镜像服务器）来加速： - -{% label %}运行命令{% endlabel %} -```bash -export RUSTUP_DIST_SERVER=https://mirrors.ustc.edu.cn/rust-static -export RUSTUP_UPDATE_ROOT=https://mirrors.ustc.edu.cn/rust-static/rustup -curl https://sh.rustup.rs -sSf | sh -``` - -**或者**也可以通过在运行前设置命令行中的科学上网代理来实现： - -{% label %}运行命令{% endlabel %} -```bash -# e.g. Shadowsocks 代理 -export https_proxy=http://127.0.0.1:1080 -export http_proxy=http://127.0.0.1:1080 -export ftp_proxy=http://127.0.0.1:1080 -``` - -安装完成后，**最好**我们也可以把软件包管理器 cargo 所用的软件包镜像地址 crates.io 也换成中国科学技术大学的镜像服务器来加速。我们打开（如果没有就新建）`~/.cargo/config` 文件，并把内容修改为： - -{% label %}~/.cargo/config{% endlabel %} -```toml -[source.crates-io] -registry = "https://github.com/rust-lang/crates.io-index" -replace-with = 'ustc' -[source.ustc] -registry = "git://mirrors.ustc.edu.cn/crates.io-index" -``` - -## 安装完成后 -在相关软件包安装完成之后，只需要下面的命令，就可以把整个教程完成之后的 rCore 系统在你的系统上运行起来： - -{% label %}运行命令{% endlabel %} -```bash -# 克隆仓库并编译运行 -git clone TODO -cd rCore-Tutorial -git checkout master - -# 编译运行 -make run -``` - -如果一切正常，则 QEMU 模拟的 RISC-V 64 处理器将输出 - -{% label %}运行输出{% endlabel %} -```bash -TODO -``` - -需要说明的是，Rust 包含 stable、beta 和 nightly 三个版本。默认情况下我们安装的是 stable 稳定版。由于在编写操作系统时需要使用 Rust 的一些不稳定的实验功能，因此我们使用 nightly 每日构建版。 - -但是，由于官方不保证 nightly 版本的 ABI 稳定性，也就意味着今天写的代码用未来的 nightly 可能无法编译通过，因此一般在使用 nightly 时应该锁定一个日期。 - -所以我们的工作目录下会有一个名为 `rust-toolchain` 的文件（无后缀名），在其中有所需的工具链版本： - -{% label %}rust-toolchain{% endlabel %} -``` -nightly-2020-06-27 -``` - -在第一次编译项目时，rustup 会自动去下载对应版本的工具链。今后所有在这个目录或其子目录下使用 Rust 时都会自动切换到这个版本的工具链。随着日后的更新，后面的日期可能会变化，请以 GitHub 仓库上的版本为准。 \ No newline at end of file diff --git a/docs/pre-lab/gdb.md b/docs/pre-lab/gdb.md deleted file mode 100644 index 72fe3be..0000000 --- a/docs/pre-lab/gdb.md +++ /dev/null @@ -1,77 +0,0 @@ -# 使用 GDB 对 rCore 进行 debug* - -> *：使用 GDB 调试可以方便观察 rCore 运行过程，但不属于教程要求 - -GDB 需要支持 riscv64 架构才能够对 rCore 进行 debug。 - -- 运行 `gdb --configuration` 来查看本地的 GDB 支持什么架构，其中 `--target` 参数指定了它可以 debug 的架构 -- 如果 `gdb` 不支持，可以按照下面的步骤来安装 `riscv64-unknown-elf-gdb` - -## 安装 `riscv64-unknown-elf-gdb` - -0. 安装依赖（针对 Linux，macOS 可以遇到错误再去搜索） - - python 并非必须 - - 在 `Ubuntu 20.04` 等系统中，`python` 和 `python-dev` 需要替换成 `python2` 和 `python2-dev` - ```bash - sudo apt-get install libncurses5-dev python python-dev texinfo libreadline-dev - ``` - -1. 前往[清华镜像](https://mirrors.tuna.tsinghua.edu.cn/gnu/gdb/?C=M&O=D)下载最新的 GDB 源代码 - -2. 解压源代码，并定位到目录 - -3. 执行以下命令 - - `--prefix` 是安装的路径，按照以上指令会安装到 `/usr/local/bin/` 下 - - `--with-python` 是 `python2` 的地址，它和 `--enable-tui` 都是为了支持后续安装一个可视化插件，并非必须 - ```bash - mkdir build - cd build - ../configure --prefix=/usr/local --with-python=/usr/bin/python --target=riscv64-unknown-elf --enable-tui=yes - ``` - -4. 编译安装 - - ```bash - # Linux - make -j$(nproc) - # macOS - make -j$(sysctl -n hw.ncpu) - - sudo make install - ``` - -5. （可选）安装 [`gdb-dashboard`](https://github.com/cyrus-and/gdb-dashboard/) 插件，优化 debug 体验 - ```bash - wget -P ~ https://git.io/.gdbinit - ``` - -## 使用 GDB 对 rCore 进行 debug - -在 `os/Makefile` 中，包含了 `debug` 方法，可以执行 `make debug` 来在 `tmux` 中开启调试。 - -手动： - -- 将 QEMU 的运行参数加上 `-s -S`，它将在 1234 端口等待调试器接入 -- 运行 `riscv64-unknown-elf-gdb` -- 在 GDB 中执行 `file target/riscv64imac-unknown-none-elf/debug/os` 来加载未被 `strip` 过的内核文件中的各种符号 -- 在 GDB 中执行 `target remote localhost:1234` 来连接 QEMU，开始调试 - -## GDB 简单使用方法 - -### 控制流 - -- `b <函数名>` 在函数进入时设置断点，例如 `b rust_main` 或 `b os::memory::heap::init` -- `cont` 继续执行 -- `n` 执行下一行代码，不进入函数 -- `ni` 执行下一条指令（跳转指令则执行至返回） -- `s` 执行下一行代码，进入函数 -- `si` 执行下一条指令，包括跳转指令 - -### 查看状态 - -- 如果没有安装 `gdb-dashboard`，可以通过 `layout` 指令来呈现寄存器等信息，具体查看 `help layout` -- 使用 `x/<格式> <地址>` 来查看内存，例如 `x/8i 0x80200000` 表示查看 `0x80200000` 起始的 8 条指令。具体格式查看 `help x` - -## 注意 - -调试虚实地址转换时，GDB 完全通过读取文件来判断函数地址，因此可能会遇到一些问题，需要手动设置地址来调试 diff --git a/docs/pre-lab/os.md b/docs/pre-lab/os.md deleted file mode 100644 index 02ad10c..0000000 --- a/docs/pre-lab/os.md +++ /dev/null @@ -1,3 +0,0 @@ -# 操作系统背景知识 - - \ No newline at end of file diff --git a/docs/pre-lab/rust.md b/docs/pre-lab/rust.md deleted file mode 100644 index 06d45eb..0000000 --- a/docs/pre-lab/rust.md +++ /dev/null @@ -1,3 +0,0 @@ -# Rust 基础介绍 - - \ No newline at end of file diff --git a/gitalk.html b/gitalk.html deleted file mode 100644 index 3e3e617..0000000 --- a/gitalk.html +++ /dev/null @@ -1,22 +0,0 @@ - - -
- \ No newline at end of file diff --git "a/notes/\345\205\263\344\272\216\350\257\276\347\250\213\350\256\276\350\256\241.md" "b/notes/\345\205\263\344\272\216\350\257\276\347\250\213\350\256\276\350\256\241.md" deleted file mode 100755 index 0d7a052..0000000 --- "a/notes/\345\205\263\344\272\216\350\257\276\347\250\213\350\256\276\350\256\241.md" +++ /dev/null @@ -1,20 +0,0 @@ -- 目前的 rCore tutorial 存在一些问题： - - 代码 - - 完全没有体现出 Rust 的优点，几乎所有需要做 borrow check 之类的地方都用 unsafe 糊过去了 - - 设计模式极为混乱，基本不考虑封装、模块化，互相有关的代码也零散在不同文件、不同类型中 - - 有些地方可读性不强，而且注释非常少，很多风格也不统一，也有一些 hardcoded 的部分 - - 文档部分，在最后几个章节没有前几个章节更加细致，很多行的代码只用了一句话来带过 - - 实验设计 - - 比较简单？而且这还是 140 分。在有同学帮助的情况下三天做完没什么问题 - - 涵盖的知识点比较少，我不看课件，文档也不完全看一遍，也能直接做题（不过因为有考试这方面倒是不太重要） - - 缺少自动化的测试 -- 做 tutorial 的理由（为什么做一个 tutorial 就有大实验的分量）： - - 希望能够帮到学弟学妹，目标是把整个 OS 课程内容融合到里面去，增加同学的参与程度 - - 做一套 tutorial 涉及重构整个 rCore，不会像现有 tutorial 一样参照原版，因此可以说非常全面地掌握了 OS 课程所有内容 - - 如果和之前一样，是做一个 tutorial 附带好多别的东西，会导致 tutorial 赶工质量粗糙（感觉好对不起小班助教） -- 我们的计划： - - 重新写一个简化版操作系统 + 教程 - - 实验内容修改 - - 这个看老师意见，我们可以把实验设计得更多更难，也可以不增加代码量而涵盖更多知识点 - - 要带大家用 qemu + gdb 从汇编层面理解代码，理解操作系统是怎么 work 的 - - 我写实验作业的时候就跑过，配置起来很容易 diff --git "a/notes/\346\226\271\346\241\210\350\256\276\350\256\241\346\226\207\346\241\243.md" "b/notes/\346\226\271\346\241\210\350\256\276\350\256\241\346\226\207\346\241\243.md" deleted file mode 100644 index 5839b2f..0000000 --- "a/notes/\346\226\271\346\241\210\350\256\276\350\256\241\346\226\207\346\241\243.md" +++ /dev/null @@ -1,91 +0,0 @@ -# 大实验方案设计文档：rCore Tutorial 重构 - -涂轶翔 2017011422 -赵成钢 2017011362 - - - -### 相关工作参考 - -- [**rCore_tutorial**](https://github.com/rcore-os/rCore_tutorial) 和 [**rCore**](https://github.com/rcore-os/rCore) - - 代码的主要参考，会在其基础上重构代码结构，而保留大部分的具体实现 -- [**uCore 实验指导书**](https://learningos.github.io/ucore_os_webdocs/) - - 实验设计主要参照，视进度尝试移植更多挑战实验 -- [Writing an OS in Rust](https://os.phil-opp.com/) - - - -### 设计方案 - -#### 1. 在多个方面改善 rCore 教学代码、文档和实验内容 - -##### 实验设计 - -- 改善自动化测试 - *目前部分测试需要手动终止运行并人工观察输出* - - - 测试指令直接返回成绩，节省助教检查的时间 - - 使用更强（例如随机化）的测例 - -- 探索更丰富的实验方法，不增加工作量而更考察知识 - - - 例如，要求学生设计函数，使得某种调度算法的效率提升 / 降低 - - 例如，要求学生修改一些汇编，使得用户程序越界访问 - -- 尝试结合随堂作业、涵盖更多知识点 - -- - 部分作业比较适合作为额外挑战放在实验中 - -##### 代码 - -- 优化设计模式 - *目前代码中存在许多软件工程角度的缺陷* - - 贯彻封装思想，将各个模块之间最大化地解耦合 - - 更多利用 rust 的特有功能，例如 Clone Drop 等 trait -- 提升代码可读性 - *目前代码注释较少且不够起到解释作用* - - 添加规范格式的注释 - - 使用更加清晰的变量命名 - - 通过提取函数等形式让程序工作流程更加易读 -- 规范代码 - - 让代码格式更加符合 rust 的 best practice，消除 Warning -- 完善对 Windows / macOS / Linux 的环境支持 - -##### 文档 - -- 细化对代码的讲解 - - 为函数添加规范的功能注释，可以自动生成 doc - - 重要的代码添加注释 -- 文档中深入阐释涉及的原理 - *这部分现有文档仍有不足* - -##### 功能 - -- 实现一些目前框架缺少的功能 - - 资源的释放 - - 进程 vs 线程等 - -#### 2. 与 uCore 小组进行协作 - -- 尽可能在实验内容上达成统一 -- 文档在代码讲解上差异会很大，而原理讲解上尽量做到一致 - -#### 3. 可能的额外项目 - -- 移植 uCore 中的扩展练习 和/或 将随堂作业相关内容作为挑战作业 -- 物理硬件上运行 及 多核支持 - - - -### 实验计划 - -#### 分工 - -- 对于每个实验，一人负责代码与测试，另一人负责注释与文档 -- 所有实验开发过程中会有轮换 - -#### 时间计划 - -- 7 ~ 10 周完成 8 个基础 lab（每周 2 个） -- 最晚 11 周时完成度达到足以供教学使用的进度 -- 后续开发更多 lab 内容 和/或 拓展框架 \ No newline at end of file diff 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deleted file mode 100755 index eadbf60..0000000 --- "a/notes/\350\256\276\350\256\241\351\242\204\346\234\237\345\222\214\347\233\256\346\240\207.md" +++ /dev/null @@ -1,23 +0,0 @@ -- 代码层面 - - 进一步体现 Rust 的优点，更接近真实开发社区的规范 - - 重新设计结构，完善设计模式 - - 增强可读性，添加可以完善了解系统代码的注释 - - 完善代码规范和风格，更贴近现代软件工程的准则 - - 完善 Windows / macOS / Linux 的环境支持和配置 -- 功能层面 - - 进一步完善教学版 rCore 的功能（如进程、线程进一步区分），使得教学版有更具完整更加贴近课程 -- 文档层面 - - 完善文档到非常细节的程度 - - 添加一些扩展信息 - - 进一步贴合课程所学 - - 微调文档的结构 - - 添加一些比如 qemu + gdb 从汇编层面的实践认知上的理解，添加例子进一步让同学理解操作系统如何工作 -- 实验设计层面 - - 目标是让同学有对操作系统从前到后的完整理解，少一些类似数据结构的题目 - - 让工作量多一些系统层面原理的认识，减少一部分简单算法的 dirty work - - 测试的方法会完善，强度会进一步加大，尽可能实现全自动化测试而且避免一些在代码中 cheet 的可能性 - - 设计上尽量可以检验同学们阅读代码的成果，可以设计些贯穿流程的问题或者代码填空，而不是基于可以运行的系统上来增量开发 - - 更加具体的内容和难度上需要参考老师的建议，可以把实验设计得更多更难，也可以不增加代码量而涵盖更多知识点 - - 测评尽量从每个章节的版本出发，而不是基于一个大的完整版 -- 其他 - - 和做 uCore 的 RISC-V 支持的同学沟通并统一意见 diff --git "a/notes/\350\257\276\347\250\213\350\256\276\350\256\241\346\226\271\346\241\210\345\271\273\347\201\257\347\211\207.pdf" "b/notes/\350\257\276\347\250\213\350\256\276\350\256\241\346\226\271\346\241\210\345\271\273\347\201\257\347\211\207.pdf" deleted file mode 100644 index a1a0aa2..0000000 Binary files "a/notes/\350\257\276\347\250\213\350\256\276\350\256\241\346\226\271\346\241\210\345\271\273\347\201\257\347\211\207.pdf" and /dev/null differ diff --git a/os/Cargo.toml b/os/Cargo.toml index d3f9735..44dbee4 100644 --- a/os/Cargo.toml +++ b/os/Cargo.toml @@ -20,6 +20,12 @@ virtio-drivers = { git = "https://github.com/rcore-os/virtio-drivers" } rcore-fs = { git = "https://github.com/rcore-os/rcore-fs"} rcore-fs-sfs = { git = "https://github.com/rcore-os/rcore-fs"} xmas-elf = "0.7.0" +k210-hal = { path = "../tools/k210-hal" } +k210-pac = { path = "../tools/k210-pac" } + +[features] +board_qemu = [] +board_k210 = [] # panic 时直接终止，因为我们没有实现堆栈展开的功能 [profile.dev] diff --git a/os/Makefile b/os/Makefile index 23b61bc..4f6278e 100644 --- a/os/Makefile +++ b/os/Makefile @@ -3,6 +3,17 @@ MODE := debug KERNEL_FILE := target/$(TARGET)/$(MODE)/os BIN_FILE := target/$(TARGET)/$(MODE)/kernel.bin +BOARD ?= qemu +SBI ?= rustsbi +BOOTLOADER := ../bootloader/$(SBI)-$(BOARD).bin + +# Run K210 +K210-SERIALPORT = /dev/ttyUSB0 +K210-BURNER = ../tools/kflash.py + +# Disassembly +DISASM ?= -D + USER_DIR := ../user USER_BUILD := $(USER_DIR)/build IMG_FILE := $(USER_BUILD)/disk.img @@ -21,32 +32,45 @@ doc: # 编译 kernel kernel: - @cargo build + @cp src/board/$(BOARD)/linker.ld src/linker.ld + @cargo build --features "board_$(BOARD)" # 生成 kernel 的二进制文件 $(BIN_FILE): kernel @$(OBJCOPY) $(KERNEL_FILE) --strip-all -O binary $@ + # 查看反汇编结果 asm: - @$(OBJDUMP) -d $(KERNEL_FILE) | less + @$(OBJDUMP) $(DISASM) $(KERNEL_FILE) | less + +asm-save: + @$(OBJDUMP) $(DISASM) $(KERNEL_FILE) > asm # 清理编译出的文件 clean: @cargo clean # 运行 QEMU -qemu: build +run-inner: build +ifeq ($(BOARD),qemu) @qemu-system-riscv64 \ -machine virt \ -nographic \ - -bios default \ + -bios $(BOOTLOADER) \ -device loader,file=$(BIN_FILE),addr=0x80200000 \ -drive file=$(IMG_FILE),format=qcow2,id=sfs \ -device virtio-blk-device,drive=sfs +else + @cp $(BOOTLOADER) $(BOOTLOADER).copy + @dd if=$(BIN_FILE) of=$(BOOTLOADER).copy bs=128K seek=1 + @mv $(BOOTLOADER).copy $(BIN_FILE) + @sudo chmod 777 $(K210-SERIALPORT) + python3 $(K210-BURNER) -p $(K210-SERIALPORT) -b 1500000 -t $(BIN_FILE) +endif # 一键运行 -run: build qemu +run: build run-inner # 一键 gdb debug: build @@ -54,4 +78,4 @@ debug: build "qemu-system-riscv64 -machine virt -nographic -bios default -device loader,file=$(BIN_FILE),addr=0x80200000 \ -drive file=$(IMG_FILE),format=qcow2,id=sfs -device virtio-blk-device,drive=sfs -s -S" && \ tmux split-window -h "riscv64-unknown-elf-gdb -ex 'file $(KERNEL_FILE)' -ex 'set arch riscv:rv64' -ex 'target remote localhost:1234'" && \ - tmux -2 attach-session -d \ No newline at end of file + tmux -2 attach-session -d diff --git a/os/build.rs b/os/build.rs new file mode 100644 index 0000000..3ec3d66 --- /dev/null +++ b/os/build.rs @@ -0,0 +1,3 @@ +fn main() { + println!("cargo:rerun-if-changed=src/linker.ld"); +} diff --git a/os/src/board/k210/config.rs b/os/src/board/k210/config.rs new file mode 100644 index 0000000..9adbe4a --- /dev/null +++ b/os/src/board/k210/config.rs @@ -0,0 +1,27 @@ +#![allow(dead_code)] + +pub const BOARD_MEMORY_END_ADDRESS: usize = 0x8060_0000; +pub const BOARD_KERNEL_HEAP_SIZE: usize = 0x30_0000; +pub const BOARD_STACK_SIZE: usize = 0x8_0000; +pub const BOARD_KERNEL_STACK_SIZE: usize = 0x8_0000; + +pub const MMIO_INTERVALS: &[(usize, usize)] = &[ + (0x0200_0000, 0x1000), /* CLINT */ + (0x0C00_0000, 0x1000), /* PLIC */ + (0x3800_0000, 0x1000), /* UARTHS */ + (0x3800_1000, 0x1000), /* GPIOHS */ + (0x5020_0000, 0x1000), /* GPIO */ + (0x5024_0000, 0x1000), /* SPI_SLAVE */ + (0x502B_0000, 0x1000), /* FPIOA */ + (0x502D_0000, 0x1000), /* TIMER0 */ + (0x502E_0000, 0x1000), /* TIMER1 */ + (0x502F_0000, 0x1000), /* TIMER2 */ + (0x5044_0000, 0x1000), /* SYSCTL */ + (0x5200_0000, 0x1000), /* SPI0 */ + (0x5300_0000, 0x1000), /* SPI1 */ + (0x5400_0000, 0x1000), /* SPI2 */ +]; + +pub const RISCV_SPEC_MAJOR: usize = 1; +pub const RISCV_SPEC_MINOR: usize = 9; +pub const RISCV_SPEC_PATCH: usize = 1; \ No newline at end of file diff --git a/os/src/board/k210/interrupt.rs b/os/src/board/k210/interrupt.rs new file mode 100644 index 0000000..ee7ebaa --- /dev/null +++ b/os/src/board/k210/interrupt.rs @@ -0,0 +1,40 @@ +use crate::interrupt::{Context, timer}; +use riscv::register::{scause::Scause, stval}; +use crate::PROCESSOR; +use crate::fs::STDIN; + +/// 处理 ebreak 断点 +/// +/// 继续执行，其中 `sepc` 增加 2 字节，以跳过当前这条 `ebreak` 指令 +pub fn breakpoint(context: &mut Context) -> *mut Context { + println!("Breakpoint at 0x{:x}", context.sepc); + context.sepc += 2; + context +} + +/// 处理时钟中断 +pub fn supervisor_timer(context: &mut Context) -> *mut Context { + timer::tick(); + PROCESSOR.lock().park_current_thread(context); + PROCESSOR.lock().prepare_next_thread() +} + +/// 处理外部中断，只实现了键盘输入 +pub fn supervisor_external(context: &mut Context) -> *mut Context { + context +} + +pub fn supervisor_soft(context: &mut Context) -> *mut Context { + let mut c = stval::read(); + if c <= 255 { + if c == '\r' as usize { + c = '\n' as usize; + } + STDIN.push(c as u8); + } + unsafe { + let mut _sip: usize = 0; + llvm_asm!("csrci sip, 1 << 1" : "=r"(_sip) ::: "volatile"); + } + context +} diff --git a/os/src/board/k210/linker.ld b/os/src/board/k210/linker.ld new file mode 100644 index 0000000..88900fe --- /dev/null +++ b/os/src/board/k210/linker.ld @@ -0,0 +1,51 @@ + +OUTPUT_ARCH(riscv) +ENTRY(_start) + +BASE_ADDRESS = 0xffffffff80020000; + +SECTIONS +{ + /* Load the kernel at this address: "." means the current address */ + . = BASE_ADDRESS; + + kernel_start = .; + + . = ALIGN(4K); + + text_start = .; + .text : { + stext = .; + *(.text.entry) + *(.text .text.*) + etext = .; + } + + . = ALIGN(4K); + rodata_start = .; + .rodata : { + srodata = .; + *(.rodata .rodata.*) + erodata = .; + } + + . = ALIGN(4K); + data_start = .; + .data : { + sdata = .; + *(.data .data.*) + edata = .; + } + + . = ALIGN(4K); + bss_start = .; + .bss : { + *(.bss.stack) + sbss_clear = .; + *(.sbss .bss .bss.*) + ebss_clear = .; + } + + . = ALIGN(4K); + PROVIDE(kernel_end = .); +} diff --git a/os/src/board/k210/mod.rs b/os/src/board/k210/mod.rs new file mode 100644 index 0000000..653e745 --- /dev/null +++ b/os/src/board/k210/mod.rs @@ -0,0 +1,28 @@ +use crate::memory::address::PhysicalAddress; + +pub mod config; +pub mod interrupt; + +pub fn device_init(_: PhysicalAddress) { + // after RustSBI, txen = rxen = 1, rxie = 1, rxcnt = 0 + // start UART interrupt configuration + // disable external interrupt on hart1 by setting threshold + let hart0_m_threshold: *mut u32 = 0x0c20_0000 as *mut u32; + let hart1_m_threshold: *mut u32 = 0x0c20_2000 as *mut u32; + unsafe { + hart0_m_threshold.write_volatile(0u32); + hart1_m_threshold.write_volatile(1u32); + } + // now using UARTHS whose IRQID = 33 + // assure that its priority equals 1 + let uarths_irq_priority: *mut u32 = (0x0c00_0000 + 33 * 4) as *mut u32; + assert_eq!(unsafe{ uarths_irq_priority.read_volatile() }, 1); + // open interrupt enable register on PLIC + let hart0_m_int_enable_hi: *mut u32 = 0x0c00_2004 as *mut u32; + unsafe { + hart0_m_int_enable_hi.write_volatile(1 << 0x1); + } + // now, we can receive UARTHS interrupt on hart0! + + crate::drivers::soc::sleep::usleep(1000000); +} \ No newline at end of file diff --git a/os/src/board/mod.rs b/os/src/board/mod.rs new file mode 100644 index 0000000..f397d37 --- /dev/null +++ b/os/src/board/mod.rs @@ -0,0 +1,8 @@ +mod k210; +mod qemu; + +#[cfg(feature = "board_k210")] +pub use k210::{config, device_init, interrupt}; + +#[cfg(feature = "board_qemu")] +pub use qemu::{config, device_init, interrupt}; \ No newline at end of file diff --git a/os/src/board/qemu/config.rs b/os/src/board/qemu/config.rs new file mode 100644 index 0000000..a6fabe8 --- /dev/null +++ b/os/src/board/qemu/config.rs @@ -0,0 +1,13 @@ +#![allow(dead_code)] + +pub const BOARD_MEMORY_END_ADDRESS: usize = 0x8800_0000; +pub const BOARD_KERNEL_HEAP_SIZE: usize = 0x80_0000; +pub const BOARD_STACK_SIZE: usize = 0x8_0000; +pub const BOARD_KERNEL_STACK_SIZE: usize = 0x8_0000; + +pub const MMIO_INTERVALS: &[(usize, usize)] = &[]; + + +pub const RISCV_SPEC_MAJOR: usize = 1; +pub const RISCV_SPEC_MINOR: usize = 11; +pub const RISCV_SPEC_PATCH: usize = 1; \ No newline at end of file diff --git a/os/src/board/qemu/interrupt.rs b/os/src/board/qemu/interrupt.rs new file mode 100644 index 0000000..9e8644c --- /dev/null +++ b/os/src/board/qemu/interrupt.rs @@ -0,0 +1,49 @@ +use crate::interrupt::{Context, timer}; +use crate::sbi::console_getchar; +use riscv::register::scause::Scause; +use crate::PROCESSOR; +use crate::fs::STDIN; + +/// 处理 ebreak 断点 +/// +/// 继续执行，其中 `sepc` 增加 2 字节，以跳过当前这条 `ebreak` 指令 +pub fn breakpoint(context: &mut Context) -> *mut Context { + println!("Breakpoint at 0x{:x}", context.sepc); + context.sepc += 2; + context +} + +/// 处理时钟中断 +pub fn supervisor_timer(context: &mut Context) -> *mut Context { + timer::tick(); + PROCESSOR.lock().park_current_thread(context); + PROCESSOR.lock().prepare_next_thread() +} + +/// 处理外部中断，只实现了键盘输入 +pub fn supervisor_external(context: &mut Context) -> *mut Context { + let mut c = console_getchar(); + if c <= 255 { + if c == '\r' as usize { + c = '\n' as usize; + } + STDIN.push(c as u8); + } + context +} + +pub fn supervisor_soft(context: &mut Context) -> *mut Context { context } + +/// 出现未能解决的异常，终止当前线程 +pub fn fault(msg: &str, scause: Scause, stval: usize) -> *mut Context { + println!( + "{:#x?} terminated: {}", + PROCESSOR.lock().current_thread(), + msg + ); + println!("cause: {:?}, stval: {:x}", scause.cause(), stval); + + PROCESSOR.lock().kill_current_thread(); + // 跳转到 PROCESSOR 调度的下一个线程 + PROCESSOR.lock().prepare_next_thread() +} \ No newline at end of file diff --git a/os/src/board/qemu/linker.ld b/os/src/board/qemu/linker.ld new file mode 100644 index 0000000..b49ebc2 --- /dev/null +++ b/os/src/board/qemu/linker.ld @@ -0,0 +1,51 @@ + +OUTPUT_ARCH(riscv) +ENTRY(_start) + +BASE_ADDRESS = 0xffffffff80200000; + +SECTIONS +{ + /* Load the kernel at this address: "." means the current address */ + . = BASE_ADDRESS; + + kernel_start = .; + + . = ALIGN(4K); + + text_start = .; + .text : { + stext = .; + *(.text.entry) + *(.text .text.*) + etext = .; + } + + . = ALIGN(4K); + rodata_start = .; + .rodata : { + srodata = .; + *(.rodata .rodata.*) + erodata = .; + } + + . = ALIGN(4K); + data_start = .; + .data : { + sdata = .; + *(.data .data.*) + edata = .; + } + + . = ALIGN(4K); + bss_start = .; + .bss : { + *(.bss.stack) + sbss_clear = .; + *(.sbss .bss .bss.*) + ebss_clear = .; + } + + . = ALIGN(4K); + PROVIDE(kernel_end = .); +} diff --git a/os/src/board/qemu/mod.rs b/os/src/board/qemu/mod.rs new file mode 100644 index 0000000..3e75a40 --- /dev/null +++ b/os/src/board/qemu/mod.rs @@ -0,0 +1,19 @@ +pub mod config; +pub mod interrupt; + +use crate::drivers::init; +use crate::memory::address::PhysicalAddress; + +pub fn device_init(dtb_pa: PhysicalAddress) { + unsafe { + // 在 OpenSBI 中开启外部中断 + (0x0C00_2080 as *mut u32).write_volatile(1u32 << 10); + // 在 OpenSBI 中开启串口 + (0x1000_0004 as *mut u8).write_volatile(0x0bu8); + (0x1000_0001 as *mut u8).write_volatile(0x01u8); + // 其他一些外部中断相关魔数 + (0x0C00_0028 as *mut u32).write_volatile(0x07u32); + (0x0C20_1000 as *mut u32).write_volatile(0); + } + init(dtb_pa); +} \ No newline at end of file diff --git a/os/src/drivers/block/mod.rs b/os/src/drivers/block/mod.rs index b5753ee..a4d3c8b 100644 --- a/os/src/drivers/block/mod.rs +++ b/os/src/drivers/block/mod.rs @@ -7,6 +7,7 @@ use alloc::sync::Arc; use rcore_fs::dev; pub mod virtio_blk; +pub mod sdcard; /// 块设备抽象（驱动的引用） pub struct BlockDevice(pub Arc); diff --git a/os/src/drivers/block/sdcard.rs b/os/src/drivers/block/sdcard.rs new file mode 100644 index 0000000..8ce7f1b --- /dev/null +++ b/os/src/drivers/block/sdcard.rs @@ -0,0 +1,852 @@ +#![allow(non_snake_case)] +#![allow(unused)] +#![allow(non_camel_case_types)] + +use core::convert::TryInto; +use crate::drivers::soc::dmac::{dma_channel, DMAC}; +use crate::drivers::soc::gpio; +use crate::drivers::soc::gpiohs; +use crate::drivers::soc::spi::{aitm, frame_format, tmod, work_mode, SPI}; +use rcore_fs::dev::BlockDevice; + +pub struct SDCard { + spi: SPI, + spi_cs: u32, + cs_gpionum: u8, + //dmac: &'a DMAC, + //channel: dma_channel, +} + +/* + * Start Data tokens: + * Tokens (necessary because at nop/idle (and CS active) only 0xff is + * on the data/command line) + */ +/** Data token start byte, Start Single Block Read */ +pub const SD_START_DATA_SINGLE_BLOCK_READ: u8 = 0xFE; +/** Data token start byte, Start Multiple Block Read */ +pub const SD_START_DATA_MULTIPLE_BLOCK_READ: u8 = 0xFE; +/** Data token start byte, Start Single Block Write */ +pub const SD_START_DATA_SINGLE_BLOCK_WRITE: u8 = 0xFE; +/** Data token start byte, Start Multiple Block Write */ +pub const SD_START_DATA_MULTIPLE_BLOCK_WRITE: u8 = 0xFC; + +pub const SEC_LEN: usize = 512; + +/** SD commands */ +#[repr(u8)] +#[derive(Debug, PartialEq, Eq, Copy, Clone)] +pub enum CMD { + /** Software reset */ + CMD0 = 0, + /** Check voltage range (SDC V2) */ + CMD8 = 8, + /** Read CSD register */ + CMD9 = 9, + /** Read CID register */ + CMD10 = 10, + /** Stop to read data */ + CMD12 = 12, + /** Change R/W block size */ + CMD16 = 16, + /** Read block */ + CMD17 = 17, + /** Read multiple blocks */ + CMD18 = 18, + /** Number of blocks to erase (SDC) */ + ACMD23 = 23, + /** Write a block */ + CMD24 = 24, + /** Write multiple blocks */ + CMD25 = 25, + /** Initiate initialization process (SDC) */ + ACMD41 = 41, + /** Leading command for ACMD* */ + CMD55 = 55, + /** Read OCR */ + CMD58 = 58, + /** Enable/disable CRC check */ + CMD59 = 59, +} + +#[derive(Debug, Copy, Clone)] +pub enum InitError { + CMDFailed(CMD, u8), + CardCapacityStatusNotSet([u8; 4]), + CannotGetCardInfo, +} + +/** + * Card Specific Data: CSD Register + */ +#[derive(Debug, Copy, Clone)] +pub struct SD_CSD { + pub CSDStruct: u8, /* CSD structure */ + pub SysSpecVersion: u8, /* System specification version */ + pub Reserved1: u8, /* Reserved */ + pub TAAC: u8, /* Data read access-time 1 */ + pub NSAC: u8, /* Data read access-time 2 in CLK cycles */ + pub MaxBusClkFrec: u8, /* Max. bus clock frequency */ + pub CardComdClasses: u16, /* Card command classes */ + pub RdBlockLen: u8, /* Max. read data block length */ + pub PartBlockRead: u8, /* Partial blocks for read allowed */ + pub WrBlockMisalign: u8, /* Write block misalignment */ + pub RdBlockMisalign: u8, /* Read block misalignment */ + pub DSRImpl: u8, /* DSR implemented */ + pub Reserved2: u8, /* Reserved */ + pub DeviceSize: u32, /* Device Size */ + //MaxRdCurrentVDDMin: u8, /* Max. read current @ VDD min */ + //MaxRdCurrentVDDMax: u8, /* Max. read current @ VDD max */ + //MaxWrCurrentVDDMin: u8, /* Max. write current @ VDD min */ + //MaxWrCurrentVDDMax: u8, /* Max. write current @ VDD max */ + //DeviceSizeMul: u8, /* Device size multiplier */ + pub EraseGrSize: u8, /* Erase group size */ + pub EraseGrMul: u8, /* Erase group size multiplier */ + pub WrProtectGrSize: u8, /* Write protect group size */ + pub WrProtectGrEnable: u8, /* Write protect group enable */ + pub ManDeflECC: u8, /* Manufacturer default ECC */ + pub WrSpeedFact: u8, /* Write speed factor */ + pub MaxWrBlockLen: u8, /* Max. write data block length */ + pub WriteBlockPaPartial: u8, /* Partial blocks for write allowed */ + pub Reserved3: u8, /* Reserded */ + pub ContentProtectAppli: u8, /* Content protection application */ + pub FileFormatGroup: u8, /* File format group */ + pub CopyFlag: u8, /* Copy flag (OTP) */ + pub PermWrProtect: u8, /* Permanent write protection */ + pub TempWrProtect: u8, /* Temporary write protection */ + pub FileFormat: u8, /* File Format */ + pub ECC: u8, /* ECC code */ + pub CSD_CRC: u8, /* CSD CRC */ + pub Reserved4: u8, /* always 1*/ +} + +/** + * Card Identification Data: CID Register + */ +#[derive(Debug, Copy, Clone)] +pub struct SD_CID { + pub ManufacturerID: u8, /* ManufacturerID */ + pub OEM_AppliID: u16, /* OEM/Application ID */ + pub ProdName1: u32, /* Product Name part1 */ + pub ProdName2: u8, /* Product Name part2*/ + pub ProdRev: u8, /* Product Revision */ + pub ProdSN: u32, /* Product Serial Number */ + pub Reserved1: u8, /* Reserved1 */ + pub ManufactDate: u16, /* Manufacturing Date */ + pub CID_CRC: u8, /* CID CRC */ + pub Reserved2: u8, /* always 1 */ +} + +/** + * Card information + */ +#[derive(Debug, Copy, Clone)] +pub struct SD_CardInfo { + pub SD_csd: SD_CSD, + pub SD_cid: SD_CID, + pub CardCapacity: u64, /* Card Capacity */ + pub CardBlockSize: u64, /* Card Block Size */ +} + +impl SDCard { + pub fn new(spi: X, spi_cs: u32, cs_gpionum: u8/*, dmac: &'a DMAC, channel: dma_channel*/) -> Self { + Self { + spi, + spi_cs, + cs_gpionum, + /* + dmac, + channel, + */ + } + } + + fn CS_HIGH(&self) { + gpiohs::set_pin(self.cs_gpionum, true); + } + + fn CS_LOW(&self) { + gpiohs::set_pin(self.cs_gpionum, false); + } + + fn HIGH_SPEED_ENABLE(&self) { + self.spi.set_clk_rate(10000000); + } + + fn lowlevel_init(&self) { + gpiohs::set_direction(self.cs_gpionum, gpio::direction::OUTPUT); + self.spi.set_clk_rate(200000); + } + + fn write_data(&self, data: &[u8]) { + self.spi.configure( + work_mode::MODE0, + frame_format::STANDARD, + 8, /* data bits */ + 0, /* endian */ + 0, /*instruction length*/ + 0, /*address length*/ + 0, /*wait cycles*/ + aitm::STANDARD, + tmod::TRANS, + ); + self.spi.send_data(self.spi_cs, data); + } + + /* + fn write_data_dma(&self, data: &[u32]) { + self.spi.configure( + work_mode::MODE0, + frame_format::STANDARD, + 8, /* data bits */ + 0, /* endian */ + 0, /*instruction length*/ + 0, /*address length*/ + 0, /*wait cycles*/ + aitm::STANDARD, + tmod::TRANS, + ); + self.spi + .send_data_dma(self.dmac, self.channel, self.spi_cs, data); + } + */ + + fn read_data(&self, data: &mut [u8]) { + self.spi.configure( + work_mode::MODE0, + frame_format::STANDARD, + 8, /* data bits */ + 0, /* endian */ + 0, /*instruction length*/ + 0, /*address length*/ + 0, /*wait cycles*/ + aitm::STANDARD, + tmod::RECV, + ); + self.spi.recv_data(self.spi_cs, data); + } + + /* + fn read_data_dma(&self, data: &mut [u32]) { + self.spi.configure( + work_mode::MODE0, + frame_format::STANDARD, + 8, /* data bits */ + 0, /* endian */ + 0, /*instruction length*/ + 0, /*address length*/ + 0, /*wait cycles*/ + aitm::STANDARD, + tmod::RECV, + ); + self.spi + .recv_data_dma(self.dmac, self.channel, self.spi_cs, data); + } + */ + + /* + * Send 5 bytes command to the SD card. + * @param cmd: The user expected command to send to SD card. + * @param arg: The command argument. + * @param crc: The CRC. + * @retval None + */ + fn send_cmd(&self, cmd: CMD, arg: u32, crc: u8) { + /* SD chip select low */ + self.CS_LOW(); + /* Send the Cmd bytes */ + self.write_data(&[ + /* Construct byte 1 */ + ((cmd as u8) | 0x40), + /* Construct byte 2 */ + (arg >> 24) as u8, + /* Construct byte 3 */ + ((arg >> 16) & 0xff) as u8, + /* Construct byte 4 */ + ((arg >> 8) & 0xff) as u8, + /* Construct byte 5 */ + (arg & 0xff) as u8, + /* Construct CRC: byte 6 */ + crc, + ]); + } + + /* Send end-command sequence to SD card */ + fn end_cmd(&self) { + /* SD chip select high */ + self.CS_HIGH(); + /* Send the cmd byte */ + self.write_data(&[0xff]); + } + + /* + * Returns the SD response. + * @param None + * @retval The SD Response: + * - 0xFF: Sequence failed + * - 0: Sequence succeed + */ + fn get_response(&self) -> u8 { + let result = &mut [0u8]; + let mut timeout = 0x0FFF; + /* Check if response is got or a timeout is happen */ + while timeout != 0 { + self.read_data(result); + /* Right response got */ + if result[0] != 0xFF { + return result[0]; + } + timeout -= 1; + } + /* After time out */ + return 0xFF; + } + + /* + * Get SD card data response. + * @param None + * @retval The SD status: Read data response xxx01 + * - status 010: Data accecpted + * - status 101: Data rejected due to a crc error + * - status 110: Data rejected due to a Write error. + * - status 111: Data rejected due to other error. + */ + fn get_dataresponse(&self) -> u8 { + let response = &mut [0u8]; + /* Read resonse */ + self.read_data(response); + /* Mask unused bits */ + response[0] &= 0x1F; + if response[0] != 0x05 { + return 0xFF; + } + /* Wait null data */ + self.read_data(response); + while response[0] == 0 { + self.read_data(response); + } + /* Return response */ + return 0; + } + + /* + * Read the CSD card register + * Reading the contents of the CSD register in SPI mode is a simple + * read-block transaction. + * @param SD_csd: pointer on an SCD register structure + * @retval The SD Response: + * - `Err()`: Sequence failed + * - `Ok(info)`: Sequence succeed + */ + fn get_csdregister(&self) -> Result { + let mut csd_tab = [0u8; 18]; + /* Send CMD9 (CSD register) */ + self.send_cmd(CMD::CMD9, 0, 0); + /* Wait for response in the R1 format (0x00 is no errors) */ + if self.get_response() != 0x00 { + self.end_cmd(); + return Err(()); + } + if self.get_response() != SD_START_DATA_SINGLE_BLOCK_READ { + self.end_cmd(); + return Err(()); + } + /* Store CSD register value on csd_tab */ + /* Get CRC bytes (not really needed by us, but required by SD) */ + self.read_data(&mut csd_tab); + self.end_cmd(); + /* see also: https://cdn-shop.adafruit.com/datasheets/TS16GUSDHC6.pdf */ + return Ok(SD_CSD { + /* Byte 0 */ + CSDStruct: (csd_tab[0] & 0xC0) >> 6, + SysSpecVersion: (csd_tab[0] & 0x3C) >> 2, + Reserved1: csd_tab[0] & 0x03, + /* Byte 1 */ + TAAC: csd_tab[1], + /* Byte 2 */ + NSAC: csd_tab[2], + /* Byte 3 */ + MaxBusClkFrec: csd_tab[3], + /* Byte 4, 5 */ + CardComdClasses: (u16::from(csd_tab[4]) << 4) | ((u16::from(csd_tab[5]) & 0xF0) >> 4), + /* Byte 5 */ + RdBlockLen: csd_tab[5] & 0x0F, + /* Byte 6 */ + PartBlockRead: (csd_tab[6] & 0x80) >> 7, + WrBlockMisalign: (csd_tab[6] & 0x40) >> 6, + RdBlockMisalign: (csd_tab[6] & 0x20) >> 5, + DSRImpl: (csd_tab[6] & 0x10) >> 4, + Reserved2: 0, + // DeviceSize: (csd_tab[6] & 0x03) << 10, + /* Byte 7, 8, 9 */ + DeviceSize: ((u32::from(csd_tab[7]) & 0x3F) << 16) + | (u32::from(csd_tab[8]) << 8) + | u32::from(csd_tab[9]), + /* Byte 10 */ + EraseGrSize: (csd_tab[10] & 0x40) >> 6, + /* Byte 10, 11 */ + EraseGrMul: ((csd_tab[10] & 0x3F) << 1) | ((csd_tab[11] & 0x80) >> 7), + /* Byte 11 */ + WrProtectGrSize: (csd_tab[11] & 0x7F), + /* Byte 12 */ + WrProtectGrEnable: (csd_tab[12] & 0x80) >> 7, + ManDeflECC: (csd_tab[12] & 0x60) >> 5, + WrSpeedFact: (csd_tab[12] & 0x1C) >> 2, + /* Byte 12,13 */ + MaxWrBlockLen: ((csd_tab[12] & 0x03) << 2) | ((csd_tab[13] & 0xC0) >> 6), + /* Byte 13 */ + WriteBlockPaPartial: (csd_tab[13] & 0x20) >> 5, + Reserved3: 0, + ContentProtectAppli: (csd_tab[13] & 0x01), + /* Byte 14 */ + FileFormatGroup: (csd_tab[14] & 0x80) >> 7, + CopyFlag: (csd_tab[14] & 0x40) >> 6, + PermWrProtect: (csd_tab[14] & 0x20) >> 5, + TempWrProtect: (csd_tab[14] & 0x10) >> 4, + FileFormat: (csd_tab[14] & 0x0C) >> 2, + ECC: (csd_tab[14] & 0x03), + /* Byte 15 */ + CSD_CRC: (csd_tab[15] & 0xFE) >> 1, + Reserved4: 1, + /* Return the reponse */ + }); + } + + /* + * Read the CID card register. + * Reading the contents of the CID register in SPI mode is a simple + * read-block transaction. + * @param SD_cid: pointer on an CID register structure + * @retval The SD Response: + * - `Err()`: Sequence failed + * - `Ok(info)`: Sequence succeed + */ + fn get_cidregister(&self) -> Result { + let mut cid_tab = [0u8; 18]; + /* Send CMD10 (CID register) */ + self.send_cmd(CMD::CMD10, 0, 0); + /* Wait for response in the R1 format (0x00 is no errors) */ + if self.get_response() != 0x00 { + self.end_cmd(); + return Err(()); + } + if self.get_response() != SD_START_DATA_SINGLE_BLOCK_READ { + self.end_cmd(); + return Err(()); + } + /* Store CID register value on cid_tab */ + /* Get CRC bytes (not really needed by us, but required by SD) */ + self.read_data(&mut cid_tab); + self.end_cmd(); + return Ok(SD_CID { + /* Byte 0 */ + ManufacturerID: cid_tab[0], + /* Byte 1, 2 */ + OEM_AppliID: (u16::from(cid_tab[1]) << 8) | u16::from(cid_tab[2]), + /* Byte 3, 4, 5, 6 */ + ProdName1: (u32::from(cid_tab[3]) << 24) + | (u32::from(cid_tab[4]) << 16) + | (u32::from(cid_tab[5]) << 8) + | u32::from(cid_tab[6]), + /* Byte 7 */ + ProdName2: cid_tab[7], + /* Byte 8 */ + ProdRev: cid_tab[8], + /* Byte 9, 10, 11, 12 */ + ProdSN: (u32::from(cid_tab[9]) << 24) + | (u32::from(cid_tab[10]) << 16) + | (u32::from(cid_tab[11]) << 8) + | u32::from(cid_tab[12]), + /* Byte 13, 14 */ + Reserved1: (cid_tab[13] & 0xF0) >> 4, + ManufactDate: ((u16::from(cid_tab[13]) & 0x0F) << 8) | u16::from(cid_tab[14]), + /* Byte 15 */ + CID_CRC: (cid_tab[15] & 0xFE) >> 1, + Reserved2: 1, + }); + } + + /* + * Returns information about specific card. + * @param cardinfo: pointer to a SD_CardInfo structure that contains all SD + * card information. + * @retval The SD Response: + * - `Err(())`: Sequence failed + * - `Ok(info)`: Sequence succeed + */ + fn get_cardinfo(&self) -> Result { + let mut info = SD_CardInfo { + SD_csd: self.get_csdregister()?, + SD_cid: self.get_cidregister()?, + CardCapacity: 0, + CardBlockSize: 0, + }; + info.CardBlockSize = 1 << u64::from(info.SD_csd.RdBlockLen); + info.CardCapacity = (u64::from(info.SD_csd.DeviceSize) + 1) * 1024 * info.CardBlockSize; + + Ok(info) + } + + /* + * Initializes the SD/SD communication in SPI mode. + * @param None + * @retval The SD Response info if succeeeded, otherwise Err + */ + pub fn init(&self) -> Result { + /* Initialize SD_SPI */ + self.lowlevel_init(); + /* SD chip select high */ + self.CS_HIGH(); + /* NOTE: this reset doesn't always seem to work if the SD access was broken off in the + * middle of an operation: CMDFailed(CMD0, 127). */ + + /* Send dummy byte 0xFF, 10 times with CS high */ + /* Rise CS and MOSI for 80 clocks cycles */ + /* Send dummy byte 0xFF */ + self.write_data(&[0xff; 10]); + /*------------Put SD in SPI mode--------------*/ + /* SD initialized and set to SPI mode properly */ + + /* Send software reset */ + self.send_cmd(CMD::CMD0, 0, 0x95); + let result = self.get_response(); + self.end_cmd(); + if result != 0x01 { + return Err(InitError::CMDFailed(CMD::CMD0, result)); + } + + /* Check voltage range */ + self.send_cmd(CMD::CMD8, 0x01AA, 0x87); + /* 0x01 or 0x05 */ + let result = self.get_response(); + let mut frame = [0u8; 4]; + self.read_data(&mut frame); + self.end_cmd(); + if result != 0x01 { + return Err(InitError::CMDFailed(CMD::CMD8, result)); + } + let mut index = 255; + while index != 0 { + /* */ + self.send_cmd(CMD::CMD55, 0, 0); + let result = self.get_response(); + self.end_cmd(); + if result != 0x01 { + return Err(InitError::CMDFailed(CMD::CMD55, result)); + } + /* Initiate SDC initialization process */ + self.send_cmd(CMD::ACMD41, 0x40000000, 0); + let result = self.get_response(); + self.end_cmd(); + if result == 0x00 { + break; + } + index -= 1; + } + if index == 0 { + return Err(InitError::CMDFailed(CMD::ACMD41, result)); + } + index = 255; + let mut frame = [0u8; 4]; + while index != 0 { + /* Read OCR */ + self.send_cmd(CMD::CMD58, 0, 1); + let result = self.get_response(); + self.read_data(&mut frame); + self.end_cmd(); + if result == 0 { + break; + } + index -= 1; + } + if index == 0 { + return Err(InitError::CMDFailed(CMD::CMD58, result)); + } + if (frame[0] & 0x40) == 0 { + return Err(InitError::CardCapacityStatusNotSet(frame)); + } + self.HIGH_SPEED_ENABLE(); + self.get_cardinfo() + .map_err(|_| InitError::CannotGetCardInfo) + } + + /* + * Reads a block of data from the SD. + * @param data_buf: slice that receives the data read from the SD. + * @param sector: SD's internal address to read from. + * @retval The SD Response: + * - `Err(())`: Sequence failed + * - `Ok(())`: Sequence succeed + */ + pub fn read_sector(&self, data_buf: &mut [u8], sector: u32) -> Result<(), ()> { + assert!(data_buf.len() >= SEC_LEN && (data_buf.len() % SEC_LEN) == 0); + /* Send CMD17 to read one block, or CMD18 for multiple */ + let flag = if data_buf.len() == SEC_LEN { + self.send_cmd(CMD::CMD17, sector, 0); + false + } else { + self.send_cmd(CMD::CMD18, sector, 0); + true + }; + /* Check if the SD acknowledged the read block command: R1 response (0x00: no errors) */ + if self.get_response() != 0x00 { + self.end_cmd(); + return Err(()); + } + let mut error = false; + //let mut dma_chunk = [0u32; SEC_LEN]; + let mut tmp_chunk= [0u8; SEC_LEN]; + for chunk in data_buf.chunks_mut(SEC_LEN) { + if self.get_response() != SD_START_DATA_SINGLE_BLOCK_READ { + error = true; + break; + } + /* Read the SD block data : read NumByteToRead data */ + //self.read_data_dma(&mut dma_chunk); + self.read_data(&mut tmp_chunk); + /* Place the data received as u32 units from DMA into the u8 target buffer */ + for (a, b) in chunk.iter_mut().zip(/*dma_chunk*/tmp_chunk.iter()) { + //*a = (b & 0xff) as u8; + *a = *b; + } + /* Get CRC bytes (not really needed by us, but required by SD) */ + let mut frame = [0u8; 2]; + self.read_data(&mut frame); + } + self.end_cmd(); + if flag { + self.send_cmd(CMD::CMD12, 0, 0); + self.get_response(); + self.end_cmd(); + self.end_cmd(); + } + /* It is an error if not everything requested was read */ + if error { + Err(()) + } else { + Ok(()) + } + } + + /* + * Writes a block to the SD + * @param data_buf: slice containing the data to be written to the SD. + * @param sector: address to write on. + * @retval The SD Response: + * - `Err(())`: Sequence failed + * - `Ok(())`: Sequence succeed + */ + pub fn write_sector(&self, data_buf: &[u8], sector: u32) -> Result<(), ()> { + assert!(data_buf.len() >= SEC_LEN && (data_buf.len() % SEC_LEN) == 0); + let mut frame = [0xff, 0x00]; + if data_buf.len() == SEC_LEN { + frame[1] = SD_START_DATA_SINGLE_BLOCK_WRITE; + self.send_cmd(CMD::CMD24, sector, 0); + } else { + frame[1] = SD_START_DATA_MULTIPLE_BLOCK_WRITE; + self.send_cmd( + CMD::ACMD23, + (data_buf.len() / SEC_LEN).try_into().unwrap(), + 0, + ); + self.get_response(); + self.end_cmd(); + self.send_cmd(CMD::CMD25, sector, 0); + } + /* Check if the SD acknowledged the write block command: R1 response (0x00: no errors) */ + if self.get_response() != 0x00 { + self.end_cmd(); + return Err(()); + } + //let mut dma_chunk = [0u32; SEC_LEN]; + let mut tmp_chunk = [0u8; SEC_LEN]; + for chunk in data_buf.chunks(SEC_LEN) { + /* Send the data token to signify the start of the data */ + self.write_data(&frame); + /* Write the block data to SD : write count data by block */ + for (a, &b) in /*dma_chunk*/tmp_chunk.iter_mut().zip(chunk.iter()) { + //*a = b.into(); + *a = b; + } + //self.write_data_dma(&mut dma_chunk); + self.write_data(&mut tmp_chunk); + /* Put dummy CRC bytes */ + self.write_data(&[0xff, 0xff]); + /* Read data response */ + if self.get_dataresponse() != 0x00 { + self.end_cmd(); + return Err(()); + } + } + self.end_cmd(); + self.end_cmd(); + Ok(()) + } +} + +/** GPIOHS GPIO number to use for controlling the SD card CS pin */ +const SD_CS_GPIONUM: u8 = 7; +/** CS value passed to SPI controller, this is a dummy value as SPI0_CS3 is not mapping to anything + * in the FPIOA */ +const SD_CS: u32 = 3; + +use k210_pac::{Peripherals, SPI0}; +use k210_hal::prelude::*; +use crate::drivers::soc::{ + fpioa::{self, io}, + sysctl, + sleep::usleep, + dmac::DMACExt, + spi::{ + SPIExt, + SPIImpl, + }, +}; +use spin::Mutex; +use lazy_static::*; +use bitflags::_core::ptr::null; + +/** Connect pins to internal functions */ +fn io_init() { + fpioa::set_function(io::SPI0_SCLK, fpioa::function::SPI0_SCLK); + fpioa::set_function(io::SPI0_MOSI, fpioa::function::SPI0_D0); + fpioa::set_function(io::SPI0_MISO, fpioa::function::SPI0_D1); + fpioa::set_function(io::SPI0_CS0, fpioa::function::gpiohs(SD_CS_GPIONUM)); + fpioa::set_io_pull(io::SPI0_CS0, fpioa::pull::DOWN); // GPIO output=pull down +} + +fn ch(i: u8) -> char { + if i >= 0x20 && i < 0x80 { + i.into() + } else { + '.' + } +} + +fn hexdump(buffer: &[u8], base: usize) { + for (i, chunk) in buffer.chunks_exact(16).enumerate() { + println!("{:08x}: {:02x} {:02x} {:02x} {:02x} {:02x} {:02x} {:02x} {:02x} {:02x} {:02x} {:02x} {:02x} {:02x} {:02x} {:02x} {:02x} {}{}{}{}{}{}{}{}{}{}{}{}{}{}{}{}", + base + i * 16, + chunk[0], chunk[1], chunk[2], chunk[3], + chunk[4], chunk[5], chunk[6], chunk[7], + chunk[8], chunk[9], chunk[10], chunk[11], + chunk[12], chunk[13], chunk[14], chunk[15], + ch(chunk[0]), ch(chunk[1]), ch(chunk[2]), ch(chunk[3]), + ch(chunk[4]), ch(chunk[5]), ch(chunk[6]), ch(chunk[7]), + ch(chunk[8]), ch(chunk[9]), ch(chunk[10]), ch(chunk[11]), + ch(chunk[12]), ch(chunk[13]), ch(chunk[14]), ch(chunk[15]), + ); + } +} + +lazy_static! { + pub static ref PERIPHERALS: Mutex = Mutex::new(Peripherals::take().unwrap()); + + /* + pub static ref SDCARD: Mutex>> = Mutex::new({ + sysctl::pll_set_freq(sysctl::pll::PLL0, 800_000_000).unwrap(); + sysctl::pll_set_freq(sysctl::pll::PLL1, 300_000_000).unwrap(); + sysctl::pll_set_freq(sysctl::pll::PLL2, 45_158_400).unwrap(); + let clocks = k210_hal::clock::Clocks::new(); + PERIPHERALS.UARTHS.configure(115_200.bps(), &clocks); + + usleep(200000); + println!("Hello world!"); + + io_init(); + + //let dmac = p.DMAC.configure(); + let spi = PERIPHERALS.SPI0.constrain(); + + SDCard::new(spi, SD_CS, SD_CS_GPIONUM/*, &dmac, dma_channel::CHANNEL0*/) + }); + */ +} + +pub fn init_sdcard()->SDCard>{ + let peripherals = Peripherals::take().unwrap(); + sysctl::pll_set_freq(sysctl::pll::PLL0, 800_000_000).unwrap(); + sysctl::pll_set_freq(sysctl::pll::PLL1, 300_000_000).unwrap(); + sysctl::pll_set_freq(sysctl::pll::PLL2, 45_158_400).unwrap(); + let clocks = k210_hal::clock::Clocks::new(); + peripherals.UARTHS.configure(115_200.bps(), &clocks); + io_init(); + + let spi = peripherals.SPI0.constrain(); + let sd = SDCard::new(spi, SD_CS, SD_CS_GPIONUM); + let info = sd.init().unwrap(); + let num_sectors = info.CardCapacity / 512; + assert!(num_sectors > 0); + + println!("++++ setup sdcard ++++"); + sd +} + +pub fn sdcard_test() { + let num_sectors = get_sdcard_sectors(); + let sector: u32 = (num_sectors - 10).try_into().unwrap(); + let mut buffer = [0u8; 512]; + sdcard_read_sector(&mut buffer, sector); + println!("sector {} succesfully read", sector); + + hexdump(&buffer, 0); + + // Warning: uncommenting this will write to the SD card + let msg = b"Well! I've often seen a cat without a grin', thought Alice, 'but a grin without a cat! It's the most curious thing I ever saw in my life!'"; + let mut buffer = [0u8; 512]; + (&mut buffer[0..msg.len()]).copy_from_slice(msg); + sdcard_write_sector(&mut buffer, sector); + println!("sector {} succesfully written", sector); + + let mut read_buffer = [0u8; 512]; + sdcard_read_sector(&mut read_buffer, sector); + let string = core::str::from_utf8(&read_buffer).unwrap(); + println!("{}", string); + + sdcard_write_sector(&mut buffer, sector); + println!("sdcard test passed!"); +} + +pub fn sdcard_read_sector(data_buf: &mut [u8], sector: u32) { + let peripherals = Peripherals::take().unwrap(); + let spi = peripherals.SPI0.constrain(); + let sd = SDCard::new(spi, SD_CS, SD_CS_GPIONUM/*, &dmac, dma_channel::CHANNEL0*/); + sd.read_sector(data_buf, sector).unwrap(); +} + +pub fn sdcard_write_sector(data_buf: &mut [u8], sector: u32) { + let peripherals = Peripherals::take().unwrap(); + let spi = peripherals.SPI0.constrain(); + let sd = SDCard::new(spi, SD_CS, SD_CS_GPIONUM/*, &dmac, dma_channel::CHANNEL0*/); + sd.write_sector(data_buf, sector).unwrap(); +} + +pub fn get_sdcard_sectors() -> u64 { + let peripherals = Peripherals::take().unwrap(); + let spi = peripherals.SPI0.constrain(); + let sd = SDCard::new(spi, SD_CS, SD_CS_GPIONUM/*, &dmac, dma_channel::CHANNEL0*/); + sd.get_cardinfo().unwrap().CardCapacity / 512 +} + +pub struct Sd_card(Mutex>>); + +impl Sd_card { + pub fn new() -> Self { + Sd_card(Mutex::new(init_sdcard())) + } +} + +impl BlockDevice for Sd_card { + const BLOCK_SIZE_LOG2: u8 =9; + fn read_at(&self, block_id: usize, buf: &mut [u8]) -> rcore_fs::dev::Result<()> { + self.0.lock().read_sector(buf,block_id as u32); + Ok(()) + } + fn write_at(&self, block_id: usize, buf: &[u8]) -> rcore_fs::dev::Result<()> { + self.0.lock().write_sector(buf,block_id as u32); + Ok(()) + } + fn sync(&self) -> rcore_fs::dev::Result<()> { + Ok(()) + } +} \ No newline at end of file diff --git a/os/src/drivers/mod.rs b/os/src/drivers/mod.rs index 013c4e1..07f9fbf 100644 --- a/os/src/drivers/mod.rs +++ b/os/src/drivers/mod.rs @@ -8,6 +8,7 @@ pub mod block; pub mod bus; pub mod device_tree; pub mod driver; +pub mod soc; /// 从设备树的物理地址来获取全部设备信息并初始化 pub fn init(dtb_pa: PhysicalAddress) { diff --git a/os/src/drivers/soc/dmac.rs b/os/src/drivers/soc/dmac.rs new file mode 100644 index 0000000..5588548 --- /dev/null +++ b/os/src/drivers/soc/dmac.rs @@ -0,0 +1,637 @@ +#![allow(unused)] +#![allow(non_camel_case_types)] + +//! DMAC peripheral +//use k210_hal::pac; +use k210_pac as pac; +use pac::dmac::channel::cfg::{TT_FC_A,HS_SEL_SRC_A}; +use pac::dmac::channel::ctl::{SMS_A}; + +use super::sysctl; + +/** Extension trait for adding configure() to DMAC peripheral */ +pub trait DMACExt: Sized { + /// Constrains DVP peripheral + fn configure(self) -> DMAC; +} + +impl DMACExt for pac::DMAC { + fn configure(self) -> DMAC { DMAC::new(self) } +} + +/** DMAC peripheral abstraction */ +pub struct DMAC { + dmac: pac::DMAC, +} + +/* +typedef struct _dmac_context +{ + dmac_channel_number_t dmac_channel; + plic_irq_callback_t callback; + void *ctx; +} dmac_context_t; + +dmac_context_t dmac_context[6]; +*/ + +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub enum src_dst_select { + SRC = 0x1, + DST = 0x2, + SRC_DST = 0x3, +} + +pub use super::sysctl::dma_channel; +pub type master_number = pac::dmac::channel::ctl::SMS_A; +pub type address_increment = pac::dmac::channel::ctl::SINC_A; +pub type burst_length = pac::dmac::channel::ctl::SRC_MSIZE_A; +pub type transfer_width = pac::dmac::channel::ctl::SRC_TR_WIDTH_A; + +/** Return whether a specific address considered considered memory or peripheral */ +fn is_memory(address: u64) -> bool { + let mem_len = 6 * 1024 * 1024; + let mem_no_cache_len = 8 * 1024 * 1024; + // Note: This comes from the Kendryte SDK as-is. No, I have no idea why the AES accelerator + // input address 0x50450040 is considered memory, either. + ((address >= 0x80000000) && (address < 0x80000000 + mem_len)) + || ((address >= 0x40000000) && (address < 0x40000000 + mem_no_cache_len)) + || (address == 0x50450040) +} + +impl DMAC { + fn new(dmac: pac::DMAC) -> Self { + let rv = Self { dmac }; + rv.init(); + rv + } + + /** Get DMAC ID */ + pub fn read_id(&self) -> u64 { + return self.dmac.id.read().bits(); + } + + /** Get DMAC version */ + pub fn read_version(&self) -> u64 { + return self.dmac.compver.read().bits(); + } + + /** Get AXI ID for channel */ + pub fn read_channel_id(&self, channel_num: dma_channel) -> u64 { + return self.dmac.channel[channel_num.idx()].axi_id.read().bits(); + } + + /** Enable DMAC peripheral. */ + fn enable(&self) { + self.dmac.cfg.modify(|_,w| w.dmac_en().set_bit() + .int_en().set_bit()); + } + + /** Disable DMAC peripheral. */ + pub fn disable(&self) { + self.dmac.cfg.modify(|_,w| w.dmac_en().clear_bit() + .int_en().clear_bit()); + } + + pub fn src_transaction_complete_int_enable(&self, channel_num: dma_channel) { + self.dmac.channel[channel_num.idx()].intstatus_en.modify( + |_,w| w.src_transcomp().set_bit()); + } + + /** Enable a DMA channel. */ + pub fn channel_enable(&self, channel_num: dma_channel) { + use dma_channel::*; + // Note: chX bit names start counting from 1, while channels start counting from 0 + match channel_num { + CHANNEL0 => { + self.dmac.chen.modify(|_,w| w.ch1_en().set_bit() + .ch1_en_we().set_bit()); + } + CHANNEL1 => { + self.dmac.chen.modify(|_,w| w.ch2_en().set_bit() + .ch2_en_we().set_bit()); + } + CHANNEL2 => { + self.dmac.chen.modify(|_,w| w.ch3_en().set_bit() + .ch3_en_we().set_bit()); + } + CHANNEL3 => { + self.dmac.chen.modify(|_,w| w.ch4_en().set_bit() + .ch4_en_we().set_bit()); + } + CHANNEL4 => { + self.dmac.chen.modify(|_,w| w.ch5_en().set_bit() + .ch5_en_we().set_bit()); + } + CHANNEL5 => { + self.dmac.chen.modify(|_,w| w.ch6_en().set_bit() + .ch6_en_we().set_bit()); + } + } + } + + /** Disable a DMA channel. */ + pub fn channel_disable(&self, channel_num: dma_channel) { + use dma_channel::*; + // Note: chX bit names start counting from 1, while channels start counting from 0 + match channel_num { + CHANNEL0 => { + self.dmac.chen.modify(|_,w| w.ch1_en().clear_bit() + .ch1_en_we().set_bit()); + } + CHANNEL1 => { + self.dmac.chen.modify(|_,w| w.ch2_en().clear_bit() + .ch2_en_we().set_bit()); + } + CHANNEL2 => { + self.dmac.chen.modify(|_,w| w.ch3_en().clear_bit() + .ch3_en_we().set_bit()); + } + CHANNEL3 => { + self.dmac.chen.modify(|_,w| w.ch4_en().clear_bit() + .ch4_en_we().set_bit()); + } + CHANNEL4 => { + self.dmac.chen.modify(|_,w| w.ch5_en().clear_bit() + .ch5_en_we().set_bit()); + } + CHANNEL5 => { + self.dmac.chen.modify(|_,w| w.ch6_en().clear_bit() + .ch6_en_we().set_bit()); + } + } + } + + /** Check if a DMA channel is busy. */ + pub fn check_channel_busy(&self, channel_num: dma_channel) -> bool { + use dma_channel::*; + match channel_num { + CHANNEL0 => self.dmac.chen.read().ch1_en().bit(), + CHANNEL1 => self.dmac.chen.read().ch2_en().bit(), + CHANNEL2 => self.dmac.chen.read().ch3_en().bit(), + CHANNEL3 => self.dmac.chen.read().ch4_en().bit(), + CHANNEL4 => self.dmac.chen.read().ch5_en().bit(), + CHANNEL5 => self.dmac.chen.read().ch6_en().bit(), + } + // Note: Kendryte SDK writes back the value after reading it, + // is this necessary? It seems not. + } + + pub fn set_list_master_select(&self, channel_num: dma_channel, sd_sel: src_dst_select, mst_num: master_number) -> Result<(),()> { + if !self.check_channel_busy(channel_num) { + use src_dst_select::*; + self.dmac.channel[channel_num.idx()].ctl.modify(|_,w| { + let w = if sd_sel == SRC || sd_sel == SRC_DST { + w.sms().variant(mst_num) + } else { + w + }; + if sd_sel == DST || sd_sel == SRC_DST { + w.dms().variant(mst_num) + } else { + w + } + }); + // Note: there's some weird tmp|= line here in the Kendryte SDK + // with the result going unused. I've decided to leave this out + // because I assume it's another C UB workaround. + Ok(()) + } else { + Err(()) + } + } + + pub fn enable_common_interrupt_status(&self) { + self.dmac.com_intstatus_en.modify(|_,w| + w.slvif_dec_err().set_bit() + .slvif_wr2ro_err().set_bit() + .slvif_rd2wo_err().set_bit() + .slvif_wronhold_err().set_bit() + .slvif_undefinedreg_dec_err().set_bit() + ); + } + + pub fn enable_common_interrupt_signal(&self) { + self.dmac.com_intsignal_en.modify(|_,w| + w.slvif_dec_err().set_bit() + .slvif_wr2ro_err().set_bit() + .slvif_rd2wo_err().set_bit() + .slvif_wronhold_err().set_bit() + .slvif_undefinedreg_dec_err().set_bit() + ); + } + + fn enable_channel_interrupt(&self, channel_num: dma_channel) { + unsafe { + let ch = &self.dmac.channel[channel_num.idx()]; + ch.intclear.write(|w| w.bits(0xffffffff)); + ch.intstatus_en.write(|w| w.bits(0x2)); + } + } + + pub fn disable_channel_interrupt(&self, channel_num: dma_channel) { + unsafe { + self.dmac.channel[channel_num.idx()].intstatus_en.write( + |w| w.bits(0x0)); + } + } + + fn channel_interrupt_clear(&self, channel_num: dma_channel) { + unsafe { + self.dmac.channel[channel_num.idx()].intclear.write( + |w| w.bits(0xffffffff)); + } + } + + /** Set DMA channel parameters. */ + pub fn set_channel_param(&self, channel_num: dma_channel, + src: u64, dest: u64, src_inc: address_increment, dest_inc: address_increment, + burst_size: burst_length, + trans_width: transfer_width, + block_size: u32) { + unsafe { + let ch = &self.dmac.channel[channel_num.idx()]; + let src_is_mem = is_memory(src); + let dest_is_mem = is_memory(dest); + let flow_control = match (src_is_mem, dest_is_mem) { + (false, false) => TT_FC_A::PRF2PRF_DMA, + (true, false) => TT_FC_A::MEM2PRF_DMA, + (false, true) => TT_FC_A::PRF2MEM_DMA, + (true, true) => TT_FC_A::MEM2MEM_DMA, + }; + + /* + * cfg register must configure before ts_block and + * sar dar register + */ + ch.cfg.modify(|_,w| + w.tt_fc().variant(flow_control) + .hs_sel_src().variant(if src_is_mem { HS_SEL_SRC_A::SOFTWARE } else { HS_SEL_SRC_A::HARDWARE } ) + .hs_sel_dst().variant(if dest_is_mem { HS_SEL_SRC_A::SOFTWARE } else { HS_SEL_SRC_A::HARDWARE } ) + // Note: from SVD: "Assign a hardware handshaking interface to source of channel", + // these are set using sysctl::dma_select; this configuration seems to indicate + // that in principle, it's possible to use a different source and destination + // handshaking interface for a channel, but that would sacrifice the interface of + // another channel. + .src_per().bits(channel_num as u8) + .dst_per().bits(channel_num as u8) + .src_multblk_type().bits(0) + .dst_multblk_type().bits(0) + ); + + ch.sar.write(|w| w.bits(src)); + ch.dar.write(|w| w.bits(dest)); + + ch.ctl.modify(|_,w| + w.sms().variant(SMS_A::AXI_MASTER_1) + .dms().variant(SMS_A::AXI_MASTER_2) + /* master select */ + .sinc().variant(src_inc) + .dinc().variant(dest_inc) + /* address incrememt */ + .src_tr_width().variant(trans_width) + .dst_tr_width().variant(trans_width) + /* transfer width */ + .src_msize().variant(burst_size) + .dst_msize().variant(burst_size) + ); + + ch.block_ts.write(|w| w.block_ts().bits(block_size - 1)); + /*the number of (blcok_ts +1) data of width SRC_TR_WIDTF to be */ + /* transferred in a dma block transfer */ + } + } + + /* + pub void set_address(&self, dmac_channel_number_t channel_num, uint64_t src_addr, + uint64_t dst_addr) { + writeq(src_addr, &dmac->channel[channel_num].sar); + writeq(dst_addr, &dmac->channel[channel_num].dar); + } + */ + + /* + pub void set_block_ts(&self, dmac_channel_number_t channel_num, + uint32_t block_size) { + uint32_t block_ts; + + block_ts = block_size & 0x3fffff; + writeq(block_ts, &dmac->channel[channel_num].block_ts); + } + */ + + /* + pub void source_control(&self, dmac_channel_number_t channel_num, + dmac_master_number_t master_select, + dmac_address_increment_t address_mode, + dmac_transfer_width_t tr_width, + dmac_burst_length_t burst_length) { + dmac_ch_ctl_u_t ctl_u; + + ctl_u.data = readq(&dmac->channel[channel_num].ctl); + ctl_u.ch_ctl.sms = master_select; + ctl_u.ch_ctl.sinc = address_mode; + ctl_u.ch_ctl.src_tr_width = tr_width; + ctl_u.ch_ctl.src_msize = burst_length; + + writeq(ctl_u.data, &dmac->channel[channel_num].ctl); + } + */ + + /* + pub void master_control(&self, dmac_channel_number_t channel_num, + dmac_master_number_t master_select, + dmac_address_increment_t address_mode, + dmac_transfer_width_t tr_width, + dmac_burst_length_t burst_length) { + dmac_ch_ctl_u_t ctl_u; + + ctl_u.data = readq(&dmac->channel[channel_num].ctl); + ctl_u.ch_ctl.dms = master_select; + ctl_u.ch_ctl.dinc = address_mode; + ctl_u.ch_ctl.dst_tr_width = tr_width; + ctl_u.ch_ctl.dst_msize = burst_length; + + writeq(ctl_u.data, &dmac->channel[channel_num].ctl); + } + */ + + /* + pub void set_source_transfer_control(&self, dmac_channel_number_t channel_num, + dmac_multiblk_transfer_type_t transfer_type, + dmac_sw_hw_hs_select_t handshak_select) { + dmac_ch_cfg_u_t cfg_u; + + cfg_u.data = readq(&dmac->channel[channel_num].cfg); + cfg_u.ch_cfg.src_multblk_type = transfer_type; + cfg_u.ch_cfg.hs_sel_src = handshak_select; + + writeq(cfg_u.data, &dmac->channel[channel_num].cfg); + } + */ + + /* + pub void set_destination_transfer_control(&self, dmac_channel_number_t channel_num, + dmac_multiblk_transfer_type_t transfer_type, + dmac_sw_hw_hs_select_t handshak_select) { + dmac_ch_cfg_u_t cfg_u; + + cfg_u.data = readq(&dmac->channel[channel_num].cfg); + cfg_u.ch_cfg.dst_multblk_type = transfer_type; + cfg_u.ch_cfg.hs_sel_dst = handshak_select; + + writeq(cfg_u.data, &dmac->channel[channel_num].cfg); + } + */ + + /* + pub void set_flow_control(&self, dmac_channel_number_t channel_num, + dmac_transfer_flow_t flow_control) { + dmac_ch_cfg_u_t cfg_u; + + cfg_u.data = readq(&dmac->channel[channel_num].cfg); + cfg_u.ch_cfg.tt_fc = flow_control; + + writeq(cfg_u.data, &dmac->channel[channel_num].cfg); + } + */ + + /* + pub void set_linked_list_addr_point(&self, dmac_channel_number_t channel_num, + uint64_t *addr) { + dmac_ch_llp_u_t llp_u; + + llp_u.data = readq(&dmac->channel[channel_num].llp); + /* Cast pointer to uint64_t */ + llp_u.llp.loc = (uint64_t)addr; + writeq(llp_u.data, &dmac->channel[channel_num].llp); + } + */ + + /** Initialize DMA controller */ + pub fn init(&self) { + sysctl::clock_enable(sysctl::clock::DMA); + + /* reset dmac */ + self.dmac.reset.modify(|_,w| w.rst().set_bit()); + while self.dmac.reset.read().rst().bit() { + // IDLE + } + + /* clear common register interrupt */ + self.dmac.com_intclear.modify(|_,w| + w.slvif_dec_err().set_bit() + .slvif_wr2ro_err().set_bit() + .slvif_rd2wo_err().set_bit() + .slvif_wronhold_err().set_bit() + .slvif_undefinedreg_dec_err().set_bit() + ); + + /* disable dmac and disable interrupt */ + self.dmac.cfg.modify(|_,w| + w.dmac_en().clear_bit() + .int_en().clear_bit() + ); + + while self.dmac.cfg.read().bits() != 0 { + // IDLE + } + /* disable all channel before configure */ + /* Note: changed from the SDK code, which doesn't clear channel 4 and 5, + * and doesn't set associated _we bits */ + self.dmac.chen.modify(|_,w| + w.ch1_en().clear_bit() + .ch1_en_we().set_bit() + .ch2_en().clear_bit() + .ch2_en_we().set_bit() + .ch3_en().clear_bit() + .ch3_en_we().set_bit() + .ch4_en().clear_bit() + .ch4_en_we().set_bit() + .ch5_en().clear_bit() + .ch5_en_we().set_bit() + ); + + self.enable(); + } + +// TODO: list (scatter/gather) functionality + + /* + static void list_add(struct list_head_t *new, struct list_head_t *prev, + struct list_head_t *next) { + next->prev = new; + new->next = next; + new->prev = prev; + prev->next = new; + } + */ + + /* + pub void list_add_tail(struct list_head_t *new, struct list_head_t *head) { + list_add(new, head->prev, head); + } + */ + + /* + pub void INIT_LIST_HEAD(struct list_head_t *list) { + list->next = list; + list->prev = list; + } + */ + + /* + pub void link_list_item(dmac_channel_number_t channel_num, + uint8_t LLI_row_num, int8_t LLI_last_row, + dmac_lli_item_t *lli_item, + dmac_channel_config_t *cfg_param) { + dmac_ch_ctl_u_t ctl; + dmac_ch_llp_u_t llp_u; + + lli_item[LLI_row_num].sar = cfg_param->sar; + lli_item[LLI_row_num].dar = cfg_param->dar; + + ctl.data = readq(&dmac->channel[channel_num].ctl); + ctl.ch_ctl.sms = cfg_param->ctl_sms; + ctl.ch_ctl.dms = cfg_param->ctl_dms; + ctl.ch_ctl.sinc = cfg_param->ctl_sinc; + ctl.ch_ctl.dinc = cfg_param->ctl_dinc; + ctl.ch_ctl.src_tr_width = cfg_param->ctl_src_tr_width; + ctl.ch_ctl.dst_tr_width = cfg_param->ctl_dst_tr_width; + ctl.ch_ctl.src_msize = cfg_param->ctl_src_msize; + ctl.ch_ctl.dst_msize = cfg_param->ctl_drc_msize; + ctl.ch_ctl.src_stat_en = cfg_param->ctl_src_stat_en; + ctl.ch_ctl.dst_stat_en = cfg_param->ctl_dst_stat_en; + + if(LLI_last_row != LAST_ROW) + { + ctl.ch_ctl.shadowreg_or_lli_valid = 1; + ctl.ch_ctl.shadowreg_or_lli_last = 0; + } else + { + ctl.ch_ctl.shadowreg_or_lli_valid = 1; + ctl.ch_ctl.shadowreg_or_lli_last = 1; + } + + lli_item[LLI_row_num].ctl = ctl.data; + + lli_item[LLI_row_num].ch_block_ts = cfg_param->ctl_block_ts; + lli_item[LLI_row_num].sstat = 0; + lli_item[LLI_row_num].dstat = 0; + + llp_u.data = readq(&dmac->channel[channel_num].llp); + + if(LLI_last_row != LAST_ROW) + llp_u.llp.loc = ((uint64_t)&lli_item[LLI_row_num + 1]) >> 6; + else + llp_u.llp.loc = 0; + + lli_item[LLI_row_num].llp = llp_u.data; + } + + pub void update_shadow_register(&self, dmac_channel_number_t channel_num, + int8_t last_block, dmac_channel_config_t *cfg_param) { + dmac_ch_ctl_u_t ctl_u; + + do + { + ctl_u.data = readq(&dmac->channel[channel_num].ctl); + } while(ctl_u.ch_ctl.shadowreg_or_lli_valid); + + writeq(cfg_param->sar, &dmac->channel[channel_num].sar); + writeq(cfg_param->dar, &dmac->channel[channel_num].dar); + writeq(cfg_param->ctl_block_ts, &dmac->channel[channel_num].block_ts); + + ctl_u.ch_ctl.sms = cfg_param->ctl_sms; + ctl_u.ch_ctl.dms = cfg_param->ctl_dms; + ctl_u.ch_ctl.sinc = cfg_param->ctl_sinc; + ctl_u.ch_ctl.dinc = cfg_param->ctl_dinc; + ctl_u.ch_ctl.src_tr_width = cfg_param->ctl_src_tr_width; + ctl_u.ch_ctl.dst_tr_width = cfg_param->ctl_dst_tr_width; + ctl_u.ch_ctl.src_msize = cfg_param->ctl_src_msize; + ctl_u.ch_ctl.dst_msize = cfg_param->ctl_drc_msize; + ctl_u.ch_ctl.src_stat_en = cfg_param->ctl_src_stat_en; + ctl_u.ch_ctl.dst_stat_en = cfg_param->ctl_dst_stat_en; + if(last_block != LAST_ROW) + { + ctl_u.ch_ctl.shadowreg_or_lli_valid = 1; + ctl_u.ch_ctl.shadowreg_or_lli_last = 0; + } else + { + ctl_u.ch_ctl.shadowreg_or_lli_valid = 1; + ctl_u.ch_ctl.shadowreg_or_lli_last = 1; + } + + writeq(ctl_u.data, &dmac->channel[channel_num].ctl); + writeq(0, &dmac->channel[channel_num].blk_tfr); + } + */ + + /* + pub void set_shadow_invalid_flag(&self, dmac_channel_number_t channel_num) { + dmac_ch_ctl_u_t ctl_u; + + ctl_u.data = readq(&dmac->channel[channel_num].ctl); + ctl_u.ch_ctl.shadowreg_or_lli_valid = 1; + ctl_u.ch_ctl.shadowreg_or_lli_last = 0; + writeq(ctl_u.data, &dmac->channel[channel_num].ctl); + } + */ + + /** Start a single DMA transfer. */ + pub fn set_single_mode(&self, channel_num: dma_channel, + src: u64, dest: u64, src_inc: address_increment, + dest_inc: address_increment, + burst_size: burst_length, + trans_width: transfer_width, + block_size: u32) { + self.channel_interrupt_clear(channel_num); + self.channel_disable(channel_num); + self.wait_idle(channel_num); + self.set_channel_param(channel_num, src, dest, src_inc, dest_inc, + burst_size, trans_width, block_size); + self.enable(); + self.channel_enable(channel_num); + } + + /* + pub int is_done(&self, dmac_channel_number_t channel_num) { + if(readq(&dmac->channel[channel_num].intstatus) & 0x2) + return 1; + else + return 0; + } + */ + + /** Wait for dmac work done. */ + pub fn wait_done(&self, channel_num: dma_channel) { + self.wait_idle(channel_num); + } + + /** Determine if a DMA channel is idle or not. */ + pub fn is_idle(&self, channel_num: dma_channel) -> bool { + !self.check_channel_busy(channel_num) + } + + /** Wait for a DMA channel to be idle. */ + pub fn wait_idle(&self, channel_num: dma_channel) { + while !self.is_idle(channel_num) { + } + self.channel_interrupt_clear(channel_num); /* clear interrupt */ + } + + /* + pub void set_src_dest_length(&self, dmac_channel_number_t channel_num, const void *src, void *dest, size_t len) { + if(src != NULL) + dmac->channel[channel_num].sar = (uint64_t)src; + if(dest != NULL) + dmac->channel[channel_num].dar = (uint64_t)dest; + if(len > 0) + dmac_set_block_ts(channel_num, len - 1); + dmac_channel_enable(channel_num); + } + */ + +// TODO: completion IRQ functionality + +} diff --git a/os/src/drivers/soc/fpioa.rs b/os/src/drivers/soc/fpioa.rs new file mode 100644 index 0000000..83662e1 --- /dev/null +++ b/os/src/drivers/soc/fpioa.rs @@ -0,0 +1,481 @@ +//! FPIOA peripheral + +#![allow(unused)] +#![allow(non_camel_case_types)] + +//use k210_hal::pac; +use k210_pac as pac; + +#[derive(Copy, Clone)] +pub enum function { + JTAG_TCLK = 0, /* JTAG Test Clock */ + JTAG_TDI = 1, /* JTAG Test Data In */ + JTAG_TMS = 2, /* JTAG Test Mode Select */ + JTAG_TDO = 3, /* JTAG Test Data Out */ + SPI0_D0 = 4, /* SPI0 Data 0 */ + SPI0_D1 = 5, /* SPI0 Data 1 */ + SPI0_D2 = 6, /* SPI0 Data 2 */ + SPI0_D3 = 7, /* SPI0 Data 3 */ + SPI0_D4 = 8, /* SPI0 Data 4 */ + SPI0_D5 = 9, /* SPI0 Data 5 */ + SPI0_D6 = 10, /* SPI0 Data 6 */ + SPI0_D7 = 11, /* SPI0 Data 7 */ + SPI0_SS0 = 12, /* SPI0 Chip Select 0 */ + SPI0_SS1 = 13, /* SPI0 Chip Select 1 */ + SPI0_SS2 = 14, /* SPI0 Chip Select 2 */ + SPI0_SS3 = 15, /* SPI0 Chip Select 3 */ + SPI0_ARB = 16, /* SPI0 Arbitration */ + SPI0_SCLK = 17, /* SPI0 Serial Clock */ + UARTHS_RX = 18, /* UART High speed Receiver */ + UARTHS_TX = 19, /* UART High speed Transmitter */ + RESV6 = 20, /* Reserved function */ + RESV7 = 21, /* Reserved function */ + CLK_SPI1 = 22, /* Clock SPI1 */ + CLK_I2C1 = 23, /* Clock I2C1 */ + GPIOHS0 = 24, /* GPIO High speed 0 */ + GPIOHS1 = 25, /* GPIO High speed 1 */ + GPIOHS2 = 26, /* GPIO High speed 2 */ + GPIOHS3 = 27, /* GPIO High speed 3 */ + GPIOHS4 = 28, /* GPIO High speed 4 */ + GPIOHS5 = 29, /* GPIO High speed 5 */ + GPIOHS6 = 30, /* GPIO High speed 6 */ + GPIOHS7 = 31, /* GPIO High speed 7 */ + GPIOHS8 = 32, /* GPIO High speed 8 */ + GPIOHS9 = 33, /* GPIO High speed 9 */ + GPIOHS10 = 34, /* GPIO High speed 10 */ + GPIOHS11 = 35, /* GPIO High speed 11 */ + GPIOHS12 = 36, /* GPIO High speed 12 */ + GPIOHS13 = 37, /* GPIO High speed 13 */ + GPIOHS14 = 38, /* GPIO High speed 14 */ + GPIOHS15 = 39, /* GPIO High speed 15 */ + GPIOHS16 = 40, /* GPIO High speed 16 */ + GPIOHS17 = 41, /* GPIO High speed 17 */ + GPIOHS18 = 42, /* GPIO High speed 18 */ + GPIOHS19 = 43, /* GPIO High speed 19 */ + GPIOHS20 = 44, /* GPIO High speed 20 */ + GPIOHS21 = 45, /* GPIO High speed 21 */ + GPIOHS22 = 46, /* GPIO High speed 22 */ + GPIOHS23 = 47, /* GPIO High speed 23 */ + GPIOHS24 = 48, /* GPIO High speed 24 */ + GPIOHS25 = 49, /* GPIO High speed 25 */ + GPIOHS26 = 50, /* GPIO High speed 26 */ + GPIOHS27 = 51, /* GPIO High speed 27 */ + GPIOHS28 = 52, /* GPIO High speed 28 */ + GPIOHS29 = 53, /* GPIO High speed 29 */ + GPIOHS30 = 54, /* GPIO High speed 30 */ + GPIOHS31 = 55, /* GPIO High speed 31 */ + GPIO0 = 56, /* GPIO pin 0 */ + GPIO1 = 57, /* GPIO pin 1 */ + GPIO2 = 58, /* GPIO pin 2 */ + GPIO3 = 59, /* GPIO pin 3 */ + GPIO4 = 60, /* GPIO pin 4 */ + GPIO5 = 61, /* GPIO pin 5 */ + GPIO6 = 62, /* GPIO pin 6 */ + GPIO7 = 63, /* GPIO pin 7 */ + UART1_RX = 64, /* UART1 Receiver */ + UART1_TX = 65, /* UART1 Transmitter */ + UART2_RX = 66, /* UART2 Receiver */ + UART2_TX = 67, /* UART2 Transmitter */ + UART3_RX = 68, /* UART3 Receiver */ + UART3_TX = 69, /* UART3 Transmitter */ + SPI1_D0 = 70, /* SPI1 Data 0 */ + SPI1_D1 = 71, /* SPI1 Data 1 */ + SPI1_D2 = 72, /* SPI1 Data 2 */ + SPI1_D3 = 73, /* SPI1 Data 3 */ + SPI1_D4 = 74, /* SPI1 Data 4 */ + SPI1_D5 = 75, /* SPI1 Data 5 */ + SPI1_D6 = 76, /* SPI1 Data 6 */ + SPI1_D7 = 77, /* SPI1 Data 7 */ + SPI1_SS0 = 78, /* SPI1 Chip Select 0 */ + SPI1_SS1 = 79, /* SPI1 Chip Select 1 */ + SPI1_SS2 = 80, /* SPI1 Chip Select 2 */ + SPI1_SS3 = 81, /* SPI1 Chip Select 3 */ + SPI1_ARB = 82, /* SPI1 Arbitration */ + SPI1_SCLK = 83, /* SPI1 Serial Clock */ + SPI_SLAVE_D0 = 84, /* SPI Slave Data 0 */ + SPI_SLAVE_SS = 85, /* SPI Slave Select */ + SPI_SLAVE_SCLK = 86, /* SPI Slave Serial Clock */ + I2S0_MCLK = 87, /* I2S0 Master Clock */ + I2S0_SCLK = 88, /* I2S0 Serial Clock(BCLK) */ + I2S0_WS = 89, /* I2S0 Word Select(LRCLK) */ + I2S0_IN_D0 = 90, /* I2S0 Serial Data Input 0 */ + I2S0_IN_D1 = 91, /* I2S0 Serial Data Input 1 */ + I2S0_IN_D2 = 92, /* I2S0 Serial Data Input 2 */ + I2S0_IN_D3 = 93, /* I2S0 Serial Data Input 3 */ + I2S0_OUT_D0 = 94, /* I2S0 Serial Data Output 0 */ + I2S0_OUT_D1 = 95, /* I2S0 Serial Data Output 1 */ + I2S0_OUT_D2 = 96, /* I2S0 Serial Data Output 2 */ + I2S0_OUT_D3 = 97, /* I2S0 Serial Data Output 3 */ + I2S1_MCLK = 98, /* I2S1 Master Clock */ + I2S1_SCLK = 99, /* I2S1 Serial Clock(BCLK) */ + I2S1_WS = 100, /* I2S1 Word Select(LRCLK) */ + I2S1_IN_D0 = 101, /* I2S1 Serial Data Input 0 */ + I2S1_IN_D1 = 102, /* I2S1 Serial Data Input 1 */ + I2S1_IN_D2 = 103, /* I2S1 Serial Data Input 2 */ + I2S1_IN_D3 = 104, /* I2S1 Serial Data Input 3 */ + I2S1_OUT_D0 = 105, /* I2S1 Serial Data Output 0 */ + I2S1_OUT_D1 = 106, /* I2S1 Serial Data Output 1 */ + I2S1_OUT_D2 = 107, /* I2S1 Serial Data Output 2 */ + I2S1_OUT_D3 = 108, /* I2S1 Serial Data Output 3 */ + I2S2_MCLK = 109, /* I2S2 Master Clock */ + I2S2_SCLK = 110, /* I2S2 Serial Clock(BCLK) */ + I2S2_WS = 111, /* I2S2 Word Select(LRCLK) */ + I2S2_IN_D0 = 112, /* I2S2 Serial Data Input 0 */ + I2S2_IN_D1 = 113, /* I2S2 Serial Data Input 1 */ + I2S2_IN_D2 = 114, /* I2S2 Serial Data Input 2 */ + I2S2_IN_D3 = 115, /* I2S2 Serial Data Input 3 */ + I2S2_OUT_D0 = 116, /* I2S2 Serial Data Output 0 */ + I2S2_OUT_D1 = 117, /* I2S2 Serial Data Output 1 */ + I2S2_OUT_D2 = 118, /* I2S2 Serial Data Output 2 */ + I2S2_OUT_D3 = 119, /* I2S2 Serial Data Output 3 */ + RESV0 = 120, /* Reserved function */ + RESV1 = 121, /* Reserved function */ + RESV2 = 122, /* Reserved function */ + RESV3 = 123, /* Reserved function */ + RESV4 = 124, /* Reserved function */ + RESV5 = 125, /* Reserved function */ + I2C0_SCLK = 126, /* I2C0 Serial Clock */ + I2C0_SDA = 127, /* I2C0 Serial Data */ + I2C1_SCLK = 128, /* I2C1 Serial Clock */ + I2C1_SDA = 129, /* I2C1 Serial Data */ + I2C2_SCLK = 130, /* I2C2 Serial Clock */ + I2C2_SDA = 131, /* I2C2 Serial Data */ + CMOS_XCLK = 132, /* DVP System Clock */ + CMOS_RST = 133, /* DVP System Reset */ + CMOS_PWDN = 134, /* DVP Power Down Mode */ + CMOS_VSYNC = 135, /* DVP Vertical Sync */ + CMOS_HREF = 136, /* DVP Horizontal Reference output */ + CMOS_PCLK = 137, /* Pixel Clock */ + CMOS_D0 = 138, /* Data Bit 0 */ + CMOS_D1 = 139, /* Data Bit 1 */ + CMOS_D2 = 140, /* Data Bit 2 */ + CMOS_D3 = 141, /* Data Bit 3 */ + CMOS_D4 = 142, /* Data Bit 4 */ + CMOS_D5 = 143, /* Data Bit 5 */ + CMOS_D6 = 144, /* Data Bit 6 */ + CMOS_D7 = 145, /* Data Bit 7 */ + SCCB_SCLK = 146, /* SCCB Serial Clock */ + SCCB_SDA = 147, /* SCCB Serial Data */ + UART1_CTS = 148, /* UART1 Clear To Send */ + UART1_DSR = 149, /* UART1 Data Set Ready */ + UART1_DCD = 150, /* UART1 Data Carrier Detect */ + UART1_RI = 151, /* UART1 Ring Indicator */ + UART1_SIR_IN = 152, /* UART1 Serial Infrared Input */ + UART1_DTR = 153, /* UART1 Data Terminal Ready */ + UART1_RTS = 154, /* UART1 Request To Send */ + UART1_OUT2 = 155, /* UART1 User-designated Output 2 */ + UART1_OUT1 = 156, /* UART1 User-designated Output 1 */ + UART1_SIR_OUT = 157, /* UART1 Serial Infrared Output */ + UART1_BAUD = 158, /* UART1 Transmit Clock Output */ + UART1_RE = 159, /* UART1 Receiver Output Enable */ + UART1_DE = 160, /* UART1 Driver Output Enable */ + UART1_RS485_EN = 161, /* UART1 RS485 Enable */ + UART2_CTS = 162, /* UART2 Clear To Send */ + UART2_DSR = 163, /* UART2 Data Set Ready */ + UART2_DCD = 164, /* UART2 Data Carrier Detect */ + UART2_RI = 165, /* UART2 Ring Indicator */ + UART2_SIR_IN = 166, /* UART2 Serial Infrared Input */ + UART2_DTR = 167, /* UART2 Data Terminal Ready */ + UART2_RTS = 168, /* UART2 Request To Send */ + UART2_OUT2 = 169, /* UART2 User-designated Output 2 */ + UART2_OUT1 = 170, /* UART2 User-designated Output 1 */ + UART2_SIR_OUT = 171, /* UART2 Serial Infrared Output */ + UART2_BAUD = 172, /* UART2 Transmit Clock Output */ + UART2_RE = 173, /* UART2 Receiver Output Enable */ + UART2_DE = 174, /* UART2 Driver Output Enable */ + UART2_RS485_EN = 175, /* UART2 RS485 Enable */ + UART3_CTS = 176, /* UART3 Clear To Send */ + UART3_DSR = 177, /* UART3 Data Set Ready */ + UART3_DCD = 178, /* UART3 Data Carrier Detect */ + UART3_RI = 179, /* UART3 Ring Indicator */ + UART3_SIR_IN = 180, /* UART3 Serial Infrared Input */ + UART3_DTR = 181, /* UART3 Data Terminal Ready */ + UART3_RTS = 182, /* UART3 Request To Send */ + UART3_OUT2 = 183, /* UART3 User-designated Output 2 */ + UART3_OUT1 = 184, /* UART3 User-designated Output 1 */ + UART3_SIR_OUT = 185, /* UART3 Serial Infrared Output */ + UART3_BAUD = 186, /* UART3 Transmit Clock Output */ + UART3_RE = 187, /* UART3 Receiver Output Enable */ + UART3_DE = 188, /* UART3 Driver Output Enable */ + UART3_RS485_EN = 189, /* UART3 RS485 Enable */ + TIMER0_TOGGLE1 = 190, /* TIMER0 Toggle Output 1 */ + TIMER0_TOGGLE2 = 191, /* TIMER0 Toggle Output 2 */ + TIMER0_TOGGLE3 = 192, /* TIMER0 Toggle Output 3 */ + TIMER0_TOGGLE4 = 193, /* TIMER0 Toggle Output 4 */ + TIMER1_TOGGLE1 = 194, /* TIMER1 Toggle Output 1 */ + TIMER1_TOGGLE2 = 195, /* TIMER1 Toggle Output 2 */ + TIMER1_TOGGLE3 = 196, /* TIMER1 Toggle Output 3 */ + TIMER1_TOGGLE4 = 197, /* TIMER1 Toggle Output 4 */ + TIMER2_TOGGLE1 = 198, /* TIMER2 Toggle Output 1 */ + TIMER2_TOGGLE2 = 199, /* TIMER2 Toggle Output 2 */ + TIMER2_TOGGLE3 = 200, /* TIMER2 Toggle Output 3 */ + TIMER2_TOGGLE4 = 201, /* TIMER2 Toggle Output 4 */ + CLK_SPI2 = 202, /* Clock SPI2 */ + CLK_I2C2 = 203, /* Clock I2C2 */ + INTERNAL0 = 204, /* Internal function signal 0 */ + INTERNAL1 = 205, /* Internal function signal 1 */ + INTERNAL2 = 206, /* Internal function signal 2 */ + INTERNAL3 = 207, /* Internal function signal 3 */ + INTERNAL4 = 208, /* Internal function signal 4 */ + INTERNAL5 = 209, /* Internal function signal 5 */ + INTERNAL6 = 210, /* Internal function signal 6 */ + INTERNAL7 = 211, /* Internal function signal 7 */ + INTERNAL8 = 212, /* Internal function signal 8 */ + INTERNAL9 = 213, /* Internal function signal 9 */ + INTERNAL10 = 214, /* Internal function signal 10 */ + INTERNAL11 = 215, /* Internal function signal 11 */ + INTERNAL12 = 216, /* Internal function signal 12 */ + INTERNAL13 = 217, /* Internal function signal 13 */ + INTERNAL14 = 218, /* Internal function signal 14 */ + INTERNAL15 = 219, /* Internal function signal 15 */ + INTERNAL16 = 220, /* Internal function signal 16 */ + INTERNAL17 = 221, /* Internal function signal 17 */ + CONSTANT = 222, /* Constant function */ + INTERNAL18 = 223, /* Internal function signal 18 */ + DEBUG0 = 224, /* Debug function 0 */ + DEBUG1 = 225, /* Debug function 1 */ + DEBUG2 = 226, /* Debug function 2 */ + DEBUG3 = 227, /* Debug function 3 */ + DEBUG4 = 228, /* Debug function 4 */ + DEBUG5 = 229, /* Debug function 5 */ + DEBUG6 = 230, /* Debug function 6 */ + DEBUG7 = 231, /* Debug function 7 */ + DEBUG8 = 232, /* Debug function 8 */ + DEBUG9 = 233, /* Debug function 9 */ + DEBUG10 = 234, /* Debug function 10 */ + DEBUG11 = 235, /* Debug function 11 */ + DEBUG12 = 236, /* Debug function 12 */ + DEBUG13 = 237, /* Debug function 13 */ + DEBUG14 = 238, /* Debug function 14 */ + DEBUG15 = 239, /* Debug function 15 */ + DEBUG16 = 240, /* Debug function 16 */ + DEBUG17 = 241, /* Debug function 17 */ + DEBUG18 = 242, /* Debug function 18 */ + DEBUG19 = 243, /* Debug function 19 */ + DEBUG20 = 244, /* Debug function 20 */ + DEBUG21 = 245, /* Debug function 21 */ + DEBUG22 = 246, /* Debug function 22 */ + DEBUG23 = 247, /* Debug function 23 */ + DEBUG24 = 248, /* Debug function 24 */ + DEBUG25 = 249, /* Debug function 25 */ + DEBUG26 = 250, /* Debug function 26 */ + DEBUG27 = 251, /* Debug function 27 */ + DEBUG28 = 252, /* Debug function 28 */ + DEBUG29 = 253, /* Debug function 29 */ + DEBUG30 = 254, /* Debug function 30 */ + DEBUG31 = 255, /* Debug function 31 */ +} + +impl function { + /** GPIOHS pin to function */ + pub fn gpiohs(num: u8) -> function { + use function::*; + match num { + 0 => GPIOHS0, + 1 => GPIOHS1, + 2 => GPIOHS2, + 3 => GPIOHS3, + 4 => GPIOHS4, + 5 => GPIOHS5, + 6 => GPIOHS6, + 7 => GPIOHS7, + 8 => GPIOHS8, + 9 => GPIOHS9, + 10 => GPIOHS10, + 11 => GPIOHS11, + 12 => GPIOHS12, + 13 => GPIOHS13, + 14 => GPIOHS14, + 15 => GPIOHS15, + 16 => GPIOHS16, + 17 => GPIOHS17, + 18 => GPIOHS18, + 19 => GPIOHS19, + 20 => GPIOHS20, + 21 => GPIOHS21, + 22 => GPIOHS22, + 23 => GPIOHS23, + 24 => GPIOHS24, + 25 => GPIOHS25, + 26 => GPIOHS26, + 27 => GPIOHS27, + 28 => GPIOHS28, + 29 => GPIOHS29, + 30 => GPIOHS30, + 31 => GPIOHS31, + _ => panic!("no such GPIO pin"), + } + } +} + +#[derive(Copy, Clone)] +pub enum pull { + /** No Pull */ + NONE, + /** Pull Down */ + DOWN, + /** Pull Up */ + UP, +} + +/** Defaults per function (from Kendryte fpioa.c) */ +#[cfg_attr(rustfmt, rustfmt_skip)] +static FUNCTION_DEFAULTS: &[u32] = &[ + 0x00900000, 0x00900001, 0x00900002, 0x00001f03, 0x00b03f04, 0x00b03f05, 0x00b03f06, 0x00b03f07, + 0x00b03f08, 0x00b03f09, 0x00b03f0a, 0x00b03f0b, 0x00001f0c, 0x00001f0d, 0x00001f0e, 0x00001f0f, + 0x03900010, 0x00001f11, 0x00900012, 0x00001f13, 0x00900014, 0x00900015, 0x00001f16, 0x00001f17, + 0x00901f18, 0x00901f19, 0x00901f1a, 0x00901f1b, 0x00901f1c, 0x00901f1d, 0x00901f1e, 0x00901f1f, + 0x00901f20, 0x00901f21, 0x00901f22, 0x00901f23, 0x00901f24, 0x00901f25, 0x00901f26, 0x00901f27, + 0x00901f28, 0x00901f29, 0x00901f2a, 0x00901f2b, 0x00901f2c, 0x00901f2d, 0x00901f2e, 0x00901f2f, + 0x00901f30, 0x00901f31, 0x00901f32, 0x00901f33, 0x00901f34, 0x00901f35, 0x00901f36, 0x00901f37, + 0x00901f38, 0x00901f39, 0x00901f3a, 0x00901f3b, 0x00901f3c, 0x00901f3d, 0x00901f3e, 0x00901f3f, + 0x00900040, 0x00001f41, 0x00900042, 0x00001f43, 0x00900044, 0x00001f45, 0x00b03f46, 0x00b03f47, + 0x00b03f48, 0x00b03f49, 0x00b03f4a, 0x00b03f4b, 0x00b03f4c, 0x00b03f4d, 0x00001f4e, 0x00001f4f, + 0x00001f50, 0x00001f51, 0x03900052, 0x00001f53, 0x00b03f54, 0x00900055, 0x00900056, 0x00001f57, + 0x00001f58, 0x00001f59, 0x0090005a, 0x0090005b, 0x0090005c, 0x0090005d, 0x00001f5e, 0x00001f5f, + 0x00001f60, 0x00001f61, 0x00001f62, 0x00001f63, 0x00001f64, 0x00900065, 0x00900066, 0x00900067, + 0x00900068, 0x00001f69, 0x00001f6a, 0x00001f6b, 0x00001f6c, 0x00001f6d, 0x00001f6e, 0x00001f6f, + 0x00900070, 0x00900071, 0x00900072, 0x00900073, 0x00001f74, 0x00001f75, 0x00001f76, 0x00001f77, + 0x00000078, 0x00000079, 0x0000007a, 0x0000007b, 0x0000007c, 0x0000007d, 0x0099107e, 0x0099107f, + 0x00991080, 0x00991081, 0x00991082, 0x00991083, 0x00001f84, 0x00001f85, 0x00001f86, 0x00900087, + 0x00900088, 0x00900089, 0x0090008a, 0x0090008b, 0x0090008c, 0x0090008d, 0x0090008e, 0x0090008f, + 0x00900090, 0x00900091, 0x00993092, 0x00993093, 0x00900094, 0x00900095, 0x00900096, 0x00900097, + 0x00900098, 0x00001f99, 0x00001f9a, 0x00001f9b, 0x00001f9c, 0x00001f9d, 0x00001f9e, 0x00001f9f, + 0x00001fa0, 0x00001fa1, 0x009000a2, 0x009000a3, 0x009000a4, 0x009000a5, 0x009000a6, 0x00001fa7, + 0x00001fa8, 0x00001fa9, 0x00001faa, 0x00001fab, 0x00001fac, 0x00001fad, 0x00001fae, 0x00001faf, + 0x009000b0, 0x009000b1, 0x009000b2, 0x009000b3, 0x009000b4, 0x00001fb5, 0x00001fb6, 0x00001fb7, + 0x00001fb8, 0x00001fb9, 0x00001fba, 0x00001fbb, 0x00001fbc, 0x00001fbd, 0x00001fbe, 0x00001fbf, + 0x00001fc0, 0x00001fc1, 0x00001fc2, 0x00001fc3, 0x00001fc4, 0x00001fc5, 0x00001fc6, 0x00001fc7, + 0x00001fc8, 0x00001fc9, 0x00001fca, 0x00001fcb, 0x00001fcc, 0x00001fcd, 0x00001fce, 0x00001fcf, + 0x00001fd0, 0x00001fd1, 0x00001fd2, 0x00001fd3, 0x00001fd4, 0x009000d5, 0x009000d6, 0x009000d7, + 0x009000d8, 0x009100d9, 0x00991fda, 0x009000db, 0x009000dc, 0x009000dd, 0x000000de, 0x009000df, + 0x00001fe0, 0x00001fe1, 0x00001fe2, 0x00001fe3, 0x00001fe4, 0x00001fe5, 0x00001fe6, 0x00001fe7, + 0x00001fe8, 0x00001fe9, 0x00001fea, 0x00001feb, 0x00001fec, 0x00001fed, 0x00001fee, 0x00001fef, + 0x00001ff0, 0x00001ff1, 0x00001ff2, 0x00001ff3, 0x00001ff4, 0x00001ff5, 0x00001ff6, 0x00001ff7, + 0x00001ff8, 0x00001ff9, 0x00001ffa, 0x00001ffb, 0x00001ffc, 0x00001ffd, 0x00001ffe, 0x00001fff, +]; + +pub fn set_function>(number: N, function: function) { + // TODO: check for overlapping assignments and assign to RESV0 as the Kendryte SDK does? + unsafe { + let ptr = pac::FPIOA::ptr(); + (*ptr).io[number.into()].write(|w| w.bits(FUNCTION_DEFAULTS[function as usize])); + } +} + +pub fn set_io_pull>(number: N, pull: pull) { + unsafe { + (*pac::FPIOA::ptr()).io[number.into()].modify(|_, w| match pull { + pull::NONE => w.pu().bit(false).pd().bit(false), + pull::DOWN => w.pu().bit(false).pd().bit(true), + pull::UP => w.pu().bit(true).pd().bit(false), + }); + } +} + +/** I/O pins for FPIOA */ +#[derive(Copy, Clone)] +pub enum io { + /** JTAG TCK */ + JTAG_TCK = 0, + /** JTAG TDI */ + JTAG_TDI = 1, + /** JTAG TMS */ + JTAG_TMS = 2, + /** JTAG TDO */ + JTAG_TDO = 3, + /** Host RX (from STM32F103C8) */ + ISP_RX = 4, + /** Host TX (to STM32F103C8) */ + ISP_TX = 5, + /** WIFI serial TX (from perspective of ESP8285, so our RX) */ + WIFI_TX = 6, + /** WIFI serial RX (from perspective of ESP8285, so our TX) */ + WIFI_RX = 7, + /** WIFI enable (to ESP8285) */ + WIFI_EN = 8, + /** Unused */ + BPSK_P = 9, + /** Unused */ + BPSK_N = 10, + /** General purpose I/O pin */ + IO11 = 11, + /** Blue led (output) */ + LED_B = 12, + /** Green led (output) */ + LED_G = 13, + /** Red led (output) */ + LED_R = 14, + /** Key direction 1 press (input) */ + KEY1 = 15, + /** Key center press (input) */ + BOOT_KEY0 = 16, + /** Key direction 2 press (input) */ + KEY2 = 17, + /** Microphone I2S BCK */ + MIC_BCK = 18, + /** Microphone I2S WS */ + MIC_WS = 19, + /** Microphone I2S DAT3 */ + MIC_DAT3 = 20, + /** Microphone I2S DAT2 */ + MIC_DAT2 = 21, + /** Microphone I2S DAT1 */ + MIC_DAT1 = 22, + /** Microphone I2S DAT0 */ + MIC_DAT0 = 23, + /** Microphone LED DAT */ + MIC_LED_DAT = 24, + /** Microphone LED CLK */ + MIC_LED_CLK = 25, + /** SDCARD SPI MISO */ + SPI0_MISO = 26, + /** SDCARD SPI SCLK */ + SPI0_SCLK = 27, + /** SDCARD SPI MOSI */ + SPI0_MOSI = 28, + /** SDCARD SPI CS */ + SPI0_CS0 = 29, + /** I2C bus 1 SCLK (NS2009, MSA300) */ + I2C1_SCL = 30, + /** I2C bus 2 SDA (NS2009, MSA300) */ + I2C1_SDA = 31, + /** General purpose I/O pin */ + IO32 = 32, + /** DAC I2S WS */ + I2S_WS = 33, + /** DAC I2S DA */ + I2S_DA = 34, + /** DAC I2S BCK */ + I2S_BCK = 35, + /** LCD chip select (output) */ + LCD_CS = 36, + /** LCD reset (output) */ + LCD_RST = 37, + /** LCD Data/Command */ + LCD_DC = 38, + /** LCD SPI SCLK */ + LCD_WR = 39, + /** Camera DVP SDA */ + DVP_SDA = 40, + /** Camera DVP SCL */ + DVP_SCL = 41, + /** Camera DVP RST */ + DVP_RST = 42, + /** Camera DVP VSYNC */ + DVP_VSYNC = 43, + /** Camera DVP PWDN */ + DVP_PWDN = 44, + /** Camera DVP HSYNC */ + DVP_HSYNC = 45, + /** Camera DVP XCLK */ + DVP_XCLK = 46, + /** Camera DVP PCLK */ + DVP_PCLK = 47, +} + +impl From for usize { + fn from(io: io) -> Self { + io as usize + } +} \ No newline at end of file diff --git a/os/src/drivers/soc/gpio.rs b/os/src/drivers/soc/gpio.rs new file mode 100644 index 0000000..fc2a665 --- /dev/null +++ b/os/src/drivers/soc/gpio.rs @@ -0,0 +1,11 @@ +//! GPIO peripheral + +#![allow(non_camel_case_types)] + +#[derive(Copy, Clone, PartialEq, Eq)] +pub enum direction { + INPUT, + OUTPUT, +} + +// TODO \ No newline at end of file diff --git a/os/src/drivers/soc/gpiohs.rs b/os/src/drivers/soc/gpiohs.rs new file mode 100644 index 0000000..f8e0815 --- /dev/null +++ b/os/src/drivers/soc/gpiohs.rs @@ -0,0 +1,41 @@ +#![allow(unused)] + +//! GPIOHS peripheral +//use k210_hal::pac; +use k210_pac as pac; + +use super::gpio; +use super::utils::{set_bit,get_bit}; + +// TODO embedded-hal::digital::v2::{InputPin, OutputPin} + +/** Set input/output direction for a GPIOHS pin */ +pub fn set_direction(pin: u8, direction: gpio::direction) { + unsafe { + let ptr = pac::GPIOHS::ptr(); + (*ptr) + .output_en + .modify(|r, w| w.bits(set_bit(r.bits(), pin, direction == gpio::direction::OUTPUT))); + (*ptr) + .input_en + .modify(|r, w| w.bits(set_bit(r.bits(), pin, direction == gpio::direction::INPUT))); + } +} + +/** Set output value for a GPIOHS pin */ +pub fn set_pin(pin: u8, value: bool) { + unsafe { + let ptr = pac::GPIOHS::ptr(); + (*ptr) + .output_val + .modify(|r, w| w.bits(set_bit(r.bits(), pin, value))); + } +} + +/** Get input value for a GPIOHS pin */ +pub fn get_pin(pin: u8) -> bool { + unsafe { + let ptr = pac::GPIOHS::ptr(); + get_bit((*ptr).input_val.read().bits(), pin) + } +} \ No newline at end of file diff --git a/os/src/drivers/soc/mod.rs b/os/src/drivers/soc/mod.rs new file mode 100644 index 0000000..0ace04b --- /dev/null +++ b/os/src/drivers/soc/mod.rs @@ -0,0 +1,8 @@ +pub mod dmac; +pub mod fpioa; +pub mod gpio; +pub mod gpiohs; +pub mod sleep; +pub mod spi; +pub mod sysctl; +pub mod utils; \ No newline at end of file diff --git a/os/src/drivers/soc/sleep.rs b/os/src/drivers/soc/sleep.rs new file mode 100644 index 0000000..1358a84 --- /dev/null +++ b/os/src/drivers/soc/sleep.rs @@ -0,0 +1,15 @@ +use crate::interrupt::timer::read_time; +use super::sysctl; + +pub fn cycle_sleep(n: usize) { + //let start = mcycle::read(); + let start = read_time(); + while (/*mcycle::read()*/read_time().wrapping_sub(start)) < n { + // IDLE + } +} + +pub fn usleep(n: usize) { + let freq = sysctl::clock_get_freq(sysctl::clock::CPU) as usize; + cycle_sleep(freq * n / 1000000); +} \ No newline at end of file diff --git a/os/src/drivers/soc/spi.rs b/os/src/drivers/soc/spi.rs new file mode 100644 index 0000000..e3aeb36 --- /dev/null +++ b/os/src/drivers/soc/spi.rs @@ -0,0 +1,316 @@ +//! SPI peripherals handling +use core::cmp; +use core::convert::TryInto; +use core::ops::Deref; +//use k210_hal::pac; +use k210_pac as pac; +use pac::{SPI0,SPI1,spi0}; +use pac::spi0::ctrlr0; +use pac::spi0::spi_ctrlr0; + +//use super::sysctl; +use super::sysctl::{dma_channel, self}; +use super::dmac::{DMAC, address_increment, burst_length, transfer_width}; + +/// Extension trait that constrains SPI peripherals +pub trait SPIExt: Sized { + /// Constrains SPI peripheral so it plays nicely with the other abstractions + fn constrain(self) -> SPIImpl; +} + +/// Trait for generalizing over SPI0 and SPI1 (SPI2 is slave-only and SPI3 is !!!special!!!) +pub trait SPI01: Deref { + #[doc(hidden)] + const CLK: sysctl::clock; + #[doc(hidden)] + const DIV: sysctl::threshold; + #[doc(hidden)] + const DMA_RX: sysctl::dma_select; + #[doc(hidden)] + const DMA_TX: sysctl::dma_select; +} + +impl SPI01 for SPI0 { + const CLK: sysctl::clock = sysctl::clock::SPI0; + const DIV: sysctl::threshold = sysctl::threshold::SPI0; + const DMA_RX: sysctl::dma_select = sysctl::dma_select::SSI0_RX_REQ; + const DMA_TX: sysctl::dma_select = sysctl::dma_select::SSI0_TX_REQ; +} +impl SPI01 for SPI1 { + const CLK: sysctl::clock = sysctl::clock::SPI1; + const DIV: sysctl::threshold = sysctl::threshold::SPI1; + const DMA_RX: sysctl::dma_select = sysctl::dma_select::SSI1_RX_REQ; + const DMA_TX: sysctl::dma_select = sysctl::dma_select::SSI1_TX_REQ; +} + +impl SPIExt for SPI { + fn constrain(self) -> SPIImpl { + SPIImpl::::new(self) + } +} + +pub struct SPIImpl { + spi: IF, +} + +/** Borrow work mode from pac */ +pub use ctrlr0::WORK_MODE_A as work_mode; +/** Borrow frame format from pac */ +pub use ctrlr0::FRAME_FORMAT_A as frame_format; +/** Borrow aitm from pac */ +pub use spi_ctrlr0::AITM_A as aitm; +/** Borrow tmod from pac */ +pub use ctrlr0::TMOD_A as tmod; + +pub trait SPI { + fn configure( + &self, + work_mode: work_mode, + frame_format: frame_format, + data_bit_length: u8, + endian: u32, + instruction_length: u8, + address_length: u8, + wait_cycles: u8, + instruction_address_trans_mode: aitm, + tmod: tmod, + ); + fn set_clk_rate(&self, spi_clk: u32) -> u32; + fn recv_data(&self, chip_select: u32, rx: &mut [X]); + fn recv_data_dma(&self, dmac: &DMAC, channel_num: dma_channel, chip_select: u32, rx: &mut [u32]); + fn send_data + Copy>(&self, chip_select: u32, tx: &[X]); + fn send_data_dma(&self, dmac: &DMAC, channel_num: dma_channel, chip_select: u32, tx: &[u32]); + fn fill_data(&self, chip_select: u32, value: u32, tx_len: usize); + fn fill_data_dma(&self, dmac: &DMAC, channel_num: dma_channel, chip_select: u32, value: u32, tx_len: usize); +} + +impl SPIImpl { + pub fn new(spi: IF) -> Self { + Self { spi } + } +} + +/** Trait for trunction of a SPI frame from u32 register to other unsigned integer types. */ +pub trait TruncU32 { + fn trunc(val: u32)-> Self; +} +impl TruncU32 for u32 { fn trunc(val: u32) -> u32 { return val; } } +impl TruncU32 for u16 { fn trunc(val: u32) -> u16 { return (val & 0xffff) as u16; } } +impl TruncU32 for u8 { fn trunc(val: u32) -> u8 { return (val & 0xff) as u8; } } + +impl SPI for SPIImpl { + /// Configure SPI transaction + fn configure( + &self, + work_mode: work_mode, + frame_format: frame_format, + data_bit_length: u8, + endian: u32, + instruction_length: u8, + address_length: u8, + wait_cycles: u8, + instruction_address_trans_mode: aitm, + tmod: tmod, + ) { + assert!(data_bit_length >= 4 && data_bit_length <= 32); + assert!(wait_cycles < (1 << 5)); + let inst_l: u8 = match instruction_length { + 0 => 0, + 4 => 1, + 8 => 2, + 16 => 3, + _ => panic!("unhandled intruction length"), + }; + + assert!(address_length % 4 == 0 && address_length <= 60); + let addr_l: u8 = address_length / 4; + + unsafe { + self.spi.imr.write(|w| w.bits(0x00)); + self.spi.dmacr.write(|w| w.bits(0x00)); + self.spi.dmatdlr.write(|w| w.bits(0x10)); + self.spi.dmardlr.write(|w| w.bits(0x00)); + self.spi.ser.write(|w| w.bits(0x00)); + self.spi.ssienr.write(|w| w.bits(0x00)); + self.spi.ctrlr0.write(|w| { + w.work_mode() + .variant(work_mode) + .tmod() + .variant(tmod) + .frame_format() + .variant(frame_format) + .data_length() + .bits(data_bit_length - 1) + }); + self.spi.spi_ctrlr0.write(|w| { + w.aitm() + .variant(instruction_address_trans_mode) + .addr_length() + .bits(addr_l) + .inst_length() + .bits(inst_l) + .wait_cycles() + .bits(wait_cycles) + }); + self.spi.endian.write(|w| w.bits(endian)); + } + } + + /// Set SPI clock rate + fn set_clk_rate(&self, spi_clk: u32) -> u32 { + sysctl::clock_enable(IF::CLK); + sysctl::clock_set_threshold(IF::DIV, 0); + let clock_freq: u32 = sysctl::clock_get_freq(sysctl::clock::SPI0); + let spi_baudr = clock_freq / spi_clk; + // Clamp baudrate divider to valid range + let spi_baudr = cmp::min(cmp::max(spi_baudr, 2), 65534); + unsafe { + self.spi.baudr.write(|w| w.bits(spi_baudr)); + } + clock_freq / spi_baudr + } + + /// Receive arbitrary data + // make sure to set tmod to tmod::RECV + fn recv_data(&self, chip_select: u32, rx: &mut [X]) { + if rx.len() == 0 { + return; + } + unsafe { + self.spi.ctrlr1.write(|w| w.bits((rx.len() - 1).try_into().unwrap())); + self.spi.ssienr.write(|w| w.bits(0x01)); + self.spi.dr[0].write(|w| w.bits(0xffffffff)); + self.spi.ser.write(|w| w.bits(1 << chip_select)); + + let mut fifo_len = 0; + for val in rx.iter_mut() { + while fifo_len == 0 { + fifo_len = self.spi.rxflr.read().bits(); + } + *val = X::trunc(self.spi.dr[0].read().bits()); + fifo_len -= 1; + } + + self.spi.ser.write(|w| w.bits(0x00)); + self.spi.ssienr.write(|w| w.bits(0x00)); + } + } + + /// Receive 32-bit data using DMA. + // make sure to set tmod to tmod::RECV + fn recv_data_dma(&self, dmac: &DMAC, channel_num: dma_channel, chip_select: u32, rx: &mut [u32]) { + if rx.len() == 0 { + return; + } + unsafe { + self.spi.ctrlr1.write(|w| w.bits((rx.len() - 1).try_into().unwrap())); + self.spi.ssienr.write(|w| w.bits(0x01)); + self.spi.dmacr.write(|w| w.bits(0x3)); /*enable dma receive */ + + sysctl::dma_select(channel_num, IF::DMA_RX); + dmac.set_single_mode(channel_num, self.spi.dr.as_ptr() as u64, rx.as_ptr() as u64, + address_increment::NOCHANGE, address_increment::INCREMENT, + burst_length::LENGTH_1, transfer_width::WIDTH_32, rx.len() as u32); + self.spi.dr[0].write(|w| w.bits(0xffffffff)); + self.spi.ser.write(|w| w.bits(1 << chip_select)); + dmac.wait_done(channel_num); + + self.spi.ser.write(|w| w.bits(0x00)); + self.spi.ssienr.write(|w| w.bits(0x00)); + } + } + + /// Send arbitrary data + fn send_data + Copy>(&self, chip_select: u32, tx: &[X]) { + unsafe { + self.spi.ser.write(|w| w.bits(1 << chip_select)); + self.spi.ssienr.write(|w| w.bits(0x01)); + + let mut fifo_len = 0; + for &val in tx { + while fifo_len == 0 { + fifo_len = 32 - self.spi.txflr.read().bits(); + } + self.spi.dr[0].write(|f| f.bits(val.into())); + fifo_len -= 1; + } + + while (self.spi.sr.read().bits() & 0x05) != 0x04 { + // IDLE + } + self.spi.ser.write(|w| w.bits(0x00)); + self.spi.ssienr.write(|w| w.bits(0x00)); + } + } + + /// Send 32-bit data using DMA. + /// If you want to use this function to send 8-bit or 16-bit data, you need to wrap each + /// data unit in a 32-bit word. + /// This is intentionally left to the caller: the difficulty here is to avoid the need for alloc/freeing() + /// buffers every time as the SDK does because this is highly undesirable! + fn send_data_dma(&self, dmac: &DMAC, channel_num: dma_channel, chip_select: u32, tx: &[u32]) { + unsafe { + self.spi.dmacr.write(|w| w.bits(0x2)); /*enable dma transmit*/ + self.spi.ssienr.write(|w| w.bits(0x01)); + + sysctl::dma_select(channel_num, IF::DMA_TX); + dmac.set_single_mode(channel_num, tx.as_ptr() as u64, self.spi.dr.as_ptr() as u64, + address_increment::INCREMENT, address_increment::NOCHANGE, + burst_length::LENGTH_4, transfer_width::WIDTH_32, tx.len() as u32); + self.spi.ser.write(|w| w.bits(1 << chip_select)); + dmac.wait_done(channel_num); + + while (self.spi.sr.read().bits() & 0x05) != 0x04 { + // IDLE + } + self.spi.ser.write(|w| w.bits(0x00)); + self.spi.ssienr.write(|w| w.bits(0x00)); + } + } + + /// Send repeated data + fn fill_data(&self, chip_select: u32, value: u32, mut tx_len: usize) { + unsafe { + self.spi.ser.write(|w| w.bits(1 << chip_select)); + self.spi.ssienr.write(|w| w.bits(0x01)); + + while tx_len != 0 { + let fifo_len = (32 - self.spi.txflr.read().bits()) as usize; + let fifo_len = cmp::min(fifo_len, tx_len); + for _ in 0..fifo_len { + self.spi.dr[0].write(|f| f.bits(value)); + } + tx_len -= fifo_len; + } + + while (self.spi.sr.read().bits() & 0x05) != 0x04 { + // IDLE + } + self.spi.ser.write(|w| w.bits(0x00)); + self.spi.ssienr.write(|w| w.bits(0x00)); + } + } + + /// Send repeated data (using DMA) + fn fill_data_dma(&self, dmac: &DMAC, channel_num: dma_channel, chip_select: u32, value: u32, tx_len: usize) { + unsafe { + self.spi.dmacr.write(|w| w.bits(0x2)); /*enable dma transmit*/ + self.spi.ssienr.write(|w| w.bits(0x01)); + + sysctl::dma_select(channel_num, IF::DMA_TX); + let val = [value]; + // simple trick to repeating a value: don't increment the source address + dmac.set_single_mode(channel_num, val.as_ptr() as u64, self.spi.dr.as_ptr() as u64, + address_increment::NOCHANGE, address_increment::NOCHANGE, + burst_length::LENGTH_4, transfer_width::WIDTH_32, tx_len.try_into().unwrap()); + self.spi.ser.write(|w| w.bits(1 << chip_select)); + dmac.wait_done(channel_num); + + while (self.spi.sr.read().bits() & 0x05) != 0x04 { + // IDLE + } + self.spi.ser.write(|w| w.bits(0x00)); + self.spi.ssienr.write(|w| w.bits(0x00)); + } + } +} \ No newline at end of file diff --git a/os/src/drivers/soc/sysctl.rs b/os/src/drivers/soc/sysctl.rs new file mode 100644 index 0000000..6ee2b9d --- /dev/null +++ b/os/src/drivers/soc/sysctl.rs @@ -0,0 +1,854 @@ +#![allow(unused)] +#![allow(non_snake_case)] +#![allow(non_camel_case_types)] + +//! SYSCTL peripheral +//use k210_hal::pac; +use k210_pac as pac; + +use core::convert::TryInto; + +use super::utils::set_bit; +use super::sleep::usleep; + +mod pll_compute; + +const SYSCTRL_CLOCK_FREQ_IN0: u32 = 26000000; + +#[derive(Copy, Clone, PartialEq, Eq)] +pub enum pll { + /** PLL0 can usually be selected as alternative to IN0, for example the CPU + * clock speed. It can be used as source for PLL2. */ + PLL0, + /** PLL1 is used for the KPU clock, and can be used as source for PLL2. */ + PLL1, + /** PLL2 is used for I2S clocks. */ + PLL2, +} + +#[derive(Copy, Clone, PartialEq, Eq)] +pub enum clock_source { + IN0, + PLL0, + PLL1, + PLL2, + ACLK, +} + +#[derive(Copy, Clone, PartialEq, Eq)] +pub enum clock { + PLL0, + PLL1, + PLL2, + CPU, + SRAM0, + SRAM1, + APB0, + APB1, + APB2, + ROM, + DMA, + AI, + DVP, + FFT, + GPIO, + SPI0, + SPI1, + SPI2, + SPI3, + I2S0, + I2S1, + I2S2, + I2C0, + I2C1, + I2C2, + UART1, + UART2, + UART3, + AES, + FPIOA, + TIMER0, + TIMER1, + TIMER2, + WDT0, + WDT1, + SHA, + OTP, + RTC, + ACLK, + HCLK, + IN0, +} + +#[derive(Copy, Clone, PartialEq, Eq)] +pub enum threshold { + ACLK, + APB0, + APB1, + APB2, + SRAM0, + SRAM1, + AI, + DVP, + ROM, + SPI0, + SPI1, + SPI2, + SPI3, + TIMER0, + TIMER1, + TIMER2, + I2S0, + I2S1, + I2S2, + I2S0_M, + I2S1_M, + I2S2_M, + I2C0, + I2C1, + I2C2, + WDT0, + WDT1, +} + +#[derive(Copy, Clone, PartialEq, Eq)] +pub enum clock_select { + PLL0_BYPASS, + PLL1_BYPASS, + PLL2_BYPASS, + PLL2, + ACLK, + SPI3, + TIMER0, + TIMER1, + TIMER2, + SPI3_SAMPLE, +} + +#[derive(Copy, Clone, PartialEq, Eq)] +pub enum io_power_mode { + V33, + V18, +} + +#[derive(Copy, Clone, PartialEq, Eq)] +pub enum power_bank { + BANK0 = 0, + BANK1, + BANK2, + BANK3, + BANK4, + BANK5, + BANK6, + BANK7, +} + +#[derive(Copy, Clone, PartialEq, Eq)] +pub enum reset { + SOC, + ROM, + DMA, + AI, + DVP, + FFT, + GPIO, + SPI0, + SPI1, + SPI2, + SPI3, + I2S0, + I2S1, + I2S2, + I2C0, + I2C1, + I2C2, + UART1, + UART2, + UART3, + AES, + FPIOA, + TIMER0, + TIMER1, + TIMER2, + WDT0, + WDT1, + SHA, + RTC, +} + +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub enum dma_channel { + CHANNEL0 = 0, + CHANNEL1 = 1, + CHANNEL2 = 2, + CHANNEL3 = 3, + CHANNEL4 = 4, + CHANNEL5 = 5, +} + +impl dma_channel { + pub fn idx(self) -> usize { self as usize } +} + +pub type dma_select = pac::sysctl::dma_sel0::DMA_SEL0_A; + +fn clock_bus_en(clock: clock, en: bool) { + /* + * The timer is under APB0, to prevent apb0_clk_en1 and apb0_clk_en0 + * on same register, we split it to peripheral and central two + * registers, to protect CPU close apb0 clock accidentally. + * + * The apb0_clk_en0 and apb0_clk_en1 have same function, + * one of them set, the APB0 clock enable. + */ + + /* The APB clock should carefully disable */ + if en { + match clock { + /* + * These peripheral devices are under APB0 + * GPIO, UART1, UART2, UART3, SPI_SLAVE, I2S0, I2S1, + * I2S2, I2C0, I2C1, I2C2, FPIOA, SHA256, TIMER0, + * TIMER1, TIMER2 + */ + clock::GPIO + | clock::SPI2 + | clock::I2S0 + | clock::I2S1 + | clock::I2S2 + | clock::I2C0 + | clock::I2C1 + | clock::I2C2 + | clock::UART1 + | clock::UART2 + | clock::UART3 + | clock::FPIOA + | clock::TIMER0 + | clock::TIMER1 + | clock::TIMER2 + | clock::SHA => unsafe { + (*pac::SYSCTL::ptr()) + .clk_en_cent + .modify(|_, w| w.apb0_clk_en().bit(en)); + }, + + /* + * These peripheral devices are under APB1 + * WDT, AES, OTP, DVP, SYSCTL + */ + clock::AES | clock::WDT0 | clock::WDT1 | clock::OTP | clock::RTC => unsafe { + (*pac::SYSCTL::ptr()) + .clk_en_cent + .modify(|_, w| w.apb1_clk_en().bit(en)); + }, + + /* + * These peripheral devices are under APB2 + * SPI0, SPI1 + */ + clock::SPI0 | clock::SPI1 => unsafe { + (*pac::SYSCTL::ptr()) + .clk_en_cent + .modify(|_, w| w.apb2_clk_en().bit(en)); + }, + + _ => {} + } + } +} + +fn clock_device_en(clock: clock, en: bool) { + unsafe { + let ptr = pac::SYSCTL::ptr(); + match clock { + clock::PLL0 => (*ptr).pll0.modify(|_, w| w.out_en().bit(en)), + clock::PLL1 => (*ptr).pll1.modify(|_, w| w.out_en().bit(en)), + clock::PLL2 => (*ptr).pll2.modify(|_, w| w.out_en().bit(en)), + clock::CPU => (*ptr).clk_en_cent.modify(|_, w| w.cpu_clk_en().bit(en)), + clock::SRAM0 => (*ptr).clk_en_cent.modify(|_, w| w.sram0_clk_en().bit(en)), + clock::SRAM1 => (*ptr).clk_en_cent.modify(|_, w| w.sram1_clk_en().bit(en)), + clock::APB0 => (*ptr).clk_en_cent.modify(|_, w| w.apb0_clk_en().bit(en)), + clock::APB1 => (*ptr).clk_en_cent.modify(|_, w| w.apb1_clk_en().bit(en)), + clock::APB2 => (*ptr).clk_en_cent.modify(|_, w| w.apb2_clk_en().bit(en)), + clock::ROM => (*ptr).clk_en_peri.modify(|_, w| w.rom_clk_en().bit(en)), + clock::DMA => (*ptr).clk_en_peri.modify(|_, w| w.dma_clk_en().bit(en)), + clock::AI => (*ptr).clk_en_peri.modify(|_, w| w.ai_clk_en().bit(en)), + clock::DVP => (*ptr).clk_en_peri.modify(|_, w| w.dvp_clk_en().bit(en)), + clock::FFT => (*ptr).clk_en_peri.modify(|_, w| w.fft_clk_en().bit(en)), + clock::SPI3 => (*ptr).clk_en_peri.modify(|_, w| w.spi3_clk_en().bit(en)), + clock::GPIO => (*ptr).clk_en_peri.modify(|_, w| w.gpio_clk_en().bit(en)), + clock::SPI2 => (*ptr).clk_en_peri.modify(|_, w| w.spi2_clk_en().bit(en)), + clock::I2S0 => (*ptr).clk_en_peri.modify(|_, w| w.i2s0_clk_en().bit(en)), + clock::I2S1 => (*ptr).clk_en_peri.modify(|_, w| w.i2s1_clk_en().bit(en)), + clock::I2S2 => (*ptr).clk_en_peri.modify(|_, w| w.i2s2_clk_en().bit(en)), + clock::I2C0 => (*ptr).clk_en_peri.modify(|_, w| w.i2c0_clk_en().bit(en)), + clock::I2C1 => (*ptr).clk_en_peri.modify(|_, w| w.i2c1_clk_en().bit(en)), + clock::I2C2 => (*ptr).clk_en_peri.modify(|_, w| w.i2c2_clk_en().bit(en)), + clock::UART1 => (*ptr).clk_en_peri.modify(|_, w| w.uart1_clk_en().bit(en)), + clock::UART2 => (*ptr).clk_en_peri.modify(|_, w| w.uart2_clk_en().bit(en)), + clock::UART3 => (*ptr).clk_en_peri.modify(|_, w| w.uart3_clk_en().bit(en)), + clock::FPIOA => (*ptr).clk_en_peri.modify(|_, w| w.fpioa_clk_en().bit(en)), + clock::TIMER0 => (*ptr).clk_en_peri.modify(|_, w| w.timer0_clk_en().bit(en)), + clock::TIMER1 => (*ptr).clk_en_peri.modify(|_, w| w.timer1_clk_en().bit(en)), + clock::TIMER2 => (*ptr).clk_en_peri.modify(|_, w| w.timer2_clk_en().bit(en)), + clock::SHA => (*ptr).clk_en_peri.modify(|_, w| w.sha_clk_en().bit(en)), + clock::AES => (*ptr).clk_en_peri.modify(|_, w| w.aes_clk_en().bit(en)), + clock::WDT0 => (*ptr).clk_en_peri.modify(|_, w| w.wdt0_clk_en().bit(en)), + clock::WDT1 => (*ptr).clk_en_peri.modify(|_, w| w.wdt1_clk_en().bit(en)), + clock::OTP => (*ptr).clk_en_peri.modify(|_, w| w.otp_clk_en().bit(en)), + clock::RTC => (*ptr).clk_en_peri.modify(|_, w| w.rtc_clk_en().bit(en)), + clock::SPI0 => (*ptr).clk_en_peri.modify(|_, w| w.spi0_clk_en().bit(en)), + clock::SPI1 => (*ptr).clk_en_peri.modify(|_, w| w.spi1_clk_en().bit(en)), + clock::ACLK | clock::HCLK | clock::IN0 => { /* no separate enables */ } + } + } +} + +pub fn clock_enable(clock: clock) { + clock_bus_en(clock, true); + clock_device_en(clock, true); +} + +pub fn sysctl_clock_disable(clock: clock) { + clock_bus_en(clock, false); + clock_device_en(clock, false); +} + +/// Set clock divider +pub fn clock_set_threshold(which: threshold, threshold: u32) { + // TODO: this should take a multiplier directly, not a peripheral specific value + unsafe { + let ptr = pac::SYSCTL::ptr(); + match which { + /* 2 bit wide */ + threshold::ACLK => (*ptr).clk_sel0.modify(|_, w| w.aclk_divider_sel().bits(threshold as u8)), + + /* 3 bit wide */ + threshold::APB0 => (*ptr).clk_sel0.modify(|_, w| w.apb0_clk_sel().bits(threshold as u8)), + threshold::APB1 => (*ptr).clk_sel0.modify(|_, w| w.apb1_clk_sel().bits(threshold as u8)), + threshold::APB2 => (*ptr).clk_sel0.modify(|_, w| w.apb2_clk_sel().bits(threshold as u8)), + + /* 4 bit wide */ + threshold::SRAM0 => (*ptr).clk_th0.modify(|_, w| w.sram0_gclk().bits(threshold as u8)), + threshold::SRAM1 => (*ptr).clk_th0.modify(|_, w| w.sram1_gclk().bits(threshold as u8)), + threshold::AI => (*ptr).clk_th0.modify(|_, w| w.ai_gclk().bits(threshold as u8)), + threshold::DVP => (*ptr).clk_th0.modify(|_, w| w.dvp_gclk().bits(threshold as u8)), + threshold::ROM => (*ptr).clk_th0.modify(|_, w| w.rom_gclk().bits(threshold as u8)), + + /* 8 bit wide */ + threshold::SPI0 => (*ptr).clk_th1.modify(|_, w| w.spi0_clk().bits(threshold as u8)), + threshold::SPI1 => (*ptr).clk_th1.modify(|_, w| w.spi1_clk().bits(threshold as u8)), + threshold::SPI2 => (*ptr).clk_th1.modify(|_, w| w.spi2_clk().bits(threshold as u8)), + threshold::SPI3 => (*ptr).clk_th1.modify(|_, w| w.spi3_clk().bits(threshold as u8)), + threshold::TIMER0 => (*ptr).clk_th2.modify(|_, w| w.timer0_clk().bits(threshold as u8)), + threshold::TIMER1 => (*ptr).clk_th2.modify(|_, w| w.timer1_clk().bits(threshold as u8)), + threshold::TIMER2 => (*ptr).clk_th2.modify(|_, w| w.timer2_clk().bits(threshold as u8)), + threshold::I2S0_M => (*ptr).clk_th4.modify(|_, w| w.i2s0_mclk().bits(threshold as u8)), + threshold::I2S1_M => (*ptr).clk_th4.modify(|_, w| w.i2s1_mclk().bits(threshold as u8)), + threshold::I2S2_M => (*ptr).clk_th5.modify(|_, w| w.i2s2_mclk().bits(threshold as u8)), + threshold::I2C0 => (*ptr).clk_th5.modify(|_, w| w.i2c0_clk().bits(threshold as u8)), + threshold::I2C1 => (*ptr).clk_th5.modify(|_, w| w.i2c1_clk().bits(threshold as u8)), + threshold::I2C2 => (*ptr).clk_th5.modify(|_, w| w.i2c2_clk().bits(threshold as u8)), + threshold::WDT0 => (*ptr).clk_th6.modify(|_, w| w.wdt0_clk().bits(threshold as u8)), + threshold::WDT1 => (*ptr).clk_th6.modify(|_, w| w.wdt1_clk().bits(threshold as u8)), + + /* 16 bit wide */ + threshold::I2S0 => (*ptr).clk_th3.modify(|_, w| w.i2s0_clk().bits(threshold as u16)), + threshold::I2S1 => (*ptr).clk_th3.modify(|_, w| w.i2s1_clk().bits(threshold as u16)), + threshold::I2S2 => (*ptr).clk_th4.modify(|_, w| w.i2s2_clk().bits(threshold as u16)), + } + } +} + +/// Get clock divider +pub fn clock_get_threshold(which: threshold) -> u32 { + unsafe { + // TODO: this should return a multiplier directly, not a peripheral specific value + let ptr = pac::SYSCTL::ptr(); + match which { + /* 2 bit wide */ + threshold::ACLK => (*ptr).clk_sel0.read().aclk_divider_sel().bits().into(), + + /* 3 bit wide */ + threshold::APB0 => (*ptr).clk_sel0.read().apb0_clk_sel().bits().into(), + threshold::APB1 => (*ptr).clk_sel0.read().apb1_clk_sel().bits().into(), + threshold::APB2 => (*ptr).clk_sel0.read().apb2_clk_sel().bits().into(), + + /* 4 bit wide */ + threshold::SRAM0 => (*ptr).clk_th0.read().sram0_gclk().bits().into(), + threshold::SRAM1 => (*ptr).clk_th0.read().sram1_gclk().bits().into(), + threshold::AI => (*ptr).clk_th0.read().ai_gclk().bits().into(), + threshold::DVP => (*ptr).clk_th0.read().dvp_gclk().bits().into(), + threshold::ROM => (*ptr).clk_th0.read().rom_gclk().bits().into(), + + /* 8 bit wide */ + threshold::SPI0 => (*ptr).clk_th1.read().spi0_clk().bits().into(), + threshold::SPI1 => (*ptr).clk_th1.read().spi1_clk().bits().into(), + threshold::SPI2 => (*ptr).clk_th1.read().spi2_clk().bits().into(), + threshold::SPI3 => (*ptr).clk_th1.read().spi3_clk().bits().into(), + threshold::TIMER0 => (*ptr).clk_th2.read().timer0_clk().bits().into(), + threshold::TIMER1 => (*ptr).clk_th2.read().timer1_clk().bits().into(), + threshold::TIMER2 => (*ptr).clk_th2.read().timer2_clk().bits().into(), + threshold::I2S0_M => (*ptr).clk_th4.read().i2s0_mclk().bits().into(), + threshold::I2S1_M => (*ptr).clk_th4.read().i2s1_mclk().bits().into(), + threshold::I2S2_M => (*ptr).clk_th5.read().i2s2_mclk().bits().into(), + threshold::I2C0 => (*ptr).clk_th5.read().i2c0_clk().bits().into(), + threshold::I2C1 => (*ptr).clk_th5.read().i2c1_clk().bits().into(), + threshold::I2C2 => (*ptr).clk_th5.read().i2c2_clk().bits().into(), + threshold::WDT0 => (*ptr).clk_th6.read().wdt0_clk().bits().into(), + threshold::WDT1 => (*ptr).clk_th6.read().wdt1_clk().bits().into(), + + /* 16 bit wide */ + threshold::I2S0 => (*ptr).clk_th3.read().i2s0_clk().bits().into(), + threshold::I2S1 => (*ptr).clk_th3.read().i2s1_clk().bits().into(), + threshold::I2S2 => (*ptr).clk_th4.read().i2s2_clk().bits().into(), + } + } +} + +pub fn set_power_mode(power_bank: power_bank, mode: io_power_mode) { + unsafe { + (*pac::SYSCTL::ptr()).power_sel.modify(|r, w| { + w.bits(set_bit( + r.bits(), + power_bank as u8, + match mode { + io_power_mode::V33 => false, + io_power_mode::V18 => true, + }, + )) + }); + } +} + +/** Route SPI0_D0-D7 DVP_D0-D7 functions to SPI and DVP data pins (bypassing FPIOA). */ +pub fn set_spi0_dvp_data(status: bool) { + unsafe { + (*pac::SYSCTL::ptr()) + .misc + .modify(|_, w| w.spi_dvp_data_enable().bit(status)); + } +} + +/** Map PLL2 cksel value to clock source */ +fn pll2_cksel_to_source(bits: u8) -> clock_source { + match bits { + 0 => clock_source::IN0, + 1 => clock_source::PLL0, + 2 => clock_source::PLL1, + _ => panic!("invalid value for PLL2 ckin_sel"), + } +} + +/** Map clock source to PLL2 cksel value */ +fn pll2_source_to_cksel(source: clock_source) -> u8 { + match source { + clock_source::IN0 => 0, + clock_source::PLL0 => 1, + clock_source::PLL1 => 2, + _ => panic!("unsupported clock source for PLL2"), + } +} + +pub fn pll_get_freq(pll: pll) -> u32 { + let freq_in; + let nr; + let nf; + let od; + + match pll { + pll::PLL0 => { + freq_in = clock_source_get_freq(clock_source::IN0); + unsafe { + let val = (*pac::SYSCTL::ptr()).pll0.read(); + nr = val.clkr().bits() + 1; + nf = val.clkf().bits() + 1; + od = val.clkod().bits() + 1; + } + } + pll::PLL1 => { + freq_in = clock_source_get_freq(clock_source::IN0); + unsafe { + let val = (*pac::SYSCTL::ptr()).pll1.read(); + nr = val.clkr().bits() + 1; + nf = val.clkf().bits() + 1; + od = val.clkod().bits() + 1; + } + } + pll::PLL2 => { + /* Get input freq accrording to select register. */ + freq_in = clock_source_get_freq(pll2_cksel_to_source(clock_get_clock_select(clock_select::PLL2))); + unsafe { + let val = (*pac::SYSCTL::ptr()).pll2.read(); + nr = val.clkr().bits() + 1; + nf = val.clkf().bits() + 1; + od = val.clkod().bits() + 1; + } + } + } + + /* + * Get final PLL output freq + * FOUT = FIN / NR * NF / OD + * (rewritten as integer expression) + */ + ((u64::from(freq_in) * u64::from(nf)) / (u64::from(nr) * u64::from(od))).try_into().unwrap() +} + +pub fn clock_source_get_freq(source: clock_source) -> u32 { + match source { + clock_source::IN0 => SYSCTRL_CLOCK_FREQ_IN0, + clock_source::PLL0 => pll_get_freq(pll::PLL0), + clock_source::PLL1 => pll_get_freq(pll::PLL1), + clock_source::PLL2 => pll_get_freq(pll::PLL2), + clock_source::ACLK => clock_get_freq(clock::ACLK), + } +} + +pub fn clock_set_clock_select(which: clock_select, select: u8) { + unsafe { + let ptr = pac::SYSCTL::ptr(); + // Seems that PLL2 is the only one that takes a non-boolean clock select + // TODO: take a clock_source directly when we know the meanings of these bits + match which { + clock_select::PLL0_BYPASS => (*ptr).pll0.modify(|_, w| w.bypass().bit(select != 0)), + clock_select::PLL1_BYPASS => (*ptr).pll1.modify(|_, w| w.bypass().bit(select != 0)), + clock_select::PLL2_BYPASS => (*ptr).pll2.modify(|_, w| w.bypass().bit(select != 0)), + clock_select::PLL2 => (*ptr).pll2.modify(|_, w| w.ckin_sel().bits(select)), + clock_select::ACLK => (*ptr).clk_sel0.modify(|_, w| w.aclk_sel().bit(select != 0)), + clock_select::SPI3 => (*ptr).clk_sel0.modify(|_, w| w.spi3_clk_sel().bit(select != 0)), + clock_select::TIMER0 => (*ptr).clk_sel0.modify(|_, w| w.timer0_clk_sel().bit(select != 0)), + clock_select::TIMER1 => (*ptr).clk_sel0.modify(|_, w| w.timer1_clk_sel().bit(select != 0)), + clock_select::TIMER2 => (*ptr).clk_sel0.modify(|_, w| w.timer2_clk_sel().bit(select != 0)), + clock_select::SPI3_SAMPLE => (*ptr).clk_sel1.modify(|_, w| w.spi3_sample_clk_sel().bit(select != 0)), + } + } +} + +pub fn clock_get_clock_select(which: clock_select) -> u8 { + unsafe { + let ptr = pac::SYSCTL::ptr(); + // Seems that PLL2 is the only one that has a non-boolean clock select + // TODO: return a clock_source directly when we know the meanings of these bits + // meaning seems to be usually: + // 0 IN0 + // 1 PLL0 + // (2 PLL1) + // it's likely different for _BYPASS, which, I suspect, wires the PLL output to the + // input (IN0 for PLL0 and PLL1, selectable for PLL2) + match which { + clock_select::PLL0_BYPASS => (*ptr).pll0.read().bypass().bit().into(), + clock_select::PLL1_BYPASS => (*ptr).pll1.read().bypass().bit().into(), + clock_select::PLL2_BYPASS => (*ptr).pll2.read().bypass().bit().into(), + clock_select::PLL2 => (*ptr).pll2.read().ckin_sel().bits().into(), + clock_select::ACLK => (*ptr).clk_sel0.read().aclk_sel().bit().into(), + clock_select::SPI3 => (*ptr).clk_sel0.read().spi3_clk_sel().bit().into(), + clock_select::TIMER0 => (*ptr).clk_sel0.read().timer0_clk_sel().bit().into(), + clock_select::TIMER1 => (*ptr).clk_sel0.read().timer1_clk_sel().bit().into(), + clock_select::TIMER2 => (*ptr).clk_sel0.read().timer2_clk_sel().bit().into(), + clock_select::SPI3_SAMPLE => (*ptr).clk_sel1.read().spi3_sample_clk_sel().bit().into(), + } + } +} + +pub fn clock_get_freq(clock: clock) -> u32 { + // TODO: all of these are source / threshold, where source can depend on clock_select: generalize this + // to some kind of clock tree + // TODO: clock_source_get_freq(ACLK) calls back into here, don't do this + match clock { + clock::IN0 => clock_source_get_freq(clock_source::IN0), + clock::PLL0 => clock_source_get_freq(clock_source::PLL0), + clock::PLL1 => clock_source_get_freq(clock_source::PLL1), + clock::PLL2 => clock_source_get_freq(clock_source::PLL2), + clock::CPU | clock::DMA | clock::FFT | clock::ACLK | clock::HCLK => match clock_get_clock_select(clock_select::ACLK) { + 0 => clock_source_get_freq(clock_source::IN0), + 1 => { + clock_source_get_freq(clock_source::PLL0) + / (2 << clock_get_threshold(threshold::ACLK)) + } + _ => panic!("invalid cpu clock select"), + }, + clock::SRAM0 => clock_source_get_freq(clock_source::ACLK) / (clock_get_threshold(threshold::SRAM0) + 1), + clock::SRAM1 => clock_source_get_freq(clock_source::ACLK) / (clock_get_threshold(threshold::SRAM1) + 1), + clock::ROM => clock_source_get_freq(clock_source::ACLK) / (clock_get_threshold(threshold::ROM) + 1), + clock::DVP => clock_source_get_freq(clock_source::ACLK) / (clock_get_threshold(threshold::DVP) + 1), + clock::APB0 | clock::GPIO | clock::UART1 | clock::UART2 | clock::UART3 | clock::FPIOA | clock::SHA => + clock_source_get_freq(clock_source::ACLK) / (clock_get_threshold(threshold::APB0) + 1), + clock::APB1 | clock::AES | clock::OTP => + clock_source_get_freq(clock_source::ACLK) / (clock_get_threshold(threshold::APB1) + 1), + clock::APB2 => clock_source_get_freq(clock_source::ACLK) / (clock_get_threshold(threshold::APB2) + 1), + clock::AI => clock_source_get_freq(clock_source::PLL1) / (clock_get_threshold(threshold::AI) + 1), + clock::I2S0 => clock_source_get_freq(clock_source::PLL2) / ((clock_get_threshold(threshold::I2S0) + 1) * 2), + clock::I2S1 => clock_source_get_freq(clock_source::PLL2) / ((clock_get_threshold(threshold::I2S1) + 1) * 2), + clock::I2S2 => clock_source_get_freq(clock_source::PLL2) / ((clock_get_threshold(threshold::I2S2) + 1) * 2), + clock::WDT0 => clock_source_get_freq(clock_source::IN0) / ((clock_get_threshold(threshold::WDT0) + 1) * 2), + clock::WDT1 => clock_source_get_freq(clock_source::IN0) / ((clock_get_threshold(threshold::WDT1) + 1) * 2), + clock::SPI0 => clock_source_get_freq(clock_source::PLL0) / ((clock_get_threshold(threshold::SPI0) + 1) * 2), + clock::SPI1 => clock_source_get_freq(clock_source::PLL0) / ((clock_get_threshold(threshold::SPI1) + 1) * 2), + clock::SPI2 => clock_source_get_freq(clock_source::PLL0) / ((clock_get_threshold(threshold::SPI2) + 1) * 2), + clock::I2C0 => clock_source_get_freq(clock_source::PLL0) / ((clock_get_threshold(threshold::I2C0) + 1) * 2), + clock::I2C1 => clock_source_get_freq(clock_source::PLL0) / ((clock_get_threshold(threshold::I2C1) + 1) * 2), + clock::I2C2 => clock_source_get_freq(clock_source::PLL0) / ((clock_get_threshold(threshold::I2C2) + 1) * 2), + clock::SPI3 => { + let source = match clock_get_clock_select(clock_select::SPI3) { + 0 => clock_source_get_freq(clock_source::IN0), + 1 => clock_source_get_freq(clock_source::PLL0), + _ => panic!("unimplemented clock source"), + }; + source / ((clock_get_threshold(threshold::SPI3) + 1) * 2) + } + clock::TIMER0 => { + let source = match clock_get_clock_select(clock_select::TIMER0) { + 0 => clock_source_get_freq(clock_source::IN0), + 1 => clock_source_get_freq(clock_source::PLL0), + _ => panic!("unimplemented clock source"), + }; + source / ((clock_get_threshold(threshold::TIMER0) + 1) * 2) + } + clock::TIMER1 => { + let source = match clock_get_clock_select(clock_select::TIMER1) { + 0 => clock_source_get_freq(clock_source::IN0), + 1 => clock_source_get_freq(clock_source::PLL0), + _ => panic!("unimplemented clock source"), + }; + source / ((clock_get_threshold(threshold::TIMER1) + 1) * 2) + } + clock::TIMER2 => { + let source = match clock_get_clock_select(clock_select::TIMER2) { + 0 => clock_source_get_freq(clock_source::IN0), + 1 => clock_source_get_freq(clock_source::PLL0), + _ => panic!("unimplemented clock source"), + }; + source / ((clock_get_threshold(threshold::TIMER2) + 1) * 2) + } + clock::RTC => clock_source_get_freq(clock_source::IN0), + } +} + +fn reset_ctl(reset: reset, rst_value: bool) { + unsafe { + let ptr = pac::SYSCTL::ptr(); + match reset { + reset::SOC => (*ptr).soft_reset.modify(|_, w| w.soft_reset().bit(rst_value)), + reset::ROM => (*ptr).peri_reset.modify(|_, w| w.rom_reset().bit(rst_value)), + reset::DMA => (*ptr).peri_reset.modify(|_, w| w.dma_reset().bit(rst_value)), + reset::AI => (*ptr).peri_reset.modify(|_, w| w.ai_reset().bit(rst_value)), + reset::DVP => (*ptr).peri_reset.modify(|_, w| w.dvp_reset().bit(rst_value)), + reset::FFT => (*ptr).peri_reset.modify(|_, w| w.fft_reset().bit(rst_value)), + reset::GPIO => (*ptr).peri_reset.modify(|_, w| w.gpio_reset().bit(rst_value)), + reset::SPI0 => (*ptr).peri_reset.modify(|_, w| w.spi0_reset().bit(rst_value)), + reset::SPI1 => (*ptr).peri_reset.modify(|_, w| w.spi1_reset().bit(rst_value)), + reset::SPI2 => (*ptr).peri_reset.modify(|_, w| w.spi2_reset().bit(rst_value)), + reset::SPI3 => (*ptr).peri_reset.modify(|_, w| w.spi3_reset().bit(rst_value)), + reset::I2S0 => (*ptr).peri_reset.modify(|_, w| w.i2s0_reset().bit(rst_value)), + reset::I2S1 => (*ptr).peri_reset.modify(|_, w| w.i2s1_reset().bit(rst_value)), + reset::I2S2 => (*ptr).peri_reset.modify(|_, w| w.i2s2_reset().bit(rst_value)), + reset::I2C0 => (*ptr).peri_reset.modify(|_, w| w.i2c0_reset().bit(rst_value)), + reset::I2C1 => (*ptr).peri_reset.modify(|_, w| w.i2c1_reset().bit(rst_value)), + reset::I2C2 => (*ptr).peri_reset.modify(|_, w| w.i2c2_reset().bit(rst_value)), + reset::UART1 => (*ptr).peri_reset.modify(|_, w| w.uart1_reset().bit(rst_value)), + reset::UART2 => (*ptr).peri_reset.modify(|_, w| w.uart2_reset().bit(rst_value)), + reset::UART3 => (*ptr).peri_reset.modify(|_, w| w.uart3_reset().bit(rst_value)), + reset::AES => (*ptr).peri_reset.modify(|_, w| w.aes_reset().bit(rst_value)), + reset::FPIOA => (*ptr).peri_reset.modify(|_, w| w.fpioa_reset().bit(rst_value)), + reset::TIMER0 => (*ptr).peri_reset.modify(|_, w| w.timer0_reset().bit(rst_value)), + reset::TIMER1 => (*ptr).peri_reset.modify(|_, w| w.timer1_reset().bit(rst_value)), + reset::TIMER2 => (*ptr).peri_reset.modify(|_, w| w.timer2_reset().bit(rst_value)), + reset::WDT0 => (*ptr).peri_reset.modify(|_, w| w.wdt0_reset().bit(rst_value)), + reset::WDT1 => (*ptr).peri_reset.modify(|_, w| w.wdt1_reset().bit(rst_value)), + reset::SHA => (*ptr).peri_reset.modify(|_, w| w.sha_reset().bit(rst_value)), + reset::RTC => (*ptr).peri_reset.modify(|_, w| w.rtc_reset().bit(rst_value)), + } + } +} + +pub fn reset(reset: reset) { + reset_ctl(reset, true); + usleep(10); + reset_ctl(reset, false); +} + +/** Select DMA handshake for a channel */ +pub fn dma_select(channel: dma_channel, select: dma_select) +{ + unsafe { + use dma_channel::*; + let ptr = pac::SYSCTL::ptr(); + match channel { + CHANNEL0 => (*ptr).dma_sel0.modify(|_,w| w.dma_sel0().variant(select)), + CHANNEL1 => (*ptr).dma_sel0.modify(|_,w| w.dma_sel1().variant(select)), + CHANNEL2 => (*ptr).dma_sel0.modify(|_,w| w.dma_sel2().variant(select)), + CHANNEL3 => (*ptr).dma_sel0.modify(|_,w| w.dma_sel3().variant(select)), + CHANNEL4 => (*ptr).dma_sel0.modify(|_,w| w.dma_sel4().variant(select)), + CHANNEL5 => (*ptr).dma_sel1.modify(|_,w| w.dma_sel5().variant(select)), + } + } +} + +/** Return whether the selected PLL has achieved lock */ +fn pll_is_lock(pll: pll) -> bool { + let ptr = pac::SYSCTL::ptr(); + let pll_lock = unsafe { (*ptr).pll_lock.read() }; + match pll { + pll::PLL0 => pll_lock.pll_lock0().bits() == 3, + pll::PLL1 => (pll_lock.pll_lock1().bits() & 1) == 1, + pll::PLL2 => (pll_lock.pll_lock2().bits() & 1) == 1, + } +} + +/** Clear PLL slip, this is done repeatedly until lock is achieved */ +fn pll_clear_slip(pll: pll) -> bool { + let ptr = pac::SYSCTL::ptr(); + unsafe { + (*ptr).pll_lock.modify(|_,w| + match pll { + pll::PLL0 => w.pll_slip_clear0().set_bit(), + pll::PLL1 => w.pll_slip_clear1().set_bit(), + pll::PLL2 => w.pll_slip_clear2().set_bit(), + } + ); + } + pll_is_lock(pll) +} + +fn pll_source_set_freq(pll: pll, source: clock_source, freq: u32) -> Result { + use pll::*; + /* PLL0 and 1 can only source from IN0 */ + if (pll == PLL0 || pll == PLL1) && source != clock_source::IN0 { + return Err(()); + } + let freq_in = clock_source_get_freq(source); + if freq_in == 0 { + return Err(()); + } + if let Some(found) = pll_compute::compute_params(freq_in, freq) { + let ptr = pac::SYSCTL::ptr(); + unsafe { + match pll { + PLL0 => { + (*ptr).pll0.modify(|_,w| + w.clkr().bits(found.clkr) + .clkf().bits(found.clkf) + .clkod().bits(found.clkod) + .bwadj().bits(found.bwadj) + ); + } + PLL1 => { + (*ptr).pll1.modify(|_,w| + w.clkr().bits(found.clkr) + .clkf().bits(found.clkf) + .clkod().bits(found.clkod) + .bwadj().bits(found.bwadj) + ); + } + PLL2 => { + (*ptr).pll2.modify(|_,w| + w.ckin_sel().bits(pll2_source_to_cksel(source)) + .clkr().bits(found.clkr) + .clkf().bits(found.clkf) + .clkod().bits(found.clkod) + .bwadj().bits(found.bwadj) + ); + } + } + } + Ok(pll_get_freq(pll)) + } else { + Err(()) + } +} + +/** + * @brief Init PLL freqency + * @param[in] pll The PLL id + * @param[in] pll_freq The desired frequency in Hz + + */ +pub fn pll_set_freq(pll: pll, freq: u32) -> Result { + let ptr = pac::SYSCTL::ptr(); + use pll::*; + + /* 1. Change CPU CLK to XTAL */ + if pll == PLL0 { + clock_set_clock_select(clock_select::ACLK, 0 /* clock_source::IN0 */); + } + + /* 2. Disable PLL output */ + unsafe { + match pll { + PLL0 => (*ptr).pll0.modify(|_,w| w.out_en().clear_bit()), + PLL1 => (*ptr).pll1.modify(|_,w| w.out_en().clear_bit()), + PLL2 => (*ptr).pll2.modify(|_,w| w.out_en().clear_bit()), + }; + } + /* 3. Turn off PLL */ + unsafe { + match pll { + PLL0 => (*ptr).pll0.modify(|_,w| w.pwrd().clear_bit()), + PLL1 => (*ptr).pll1.modify(|_,w| w.pwrd().clear_bit()), + PLL2 => (*ptr).pll2.modify(|_,w| w.pwrd().clear_bit()), + }; + } + /* 4. Set PLL to new value */ + let result = if pll == PLL2 { + pll_source_set_freq(pll, pll2_cksel_to_source(clock_get_clock_select(clock_select::PLL2)), freq) + } else { + pll_source_set_freq(pll, clock_source::IN0, freq) + }; + + /* 5. Power on PLL */ + unsafe { + match pll { + PLL0 => (*ptr).pll0.modify(|_,w| w.pwrd().set_bit()), + PLL1 => (*ptr).pll1.modify(|_,w| w.pwrd().set_bit()), + PLL2 => (*ptr).pll2.modify(|_,w| w.pwrd().set_bit()), + }; + } + + + /* wait >100ns */ + usleep(1); + + /* 6. Reset PLL then Release Reset*/ + unsafe { + match pll { + PLL0 => (*ptr).pll0.modify(|_,w| w.reset().clear_bit()), + PLL1 => (*ptr).pll1.modify(|_,w| w.reset().clear_bit()), + PLL2 => (*ptr).pll2.modify(|_,w| w.reset().clear_bit()), + }; + match pll { + PLL0 => (*ptr).pll0.modify(|_,w| w.reset().set_bit()), + PLL1 => (*ptr).pll1.modify(|_,w| w.reset().set_bit()), + PLL2 => (*ptr).pll2.modify(|_,w| w.reset().set_bit()), + }; + } + /* wait >100ns */ + usleep(1); + unsafe { + match pll { + PLL0 => (*ptr).pll0.modify(|_,w| w.reset().clear_bit()), + PLL1 => (*ptr).pll1.modify(|_,w| w.reset().clear_bit()), + PLL2 => (*ptr).pll2.modify(|_,w| w.reset().clear_bit()), + }; + } + + /* 7. Get lock status, wait PLL stable */ + while !pll_is_lock(pll) { + pll_clear_slip(pll); + } + + /* 8. Enable PLL output */ + unsafe { + match pll { + PLL0 => (*ptr).pll0.modify(|_,w| w.out_en().set_bit()), + PLL1 => (*ptr).pll1.modify(|_,w| w.out_en().set_bit()), + PLL2 => (*ptr).pll2.modify(|_,w| w.out_en().set_bit()), + }; + } + + /* 9. Change CPU CLK to PLL */ + if pll == PLL0 { + clock_set_clock_select(clock_select::ACLK, 1 /*clock_source::PLL0*/); + } + result +} diff --git a/os/src/drivers/soc/sysctl/pll_compute.rs b/os/src/drivers/soc/sysctl/pll_compute.rs new file mode 100644 index 0000000..349038a --- /dev/null +++ b/os/src/drivers/soc/sysctl/pll_compute.rs @@ -0,0 +1,569 @@ +/** PLL configuration */ +#[derive(Debug, PartialEq, Eq)] +pub struct Params { + pub clkr: u8, + pub clkf: u8, + pub clkod: u8, + pub bwadj: u8, +} + +/* + * The PLL included with the Kendryte K210 appears to be a True Circuits, Inc. + * General-Purpose PLL. The logical layout of the PLL with internal feedback is + * approximately the following: + * + * +---------------+ + * |reference clock| + * +---------------+ + * | + * v + * +--+ + * |/r| + * +--+ + * | + * v + * +-------------+ + * |divided clock| + * +-------------+ + * | + * v + * +--------------+ + * |phase detector|<---+ + * +--------------+ | + * | | + * v +--------------+ + * +---+ |feedback clock| + * |VCO| +--------------+ + * +---+ ^ + * | +--+ | + * +--->|/f|---+ + * | +--+ + * v + * +---+ + * |/od| + * +---+ + * | + * v + * +------+ + * |output| + * +------+ + * + * The k210 PLLs have three factors: r, f, and od. Because of the feedback mode, + * the effect of the division by f is to multiply the input frequency. The + * equation for the output rate is + * rate = (rate_in * f) / (r * od). + * Moving knowns to one side of the equation, we get + * rate / rate_in = f / (r * od) + * Rearranging slightly, + * abs_error = abs((rate / rate_in) - (f / (r * od))). + * To get relative, error, we divide by the expected ratio + * error = abs((rate / rate_in) - (f / (r * od))) / (rate / rate_in). + * Simplifying, + * error = abs(1 - f / (r * od)) / (rate / rate_in) + * error = abs(1 - (f * rate_in) / (r * od * rate)) + * Using the constants ratio = rate / rate_in and inv_ratio = rate_in / rate, + * error = abs((f * inv_ratio) / (r * od) - 1) + * This is the error used in evaluating parameters. + * + * r and od are four bits each, while f is six bits. Because r and od are + * multiplied together, instead of the full 256 values possible if both bits + * were used fully, there are only 97 distinct products. Combined with f, there + * are 6208 theoretical settings for the PLL. However, most of these settings + * can be ruled out immediately because they do not have the correct ratio. + * + * In addition to the constraint of approximating the desired ratio, parameters + * must also keep internal pll frequencies within acceptable ranges. The divided + * clock's minimum and maximum frequencies have a ratio of around 128. This + * leaves fairly substantial room to work with, especially since the only + * affected parameter is r. The VCO's minimum and maximum frequency have a ratio + * of 5, which is considerably more restrictive. + * + * The r and od factors are stored in a table. This is to make it easy to find + * the next-largest product. Some products have multiple factorizations, but + * only when one factor has at least a 2.5x ratio to the factors of the other + * factorization. This is because any smaller ratio would not make a difference + * when ensuring the VCO's frequency is within spec. + * + * Throughout the calculation function, fixed point arithmetic is used. Because + * the range of rate and rate_in may be up to 1.75 GHz, or around 2^30, 64-bit + * 32.32 fixed-point numbers are used to represent ratios. In general, to + * implement division, the numerator is first multiplied by 2^32. This gives a + * result where the whole number part is in the upper 32 bits, and the fraction + * is in the lower 32 bits. + * + * In general, rounding is done to the closest integer. This helps find the best + * approximation for the ratio. Rounding in one direction (e.g down) could cause + * the function to miss a better ratio with one of the parameters increased by + * one. + */ + +const VCO_MIN: u64 = 340_000_000; +const VCO_MAX: u64 = 1_750_000_000; +const DIV_MIN: u32 = 13_300_000; +const DIV_MAX: u32 = 1_750_000_000; +const R_MIN: u32 = 1; +const R_MAX: u32 = 16; +const F_MIN: u32 = 1; +const F_MAX: u32 = 64; +const OD_MIN: u32 = 1; +const OD_MAX: u32 = 16; +const OUT_MIN: u32 = (VCO_MIN as u32) / OD_MAX; /* 21_250_000 */ +const OUT_MAX: u32 = (VCO_MAX as u32) / OD_MIN; /* 1_750_000_000 */ +const IN_MIN: u32 = DIV_MIN * R_MIN; /* 13_300_000 */ +const IN_MAX: u32 = OUT_MAX; /* 1_750_000_000 */ + +/* + * The factors table was generated with the following python code: + * + * def p(x, y): + * return (1.0*x/y > 2.5) or (1.0*y/x > 2.5) + * + * factors = {} + * for i in range(1, 17): + * for j in range(1, 17): + * fs = factors.get(i*j) or [] + * if fs == [] or all([ + * (p(i, x) and p(i, y)) or (p(j, x) and p(j, y)) + * for (x, y) in fs]): + * fs.append((i, j)) + * factors[i*j] = fs + * + * for k, l in sorted(factors.items()): + * for v in l: + * print("pack(%s, %s)," % v) + */ +struct Factor { + packed: u8, +} + +/* Apologies, but there are no native bitfields (yet) afaik */ +const fn pack(r: u32, od: u32) -> Factor { + Factor { packed: (((((r as u8) - 1) & 0xF) << 4) | (((od as u8) - 1) & 0xF)) } +} + +const fn unpack_r(factor: &&Factor) -> u32 { + (((factor.packed as u32) >> 4) & 0xF) + 1 +} + +const fn unpack_od(factor: &&Factor) -> u32 { + ((factor.packed as u32) & 0xF) + 1 +} + +static FACTORS: &'static [Factor] = &[ + pack(1, 1), + pack(1, 2), + pack(1, 3), + pack(1, 4), + pack(1, 5), + pack(1, 6), + pack(1, 7), + pack(1, 8), + pack(1, 9), + pack(3, 3), + pack(1, 10), + pack(1, 11), + pack(1, 12), + pack(3, 4), + pack(1, 13), + pack(1, 14), + pack(1, 15), + pack(3, 5), + pack(1, 16), + pack(4, 4), + pack(2, 9), + pack(2, 10), + pack(3, 7), + pack(2, 11), + pack(2, 12), + pack(5, 5), + pack(2, 13), + pack(3, 9), + pack(2, 14), + pack(2, 15), + pack(2, 16), + pack(3, 11), + pack(5, 7), + pack(3, 12), + pack(3, 13), + pack(4, 10), + pack(3, 14), + pack(4, 11), + pack(3, 15), + pack(3, 16), + pack(7, 7), + pack(5, 10), + pack(4, 13), + pack(6, 9), + pack(5, 11), + pack(4, 14), + pack(4, 15), + pack(7, 9), + pack(4, 16), + pack(5, 13), + pack(6, 11), + pack(5, 14), + pack(6, 12), + pack(5, 15), + pack(7, 11), + pack(6, 13), + pack(5, 16), + pack(9, 9), + pack(6, 14), + pack(8, 11), + pack(6, 15), + pack(7, 13), + pack(6, 16), + pack(7, 14), + pack(9, 11), + pack(10, 10), + pack(8, 13), + pack(7, 15), + pack(9, 12), + pack(10, 11), + pack(7, 16), + pack(9, 13), + pack(8, 15), + pack(11, 11), + pack(9, 14), + pack(8, 16), + pack(10, 13), + pack(11, 12), + pack(9, 15), + pack(10, 14), + pack(11, 13), + pack(9, 16), + pack(10, 15), + pack(11, 14), + pack(12, 13), + pack(10, 16), + pack(11, 15), + pack(12, 14), + pack(13, 13), + pack(11, 16), + pack(12, 15), + pack(13, 14), + pack(12, 16), + pack(13, 15), + pack(14, 14), + pack(13, 16), + pack(14, 15), + pack(14, 16), + pack(15, 15), + pack(15, 16), + pack(16, 16), +]; + +/* Divide and round to the closest integer */ +fn div_round_closest(n: u64, d: u32) -> u64 { + let _d: u64 = d as u64; + + (n + (_d / 2)) / _d +} + +/* Integer with that bit set */ +fn bit(bit: u8) -> u64 { + 1 << bit +} + +/* | a - b | */ +fn abs_diff(a: u32, b: u32) -> u32 { + if a > b { + a - b + } else { + b - a + } +} + +pub fn compute_params(freq_in: u32, freq_out: u32) -> Option { + let mut best: Option = None; + let mut factors = FACTORS.iter().peekable(); + let (mut error, mut best_error): (i64, i64); + let (ratio, inv_ratio): (u64, u64); /* fixed point 32.32 ratio of the freqs */ + let max_r: u32; + let (mut r, mut f, mut od): (u32, u32, u32); + + /* + * Can't go over 1.75 GHz or under 21.25 MHz due to limitations on the + * VCO frequency. These are not the same limits as below because od can + * reduce the output frequency by 16. + */ + if freq_out > OUT_MAX || freq_out < OUT_MIN { + return None; + } + + /* Similar restrictions on the input ratio */ + if freq_in > IN_MAX || freq_in < IN_MIN { + return None; + } + + ratio = div_round_closest((freq_out as u64) << 32, freq_in); + inv_ratio = div_round_closest((freq_in as u64) << 32, freq_out); + /* Can't increase by more than 64 or reduce by more than 256 */ + if freq_out > freq_in && ratio > (64 << 32) { + return None; + } else if freq_out <= freq_in && inv_ratio > (256 << 32) { + return None; + } + + /* + * The divided clock (freq_in / r) must stay between 1.75 GHz and 13.3 + * MHz. There is no minimum, since the only way to get a higher input + * clock than 26 MHz is to use a clock generated by a PLL. Because PLLs + * cannot output frequencies greater than 1.75 GHz, the minimum would + * never be greater than one. + */ + max_r = freq_in / DIV_MIN; + + /* Variables get immediately incremented, so start at -1th iteration */ + f = 0; + r = 0; + od = 0; + best_error = i64::max_value(); + error = best_error; + /* Always try at least one ratio */ + 'outer: loop { + /* + * Whether we swapped r and od while enforcing frequency limits + */ + let mut swapped: bool = false; + let last_od: u32 = od; + let last_r: u32 = r; + + /* + * Try the next largest value for f (or r and od) and + * recalculate the other parameters based on that + */ + if freq_out > freq_in { + /* + * Skip factors of the same product if we already tried + * out that product + */ + while r * od == last_r * last_od { + match factors.next() { + Some(factor) => { + r = unpack_r(&factor); + od = unpack_od(&factor); + }, + None => break 'outer, + } + } + + /* Round close */ + f = ((((r * od) as u64) * ratio + bit(31)) >> 32) as u32; + if f > F_MAX { + f = F_MAX; + } + } else { + f += 1; + let tmp: u64 = (f as u64) * inv_ratio; + let round_up: bool = tmp & bit(31) != 0; + let goal: u32 = ((tmp >> 32) as u32) + (round_up as u32); + let (err, last_err): (u32, u32); + + /* + * Get the next r/od pair in factors. If the last_* pair is better, + * then we will use it instead, so don't call next until after we're + * sure we won't need this pair. + */ + loop { + match factors.peek() { + Some(factor) => { + r = unpack_r(factor); + od = unpack_od(factor) + }, + None => break 'outer, + } + + if r * od < goal { + factors.next(); + } else { + break; + } + } + + /* + * This is a case of double rounding. If we rounded up + * above, we need to round down (in cases of ties) here. + * This prevents off-by-one errors resulting from + * choosing X+2 over X when X.Y rounds up to X+1 and + * there is no r * od = X+1. For the converse, when X.Y + * is rounded down to X, we should choose X+1 over X-1. + */ + err = abs_diff(r * od, goal); + last_err = abs_diff(last_r * last_od, goal); + if last_err < err || (round_up && last_err == err) { + r = last_r; + od = last_od; + } else { + factors.next(); + } + } + + /* + * Enforce limits on internal clock frequencies. If we + * aren't in spec, try swapping r and od. If everything is + * in-spec, calculate the relative error. + */ + loop { + /* + * Whether the intermediate frequencies are out-of-spec + */ + let mut out_of_spec: bool = false; + + if r > max_r { + out_of_spec = true; + } else { + /* + * There is no way to only divide once; we need + * to examine the frequency with and without the + * effect of od. + */ + let vco: u64 = div_round_closest((freq_in as u64) * (f as u64), r); + + if vco > VCO_MAX || vco < VCO_MIN { + out_of_spec = true; + } + } + + if out_of_spec { + if !swapped { + let tmp: u32 = r; + + r = od; + od = tmp; + swapped = true; + continue; + } else { + /* + * Try looking ahead to see if there are + * additional factors for the same + * product. + */ + match factors.peek() { + Some(factor) => { + let new_r: u32 = unpack_r(factor); + let new_od: u32 = unpack_od(factor); + + if r * od == new_r * new_od { + factors.next(); + r = new_r; + od = new_od; + swapped = false; + continue; + } else { + break; + } + }, + None => break 'outer, + } + } + } + + error = div_round_closest((f as u64) * inv_ratio, r * od) as i64; + /* The lower 16 bits are spurious */ + error = i64::abs(error - (bit(32) as i64)) >> 16; + + if error < best_error { + best_error = error; + best = Some(Params { + clkr: (r - 1) as u8, + clkf: (f - 1) as u8, + clkod: (od - 1) as u8, + bwadj: (f - 1) as u8, + }); + } + break; + } + + if error == 0 { + break; + } + } + + return best; +} + +#[cfg(test)] +mod tests { + use super::*; + + fn brute_force_params(freq_in: u32, freq_out: u32) -> Option { + let mut best: Option = None; + let (mut error, mut best_error): (i64, i64); + let (max_r, inv_ratio): (u32, u64); + + best_error = i64::max_value(); + max_r = u32::min(R_MAX, (freq_in / DIV_MIN) as u32); + inv_ratio = div_round_closest((freq_in as u64) << 32, freq_out); + + /* Brute force it */ + for r in R_MIN..=max_r { + for f in F_MIN..=F_MAX { + for od in OD_MIN..=OD_MAX { + let vco: u64 = div_round_closest((freq_in as u64) * (f as u64), r); + + if vco > VCO_MAX || vco < VCO_MIN { + continue; + } + + error = div_round_closest((f as u64) * inv_ratio, r * od) as i64; + /* The lower 16 bits are spurious */ + error = i64::abs(error - (bit(32) as i64)) >> 16; + if error < best_error { + best_error = error; + best = Some(Params { + clkr: (r - 1) as u8, + clkf: (f - 1) as u8, + clkod: (od - 1) as u8, + bwadj: (f - 1) as u8, + }); + } + } + } + } + + return best; + } + + fn params_equal(_a: Option, _b: Option) -> bool { + match (_a, _b) { + (None, None) => true, + (Some(_), None) => false, + (None, Some(_)) => false, + (Some(a), Some(b)) => { + let ar: u32 = (a.clkr + 1) as u32; + let af: u32 = (a.clkf + 1) as u32; + let aod: u32 = (a.clkod + 1) as u32; + let br: u32 = (b.clkr + 1) as u32; + let bf: u32 = (b.clkf + 1) as u32; + let bod: u32 = (b.clkod + 1) as u32; + + af * br * bod == bf * ar * aod + } + } + } + + fn verify_compute_params(freq_in: u32, freq_out: u32) -> bool { + params_equal(compute_params(freq_in, freq_out), brute_force_params(freq_in, freq_out)) + } + + #[test] + fn test_compute_params() { + assert_eq!(compute_params(26_000_000, 0), None); + assert_eq!(compute_params(0, 390_000_000), None); + assert_eq!(compute_params(26_000_000, 2_000_000_000), None); + assert_eq!(compute_params(2_000_000_000, 390_000_000), None); + assert_eq!(compute_params(20_000_000, 1_500_000_000), None); + + assert!(verify_compute_params(26_000_000, 1_500_000_000)); + assert!(verify_compute_params(26_000_000, 1_000_000_000)); + assert!(verify_compute_params(26_000_000, 800_000_000)); + assert!(verify_compute_params(26_000_000, 700_000_000)); + assert!(verify_compute_params(26_000_000, 300_000_000)); + assert!(verify_compute_params(26_000_000, 45_158_400)); + assert!(verify_compute_params(26_000_000, 27_000_000)); + assert!(verify_compute_params(27_000_000, 26_000_000)); + assert!(verify_compute_params(390_000_000, 26_000_000)); + assert!(verify_compute_params(390_000_000, 383_846_400)); + } +} \ No newline at end of file diff --git a/os/src/drivers/soc/utils.rs b/os/src/drivers/soc/utils.rs new file mode 100644 index 0000000..94154ff --- /dev/null +++ b/os/src/drivers/soc/utils.rs @@ -0,0 +1,15 @@ +#![allow(unused)] + +//! Miscelleneous utilities for SoC functions (private) + +pub fn set_bit(inval: u32, bit: u8, state: bool) -> u32 { + if state { + inval | (1 << u32::from(bit)) + } else { + inval & !(1 << u32::from(bit)) + } +} + +pub fn get_bit(inval: u32, bit: u8) -> bool { + (inval & (1 << u32::from(bit))) != 0 +} \ No newline at end of file diff --git a/os/src/entry.asm b/os/src/entry.asm index 650f358..bb22640 100644 --- a/os/src/entry.asm +++ b/os/src/entry.asm @@ -48,14 +48,14 @@ boot_stack_top: .global boot_page_table boot_page_table: # .8byte表示长度为8个字节的整数 - .8byte 0 - .8byte 0 + .8byte (0x00000 << 10) | 0xcf + .8byte (0x40000 << 10) | 0xcf # 第 2 项：0x8000_0000 -> 0x8000_0000，0xcf 表示 VRWXAD 均为 1 .8byte (0x80000 << 10) | 0xcf .zero 505 * 8 # 第 508 项（外设用）：0xffff_ffff_0000_0000 -> 0x0000_0000，0xcf 表示 VRWXAD 均为 1 .8byte (0x00000 << 10) | 0xcf - .8byte 0 + .8byte (0x40000 << 10) | 0xcf # 第 510 项：0xffff_ffff_8000_0000 -> 0x8000_0000，0xcf 表示 VRWXAD 均为 1 .8byte (0x80000 << 10) | 0xcf .8byte 0 diff --git a/os/src/fs/mod.rs b/os/src/fs/mod.rs index fa26c80..c3d3756 100644 --- a/os/src/fs/mod.rs +++ b/os/src/fs/mod.rs @@ -5,6 +5,7 @@ use crate::drivers::{ block::BlockDevice, driver::{DeviceType, DRIVERS}, + block::sdcard::Sd_card, }; use crate::kernel::Condvar; use alloc::{sync::Arc, vec::Vec}; @@ -17,13 +18,16 @@ mod config; mod inode_ext; mod stdin; mod stdout; +mod swap; pub use config::*; pub use inode_ext::INodeExt; pub use rcore_fs::{dev::block_cache::BlockCache, vfs::*}; pub use stdin::STDIN; pub use stdout::STDOUT; +pub use swap::SwapTracker; +#[cfg(feature = "board_qemu")] lazy_static! { /// 根文件系统的根目录的 INode pub static ref ROOT_INODE: Arc = { @@ -42,6 +46,16 @@ lazy_static! { }; } +#[cfg(feature = "board_k210")] +lazy_static! { + /// 根文件系统的根目录的 INode + pub static ref ROOT_INODE: Arc = { + let device = Arc::new(Sd_card::new()); + let sfs = SimpleFileSystem::open(device).expect("failed to open SFS"); + sfs.root_inode() + }; +} + /// 触发 [`static@ROOT_INODE`] 的初始化并打印根目录内容 pub fn init() { ROOT_INODE.ls(); diff --git a/os/src/fs/swap.rs b/os/src/fs/swap.rs new file mode 100644 index 0000000..16bf89f --- /dev/null +++ b/os/src/fs/swap.rs @@ -0,0 +1,90 @@ +//! 内存置换文件 + +use super::*; +use crate::memory::*; +use algorithm::{Allocator, AllocatorImpl}; + +/// 内存置换文件在硬盘镜像中的路径（在 `user/Makefile` 中预先生成） +const SWAP_FILE_PATH: &str = "SWAP_FILE"; +/// 内存置换文件可以存放的页面数量 +const SWAP_FILE_CAPACITY: usize = 4096; + +lazy_static! { + /// 内存置换文件 + static ref SWAP: Swap = Swap { + inode: ROOT_INODE + .lookup(SWAP_FILE_PATH) + .expect("cannot find swap file"), + allocator: Mutex::new(AllocatorImpl::new(4096)), + }; +} + +/// 实现对于内存置换文件的一些操作 +struct Swap { + /// 置换文件 + inode: Arc, + /// 置换算法 + allocator: Mutex, +} + +impl Swap { + /// 在置换文件中分配一个页面的位置 + pub(self) fn alloc(&self) -> MemoryResult { + self.allocator.lock().alloc().ok_or("swap file full") + } + + /// 在置换文件中释放一个页面的位置 + pub(self) fn dealloc(&self, index: usize) { + assert!(index < SWAP_FILE_CAPACITY); + self.allocator.lock().dealloc(index); + } + + /// 将数据写入置换文件指定的页面位置 + pub(self) fn write_page(&self, index: usize, data: &[u8; PAGE_SIZE]) { + assert!(index < SWAP_FILE_CAPACITY); + self.inode + .write_at(index * PAGE_SIZE, data) + .expect("failed to write swap file"); + } + + /// 从置换文件指定的页面中读取数据 + pub(self) fn read_page(&self, index: usize) -> [u8; PAGE_SIZE] { + assert!(index < SWAP_FILE_CAPACITY); + let mut data = [0u8; PAGE_SIZE]; + self.inode + .read_at(index * PAGE_SIZE, &mut data) + .expect("failed to read swap file"); + data + } +} + +/// 类似于 [`FrameTracker`]，相当于 `Box<置换文件中的一个页面>` +/// +/// 内部保存该置换页面在文件中保存的 index +/// +/// [`FrameTracker`]: crate::memory::frame::FrameTracker +#[derive(Debug, Ord, PartialOrd, Eq, PartialEq, Hash)] +pub struct SwapTracker(pub(super) usize); + +impl SwapTracker { + /// 从置换文件分配一个页面空间 + pub fn new() -> MemoryResult { + SWAP.alloc().map(Self) + } + + /// 读取页面数据 + pub fn read(&self) -> [u8; PAGE_SIZE] { + SWAP.read_page(self.0) + } + + /// 写入页面数据 + pub fn write(&self, data: &[u8; PAGE_SIZE]) { + SWAP.write_page(self.0, data); + } +} + +impl Drop for SwapTracker { + fn drop(&mut self) { + SWAP.dealloc(self.0); + } +} diff --git a/os/src/interrupt/handler.rs b/os/src/interrupt/handler.rs index 6eb54f0..490ce68 100644 --- a/os/src/interrupt/handler.rs +++ b/os/src/interrupt/handler.rs @@ -9,6 +9,12 @@ use riscv::register::{ scause::{Exception, Interrupt, Scause, Trap}, sie, stvec, }; +use crate::board::interrupt::{ + breakpoint, + supervisor_timer, + supervisor_soft, + supervisor_external, +}; global_asm!(include_str!("./interrupt.asm")); @@ -26,15 +32,7 @@ pub fn init() { // 开启外部中断使能 sie::set_sext(); - - // 在 OpenSBI 中开启外部中断 - *PhysicalAddress(0x0c00_2080).deref_kernel() = 1u32 << 10; - // 在 OpenSBI 中开启串口 - *PhysicalAddress(0x1000_0004).deref_kernel() = 0x0bu8; - *PhysicalAddress(0x1000_0001).deref_kernel() = 0x01u8; - // 其他一些外部中断相关魔数 - *PhysicalAddress(0x0C00_0028).deref_kernel() = 0x07u32; - *PhysicalAddress(0x0C20_1000).deref_kernel() = 0u32; + sie::set_ssoft(); } } @@ -54,47 +52,50 @@ pub fn handle_interrupt(context: &mut Context, scause: Scause, stval: usize) -> return processor.prepare_next_thread(); } } + //println!("into intr handle!"); + //println!("cause = {:?}", scause.cause()); // 根据中断类型来处理，返回的 Context 必须位于放在内核栈顶 match scause.cause() { // 断点中断（ebreak） Trap::Exception(Exception::Breakpoint) => breakpoint(context), // 系统调用 Trap::Exception(Exception::UserEnvCall) => syscall_handler(context), + // 缺页异常 + Trap::Exception(Exception::LoadPageFault) + | Trap::Exception(Exception::StorePageFault) + | Trap::Exception(Exception::InstructionPageFault) + | Trap::Exception(Exception::LoadFault) + | Trap::Exception(Exception::StoreFault) + | Trap::Exception(Exception::InstructionFault) => page_fault(context, scause, stval), // 时钟中断 Trap::Interrupt(Interrupt::SupervisorTimer) => supervisor_timer(context), // 外部中断（键盘输入） Trap::Interrupt(Interrupt::SupervisorExternal) => supervisor_external(context), + Trap::Interrupt(Interrupt::SupervisorSoft) => supervisor_soft(context), // 其他情况，无法处理 _ => fault("unimplemented interrupt type", scause, stval), } } -/// 处理 ebreak 断点 +/// 处理缺页异常 /// -/// 继续执行，其中 `sepc` 增加 2 字节，以跳过当前这条 `ebreak` 指令 -fn breakpoint(context: &mut Context) -> *mut Context { - println!("Breakpoint at 0x{:x}", context.sepc); - context.sepc += 2; - context -} - -/// 处理时钟中断 -fn supervisor_timer(context: &mut Context) -> *mut Context { - timer::tick(); - PROCESSOR.lock().park_current_thread(context); - PROCESSOR.lock().prepare_next_thread() -} +/// todo: 理论上这里需要判断访问类型，并与页表中的标志位进行比对 +fn page_fault(context: &mut Context, scause: Scause, stval: usize) -> *mut Context { + static mut COUNT: usize = 0; + println!("page_fault {}", unsafe { + COUNT += 1; + COUNT + }); + let current_thread = PROCESSOR.lock().current_thread(); + let memory_set = &mut current_thread.process.inner().memory_set; -/// 处理外部中断，只实现了键盘输入 -fn supervisor_external(context: &mut Context) -> *mut Context { - let mut c = console_getchar(); - if c <= 255 { - if c == '\r' as usize { - c = '\n' as usize; + match memory_set.mapping.handle_page_fault(stval) { + Ok(_) => { + memory_set.activate(); + context } - STDIN.push(c as u8); + Err(msg) => fault(msg, scause, stval), } - context } /// 出现未能解决的异常，终止当前线程 diff --git a/os/src/interrupt/mod.rs b/os/src/interrupt/mod.rs index 7bedf6c..dbe5f5a 100644 --- a/os/src/interrupt/mod.rs +++ b/os/src/interrupt/mod.rs @@ -4,7 +4,7 @@ mod context; mod handler; -mod timer; +pub mod timer; pub use context::Context; diff --git a/os/src/interrupt/timer.rs b/os/src/interrupt/timer.rs index 8f997fd..8c95b8b 100644 --- a/os/src/interrupt/timer.rs +++ b/os/src/interrupt/timer.rs @@ -40,3 +40,5 @@ pub fn tick() { // } } } + +pub fn read_time() -> usize { time::read() } \ No newline at end of file diff --git a/os/src/kernel/process.rs b/os/src/kernel/process.rs index e71f62b..64a6fa7 100644 --- a/os/src/kernel/process.rs +++ b/os/src/kernel/process.rs @@ -1,6 +1,9 @@ //! 进程相关的内核功能 use super::*; +use xmas_elf::ElfFile; +use crate::fs::ROOT_INODE; +use crate::fs::INodeExt; pub(super) fn sys_exit(code: usize) -> SyscallResult { println!( @@ -10,3 +13,32 @@ pub(super) fn sys_exit(code: usize) -> SyscallResult { ); SyscallResult::Kill } + +pub (super) fn sys_exec(path:*const u8,context:Context)->SyscallResult{ + + let name=unsafe{from_cstr(path)}; + let app = ROOT_INODE.find(name); + match app{ + Ok(inode)=>{ + let data = inode.readall().unwrap(); + let elf = ElfFile::new(data.as_slice()).unwrap(); + let process = Process::from_elf(&elf, true).unwrap(); + let thread=Thread::new(process, elf.header.pt2.entry_point() as usize, None).unwrap(); + PROCESSOR.lock().add_thread(thread); + PROCESSOR.lock().sleep_current_thread(); + PROCESSOR.lock().park_current_thread(&context); + PROCESSOR.lock().prepare_next_thread(); + }, + Err(_)=>{ + println!(""); + println!("command not found"); + } + } + SyscallResult::Proceed(0) + +} +pub unsafe fn from_cstr(s:*const u8)->&'static str{ + use core::{slice,str}; + let len=(0usize..).find(|&i| *s.add(i)==0).unwrap(); + str::from_utf8(slice::from_raw_parts(s,len)).unwrap() +} \ No newline at end of file diff --git a/os/src/kernel/syscall.rs b/os/src/kernel/syscall.rs index 191ffe1..ac4febf 100644 --- a/os/src/kernel/syscall.rs +++ b/os/src/kernel/syscall.rs @@ -5,6 +5,7 @@ use super::*; pub const SYS_READ: usize = 63; pub const SYS_WRITE: usize = 64; pub const SYS_EXIT: usize = 93; +pub const SYS_EXEC: usize = 221; /// 系统调用在内核之内的返回值 pub(super) enum SyscallResult { @@ -28,6 +29,7 @@ pub fn syscall_handler(context: &mut Context) -> *mut Context { SYS_READ => sys_read(args[0], args[1] as *mut u8, args[2]), SYS_WRITE => sys_write(args[0], args[1] as *mut u8, args[2]), SYS_EXIT => sys_exit(args[0]), + SYS_EXEC => sys_exec(args[0] as *const u8, *context), _ => { println!("unimplemented syscall: {}", syscall_id); SyscallResult::Kill diff --git a/os/src/linker.ld b/os/src/linker.ld index 38aa529..88900fe 100644 --- a/os/src/linker.ld +++ b/os/src/linker.ld @@ -1,61 +1,51 @@ -/* Linker Script 语法可以参见：http://www.scoberlin.de/content/media/http/informatik/gcc_docs/ld_3.html */ -/* 目标架构 */ OUTPUT_ARCH(riscv) - -/* 执行入口 */ ENTRY(_start) -/* 数据存放起始地址 */ -BASE_ADDRESS = 0xffffffff80200000; +BASE_ADDRESS = 0xffffffff80020000; SECTIONS -{ - /* . 表示当前地址（location counter） */ +{ + /* Load the kernel at this address: "." means the current address */ . = BASE_ADDRESS; - /* start 符号表示全部的开始位置 */ kernel_start = .; . = ALIGN(4K); - text_start = .; - /* .text 字段 */ + text_start = .; .text : { - /* 把 entry 函数放在最前面 */ + stext = .; *(.text.entry) - /* 要链接的文件的 .text 字段集中放在这里 */ *(.text .text.*) + etext = .; } . = ALIGN(4K); rodata_start = .; - - /* .rodata 字段 */ .rodata : { - /* 要链接的文件的 .rodata 字段集中放在这里 */ + srodata = .; *(.rodata .rodata.*) + erodata = .; } . = ALIGN(4K); data_start = .; - - /* .data 字段 */ .data : { - /* 要链接的文件的 .data 字段集中放在这里 */ + sdata = .; *(.data .data.*) + edata = .; } . = ALIGN(4K); bss_start = .; - - /* .bss 字段 */ .bss : { - /* 要链接的文件的 .bss 字段集中放在这里 */ + *(.bss.stack) + sbss_clear = .; *(.sbss .bss .bss.*) + ebss_clear = .; } - /* 结束地址 */ . = ALIGN(4K); - kernel_end = .; -} \ No newline at end of file + PROVIDE(kernel_end = .); +} diff --git a/os/src/main.rs b/os/src/main.rs index bedebe4..6d218cc 100644 --- a/os/src/main.rs +++ b/os/src/main.rs @@ -43,12 +43,14 @@ mod console; mod drivers; mod fs; -mod interrupt; +pub mod interrupt; mod kernel; mod memory; mod panic; mod process; mod sbi; +mod board; + extern crate alloc; use alloc::sync::Arc; @@ -65,37 +67,63 @@ global_asm!(include_str!("entry.asm")); /// 在 `_start` 为我们进行了一系列准备之后，这是第一个被调用的 Rust 函数 #[no_mangle] pub extern "C" fn rust_main(_hart_id: usize, dtb_pa: PhysicalAddress) -> ! { + memory::clear_bss(); memory::init(); interrupt::init(); - drivers::init(dtb_pa); + crate::board::device_init(dtb_pa); fs::init(); + /* { let mut processor = PROCESSOR.lock(); - // 创建一个内核进程 + println!("get processor!"); let kernel_process = Process::new_kernel().unwrap(); - // 为这个进程创建多个线程，并设置入口均为 sample_process，而参数不同 - for i in 1..9usize { - processor.add_thread(create_kernel_thread( - kernel_process.clone(), - sample_process as usize, - Some(&[i]), - )); - } + println!("kernel process created!"); + let thread = create_kernel_thread(kernel_process, test_page_fault as usize, None); + println!("kernel thread created!"); + processor.add_thread(thread); + println!("thread has been added!"); } + */ + + /* + PROCESSOR.lock().add_thread(create_kernel_thread( + Process::new_kernel().unwrap(), + test_page_fault as usize, + None, + )); + */ + + PROCESSOR.lock().add_thread(create_user_process("user_shell")); extern "C" { fn __restore(context: usize); } // 获取第一个线程的 Context let context = PROCESSOR.lock().prepare_next_thread(); + // 启动第一个线程 - unsafe { __restore(context as usize) }; + unsafe { + llvm_asm!("fence.i" :::: "volatile"); + __restore(context as usize); + } unreachable!() } -fn sample_process(id: usize) { - println!("hello from kernel thread {}", id); +/// 测试缺页异常处理 +/// +/// 为了便于体现效果，只给每个线程分配了很低的可用物理页面限额，见 [`KERNEL_PROCESS_FRAME_QUOTA`] +/// +/// [`KERNEL_PROCESS_FRAME_QUOTA`]: memory::config::KERNEL_PROCESS_FRAME_QUOTA +fn test_page_fault() { + let mut array = [0usize; 32 * 1024]; + for i in 0..array.len() { + array[i] = i; + } + for i in 0..array.len() { + assert_eq!(i, array[i]); + } + println!("\x1b[32mtest passed\x1b[0m"); } /// 创建一个内核进程 diff --git a/os/src/memory/config.rs b/os/src/memory/config.rs index df4a3b3..433680a 100644 --- a/os/src/memory/config.rs +++ b/os/src/memory/config.rs @@ -2,6 +2,10 @@ use super::address::*; use lazy_static::*; +use crate::board::config::{ + BOARD_MEMORY_END_ADDRESS, + BOARD_KERNEL_HEAP_SIZE, +}; /// 页 / 帧大小，必须是 2^n pub const PAGE_SIZE: usize = 4096; @@ -14,7 +18,7 @@ pub const DEVICE_END_ADDRESS: PhysicalAddress = PhysicalAddress(0x1001_0000); /// 可以访问的内存区域起始地址 pub const MEMORY_START_ADDRESS: PhysicalAddress = PhysicalAddress(0x8000_0000); /// 可以访问的内存区域结束地址 -pub const MEMORY_END_ADDRESS: PhysicalAddress = PhysicalAddress(0x8800_0000); +pub const MEMORY_END_ADDRESS: PhysicalAddress = PhysicalAddress(BOARD_MEMORY_END_ADDRESS); lazy_static! { /// 内核代码结束的地址，即可以用来分配的内存起始地址 @@ -23,11 +27,16 @@ lazy_static! { pub static ref KERNEL_END_ADDRESS: VirtualAddress = VirtualAddress(kernel_end as usize); } /// 操作系统动态分配内存所用的堆大小（8M） -pub const KERNEL_HEAP_SIZE: usize = 0x80_0000; +pub const KERNEL_HEAP_SIZE: usize = BOARD_KERNEL_HEAP_SIZE; /// 内核使用线性映射的偏移量 pub const KERNEL_MAP_OFFSET: usize = 0xffff_ffff_0000_0000; +/// 用户进程最多使用的物理页面数量 +pub const USER_PROCESS_FRAME_QUOTA: usize = 16; +/// 内核进程最多使用的物理页面数量 +pub const KERNEL_PROCESS_FRAME_QUOTA: usize = 16; + extern "C" { /// 由 `linker.ld` 指定的内核代码结束位置 /// diff --git a/os/src/memory/heap.rs b/os/src/memory/heap.rs index 46177d5..cf3e4d3 100644 --- a/os/src/memory/heap.rs +++ b/os/src/memory/heap.rs @@ -9,7 +9,9 @@ use buddy_system_allocator::LockedHeap; /// /// 大小为 [`KERNEL_HEAP_SIZE`] /// 这段空间编译后会被放在操作系统执行程序的 bss 段 -static mut HEAP_SPACE: [u8; KERNEL_HEAP_SIZE] = [0; KERNEL_HEAP_SIZE]; +#[repr(align(4096))] +pub struct HeapSpace(pub [u8; KERNEL_HEAP_SIZE]); +pub static mut HEAP_SPACE: HeapSpace = HeapSpace([0; KERNEL_HEAP_SIZE]); /// 堆，动态内存分配器 /// @@ -24,12 +26,12 @@ pub fn init() { // 告诉分配器使用这一段预留的空间作为堆 unsafe { HEAP.lock() - .init(HEAP_SPACE.as_ptr() as usize, KERNEL_HEAP_SIZE) + .init(HEAP_SPACE.0.as_ptr() as usize, KERNEL_HEAP_SIZE) } } /// 空间分配错误的回调，直接 panic 退出 #[alloc_error_handler] -fn alloc_error_handler(_: alloc::alloc::Layout) -> ! { - panic!("alloc error") +fn alloc_error_handler(layout: alloc::alloc::Layout) -> ! { + panic!("alloc error, layout = {:?}", layout) } diff --git a/os/src/memory/mapping/mapping.rs b/os/src/memory/mapping/mapping.rs index 4363a50..90297b0 100644 --- a/os/src/memory/mapping/mapping.rs +++ b/os/src/memory/mapping/mapping.rs @@ -3,18 +3,20 @@ //! 许多方法返回 [`Result`]，如果出现错误会返回 `Err(message)`。设计目标是，此时如果终止线程，则不会产生后续问题。 //! 但是如果错误是由操作系统代码逻辑产生的，则会直接 panic。 +use crate::fs::SwapTracker; use crate::memory::{ address::*, config::PAGE_SIZE, - frame::{FrameTracker, FRAME_ALLOCATOR}, - mapping::{Flags, MapType, PageTable, PageTableEntry, PageTableTracker, Segment}, + frame::FRAME_ALLOCATOR, + mapping::{ + Flags, MapType, PageTable, PageTableEntry, PageTableTracker, Segment, Swapper, SwapperImpl, + }, MemoryResult, }; -use alloc::{collections::VecDeque, vec, vec::Vec}; -use core::cmp::min; -use core::ptr::slice_from_raw_parts_mut; +use alloc::{vec, vec::Vec}; +use core::{cmp::min, ptr::slice_from_raw_parts_mut}; +use hashbrown::HashMap; -#[derive(Default)] /// 某个线程的内存映射关系 pub struct Mapping { /// 保存所有使用到的页表 @@ -22,7 +24,9 @@ pub struct Mapping { /// 根页表的物理页号 root_ppn: PhysicalPageNumber, /// 所有分配的物理页面映射信息 - mapped_pairs: VecDeque<(VirtualPageNumber, FrameTracker)>, + mapped_pairs: SwapperImpl, + /// 被换出的页面存储在虚拟内存文件中的 Tracker + swapped_pages: HashMap, } impl Mapping { @@ -39,13 +43,14 @@ impl Mapping { } /// 创建一个有根节点的映射 - pub fn new() -> MemoryResult { + pub fn new(frame_quota: usize) -> MemoryResult { let root_table = PageTableTracker::new(FRAME_ALLOCATOR.lock().alloc()?); let root_ppn = root_table.page_number(); Ok(Mapping { page_tables: vec![root_table], root_ppn, - mapped_pairs: VecDeque::new(), + mapped_pairs: SwapperImpl::new(frame_quota), + swapped_pages: HashMap::new(), }) } @@ -57,7 +62,7 @@ impl Mapping { // 线性映射，直接对虚拟地址进行转换 MapType::Linear => { for vpn in segment.page_range().iter() { - self.map_one(vpn, Some(vpn.into()), segment.flags | Flags::VALID)?; + self.map_one(vpn, Some(vpn.into()), segment.flags)?; } // 拷贝数据 if let Some(data) = init_data { @@ -67,44 +72,66 @@ impl Mapping { } } } + MapType::Device => { + for vpn in segment.page_range().iter() { + self.map_one(vpn, Some(PhysicalPageNumber(vpn.0)), segment.flags | Flags::VALID)?; + } + } // 需要分配帧进行映射 MapType::Framed => { for vpn in segment.page_range().iter() { - // 页面的数据，默认为全零 - let mut page_data = [0u8; PAGE_SIZE]; - // 如果提供了数据，则使用这些数据来填充 page_data - if let Some(init_data) = init_data { - if !init_data.is_empty() { - // 这里必须进行一些调整，因为传入的数据可能并非按照整页对齐 - - // 拷贝时必须考虑区间与整页不对齐的情况 - // start（仅第一页时非零） - // | stop（仅最后一页时非零） - // 0 |---data---| 4096 - // |------------page------------| - let page_address = VirtualAddress::from(vpn); - let start = if segment.range.start > page_address { - segment.range.start - page_address - } else { - 0 - }; - let stop = min(PAGE_SIZE, segment.range.end - page_address); - // 计算来源和目标区间并进行拷贝 - let dst_slice = &mut page_data[start..stop]; - let src_slice = &init_data[(page_address + start - segment.range.start) - ..(page_address + stop - segment.range.start)]; - dst_slice.copy_from_slice(src_slice); - } + // 如果有初始化数据，找到相应的数据 + let page_data = if init_data.is_none() || init_data.unwrap().is_empty() { + [0u8; PAGE_SIZE] + } else { + // 这里必须进行一些调整，因为传入的数据可能并非按照整页对齐 + + // 传入的初始化数据 + let init_data = init_data.unwrap(); + // 整理后将要返回的一整个页面的数据 + let mut page_data = [0u8; PAGE_SIZE]; + + // 拷贝时必须考虑区间与整页不对齐的情况 + // start（仅第一页时非零） + // | stop（仅最后一页时非零） + // 0 |---data---| 4096 + // |------------page------------| + let page_address = VirtualAddress::from(vpn); + let start = if segment.range.start > page_address { + segment.range.start - page_address + } else { + 0 + }; + let stop = min(PAGE_SIZE, segment.range.end - page_address); + // 计算来源和目标区间并进行拷贝 + let dst_slice = &mut page_data[start..stop]; + let src_slice = &init_data[(page_address + start - segment.range.start) + ..(page_address + stop - segment.range.start)]; + dst_slice.copy_from_slice(src_slice); + + page_data }; - // 建立映射 - let mut frame = FRAME_ALLOCATOR.lock().alloc()?; - // 更新页表 - self.map_one(vpn, Some(frame.page_number()), segment.flags)?; - // 写入数据 - (*frame).copy_from_slice(&page_data); - // 保存 - self.mapped_pairs.push_back((vpn, frame)); + // 建立映射，先检查是否有配额来分配新的物理页面 + if !self.mapped_pairs.full() { + // 有配额，分配新的物理页面 + let mut frame = FRAME_ALLOCATOR.lock().alloc()?; + // 更新页表 + let entry = self.map_one(vpn, Some(frame.page_number()), segment.flags)?; + // 写入数据 + (*frame).copy_from_slice(&page_data); + // 保存 + self.mapped_pairs.push(vpn, frame, entry); + } else { + // 配额用完，改为在置换文件中分配一个页面 + let swap_page = SwapTracker::new()?; + // 更新页表 + self.map_one(vpn, None, segment.flags)?; + // 写入数据 + swap_page.write(&page_data); + // 保存 + self.swapped_pages.insert(vpn, swap_page); + } } } } @@ -119,9 +146,10 @@ impl Mapping { // 从页表中清除项 entry.clear(); } - // 移除相应的页面 self.mapped_pairs - .retain(|(vpn, _)| !segment.page_range().contains(*vpn)) + .retain(|vpn| !segment.page_range().contains(*vpn)); + self.swapped_pages + .retain(|vpn, _| !segment.page_range().contains(*vpn)); } /// 找到给定虚拟页号的三级页表项 @@ -185,12 +213,70 @@ impl Mapping { vpn: VirtualPageNumber, ppn: Option, flags: Flags, - ) -> MemoryResult<()> { + ) -> MemoryResult<*mut PageTableEntry> { // 定位到页表项 let entry = self.find_entry(vpn)?; assert!(entry.is_empty(), "virtual address is already mapped"); // 页表项为空，则写入内容 *entry = PageTableEntry::new(ppn, flags); + Ok(entry) + } + + /// 移除一个虚拟地址的映射 + fn invalidate_one(&mut self, vpn: VirtualPageNumber) -> MemoryResult<()> { + let entry = self.find_entry(vpn).expect("swapping out unmapped address"); + assert!(entry.is_valid()); + entry.update_page_number(None); + Ok(()) + } + + /// 为指定的虚拟页号设置新的物理页面映射，要求虚拟页号在页表中但无现有映射 + fn remap_one( + &mut self, + vpn: VirtualPageNumber, + ppn: PhysicalPageNumber, + ) -> MemoryResult<*mut PageTableEntry> { + let entry = self.find_entry(vpn)?; + assert!(!entry.is_empty() && !entry.is_valid()); + // 设置页表项的物理页号和 Valid 标志 + entry.update_page_number(Some(ppn)); + Ok(entry) + } + + /// 处理缺页异常 + pub fn handle_page_fault(&mut self, stval: usize) -> MemoryResult<()> { + // 发生异常的访问页面 + let vpn = VirtualPageNumber::floor(stval.into()); + // 该页面如果在进程的内存中，则应该在 Swap 中，将其取出 + let swap_tracker: SwapTracker = self + .swapped_pages + .remove(&vpn) + .ok_or("stval page is not mapped")?; + // 读取该页面的数据 + let page_data = swap_tracker.read(); + + if self.mapped_pairs.full() { + // 取出一个映射 + let (popped_vpn, mut popped_frame) = self.mapped_pairs.pop().unwrap(); + // 交换数据 + swap_tracker.write(&*popped_frame); + (*popped_frame).copy_from_slice(&page_data); + // 修改页表映射 + self.invalidate_one(popped_vpn)?; + let entry = self.remap_one(vpn, popped_frame.page_number())?; + // 更新记录 + self.mapped_pairs.push(vpn, popped_frame, entry); + self.swapped_pages.insert(popped_vpn, swap_tracker); + } else { + // 添加新的映射 + let mut frame = FRAME_ALLOCATOR.lock().alloc()?; + // 复制数据 + (*frame).copy_from_slice(&page_data); + // 更新映射 + let entry = self.remap_one(vpn, frame.page_number())?; + // 更新记录 + self.mapped_pairs.push(vpn, frame, entry); + } Ok(()) } } diff --git a/os/src/memory/mapping/memory_set.rs b/os/src/memory/mapping/memory_set.rs index 86a5a03..52b0986 100644 --- a/os/src/memory/mapping/memory_set.rs +++ b/os/src/memory/mapping/memory_set.rs @@ -1,6 +1,6 @@ //! 一个线程中关于内存空间的所有信息 [`MemorySet`] -//! +use crate::board::config::MMIO_INTERVALS; use crate::memory::{ address::*, config::*, @@ -34,7 +34,7 @@ impl MemorySet { } // 建立字段 - let segments = vec![ + let mut segments = vec![ // DEVICE 段，rw- Segment { map_type: MapType::Linear, @@ -72,10 +72,21 @@ impl MemorySet { flags: Flags::READABLE | Flags::WRITABLE, }, ]; - let mut mapping = Mapping::new()?; + for mmio_pair in MMIO_INTERVALS.iter() { + segments.push( + Segment { + map_type: MapType::Device, + range: Range::from(VirtualAddress(mmio_pair.0)..VirtualAddress(mmio_pair.0 + mmio_pair.1)), + flags: Flags::READABLE | Flags::WRITABLE, + } + ); + } + + let mut mapping = Mapping::new(KERNEL_PROCESS_FRAME_QUOTA)?; // 每个字段在页表中进行映射 for segment in segments.iter() { + // 同时将新分配的映射关系保存到 allocated_pairs 中 mapping.map(segment, None)?; } Ok(MemorySet { mapping, segments }) diff --git a/os/src/memory/mapping/mod.rs b/os/src/memory/mapping/mod.rs index d48cc33..f815bb1 100644 --- a/os/src/memory/mapping/mod.rs +++ b/os/src/memory/mapping/mod.rs @@ -9,9 +9,11 @@ mod memory_set; mod page_table; mod page_table_entry; mod segment; +mod swapper; pub use mapping::Mapping; pub use memory_set::MemorySet; pub use page_table::{PageTable, PageTableTracker}; pub use page_table_entry::{Flags, PageTableEntry}; pub use segment::{MapType, Segment}; +pub use swapper::{Swapper, SwapperImpl}; diff --git a/os/src/memory/mapping/page_table_entry.rs b/os/src/memory/mapping/page_table_entry.rs index ded26b5..61c45d3 100644 --- a/os/src/memory/mapping/page_table_entry.rs +++ b/os/src/memory/mapping/page_table_entry.rs @@ -60,6 +60,10 @@ impl PageTableEntry { pub fn address(&self) -> PhysicalAddress { PhysicalAddress::from(self.page_number()) } + /// 设置标志位 + pub fn set_flags(&mut self, flags: Flags) { + self.0.set_bits(FLAG_RANGE, flags.bits() as usize); + } /// 获取标志位 pub fn flags(&self) -> Flags { unsafe { Flags::from_bits_unchecked(self.0.get_bits(..8) as u8) } @@ -68,12 +72,15 @@ impl PageTableEntry { pub fn is_empty(&self) -> bool { self.0 == 0 } + /// 是否为 Valid + pub fn is_valid(&self) -> bool { + self.flags().contains(Flags::VALID) + } /// 是否指向下一级（RWX 全为0） pub fn has_next_level(&self) -> bool { - let flags = self.flags(); - !(flags.contains(Flags::READABLE) - || flags.contains(Flags::WRITABLE) - || flags.contains(Flags::EXECUTABLE)) + !self + .flags() + .intersects(Flags::READABLE | Flags::WRITABLE | Flags::EXECUTABLE) } } diff --git a/os/src/memory/mapping/segment.rs b/os/src/memory/mapping/segment.rs index ec60eed..769dbde 100644 --- a/os/src/memory/mapping/segment.rs +++ b/os/src/memory/mapping/segment.rs @@ -9,6 +9,7 @@ pub enum MapType { Linear, /// 按帧分配映射 Framed, + Device, } /// 一个映射片段（对应旧 tutorial 的 `MemoryArea`） @@ -30,6 +31,7 @@ impl Segment { MapType::Linear => Some(self.page_range().into().iter()), // 按帧映射无法直接获得物理地址，需要分配 MapType::Framed => None, + MapType::Device => None, } } diff --git a/os/src/memory/mapping/swapper.rs b/os/src/memory/mapping/swapper.rs new file mode 100644 index 0000000..0fdfff7 --- /dev/null +++ b/os/src/memory/mapping/swapper.rs @@ -0,0 +1,54 @@ +//! 页面置换算法 + +use super::*; +use crate::memory::{frame::FrameTracker, *}; +use alloc::collections::VecDeque; + +/// 管理一个线程所映射的页面的置换操作 +pub trait Swapper { + /// 新建带有一个分配数量上限的置换器 + fn new(quota: usize) -> Self; + + /// 是否已达到上限 + fn full(&self) -> bool; + + /// 取出一组映射 + fn pop(&mut self) -> Option<(VirtualPageNumber, FrameTracker)>; + + /// 添加一组映射（不会在以达到分配上限时调用） + fn push(&mut self, vpn: VirtualPageNumber, frame: FrameTracker, entry: *mut PageTableEntry); + + /// 只保留符合某种条件的条目（用于移除一段虚拟地址） + fn retain(&mut self, predicate: impl Fn(&VirtualPageNumber) -> bool); +} + +pub type SwapperImpl = FIFOSwapper; + +/// 页面置换算法基础实现：FIFO +pub struct FIFOSwapper { + /// 记录映射和添加的顺序 + queue: VecDeque<(VirtualPageNumber, FrameTracker)>, + /// 映射数量上限 + quota: usize, +} + +impl Swapper for FIFOSwapper { + fn new(quota: usize) -> Self { + Self { + queue: VecDeque::new(), + quota, + } + } + fn full(&self) -> bool { + self.queue.len() == self.quota + } + fn pop(&mut self) -> Option<(VirtualPageNumber, FrameTracker)> { + self.queue.pop_front() + } + fn push(&mut self, vpn: VirtualPageNumber, frame: FrameTracker, _entry: *mut PageTableEntry) { + self.queue.push_back((vpn, frame)); + } + fn retain(&mut self, predicate: impl Fn(&VirtualPageNumber) -> bool) { + self.queue.retain(|(vpn, _)| predicate(vpn)); + } +} diff --git a/os/src/memory/mod.rs b/os/src/memory/mod.rs index 247b584..9e528bd 100644 --- a/os/src/memory/mod.rs +++ b/os/src/memory/mod.rs @@ -6,6 +6,8 @@ // 所以在模块范围内不提示「未使用的函数」等警告 #![allow(dead_code)] +use crate::board::config::RISCV_SPEC_MINOR; + pub mod address; pub mod config; pub mod frame; @@ -30,7 +32,29 @@ pub use { pub fn init() { heap::init(); // 允许内核读写用户态内存 - unsafe { riscv::register::sstatus::set_sum() }; + if RISCV_SPEC_MINOR >= 10 { + println!("riscv spec version >= 1.10!"); + unsafe { riscv::register::sstatus::set_sum() }; + } println!("mod memory initialized"); } + +pub fn clear_bss() { + extern "C" { + fn sbss_clear(); + fn ebss_clear(); + } + let bss_start = sbss_clear as usize; + let bss_end = ebss_clear as usize; + let bss_aligned = bss_end - bss_end % 8; + // clear bss section + (bss_start..bss_end).step_by(8).for_each(|p| { + unsafe { (p as *mut u64).write_volatile(0) } + }); + if bss_aligned < bss_end { + (bss_aligned..bss_end).step_by(1).for_each(|p| { + unsafe { (p as *mut u8).write_volatile(0) } + }); + } +} diff --git a/os/src/process/config.rs b/os/src/process/config.rs index ea33b1d..c744857 100644 --- a/os/src/process/config.rs +++ b/os/src/process/config.rs @@ -1,7 +1,12 @@ //! 定义一些进程相关的常量 +use crate::board::config::{ + BOARD_STACK_SIZE, + BOARD_KERNEL_STACK_SIZE, +}; + /// 每个线程的运行栈大小 512 KB -pub const STACK_SIZE: usize = 0x8_0000; +pub const STACK_SIZE: usize = BOARD_STACK_SIZE; /// 共用的内核栈大小 512 KB -pub const KERNEL_STACK_SIZE: usize = 0x8_0000; +pub const KERNEL_STACK_SIZE: usize = BOARD_KERNEL_STACK_SIZE; diff --git a/tools/k210-hal/CODE_OF_CONDUCT.md b/tools/k210-hal/CODE_OF_CONDUCT.md new file mode 100644 index 0000000..fccadf9 --- /dev/null +++ b/tools/k210-hal/CODE_OF_CONDUCT.md @@ -0,0 +1,37 @@ +# The Rust Code of Conduct + +## Conduct + +**Contact**: [RISC-V team](https://github.com/rust-embedded/wg#the-riscv-team) + +* We are committed to providing a friendly, safe and welcoming environment for all, regardless of level of experience, gender identity and expression, sexual orientation, disability, personal appearance, body size, race, ethnicity, age, religion, nationality, or other similar characteristic. +* On IRC, please avoid using overtly sexual nicknames or other nicknames that might detract from a friendly, safe and welcoming environment for all. +* Please be kind and courteous. There's no need to be mean or rude. +* Respect that people have differences of opinion and that every design or implementation choice carries a trade-off and numerous costs. There is seldom a right answer. +* Please keep unstructured critique to a minimum. If you have solid ideas you want to experiment with, make a fork and see how it works. +* We will exclude you from interaction if you insult, demean or harass anyone. That is not welcome behavior. We interpret the term "harassment" as including the definition in the [Citizen Code of Conduct](http://citizencodeofconduct.org/); if you have any lack of clarity about what might be included in that concept, please read their definition. In particular, we don't tolerate behavior that excludes people in socially marginalized groups. +* Private harassment is also unacceptable. No matter who you are, if you feel you have been or are being harassed or made uncomfortable by a community member, please contact one of the channel ops or any of the [RISC-V team][team] immediately. Whether you're a regular contributor or a newcomer, we care about making this community a safe place for you and we've got your back. +* Likewise any spamming, trolling, flaming, baiting or other attention-stealing behavior is not welcome. + +## Moderation + +These are the policies for upholding our community's standards of conduct. + +1. Remarks that violate the Rust standards of conduct, including hateful, hurtful, oppressive, or exclusionary remarks, are not allowed. (Cursing is allowed, but never targeting another user, and never in a hateful manner.) +2. Remarks that moderators find inappropriate, whether listed in the code of conduct or not, are also not allowed. +3. Moderators will first respond to such remarks with a warning. +4. If the warning is unheeded, the user will be "kicked," i.e., kicked out of the communication channel to cool off. +5. If the user comes back and continues to make trouble, they will be banned, i.e., indefinitely excluded. +6. Moderators may choose at their discretion to un-ban the user if it was a first offense and they offer the offended party a genuine apology. +7. If a moderator bans someone and you think it was unjustified, please take it up with that moderator, or with a different moderator, **in private**. Complaints about bans in-channel are not allowed. +8. Moderators are held to a higher standard than other community members. If a moderator creates an inappropriate situation, they should expect less leeway than others. + +In the Rust community we strive to go the extra step to look out for each other. Don't just aim to be technically unimpeachable, try to be your best self. In particular, avoid flirting with offensive or sensitive issues, particularly if they're off-topic; this all too often leads to unnecessary fights, hurt feelings, and damaged trust; worse, it can drive people away from the community entirely. + +And if someone takes issue with something you said or did, resist the urge to be defensive. Just stop doing what it was they complained about and apologize. Even if you feel you were misinterpreted or unfairly accused, chances are good there was something you could've communicated better — remember that it's your responsibility to make your fellow Rustaceans comfortable. Everyone wants to get along and we are all here first and foremost because we want to talk about cool technology. You will find that people will be eager to assume good intent and forgive as long as you earn their trust. + +The enforcement policies listed above apply to all official embedded WG venues; including official IRC channels (#rust-embedded); GitHub repositories under rust-embedded; and all forums under rust-embedded.org (forum.rust-embedded.org). + +*Adapted from the [Node.js Policy on Trolling](http://blog.izs.me/post/30036893703/policy-on-trolling) as well as the [Contributor Covenant v1.3.0](https://www.contributor-covenant.org/version/1/3/0/).* + +[team]: https://github.com/rust-embedded/wg#the-riscv-team diff --git a/tools/k210-hal/Cargo.toml b/tools/k210-hal/Cargo.toml new file mode 100644 index 0000000..05deb89 --- /dev/null +++ b/tools/k210-hal/Cargo.toml @@ -0,0 +1,19 @@ +[package] +name = "k210-hal" +version = "0.2.0" +authors = ["The RISC-V Team "] +categories = ["embedded", "hardware-support", "no-std"] +description = "Hardware Abstract Layer (HAL) support for K210, dual-core RV64GC SoC" +repository = "https://github.com/riscv-rust/k210-hal" +keywords = ["riscv", "k210", "hal"] +license = "ISC" +edition = "2018" + +[package.metadata.docs.rs] +targets = ["riscv64gc-unknown-none-elf"] + +[dependencies] +embedded-hal = "1.0.0-alpha.1" +nb = "0.1.1" +k210-pac = { path = "../k210-pac" } +bitflags = "1.2.1" diff --git a/tools/k210-hal/README.md b/tools/k210-hal/README.md new file mode 100644 index 0000000..a56269f --- /dev/null +++ b/tools/k210-hal/README.md @@ -0,0 +1,37 @@ +[![crates.io](https://img.shields.io/crates/d/k210-hal.svg)](https://crates.io/crates/k210-hal) +[![crates.io](https://img.shields.io/crates/v/k210-hal.svg)](https://crates.io/crates/k210-hal) +[![Build Status](https://travis-ci.org/riscv-rust/k210-hal.svg?branch=master)](https://travis-ci.org/riscv-rust/k210-hal) + +# `k210-hal` + +> Hardware abstract layer (HAL) for K210 chip, a dual RV64GC SoC with hardware +> accelerated AI peripherals. + +This project is developed and maintained by the [RISC-V team][team]. + +## [Documentation](https://docs.rs/k210-hal) + +## License + +Copyright 2019 [RISC-V team][team] + +Permission to use, copy, modify, and/or distribute this software for any +purpose with or without fee is hereby granted, provided that the above +copyright notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +## Code of Conduct + +Contribution to this crate is organized under the terms of the [Rust Code of +Conduct][CoC], the maintainer of this crate, the [RISC-V team][team], promises +to intervene to uphold that code of conduct. + +[CoC]: CODE_OF_CONDUCT.md +[team]: https://github.com/rust-embedded/wg#the-risc-v-team diff --git a/tools/k210-hal/src/aes.rs b/tools/k210-hal/src/aes.rs new file mode 100644 index 0000000..f5c8f6f --- /dev/null +++ b/tools/k210-hal/src/aes.rs @@ -0,0 +1,79 @@ +//! (TODO) Hardware AES calculator (AES) +use core::marker::PhantomData; +use crate::pac::AES; + +pub struct Aes { + aes: AES, + _mode: PhantomData, + _klen: PhantomData, +} + +pub struct Ecb; + +pub struct Cbc; + +pub struct Gcm; + +pub struct K128; + +pub struct K192; + +pub struct K256; + +#[allow(unused)] // todo: remove +impl Aes { + pub fn ecb128(aes: AES) -> Aes { + todo!() + } + + pub fn ecb192(aes: AES) -> Aes { + todo!() + } + + pub fn ecb256(aes: AES) -> Aes { + todo!() + } + + pub fn cbc128(aes: AES) -> Aes { + todo!() + } + + pub fn cbc192(aes: AES) -> Aes { + todo!() + } + + pub fn cbc256(aes: AES) -> Aes { + todo!() + } + + pub fn gcm128(aes: AES) -> Aes { + todo!() + } + + pub fn gcm192(aes: AES) -> Aes { + todo!() + } + + pub fn gcm256(aes: AES) -> Aes { + todo!() + } +} + +impl Aes { + // todo: clock + pub fn free(self) -> AES { + self.aes + } +} + +#[allow(unused)] // todo: remove +impl Aes { + // entrypt block in-place + pub fn encrypt_block(&self, block: &mut [u8], key: &[u8]) { + todo!() + } + // decrypt block in-place + pub fn decrypt_block(&self, block: &mut [u8], key: &[u8]) { + todo!() + } +} diff --git a/tools/k210-hal/src/apu.rs b/tools/k210-hal/src/apu.rs new file mode 100644 index 0000000..8f20054 --- /dev/null +++ b/tools/k210-hal/src/apu.rs @@ -0,0 +1 @@ +//! (TODO) Audio Processor Unit (APU) diff --git a/tools/k210-hal/src/cache.rs b/tools/k210-hal/src/cache.rs new file mode 100644 index 0000000..aad8218 --- /dev/null +++ b/tools/k210-hal/src/cache.rs @@ -0,0 +1,117 @@ +//! (TODO) Bypass cache +//! +//! Todo: verify this module! + +use core::slice; +use core::str; + +/// Convert a buffer or a pointer into ones with uncached address. +/// +/// Section 3.4.1, Kendryte K210 Datasheet +pub fn uncached(buf: T) -> T { + buf.uncache() +} + +/// Uncacheable buffer or pointer. +pub trait Uncache { + /// Convert this buffer or pointer to uncached addressed ones + fn uncache(self) -> Self; +} + +impl Uncache for &T { + #[inline] + fn uncache(self) -> Self { + let addr = self as *const T as usize; + assert_addr_cached(addr); + // note(unsafe): safe for source address is safe + unsafe { &*((addr - 0x4000_0000) as *const T) } + } +} + +impl Uncache for &mut T { + #[inline] + fn uncache(self) -> Self { + let addr = self as *mut T as usize; + assert_addr_cached(addr); + // note(unsafe): safe for source address is safe + unsafe { &mut *((addr - 0x4000_0000) as *mut T) } + } +} + +impl Uncache for &[T] { + #[inline] + fn uncache(self) -> Self { + let addr = self.as_ptr() as usize; + assert_addr_cached(addr); + let new_ptr = (addr - 0x4000_0000) as *const T; + // note(unsafe): source address is safe; passing ownership + unsafe { slice::from_raw_parts(new_ptr, self.len()) } + } +} + +impl Uncache for &mut [T] { + #[inline] + fn uncache(self) -> Self { + let addr = self.as_ptr() as usize; + assert_addr_cached(addr); + let new_ptr = (addr - 0x4000_0000) as *mut T; + // note(unsafe): source address is safe; passing ownership + unsafe { slice::from_raw_parts_mut(new_ptr, self.len()) } + } +} + +impl Uncache for &str { + #[inline] + fn uncache(self) -> Self { + let addr = self.as_ptr() as usize; + assert_addr_cached(addr); + let new_ptr = (addr - 0x4000_0000) as *const u8; + // note(unsafe): source address is safe; passing ownership + let slice = unsafe { slice::from_raw_parts(new_ptr, self.len()) }; + // note(unsafe): source slice is guaranteed valid in UTF-8 + unsafe { str::from_utf8_unchecked(slice) } + } +} + +impl Uncache for &mut str { + #[inline] + fn uncache(self) -> Self { + let addr = self.as_ptr() as usize; + assert_addr_cached(addr); + let new_ptr = (addr - 0x4000_0000) as *mut u8; + // note(unsafe): source address is safe; passing ownership + let slice = unsafe { slice::from_raw_parts_mut(new_ptr, self.len()) }; + // note(unsafe): source slice is guaranteed valid in UTF-8 + unsafe { str::from_utf8_unchecked_mut(slice) } + } +} + +impl Uncache for *const T { + #[inline] + fn uncache(self) -> Self { + assert_addr_cached(self as usize); + (self as usize - 0x4000_0000) as *const T + } +} + +impl Uncache for *mut T { + #[inline] + fn uncache(self) -> Self { + assert_addr_cached(self as usize); + (self as usize - 0x4000_0000) as *mut T + } +} + +#[inline] +fn assert_addr_cached(addr: usize) { + /* + SRAM memory: 0x8000_0000 to 0x805F_FFFF + AI memory: 0x8060_0000 to 0x807F_FFFF + SRAM memory includes two parts: MEM0 and MEM1 + MEM0 memory: 0x8000_0000 to 0x803F_FFFF + MEM1 memory: 0x8040_0000 to 0x805F_FFFF + */ + // assure that memory is within SRAM or AI + // todo: should we exclude AI? + assert!(addr <= 0x807F_FFFF && addr >= 0x8000_0000); +} diff --git a/tools/k210-hal/src/clint.rs b/tools/k210-hal/src/clint.rs new file mode 100644 index 0000000..6f4bbec --- /dev/null +++ b/tools/k210-hal/src/clint.rs @@ -0,0 +1,49 @@ +//! Core Local Interruptor (CLINT) +//! +//! TODO: Should this module designed in a somehow IP-core peripheral create? + +/// mtime register +pub mod mtime { + use crate::pac; + /// Read mtime register. + pub fn read() -> u64 { + unsafe { (*pac::CLINT::ptr()).mtime.read().bits() } + } +} + +/// msip register +pub mod msip { + use crate::pac; + + /// set IPI interrupt flag for one given hart + pub fn set_ipi(hart_id: usize) { + unsafe { + (*pac::CLINT::ptr()).msip[hart_id].write(|w| + w.bits(1)) + } + } + /// clear IPI interrupt flag for one given hart + pub fn clear_ipi(hart_id: usize) { + unsafe { + (*pac::CLINT::ptr()).msip[hart_id].write(|w| + w.bits(0)) + } + } +} + +/// mtimecmp register +pub mod mtimecmp { + use crate::pac; + + /// Read 64-bit mtimecmp register for certain hart id + pub fn read(hart_id: usize) -> u64 { + unsafe { (*pac::CLINT::ptr()).mtimecmp[hart_id].read().bits() } + } + + /// Write 64-bit mtimecmp register for certain hart id + pub fn write(hart_id: usize, bits: u64) { + // Volume II: RISC-V Privileged Architectures V1.10 p.31, figure 3.15 + unsafe { (*pac::CLINT::ptr()).mtimecmp[hart_id].write(|w| + w.bits(bits)) }; + } +} diff --git a/tools/k210-hal/src/clock.rs b/tools/k210-hal/src/clock.rs new file mode 100644 index 0000000..2798756 --- /dev/null +++ b/tools/k210-hal/src/clock.rs @@ -0,0 +1,42 @@ +//! Clock configuration +//use crate::pac::PRCI; +use crate::time::Hertz; + +/// Frozen clock frequencies +/// +/// The existence of this value indicates that the clock configuration can no +/// longer be changed. +#[derive(Clone, Copy)] +pub struct Clocks { + cpu: Hertz, + apb0: Hertz, +} + +impl Clocks { + #[doc(hidden)] + pub fn new() -> Self { +/* + [MAIXPY]Pll0:freq:806000000 + [MAIXPY]Pll1:freq:398666666 + [MAIXPY]Pll2:freq:45066666 + [MAIXPY]cpu:freq:403000000 + [MAIXPY]kpu:freq:398666666 + in freq: 26000000 + cpu_freq: 390000000 +*/ + Self { + cpu: Hertz(403_000_000), + apb0: Hertz(195_000_000), + } + } + + /// Returns CPU frequency + pub fn cpu(&self) -> Hertz { + Hertz(self.cpu.0) + } + + /// Returns APB0 frequency + pub fn apb0(&self) -> Hertz { + self.apb0 + } +} diff --git a/tools/k210-hal/src/dmac.rs b/tools/k210-hal/src/dmac.rs new file mode 100644 index 0000000..12811be --- /dev/null +++ b/tools/k210-hal/src/dmac.rs @@ -0,0 +1,34 @@ +//! (TODO) Direct Memory Access Controller (DMAC) +use crate::{pac, sysctl}; + +pub fn dmac_id() -> u64 { + unsafe { (*pac::DMAC::ptr()).id.read().bits() } +} + +pub fn dmac_version() -> u64 { + unsafe { (*pac::DMAC::ptr()).compver.read().bits() } +} + +pub trait DmacExt { + fn configure(self, /* sysctl ACLK clock */) -> Dmac; +} + +impl DmacExt for pac::DMAC { + fn configure(self, /* sysctl ACLK clock */) -> Dmac { + // enable + sysctl::clk_en_peri().modify(|_, w| w.dma_clk_en().set_bit()); + // todo: reset + Dmac {} // todo + } +} + +pub struct Dmac { + +} + +// pub struct C0 { +// // todo +// pub async fn poll() { + +// } +// } diff --git a/tools/k210-hal/src/fft.rs b/tools/k210-hal/src/fft.rs new file mode 100644 index 0000000..daa1d0d --- /dev/null +++ b/tools/k210-hal/src/fft.rs @@ -0,0 +1 @@ +//! (TODO) Fast Fourier Transform (FFT) diff --git a/tools/k210-hal/src/fpioa.rs b/tools/k210-hal/src/fpioa.rs new file mode 100644 index 0000000..e181944 --- /dev/null +++ b/tools/k210-hal/src/fpioa.rs @@ -0,0 +1,486 @@ +//! Field Programmable IO Array (FPIOA) + +/* + new design: Split FPIOA into several IO pins (IO0, IO1, .., IO47) + with ownership of IOx struct we may change their functions. + For GPIOs and GPIOHS's we should split them into another GpioXx structs. + + note: other modules do not need to require for ownership of certain IOx struct + for that pins and peripherals are considered separate modules. + If this design results in inconvenience or violent of Rust's ownership role + please fire an issue to tell us. +*/ + +use crate::pac::FPIOA; +use crate::sysctl::{self, APB0}; +use core::marker::PhantomData; + +/// FPIOA function +pub trait Function { + const INDEX: u8; +} + +/// Pull direction +#[derive(Copy, Clone)] +pub enum Pull { + /// No pulls + None, + /// Pull down + Down, + /// Pull up + Up, +} + +/// FPIOA I/O Pin +pub trait IoPin { + const INDEX: u8; + + fn set_io_pull(&mut self, pull: Pull) { + unsafe { + let fpioa = &*FPIOA::ptr(); + fpioa.io[Self::INDEX as usize].modify(|_, w| match pull { + Pull::None => w.pu().bit(false).pd().bit(false), + Pull::Down => w.pu().bit(false).pd().bit(true), + Pull::Up => w.pu().bit(true).pd().bit(false), + }); + } + } +} + +/// Marker trait for I/O pin function detection +pub trait Mode {} + +/// Extension trait to split a FPIOA peripheral in independent pins and registers +pub trait FpioaExt { + /// Splits the FPIOA block into independent pins and registers + /// + /// todo: split sysctl into two apb's, then use the APB0 to split Fpioa + fn split(self, apb0: &mut APB0) -> Parts; +} + +/// All I/O pins +macro_rules! def_io_pin { + ($($IoX: ident: ($id: expr, $iox: ident, $func: ident);)+) => { +impl FpioaExt for FPIOA { + fn split(self, apb0: &mut APB0) -> Parts { + // enable APB0 bus + apb0.enable(); + // enable sysctl peripheral + sysctl::clk_en_peri().modify(|_r, w| w.fpioa_clk_en().set_bit()); + // return ownership + Parts { + $( $iox: $IoX { _function: PhantomData }, )+ + } + } +} +/// FPIOA Parts +pub struct Parts { + $( + /// Programmable I/O pin + pub $iox: $IoX<$func>, + )+ + // todo: tie controller Tie (force set high or low as input) +} +pub use io_pins::*; +/// All I/O pins +pub mod io_pins { + use core::marker::PhantomData; + use super::{Function, IoPin, Mode, FUNCTION_DEFAULTS}; + use crate::pac::FPIOA; + +$( + /// Programmable I/O pin + pub struct $IoX { + pub(crate) _function: PhantomData + } + + impl $IoX { + /// Change the programmable I/O pin into given function + /// + /// You may refer to module [functions] for all functions. + /// + /// [functions]: ../functions/index.html + pub fn into_function(self, func: F) -> $IoX { + let _ = func; // note(discard): Zero-sized typestate value + unsafe { &(*FPIOA::ptr()).io[$id].write(|w| + w.bits(FUNCTION_DEFAULTS[F::INDEX as usize]) + ) }; + $IoX { _function: PhantomData } + } + } + impl IoPin for $IoX { + const INDEX: u8 = $id; + } + impl Mode for $IoX {} +)+ +} + }; +} + +def_io_pin! { + Io0: (0, io0, JTAG_TCLK); + Io1: (1, io1, JTAG_TDI); + Io2: (2, io2, JTAG_TMS); + Io3: (3, io3, JTAG_TDO); + Io4: (4, io4, UARTHS_RX); + Io5: (5, io5, UARTHS_TX); + Io6: (6, io6, RESV0); // (FLOAT*): no default function + Io7: (7, io7, RESV0); // (FLOAT*): no default function + Io8: (8, io8, GPIO0); + Io9: (9, io9, GPIO1); + Io10: (10, io10, GPIO2); + Io11: (11, io11, GPIO3); + Io12: (12, io12, GPIO4); + Io13: (13, io13, GPIO5); + Io14: (14, io14, GPIO6); + Io15: (15, io15, GPIO7); + Io16: (16, io16, GPIOHS0); + Io17: (17, io17, GPIOHS1); + Io18: (18, io18, GPIOHS2); + Io19: (19, io19, GPIOHS3); + Io20: (20, io20, GPIOHS4); + Io21: (21, io21, GPIOHS5); + Io22: (22, io22, GPIOHS6); + Io23: (23, io23, GPIOHS7); + Io24: (24, io24, GPIOHS8); + Io25: (25, io25, GPIOHS9); + Io26: (26, io26, GPIOHS10); + Io27: (27, io27, GPIOHS11); + Io28: (28, io28, GPIOHS12); + Io29: (29, io29, GPIOHS13); + Io30: (30, io30, GPIOHS14); + Io31: (31, io31, GPIOHS15); + Io32: (32, io32, GPIOHS16); + Io33: (33, io33, GPIOHS17); + Io34: (34, io34, GPIOHS18); + Io35: (35, io35, GPIOHS19); + Io36: (36, io36, GPIOHS20); + Io37: (37, io37, GPIOHS21); + Io38: (38, io38, GPIOHS22); + Io39: (39, io39, GPIOHS23); + Io40: (40, io40, GPIOHS24); + Io41: (41, io41, GPIOHS25); + Io42: (42, io42, GPIOHS26); + Io43: (43, io43, GPIOHS27); + Io44: (44, io44, GPIOHS28); + Io45: (45, io45, GPIOHS29); + Io46: (46, io46, GPIOHS30); + Io47: (47, io47, GPIOHS31); +} + +/** Defaults per function (from Kendryte fpioa.c) */ +#[rustfmt::skip] +static FUNCTION_DEFAULTS: &[u32] = &[ + 0x00900000, 0x00900001, 0x00900002, 0x00001f03, 0x00b03f04, 0x00b03f05, 0x00b03f06, 0x00b03f07, + 0x00b03f08, 0x00b03f09, 0x00b03f0a, 0x00b03f0b, 0x00001f0c, 0x00001f0d, 0x00001f0e, 0x00001f0f, + 0x03900010, 0x00001f11, 0x00900012, 0x00001f13, 0x00900014, 0x00900015, 0x00001f16, 0x00001f17, + 0x00901f18, 0x00901f19, 0x00901f1a, 0x00901f1b, 0x00901f1c, 0x00901f1d, 0x00901f1e, 0x00901f1f, + 0x00901f20, 0x00901f21, 0x00901f22, 0x00901f23, 0x00901f24, 0x00901f25, 0x00901f26, 0x00901f27, + 0x00901f28, 0x00901f29, 0x00901f2a, 0x00901f2b, 0x00901f2c, 0x00901f2d, 0x00901f2e, 0x00901f2f, + 0x00901f30, 0x00901f31, 0x00901f32, 0x00901f33, 0x00901f34, 0x00901f35, 0x00901f36, 0x00901f37, + 0x00901f38, 0x00901f39, 0x00901f3a, 0x00901f3b, 0x00901f3c, 0x00901f3d, 0x00901f3e, 0x00901f3f, + 0x00900040, 0x00001f41, 0x00900042, 0x00001f43, 0x00900044, 0x00001f45, 0x00b03f46, 0x00b03f47, + 0x00b03f48, 0x00b03f49, 0x00b03f4a, 0x00b03f4b, 0x00b03f4c, 0x00b03f4d, 0x00001f4e, 0x00001f4f, + 0x00001f50, 0x00001f51, 0x03900052, 0x00001f53, 0x00b03f54, 0x00900055, 0x00900056, 0x00001f57, + 0x00001f58, 0x00001f59, 0x0090005a, 0x0090005b, 0x0090005c, 0x0090005d, 0x00001f5e, 0x00001f5f, + 0x00001f60, 0x00001f61, 0x00001f62, 0x00001f63, 0x00001f64, 0x00900065, 0x00900066, 0x00900067, + 0x00900068, 0x00001f69, 0x00001f6a, 0x00001f6b, 0x00001f6c, 0x00001f6d, 0x00001f6e, 0x00001f6f, + 0x00900070, 0x00900071, 0x00900072, 0x00900073, 0x00001f74, 0x00001f75, 0x00001f76, 0x00001f77, + 0x00000078, 0x00000079, 0x0000007a, 0x0000007b, 0x0000007c, 0x0000007d, 0x0099107e, 0x0099107f, + 0x00991080, 0x00991081, 0x00991082, 0x00991083, 0x00001f84, 0x00001f85, 0x00001f86, 0x00900087, + 0x00900088, 0x00900089, 0x0090008a, 0x0090008b, 0x0090008c, 0x0090008d, 0x0090008e, 0x0090008f, + 0x00900090, 0x00900091, 0x00993092, 0x00993093, 0x00900094, 0x00900095, 0x00900096, 0x00900097, + 0x00900098, 0x00001f99, 0x00001f9a, 0x00001f9b, 0x00001f9c, 0x00001f9d, 0x00001f9e, 0x00001f9f, + 0x00001fa0, 0x00001fa1, 0x009000a2, 0x009000a3, 0x009000a4, 0x009000a5, 0x009000a6, 0x00001fa7, + 0x00001fa8, 0x00001fa9, 0x00001faa, 0x00001fab, 0x00001fac, 0x00001fad, 0x00001fae, 0x00001faf, + 0x009000b0, 0x009000b1, 0x009000b2, 0x009000b3, 0x009000b4, 0x00001fb5, 0x00001fb6, 0x00001fb7, + 0x00001fb8, 0x00001fb9, 0x00001fba, 0x00001fbb, 0x00001fbc, 0x00001fbd, 0x00001fbe, 0x00001fbf, + 0x00001fc0, 0x00001fc1, 0x00001fc2, 0x00001fc3, 0x00001fc4, 0x00001fc5, 0x00001fc6, 0x00001fc7, + 0x00001fc8, 0x00001fc9, 0x00001fca, 0x00001fcb, 0x00001fcc, 0x00001fcd, 0x00001fce, 0x00001fcf, + 0x00001fd0, 0x00001fd1, 0x00001fd2, 0x00001fd3, 0x00001fd4, 0x009000d5, 0x009000d6, 0x009000d7, + 0x009000d8, 0x009100d9, 0x00991fda, 0x009000db, 0x009000dc, 0x009000dd, 0x000000de, 0x009000df, + 0x00001fe0, 0x00001fe1, 0x00001fe2, 0x00001fe3, 0x00001fe4, 0x00001fe5, 0x00001fe6, 0x00001fe7, + 0x00001fe8, 0x00001fe9, 0x00001fea, 0x00001feb, 0x00001fec, 0x00001fed, 0x00001fee, 0x00001fef, + 0x00001ff0, 0x00001ff1, 0x00001ff2, 0x00001ff3, 0x00001ff4, 0x00001ff5, 0x00001ff6, 0x00001ff7, + 0x00001ff8, 0x00001ff9, 0x00001ffa, 0x00001ffb, 0x00001ffc, 0x00001ffd, 0x00001ffe, 0x00001fff, +]; + +pub use functions::*; + +/// All programmable functions +pub mod functions { + use super::Function; + + macro_rules! def_function { + ($($name: ident: ($index: expr, $doc: expr);)+) => { + $( + #[doc = $doc] + #[allow(non_camel_case_types)] + pub struct $name; + + impl Function for $name { + const INDEX: u8 = $index; + } + )+ + }; + } + + def_function! { + JTAG_TCLK: (0, "JTAG Test Clock"); + JTAG_TDI: (1, "JTAG Test Data In"); + JTAG_TMS: (2, "JTAG Test Mode Select"); + JTAG_TDO: (3, "JTAG Test Data Out"); + SPI0_D0: (4, "SPI0 Data 0"); + SPI0_D1: (5, "SPI0 Data 1"); + SPI0_D2: (6, "SPI0 Data 2"); + SPI0_D3: (7, "SPI0 Data 3"); + SPI0_D4: (8, "SPI0 Data 4"); + SPI0_D5: (9, "SPI0 Data 5"); + SPI0_D6: (10, "SPI0 Data 6"); + SPI0_D7: (11, "SPI0 Data 7"); + SPI0_SS0: (12, "SPI0 Chip Select 0"); + SPI0_SS1: (13, "SPI0 Chip Select 1"); + SPI0_SS2: (14, "SPI0 Chip Select 2"); + SPI0_SS3: (15, "SPI0 Chip Select 3"); + SPI0_ARB: (16, "SPI0 Arbitration"); + SPI0_SCLK: (17, "SPI0 Serial Clock"); + UARTHS_RX: (18, "UART High speed Receiver"); + UARTHS_TX: (19, "UART High speed Transmitter"); + RESV6: (20, "Reserved function"); + RESV7: (21, "Reserved function"); + CLK_SPI1: (22, "Clock SPI1"); + CLK_I2C1: (23, "Clock I2C1"); + GPIOHS0: (24, "GPIO High speed 0"); + GPIOHS1: (25, "GPIO High speed 1"); + GPIOHS2: (26, "GPIO High speed 2"); + GPIOHS3: (27, "GPIO High speed 3"); + GPIOHS4: (28, "GPIO High speed 4"); + GPIOHS5: (29, "GPIO High speed 5"); + GPIOHS6: (30, "GPIO High speed 6"); + GPIOHS7: (31, "GPIO High speed 7"); + GPIOHS8: (32, "GPIO High speed 8"); + GPIOHS9: (33, "GPIO High speed 9"); + GPIOHS10: (34, "GPIO High speed 10"); + GPIOHS11: (35, "GPIO High speed 11"); + GPIOHS12: (36, "GPIO High speed 12"); + GPIOHS13: (37, "GPIO High speed 13"); + GPIOHS14: (38, "GPIO High speed 14"); + GPIOHS15: (39, "GPIO High speed 15"); + GPIOHS16: (40, "GPIO High speed 16"); + GPIOHS17: (41, "GPIO High speed 17"); + GPIOHS18: (42, "GPIO High speed 18"); + GPIOHS19: (43, "GPIO High speed 19"); + GPIOHS20: (44, "GPIO High speed 20"); + GPIOHS21: (45, "GPIO High speed 21"); + GPIOHS22: (46, "GPIO High speed 22"); + GPIOHS23: (47, "GPIO High speed 23"); + GPIOHS24: (48, "GPIO High speed 24"); + GPIOHS25: (49, "GPIO High speed 25"); + GPIOHS26: (50, "GPIO High speed 26"); + GPIOHS27: (51, "GPIO High speed 27"); + GPIOHS28: (52, "GPIO High speed 28"); + GPIOHS29: (53, "GPIO High speed 29"); + GPIOHS30: (54, "GPIO High speed 30"); + GPIOHS31: (55, "GPIO High speed 31"); + GPIO0: (56, "GPIO pin 0"); + GPIO1: (57, "GPIO pin 1"); + GPIO2: (58, "GPIO pin 2"); + GPIO3: (59, "GPIO pin 3"); + GPIO4: (60, "GPIO pin 4"); + GPIO5: (61, "GPIO pin 5"); + GPIO6: (62, "GPIO pin 6"); + GPIO7: (63, "GPIO pin 7"); + UART1_RX: (64, "UART1 Receiver"); + UART1_TX: (65, "UART1 Transmitter"); + UART2_RX: (66, "UART2 Receiver"); + UART2_TX: (67, "UART2 Transmitter"); + UART3_RX: (68, "UART3 Receiver"); + UART3_TX: (69, "UART3 Transmitter"); + SPI1_D0: (70, "SPI1 Data 0"); + SPI1_D1: (71, "SPI1 Data 1"); + SPI1_D2: (72, "SPI1 Data 2"); + SPI1_D3: (73, "SPI1 Data 3"); + SPI1_D4: (74, "SPI1 Data 4"); + SPI1_D5: (75, "SPI1 Data 5"); + SPI1_D6: (76, "SPI1 Data 6"); + SPI1_D7: (77, "SPI1 Data 7"); + SPI1_SS0: (78, "SPI1 Chip Select 0"); + SPI1_SS1: (79, "SPI1 Chip Select 1"); + SPI1_SS2: (80, "SPI1 Chip Select 2"); + SPI1_SS3: (81, "SPI1 Chip Select 3"); + SPI1_ARB: (82, "SPI1 Arbitration"); + SPI1_SCLK: (83, "SPI1 Serial Clock"); + SPI_SLAVE_D0: (84, "SPI Slave Data 0"); + SPI_SLAVE_SS: (85, "SPI Slave Select"); + SPI_SLAVE_SCLK: (86, "SPI Slave Serial Clock"); + I2S0_MCLK: (87, "I2S0 Master Clock"); + I2S0_SCLK: (88, "I2S0 Serial Clock(BCLK)"); + I2S0_WS: (89, "I2S0 Word Select(LRCLK)"); + I2S0_IN_D0: (90, "I2S0 Serial Data Input 0"); + I2S0_IN_D1: (91, "I2S0 Serial Data Input 1"); + I2S0_IN_D2: (92, "I2S0 Serial Data Input 2"); + I2S0_IN_D3: (93, "I2S0 Serial Data Input 3"); + I2S0_OUT_D0: (94, "I2S0 Serial Data Output 0"); + I2S0_OUT_D1: (95, "I2S0 Serial Data Output 1"); + I2S0_OUT_D2: (96, "I2S0 Serial Data Output 2"); + I2S0_OUT_D3: (97, "I2S0 Serial Data Output 3"); + I2S1_MCLK: (98, "I2S1 Master Clock"); + I2S1_SCLK: (99, "I2S1 Serial Clock(BCLK)"); + I2S1_WS: (100, "I2S1 Word Select(LRCLK)"); + I2S1_IN_D0: (101, "I2S1 Serial Data Input 0"); + I2S1_IN_D1: (102, "I2S1 Serial Data Input 1"); + I2S1_IN_D2: (103, "I2S1 Serial Data Input 2"); + I2S1_IN_D3: (104, "I2S1 Serial Data Input 3"); + I2S1_OUT_D0: (105, "I2S1 Serial Data Output 0"); + I2S1_OUT_D1: (106, "I2S1 Serial Data Output 1"); + I2S1_OUT_D2: (107, "I2S1 Serial Data Output 2"); + I2S1_OUT_D3: (108, "I2S1 Serial Data Output 3"); + I2S2_MCLK: (109, "I2S2 Master Clock"); + I2S2_SCLK: (110, "I2S2 Serial Clock(BCLK)"); + I2S2_WS: (111, "I2S2 Word Select(LRCLK)"); + I2S2_IN_D0: (112, "I2S2 Serial Data Input 0"); + I2S2_IN_D1: (113, "I2S2 Serial Data Input 1"); + I2S2_IN_D2: (114, "I2S2 Serial Data Input 2"); + I2S2_IN_D3: (115, "I2S2 Serial Data Input 3"); + I2S2_OUT_D0: (116, "I2S2 Serial Data Output 0"); + I2S2_OUT_D1: (117, "I2S2 Serial Data Output 1"); + I2S2_OUT_D2: (118, "I2S2 Serial Data Output 2"); + I2S2_OUT_D3: (119, "I2S2 Serial Data Output 3"); + RESV0: (120, "Reserved function"); + RESV1: (121, "Reserved function"); + RESV2: (122, "Reserved function"); + RESV3: (123, "Reserved function"); + RESV4: (124, "Reserved function"); + RESV5: (125, "Reserved function"); + I2C0_SCLK: (126, "I2C0 Serial Clock"); + I2C0_SDA: (127, "I2C0 Serial Data"); + I2C1_SCLK: (128, "I2C1 Serial Clock"); + I2C1_SDA: (129, "I2C1 Serial Data"); + I2C2_SCLK: (130, "I2C2 Serial Clock"); + I2C2_SDA: (131, "I2C2 Serial Data"); + CMOS_XCLK: (132, "DVP System Clock"); + CMOS_RST: (133, "DVP System Reset"); + CMOS_PWDN: (134, "DVP Power Down Mode"); + CMOS_VSYNC: (135, "DVP Vertical Sync"); + CMOS_HREF: (136, "DVP Horizontal Reference output"); + CMOS_PCLK: (137, "Pixel Clock"); + CMOS_D0: (138, "Data Bit 0"); + CMOS_D1: (139, "Data Bit 1"); + CMOS_D2: (140, "Data Bit 2"); + CMOS_D3: (141, "Data Bit 3"); + CMOS_D4: (142, "Data Bit 4"); + CMOS_D5: (143, "Data Bit 5"); + CMOS_D6: (144, "Data Bit 6"); + CMOS_D7: (145, "Data Bit 7"); + SCCB_SCLK: (146, "SCCB Serial Clock"); + SCCB_SDA: (147, "SCCB Serial Data"); + UART1_CTS: (148, "UART1 Clear To Send"); + UART1_DSR: (149, "UART1 Data Set Ready"); + UART1_DCD: (150, "UART1 Data Carrier Detect"); + UART1_RI: (151, "UART1 Ring Indicator"); + UART1_SIR_IN: (152, "UART1 Serial Infrared Input"); + UART1_DTR: (153, "UART1 Data Terminal Ready"); + UART1_RTS: (154, "UART1 Request To Send"); + UART1_OUT2: (155, "UART1 User-designated Output 2"); + UART1_OUT1: (156, "UART1 User-designated Output 1"); + UART1_SIR_OUT: (157, "UART1 Serial Infrared Output"); + UART1_BAUD: (158, "UART1 Transmit Clock Output"); + UART1_RE: (159, "UART1 Receiver Output Enable"); + UART1_DE: (160, "UART1 Driver Output Enable"); + UART1_RS485_EN: (161, "UART1 RS485 Enable"); + UART2_CTS: (162, "UART2 Clear To Send"); + UART2_DSR: (163, "UART2 Data Set Ready"); + UART2_DCD: (164, "UART2 Data Carrier Detect"); + UART2_RI: (165, "UART2 Ring Indicator"); + UART2_SIR_IN: (166, "UART2 Serial Infrared Input"); + UART2_DTR: (167, "UART2 Data Terminal Ready"); + UART2_RTS: (168, "UART2 Request To Send"); + UART2_OUT2: (169, "UART2 User-designated Output 2"); + UART2_OUT1: (170, "UART2 User-designated Output 1"); + UART2_SIR_OUT: (171, "UART2 Serial Infrared Output"); + UART2_BAUD: (172, "UART2 Transmit Clock Output"); + UART2_RE: (173, "UART2 Receiver Output Enable"); + UART2_DE: (174, "UART2 Driver Output Enable"); + UART2_RS485_EN: (175, "UART2 RS485 Enable"); + UART3_CTS: (176, "UART3 Clear To Send"); + UART3_DSR: (177, "UART3 Data Set Ready"); + UART3_DCD: (178, "UART3 Data Carrier Detect"); + UART3_RI: (179, "UART3 Ring Indicator"); + UART3_SIR_IN: (180, "UART3 Serial Infrared Input"); + UART3_DTR: (181, "UART3 Data Terminal Ready"); + UART3_RTS: (182, "UART3 Request To Send"); + UART3_OUT2: (183, "UART3 User-designated Output 2"); + UART3_OUT1: (184, "UART3 User-designated Output 1"); + UART3_SIR_OUT: (185, "UART3 Serial Infrared Output"); + UART3_BAUD: (186, "UART3 Transmit Clock Output"); + UART3_RE: (187, "UART3 Receiver Output Enable"); + UART3_DE: (188, "UART3 Driver Output Enable"); + UART3_RS485_EN: (189, "UART3 RS485 Enable"); + TIMER0_TOGGLE1: (190, "TIMER0 Toggle Output 1"); + TIMER0_TOGGLE2: (191, "TIMER0 Toggle Output 2"); + TIMER0_TOGGLE3: (192, "TIMER0 Toggle Output 3"); + TIMER0_TOGGLE4: (193, "TIMER0 Toggle Output 4"); + TIMER1_TOGGLE1: (194, "TIMER1 Toggle Output 1"); + TIMER1_TOGGLE2: (195, "TIMER1 Toggle Output 2"); + TIMER1_TOGGLE3: (196, "TIMER1 Toggle Output 3"); + TIMER1_TOGGLE4: (197, "TIMER1 Toggle Output 4"); + TIMER2_TOGGLE1: (198, "TIMER2 Toggle Output 1"); + TIMER2_TOGGLE2: (199, "TIMER2 Toggle Output 2"); + TIMER2_TOGGLE3: (200, "TIMER2 Toggle Output 3"); + TIMER2_TOGGLE4: (201, "TIMER2 Toggle Output 4"); + CLK_SPI2: (202, "Clock SPI2"); + CLK_I2C2: (203, "Clock I2C2"); + INTERNAL0: (204, "Internal function signal 0"); + INTERNAL1: (205, "Internal function signal 1"); + INTERNAL2: (206, "Internal function signal 2"); + INTERNAL3: (207, "Internal function signal 3"); + INTERNAL4: (208, "Internal function signal 4"); + INTERNAL5: (209, "Internal function signal 5"); + INTERNAL6: (210, "Internal function signal 6"); + INTERNAL7: (211, "Internal function signal 7"); + INTERNAL8: (212, "Internal function signal 8"); + INTERNAL9: (213, "Internal function signal 9"); + INTERNAL10: (214, "Internal function signal 10"); + INTERNAL11: (215, "Internal function signal 11"); + INTERNAL12: (216, "Internal function signal 12"); + INTERNAL13: (217, "Internal function signal 13"); + INTERNAL14: (218, "Internal function signal 14"); + INTERNAL15: (219, "Internal function signal 15"); + INTERNAL16: (220, "Internal function signal 16"); + INTERNAL17: (221, "Internal function signal 17"); + CONSTANT: (222, "Constant function"); + INTERNAL18: (223, "Internal function signal 18"); + DEBUG0: (224, "Debug function 0"); + DEBUG1: (225, "Debug function 1"); + DEBUG2: (226, "Debug function 2"); + DEBUG3: (227, "Debug function 3"); + DEBUG4: (228, "Debug function 4"); + DEBUG5: (229, "Debug function 5"); + DEBUG6: (230, "Debug function 6"); + DEBUG7: (231, "Debug function 7"); + DEBUG8: (232, "Debug function 8"); + DEBUG9: (233, "Debug function 9"); + DEBUG10: (234, "Debug function 10"); + DEBUG11: (235, "Debug function 11"); + DEBUG12: (236, "Debug function 12"); + DEBUG13: (237, "Debug function 13"); + DEBUG14: (238, "Debug function 14"); + DEBUG15: (239, "Debug function 15"); + DEBUG16: (240, "Debug function 16"); + DEBUG17: (241, "Debug function 17"); + DEBUG18: (242, "Debug function 18"); + DEBUG19: (243, "Debug function 19"); + DEBUG20: (244, "Debug function 20"); + DEBUG21: (245, "Debug function 21"); + DEBUG22: (246, "Debug function 22"); + DEBUG23: (247, "Debug function 23"); + DEBUG24: (248, "Debug function 24"); + DEBUG25: (249, "Debug function 25"); + DEBUG26: (250, "Debug function 26"); + DEBUG27: (251, "Debug function 27"); + DEBUG28: (252, "Debug function 28"); + DEBUG29: (253, "Debug function 29"); + DEBUG30: (254, "Debug function 30"); + DEBUG31: (255, "Debug function 31"); + } +} diff --git a/tools/k210-hal/src/gpio.rs b/tools/k210-hal/src/gpio.rs new file mode 100644 index 0000000..efe0fb9 --- /dev/null +++ b/tools/k210-hal/src/gpio.rs @@ -0,0 +1,233 @@ +//! General Purpose Input/Output (GPIO) + +use core::marker::PhantomData; +use crate::pac; +use crate::sysctl::{self, APB0}; +use crate::fpioa::{IoPin, Pull, Mode}; +use crate::bit_utils::{u32_set_bit, u32_toggle_bit, u32_bit_is_set, u32_bit_is_clear}; +use embedded_hal::digital::{OutputPin, StatefulOutputPin, InputPin, ToggleableOutputPin}; + +/// Extension trait to split a GPIO peripheral into independent pins +pub trait GpioExt { + /// Split the GPIO peripheral into parts + fn split(self, apb0: &mut APB0) -> Parts; +} + +macro_rules! def_gpio_pins { + ($($GPIOX: ident: ($num: expr, $gpiox: ident, $func: ident);)+) => { + +impl GpioExt for pac::GPIO { + fn split(self, apb0: &mut APB0) -> Parts { + // enable APB0 bus + apb0.enable(); + // enable sysctl peripheral + sysctl::clk_en_peri().modify(|_r, w| w.gpio_clk_en().set_bit()); + // return ownership + Parts { + $( $gpiox: $GPIOX { _ownership: () }, )+ + } + } +} + +/// GPIO peripheral parts +pub struct Parts { + $( + /// GPIO pin + pub $gpiox: $GPIOX, + )+ +} + +pub use gpio_pins::*; + +/// All GPIO pins +pub mod gpio_pins { + use super::GpioIndex; +$( + /// GPIO pin + pub struct $GPIOX { + pub(crate) _ownership: () + } + + impl GpioIndex for $GPIOX { + type FUNC = crate::fpioa::functions::$func; + const INDEX: u8 = $num; + } +)+ +} + }; +} + +def_gpio_pins! { + GPIO0: (0, gpio0, GPIO0); + GPIO1: (1, gpio1, GPIO1); + GPIO2: (2, gpio2, GPIO2); + GPIO3: (3, gpio3, GPIO3); + GPIO4: (4, gpio4, GPIO4); + GPIO5: (5, gpio5, GPIO5); + GPIO6: (6, gpio6, GPIO6); + GPIO7: (7, gpio7, GPIO7); +} + +/// GPIO Index +pub trait GpioIndex { + type FUNC; + const INDEX: u8; +} + +/// Unknown mode (type state) +pub struct Unknown; + +/// Input mode (type state) +pub struct Input(MODE); + +/// Floating input (type state) +pub struct Floating; + +/// Pull down input (type state) +pub struct PullDown; + +/// Pull up input (type state) +pub struct PullUp; + +/// Output mode (type state) +pub struct Output; + +/// Marker trait for active states +pub trait Active {} + +impl Active for Unknown {} + +impl Active for Input {} + +impl Active for Input {} + +impl Active for Input {} + +impl Active for Output {} + +/// GPIO wrapper struct +pub struct Gpio { + gpio: GPIO, + pin: PIN, + _mode: PhantomData, +} + +impl> Gpio { + pub fn new(gpio: GPIO, pin: PIN) -> Gpio { + Gpio { gpio, pin, _mode: PhantomData } + } +} + +impl Gpio { + pub fn free(self) -> (GPIO, PIN) { + (self.gpio, self.pin) + } +} + +impl Gpio { + pub fn into_floating_input(mut self) -> Gpio> { + self.pin.set_io_pull(Pull::None); + self.direction_in(); + Gpio { gpio: self.gpio, pin: self.pin, _mode: PhantomData } + } + + pub fn into_pull_up_input(mut self) -> Gpio> { + self.pin.set_io_pull(Pull::Up); + self.direction_in(); + Gpio { gpio: self.gpio, pin: self.pin, _mode: PhantomData } + } + + pub fn into_pull_down_input(mut self) -> Gpio> { + self.pin.set_io_pull(Pull::Down); + self.direction_in(); + Gpio { gpio: self.gpio, pin: self.pin, _mode: PhantomData } + } + + pub fn into_push_pull_output(mut self) -> Gpio { + self.pin.set_io_pull(Pull::Down); + self.direction_out(); + Gpio { gpio: self.gpio, pin: self.pin, _mode: PhantomData } + } + + #[inline] + fn direction_in(&mut self) { + unsafe { + let p = &(*pac::GPIO::ptr()).direction as *const _ as *mut _; + u32_set_bit(p, false, GPIO::INDEX as usize); + } + } + + #[inline] + fn direction_out(&mut self) { + unsafe { + let p = &(*pac::GPIO::ptr()).direction as *const _ as *mut _; + u32_set_bit(p, true, GPIO::INDEX as usize); + } + } +} + +impl InputPin for Gpio> { + type Error = core::convert::Infallible; + + fn try_is_high(&self) -> Result { + Ok(unsafe { + let p = &(*pac::GPIO::ptr()).data_input as *const _ as *const _; + u32_bit_is_set(p, GPIO::INDEX as usize) + }) + } + + fn try_is_low(&self) -> Result { + Ok(unsafe { + let p = &(*pac::GPIO::ptr()).data_input as *const _ as *const _; + u32_bit_is_clear(p, GPIO::INDEX as usize) + }) + } +} + +impl OutputPin for Gpio { + type Error = core::convert::Infallible; + + fn try_set_high(&mut self) -> Result<(), Self::Error> { + unsafe { + let p = &(*pac::GPIO::ptr()).data_output as *const _ as *mut _; + u32_set_bit(p, true, GPIO::INDEX as usize); + } + Ok(()) + } + + fn try_set_low(&mut self) -> Result<(), Self::Error> { + unsafe { + let p = &(*pac::GPIO::ptr()).data_output as *const _ as *mut _; + u32_set_bit(p, false, GPIO::INDEX as usize); + } + Ok(()) + } +} + +impl StatefulOutputPin for Gpio { + fn try_is_set_high(&self) -> Result { + Ok(unsafe { + let p = &(*pac::GPIO::ptr()).data_output as *const _ as *const _; + u32_bit_is_set(p, GPIO::INDEX as usize) + }) + } + + fn try_is_set_low(&self) -> Result { + Ok(unsafe { + let p = &(*pac::GPIO::ptr()).data_output as *const _ as *const _; + u32_bit_is_clear(p, GPIO::INDEX as usize) + }) + } +} + +impl ToggleableOutputPin for Gpio { + type Error = core::convert::Infallible; + + fn try_toggle(&mut self) -> Result<(), Self::Error> { + unsafe { + let p = &(*pac::GPIO::ptr()).data_output as *const _ as *mut _; + u32_toggle_bit(p, GPIO::INDEX as usize); + } + Ok(()) + } +} diff --git a/tools/k210-hal/src/gpiohs.rs b/tools/k210-hal/src/gpiohs.rs new file mode 100644 index 0000000..9be4195 --- /dev/null +++ b/tools/k210-hal/src/gpiohs.rs @@ -0,0 +1,346 @@ +//! High-speed GPIO peripheral (GPIOHS) + +use crate::pac::GPIOHS; +use core::marker::PhantomData; +use crate::bit_utils::{u32_set_bit, u32_toggle_bit, u32_bit_is_set, u32_bit_is_clear}; +use embedded_hal::digital::{InputPin, OutputPin}; + +// todo: verify + +/// Floating mode (type state) +pub struct Floating; + +/// PullUp mode (type state) +pub struct PullUp; + +/// Input mode (type state) +pub struct Input(MODE); + +/// Output mode (type state) +pub struct Output(MODE); + +pub trait GpiohsExt { + fn split(self) -> Parts; +} + +impl GpiohsExt for GPIOHS { + fn split(self) -> Parts { + Parts { + gpiohs0: Gpiohs0 { _mode: PhantomData }, + } + } +} + +pub struct Parts { + pub gpiohs0: Gpiohs0>, +} + +pub struct Gpiohs0 { + _mode: PhantomData, +} + +impl Gpiohs0 { + pub fn into_pull_up_input(self) -> Gpiohs0> { + GPIOHS::set_output_en(0, false); + GPIOHS::set_input_en(0, true); + GPIOHS::set_pullup_en(0, true); + Gpiohs0 { _mode: PhantomData } + } + + // todo: all modes +} + +bitflags::bitflags! { + pub struct Edge: u8 { + const RISING = 0b00000001; + const FALLING = 0b00000010; + const HIGH = 0b00000100; + const LOW = 0b00001000; + } +} + +impl Gpiohs0 { + pub fn trigger_on_edge(&mut self, edge: Edge) { + // clear all pending bits + GPIOHS::clear_rise_ip(0); + GPIOHS::clear_fall_ip(0); + GPIOHS::clear_high_ip(0); + GPIOHS::clear_low_ip(0); + // enable interrupts according to flags + GPIOHS::set_rise_ie(0, edge.contains(Edge::RISING)); + GPIOHS::set_fall_ie(0, edge.contains(Edge::FALLING)); + GPIOHS::set_high_ie(0, edge.contains(Edge::HIGH)); + GPIOHS::set_low_ie(0, edge.contains(Edge::LOW)); + } + + pub fn check_edges(&self) -> Edge { + let mut ans = Edge::empty(); + if GPIOHS::has_rise_ip(0) { + ans |= Edge::RISING; + } + if GPIOHS::has_fall_ip(0) { + ans |= Edge::FALLING; + } + if GPIOHS::has_high_ip(0) { + ans |= Edge::HIGH; + } + if GPIOHS::has_low_ip(0) { + ans |= Edge::LOW; + } + ans + } + + pub fn clear_interrupt_pending_bits(&mut self) { + if GPIOHS::has_rise_ie(0) { + GPIOHS::set_rise_ie(0, false); + GPIOHS::clear_rise_ip(0); + GPIOHS::set_rise_ie(0, true); + } + if GPIOHS::has_fall_ie(0) { + GPIOHS::set_fall_ie(0, false); + GPIOHS::clear_fall_ip(0); + GPIOHS::set_fall_ie(0, true); + } + if GPIOHS::has_high_ie(0) { + GPIOHS::set_high_ie(0, false); + GPIOHS::clear_high_ip(0); + GPIOHS::set_high_ie(0, true); + } + if GPIOHS::has_low_ie(0) { + GPIOHS::set_low_ie(0, false); + GPIOHS::clear_low_ip(0); + GPIOHS::set_low_ie(0, true); + } + } +} + +impl InputPin for Gpiohs0> { + type Error = core::convert::Infallible; + + fn try_is_high(&self) -> Result { + Ok(unsafe { + let p = &(*GPIOHS::ptr()).input_val as *const _ as *const _; + u32_bit_is_set(p, 0) + }) + } + + fn try_is_low(&self) -> Result { + Ok(unsafe { + let p = &(*GPIOHS::ptr()).input_val as *const _ as *const _; + u32_bit_is_clear(p, 0) + }) + } +} + +impl OutputPin for Gpiohs0> { + type Error = core::convert::Infallible; + + fn try_set_high(&mut self) -> Result<(), Self::Error> { + unsafe { + let p = &(*GPIOHS::ptr()).output_val as *const _ as *mut _; + u32_set_bit(p, true, 0); + } + Ok(()) + } + + fn try_set_low(&mut self) -> Result<(), Self::Error> { + unsafe { + let p = &(*GPIOHS::ptr()).output_val as *const _ as *mut _; + u32_set_bit(p, false, 0); + } + Ok(()) + } +} + +trait GpiohsAccess { + fn peripheral() -> &'static mut crate::pac::gpiohs::RegisterBlock; + + fn set_drive(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().drive as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn input_value(index: usize) -> bool { + unsafe { + let p = &mut Self::peripheral().input_val as *mut _ as *mut _; + u32_bit_is_set(p, index) + } + } + + fn set_input_en(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().input_en as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn set_iof_en(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().iof_en as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn set_iof_sel(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().iof_sel as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn set_output_en(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().output_en as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn set_output_value(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().output_val as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn set_output_xor(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().output_xor as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn toggle_pin(index: usize) { + unsafe { + let p = &mut Self::peripheral().output_val as *mut _ as *mut _; + u32_toggle_bit(p, index); + } + } + + fn set_pullup_en(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().pullup_en as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn set_rise_ie(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().rise_ie as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn clear_rise_ip(index: usize) { + unsafe { + let p = &mut Self::peripheral().rise_ip as *mut _ as *mut _; + u32_set_bit(p, true, index); + } + } + + fn set_fall_ie(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().fall_ie as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn clear_fall_ip(index: usize) { + unsafe { + let p = &mut Self::peripheral().fall_ip as *mut _ as *mut _; + u32_set_bit(p, true, index); + } + } + + fn set_high_ie(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().high_ie as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn clear_high_ip(index: usize,) { + unsafe { + let p = &mut Self::peripheral().high_ip as *mut _ as *mut _; + u32_set_bit(p, true, index); + } + } + + fn set_low_ie(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().low_ie as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn clear_low_ip(index: usize) { + unsafe { + let p = &mut Self::peripheral().low_ip as *mut _ as *mut _; + u32_set_bit(p, true, index); + } + } + + fn has_rise_ie(index: usize) -> bool { + unsafe { + let p = &mut Self::peripheral().rise_ie as *mut _ as *mut _; + u32_bit_is_set(p, index) + } + } + + fn has_fall_ie(index: usize) -> bool { + unsafe { + let p = &mut Self::peripheral().fall_ie as *mut _ as *mut _; + u32_bit_is_set(p, index) + } + } + + fn has_high_ie(index: usize) -> bool { + unsafe { + let p = &mut Self::peripheral().high_ie as *mut _ as *mut _; + u32_bit_is_set(p, index) + } + } + + fn has_low_ie(index: usize) -> bool { + unsafe { + let p = &mut Self::peripheral().low_ie as *mut _ as *mut _; + u32_bit_is_set(p, index) + } + } + + fn has_rise_ip(index: usize) -> bool { + unsafe { + let p = &mut Self::peripheral().rise_ip as *mut _ as *mut _; + u32_bit_is_set(p, index) + } + } + + fn has_fall_ip(index: usize) -> bool { + unsafe { + let p = &mut Self::peripheral().fall_ip as *mut _ as *mut _; + u32_bit_is_set(p, index) + } + } + + fn has_high_ip(index: usize) -> bool { + unsafe { + let p = &mut Self::peripheral().high_ip as *mut _ as *mut _; + u32_bit_is_set(p, index) + } + } + + fn has_low_ip(index: usize) -> bool { + unsafe { + let p = &mut Self::peripheral().low_ip as *mut _ as *mut _; + u32_bit_is_set(p, index) + } + } + +} + +impl GpiohsAccess for GPIOHS { + fn peripheral() -> &'static mut crate::pac::gpiohs::RegisterBlock { + unsafe { &mut *(GPIOHS::ptr() as *mut _) } + } +} diff --git a/tools/k210-hal/src/lib.rs b/tools/k210-hal/src/lib.rs new file mode 100644 index 0000000..4309e86 --- /dev/null +++ b/tools/k210-hal/src/lib.rs @@ -0,0 +1,67 @@ +//! HAL for the K210 SoC +//! +//! This is an implementation of the [`embedded-hal`] traits for the K210 SoC + +// #![deny(missing_docs)] // uncomment for every releases +#![no_std] + +pub use k210_pac as pac; + +pub mod aes; +pub mod apu; +pub mod cache; +pub mod clint; +pub mod clock; +pub mod dmac; +pub mod fft; +pub mod fpioa; +pub mod gpio; +pub mod gpiohs; +pub mod plic; +pub mod serial; +pub mod spi; +pub mod sha256; +pub mod stdout; +pub mod sysctl; +pub mod time; + +/// Prelude +pub mod prelude { + pub use embedded_hal::prelude::*; + pub use crate::serial::SerialExt as _k210_hal_serial_SerialExt; + pub use crate::stdout::Write as _k210_hal_stdout_Write; + pub use crate::time::U32Ext as _k210_hal_time_U32Ext; + pub use crate::fpioa::FpioaExt as _k210_hal_fpioa_FpioaExt; + pub use crate::sysctl::SysctlExt as _k210_hal_sysctl_SysctlExt; + pub use crate::gpio::GpioExt as _k210_hal_gpio_GpioExt; + pub use crate::gpiohs::GpiohsExt as _k210_hal_gpiohs_GpiohsExt; + pub use crate::plic::PlicExt as _k210_hal_plic_PlicExt; +} + +mod bit_utils { + #[inline(always)] + pub(crate) unsafe fn u32_set_bit(p: *mut u32, bit: bool, index: usize) { + let mask = 1 << index; + if bit { + *p |= mask; + } else { + *p &= !mask; + } + } + + #[inline(always)] + pub(crate) unsafe fn u32_toggle_bit(p: *mut u32, index: usize) { + let mask = 1 << index; + *p ^= mask; + } + + #[inline(always)] + pub(crate) unsafe fn u32_bit_is_set(r: *const u32, index: usize) -> bool { + (*r & 1 << index) != 0 + } + + #[inline(always)] + pub(crate) unsafe fn u32_bit_is_clear(r: *const u32, index: usize) -> bool { + (*r & 1 << index) == 0 + } +} diff --git a/tools/k210-hal/src/plic.rs b/tools/k210-hal/src/plic.rs new file mode 100644 index 0000000..06635e2 --- /dev/null +++ b/tools/k210-hal/src/plic.rs @@ -0,0 +1,239 @@ +//! Platform-Level Interrupt Controller (PLIC) + +// I don't know if this part should be implemented in runtime +// keep by now, may be replaced on further designs +// #[doc(hidden)] +// #[link_name = "MachineExternal"] +// pub extern fn machine_external() { + +// } + +use crate::pac::{PLIC, Interrupt}; + +/// Extension trait for PLIC interrupt controller peripheral +pub trait PlicExt { + /// Interrupt wrapper type + type Interrupt: Nr; + /// Is this M-Mode interrupt enabled on given hart? + fn is_enabled(hart_id: usize, interrupt: Self::Interrupt) -> bool; + /// Enable an interrupt for a given hart + unsafe fn unmask(hart_id: usize, interrupt: Self::Interrupt); + /// Disable an interrupt for a given hart + fn mask(hart_id: usize, interrupt: Self::Interrupt); + /// Get global priority for one interrupt + fn get_priority(interrupt: Self::Interrupt) -> Priority; + /// Globally set priority for one interrupt + unsafe fn set_priority(interrupt: Self::Interrupt, prio: Priority); + /// Get priority threshold for a given hart + fn get_threshold(hart_id: usize) -> Priority; + /// Set the priority threshold for a given hart + unsafe fn set_threshold(hart_id: usize, threshold: Priority); + /// Mark that given hart have claimed to handle this interrupt + fn claim(hart_id: usize) -> Option; + /// Mark that given hart have completed handling this interrupt + fn complete(hart_id: usize, interrupt: Self::Interrupt); + /// Is this interrupt claimed and under procceeding? + fn is_pending(interrupt: Self::Interrupt) -> bool; +} + +impl PlicExt for PLIC { + type Interrupt = Interrupt; + fn is_enabled(hart_id: usize, interrupt: Interrupt) -> bool { + let irq_number = interrupt.into_bits() as usize; + unsafe { + (*PLIC::ptr()).target_enables[hart_id].enable[irq_number / 32] + .read().bits() & 1 << (irq_number % 32) != 0 + } + } + unsafe fn unmask(hart_id: usize, interrupt: Interrupt) { + let irq_number = interrupt.into_bits() as usize; + (*PLIC::ptr()).target_enables[hart_id].enable[irq_number / 32] + .modify(|r, w| + w.bits(r.bits() | 1 << (irq_number % 32))); + } + fn mask(hart_id: usize, interrupt: Interrupt) { + let irq_number = interrupt.into_bits() as usize; + unsafe { + (*PLIC::ptr()).target_enables[hart_id].enable[irq_number / 32] + .modify(|r, w| + w.bits(r.bits() & !(1 << (irq_number % 32)))); + } + } + fn get_priority(interrupt: Interrupt) -> Priority { + let irq_number = interrupt.into_bits() as usize; + let bits = unsafe { + (*PLIC::ptr()).priority[irq_number].read().bits() + }; + Priority::from_bits(bits) + } + unsafe fn set_priority(interrupt: Interrupt, prio: Priority) { + let irq_number = interrupt.into_bits() as usize; + (*PLIC::ptr()).priority[irq_number].write( + |w| + w.bits(prio.into_bits())); + } + fn get_threshold(hart_id: usize) -> Priority { + let bits = unsafe { + (*PLIC::ptr()).targets[hart_id].threshold.read().bits() + }; + Priority::from_bits(bits) + } + unsafe fn set_threshold(hart_id: usize, threshold: Priority) { + (*PLIC::ptr()).targets[hart_id].threshold.write( + |w| + w.bits(threshold.into_bits())); + } + fn claim(hart_id: usize) -> Option { + let bits = unsafe { + (*PLIC::ptr()).targets[hart_id].claim.read().bits() + }; + Nr::from_bits(bits) + } + fn complete(hart_id: usize, interrupt: Interrupt) { + unsafe { + (*PLIC::ptr()).targets[hart_id].claim.write( + |w| + w.bits(interrupt.into_bits())); + } + } + fn is_pending(interrupt: Interrupt) -> bool { + let irq_number = interrupt.into_bits() as usize; + unsafe { + (*PLIC::ptr()).pending[irq_number / 32] + .read().bits() & 1 << (irq_number % 32) != 0 + } + } +} + +impl Nr for Interrupt { + fn into_bits(&self) -> u32 { + *self as u8 as u32 + } + fn from_bits(bits: u32) -> Option { + use Interrupt::*; + match bits { + 0 => None, + 1 => Some(SPI0), + 2 => Some(SPI1), + 3 => Some(SPI_SLAVE), + 4 => Some(SPI3), + 5 => Some(I2S0), + 6 => Some(I2S1), + 7 => Some(I2S2), + 8 => Some(I2C0), + 9 => Some(I2C1), + 10 => Some(I2C2), + 11 => Some(UART1), + 12 => Some(UART2), + 13 => Some(UART3), + 14 => Some(TIMER0A), + 15 => Some(TIMER0B), + 16 => Some(TIMER1A), + 17 => Some(TIMER1B), + 18 => Some(TIMER2A), + 19 => Some(TIMER2B), + 20 => Some(RTC), + 21 => Some(WDT0), + 22 => Some(WDT1), + 23 => Some(APB_GPIO), + 24 => Some(DVP), + 25 => Some(KPU), + 26 => Some(FFT), + 27 => Some(DMA0), + 28 => Some(DMA1), + 29 => Some(DMA2), + 30 => Some(DMA3), + 31 => Some(DMA4), + 32 => Some(DMA5), + 33 => Some(UARTHS), + 34 => Some(GPIOHS0), + 35 => Some(GPIOHS1), + 36 => Some(GPIOHS2), + 37 => Some(GPIOHS3), + 38 => Some(GPIOHS4), + 39 => Some(GPIOHS5), + 40 => Some(GPIOHS6), + 41 => Some(GPIOHS7), + 42 => Some(GPIOHS8), + 43 => Some(GPIOHS9), + 44 => Some(GPIOHS10), + 45 => Some(GPIOHS11), + 46 => Some(GPIOHS12), + 47 => Some(GPIOHS13), + 48 => Some(GPIOHS14), + 49 => Some(GPIOHS15), + 50 => Some(GPIOHS16), + 51 => Some(GPIOHS17), + 52 => Some(GPIOHS18), + 53 => Some(GPIOHS19), + 54 => Some(GPIOHS20), + 55 => Some(GPIOHS21), + 56 => Some(GPIOHS22), + 57 => Some(GPIOHS23), + 58 => Some(GPIOHS24), + 59 => Some(GPIOHS25), + 60 => Some(GPIOHS26), + 61 => Some(GPIOHS27), + 62 => Some(GPIOHS28), + 63 => Some(GPIOHS29), + 64 => Some(GPIOHS30), + 65 => Some(GPIOHS31), + _ => panic!("invalid interrupt bits") + } + } +} + +#[doc(hidden)] +pub trait Nr: Sized { + fn into_bits(&self) -> u32; + fn from_bits(bits: u32) -> Option; +} + +/// Priority of an interrupt +#[derive(Clone, Copy, Debug)] +pub enum Priority { + /// Priority 0: Never interrupt + P0, + /// Priority 1: Lowest active priority + P1, + /// Priority 2 + P2, + /// Priority 3 + P3, + /// Priority 4 + P4, + /// Priority 5 + P5, + /// Priority 6 + P6, + /// Priority 7: Highest priority + P7, +} + +impl Priority { + fn into_bits(self) -> u32 { + match self { + Priority::P0 => 0, + Priority::P1 => 1, + Priority::P2 => 2, + Priority::P3 => 3, + Priority::P4 => 4, + Priority::P5 => 5, + Priority::P6 => 6, + Priority::P7 => 7, + } + } + fn from_bits(prio: u32) -> Priority { + match prio { + 0 => Priority::P0, + 1 => Priority::P1, + 2 => Priority::P2, + 3 => Priority::P3, + 4 => Priority::P4, + 5 => Priority::P5, + 6 => Priority::P6, + 7 => Priority::P7, + _ => panic!("Invalid priority"), + } + } +} diff --git a/tools/k210-hal/src/serial.rs b/tools/k210-hal/src/serial.rs new file mode 100644 index 0000000..302fbb5 --- /dev/null +++ b/tools/k210-hal/src/serial.rs @@ -0,0 +1,235 @@ +//! Serial interface +//! +//! You can use the `Serial` interface with these UART instances: +//! * [`UARTHS`](crate::pac::UARTHS) +//! * [`UART1`](crate::pac::UART1) +//! * [`UART2`](crate::pac::UART2) +//! * [`UART3`](crate::pac::UART3) + +use core::mem; +use core::convert::Infallible; + +use embedded_hal::serial; + +use crate::pac::{UARTHS,uart1,UART1,UART2,UART3}; +use crate::clock::Clocks; +use crate::time::Bps; + +/// Extension trait that constrains UART peripherals +pub trait SerialExt: Sized { + /// Configures a UART peripheral to provide serial communication + fn configure(self, baud_rate: Bps, clocks: &Clocks) -> Serial; +} + +/// Serial abstraction +pub struct Serial { + uart: UART, +} + +impl Serial { + /// Splits the `Serial` abstraction into a transmitter and a + /// receiver half + pub fn split(self) -> (Tx, Rx) { + ( + Tx { + uart: self.uart, + }, + Rx { + uart: unsafe { mem::MaybeUninit::uninit().assume_init() }, + } + ) + } + + /// Forms `Serial` abstraction from a transmitter and a + /// receiver half + pub fn join(tx: Tx, rx: Rx) -> Self { + let _ = rx; // note(discard): Zero-sized typestate struct + Serial { uart: tx.uart } + } + + /// Releases the UART peripheral + pub fn free(self) -> UART { + // todo: power down this UART + self.uart + } +} + +/// Serial transmitter +pub struct Tx { + uart: UART, +} + +/// Serial receiver +pub struct Rx { + uart: UART, +} + +impl SerialExt for UARTHS { + fn configure(self, baud_rate: Bps, clocks: &Clocks) -> Serial + { + let uart = self; + + let div = clocks.cpu().0 / baud_rate.0 - 1; + unsafe { + uart.div.write(|w| w.bits(div)); + } + + uart.txctrl.write(|w| w.txen().bit(true)); + uart.rxctrl.write(|w| w.rxen().bit(true)); + + Serial { uart } + } +} + +impl Serial { + /// Starts listening for an interrupt event + pub fn listen(self) -> Self { + self.uart.ie.write(|w| w.txwm().bit(false).rxwm().bit(true)); + self + } + + /// Stops listening for an interrupt event + pub fn unlisten(self) -> Self { + self.uart + .ie + .write(|w| w.txwm().bit(false).rxwm().bit(false)); + self + } +} + +impl serial::Read for Rx { + type Error = Infallible; + + fn try_read(&mut self) -> nb::Result { + let rxdata = self.uart.rxdata.read(); + + if rxdata.empty().bit_is_set() { + Err(nb::Error::WouldBlock) + } else { + Ok(rxdata.data().bits() as u8) + } + } +} + +impl serial::Write for Tx { + type Error = Infallible; + + fn try_write(&mut self, byte: u8) -> nb::Result<(), Infallible> { + let txdata = self.uart.txdata.read(); + + if txdata.full().bit_is_set() { + Err(nb::Error::WouldBlock) + } else { + unsafe { + (*UARTHS::ptr()).txdata.write(|w| w.data().bits(byte)); + } + Ok(()) + } + } + + fn try_flush(&mut self) -> nb::Result<(), Infallible> { + let txdata = self.uart.txdata.read(); + + if txdata.full().bit_is_set() { + Err(nb::Error::WouldBlock) + } else { + Ok(()) + } + } +} + +mod closed_trait { + use core::ops::Deref; + /// Trait to be able to generalize over UART1/UART2/UART3 + pub trait UartX: Deref { + const INDEX: u8; + } +} +use closed_trait::UartX; + +impl UartX for UART1 { const INDEX: u8 = 1; } +impl UartX for UART2 { const INDEX: u8 = 2; } +impl UartX for UART3 { const INDEX: u8 = 3; } + +const UART_RECEIVE_FIFO_1: u32 = 0; +const UART_SEND_FIFO_8: u32 = 3; + +impl SerialExt for UART { + fn configure(self, baud_rate: Bps, clocks: &Clocks) -> Serial { + let uart = self; + + // Hardcode these for now: + let data_width = 8; // 8 data bits + let stopbit_val = 0; // 1 stop bit + let parity_val = 0; // No parity + // Note: need to make sure that UARTx clock is enabled through sysctl before here + let divisor = clocks.apb0().0 / baud_rate.0; + let dlh = ((divisor >> 12) & 0xff) as u8; + let dll = ((divisor >> 4) & 0xff) as u8; + let dlf = (divisor & 0xf) as u8; + unsafe { + // Set Divisor Latch Access Bit (enables DLL DLH) to set baudrate + uart.lcr.write(|w| w.bits(1 << 7)); + uart.dlh_ier.write(|w| w.bits(dlh.into())); + uart.rbr_dll_thr.write(|w| w.bits(dll.into())); + uart.dlf.write(|w| w.bits(dlf.into())); + // Clear Divisor Latch Access Bit after setting baudrate + uart.lcr.write(|w| w.bits((data_width - 5) | (stopbit_val << 2) | (parity_val << 3))); + // Write IER + uart.dlh_ier.write(|w| w.bits(0x80)); /* THRE */ + // Write FCT + uart.fcr_iir.write(|w| w.bits(UART_RECEIVE_FIFO_1 << 6 | UART_SEND_FIFO_8 << 4 | 0x1 << 3 | 0x1)); + } + + Serial { uart } + } +} + +impl Serial { + /// Starts listening for an interrupt event + pub fn listen(self) -> Self { + self + } + + /// Stops listening for an interrupt event + pub fn unlisten(self) -> Self { + self + } +} + +impl serial::Read for Rx { + type Error = Infallible; + + fn try_read(&mut self) -> nb::Result { + let lsr = self.uart.lsr.read(); + + if (lsr.bits() & (1<<0)) == 0 { // Data Ready bit + Err(nb::Error::WouldBlock) + } else { + let rbr = self.uart.rbr_dll_thr.read(); + Ok((rbr.bits() & 0xff) as u8) + } + } +} + +impl serial::Write for Tx { + type Error = Infallible; + + fn try_write(&mut self, byte: u8) -> nb::Result<(), Infallible> { + let lsr = self.uart.lsr.read(); + + if (lsr.bits() & (1<<5)) != 0 { // Transmit Holding Register Empty bit + Err(nb::Error::WouldBlock) + } else { + unsafe { + self.uart.rbr_dll_thr.write(|w| w.bits(byte.into())); + } + Ok(()) + } + } + + fn try_flush(&mut self) -> nb::Result<(), Infallible> { + // TODO + Ok(()) + } +} diff --git a/tools/k210-hal/src/sha256.rs b/tools/k210-hal/src/sha256.rs new file mode 100644 index 0000000..e32a62b --- /dev/null +++ b/tools/k210-hal/src/sha256.rs @@ -0,0 +1,52 @@ +//! Secure Hash Algorithm-256 (SHA256) + +use crate::pac::SHA256; +use crate::sysctl::{self, APB0}; + +/// SHA256 module abstraction +pub struct Sha256 { + sha256: SHA256, +} + +impl Sha256 { + pub fn sha256(sha256: SHA256, apb0: &mut APB0) -> Sha256 { + apb0.enable(); + sysctl::clk_en_peri().modify(|_r, w| + w.sha_clk_en().set_bit()); + sysctl::peri_reset().modify(|_r, w| + w.sha_reset().set_bit()); + sysctl::peri_reset().modify(|_r, w| + w.sha_reset().clear_bit()); + Sha256 { sha256 } + } + + pub fn new_digest(self) -> Digest { + todo!() + } + + pub fn release(self) -> SHA256 { + sysctl::clk_en_peri().modify(|_r, w| + w.sha_clk_en().clear_bit()); + self.sha256 + } +} + +pub struct Digest { + sha256: SHA256, +} + +impl Digest { + pub fn write_u32(&mut self, n: u32) { + let _todo = n; + todo!() + } + + pub fn finish(&self, out: &mut [u8; 32]) { + let _todo = out; + todo!() + } + + pub fn free(self) -> Sha256 { + Sha256 { sha256: self.sha256 } + } +} diff --git a/tools/k210-hal/src/spi.rs b/tools/k210-hal/src/spi.rs new file mode 100644 index 0000000..89a7f91 --- /dev/null +++ b/tools/k210-hal/src/spi.rs @@ -0,0 +1,122 @@ +//! (TODO) Serial Peripheral Interface (SPI) + +use crate::pac::SPI0; +use crate::clock::Clocks; +use crate::sysctl::{self, APB0}; +pub use embedded_hal::spi::{Mode, Polarity, Phase}; +use core::convert::Infallible; + +/// +pub struct Spi { + spi: SPI +} + +impl Spi { + pub fn spi0( + spi: SPI0, + mode: Mode, + frame_format: FrameFormat, + endian: Endian, + clock: &Clocks, + apb0: &mut APB0 + ) -> Self { + let work_mode = hal_mode_to_pac(mode); + let frame_format = frame_format_to_pac(frame_format); + let tmod = crate::pac::spi0::ctrlr0::TMOD_A::TRANS_RECV; // todo other modes + let endian = endian as u32; + let data_bit_length = 8; // todo more length + let _ = clock; // todo + unsafe { + // no interrupts for now + spi.imr.write(|w| w.bits(0x00)); + // no dma for now + spi.dmacr.write(|w| w.bits(0x00)); + spi.dmatdlr.write(|w| w.bits(0x10)); + spi.dmardlr.write(|w| w.bits(0x00)); + // no slave access for now + spi.ser.write(|w| w.bits(0x00)); + spi.ssienr.write(|w| w.bits(0x00)); + // set control registers + spi.ctrlr0.write(|w| { + w.work_mode() + .variant(work_mode) + .tmod() + .variant(tmod) + .frame_format() + .variant(frame_format) + .data_length() + .bits(data_bit_length - 1) + }); + spi.spi_ctrlr0.reset(); // standard + spi.endian.write(|w| w.bits(endian)); + } + // enable APB0 bus + apb0.enable(); + // enable peripheral via sysctl + sysctl::clk_en_peri().modify(|_r, w| + w.spi0_clk_en().set_bit()); + Spi { spi } + } + + pub fn release(self) -> SPI0 { + // power off + sysctl::clk_en_peri().modify(|_r, w| + w.spi0_clk_en().clear_bit()); + self.spi + } +} + +impl embedded_hal::spi::FullDuplex for Spi { + /// An enumeration of SPI errors + type Error = Infallible; + + /// Reads the word stored in the shift register + /// + /// **NOTE** A word must be sent to the slave before attempting to call this + /// method. + fn try_read(&mut self) -> nb::Result { + todo!() + } + + /// Sends a word to the slave + fn try_send(&mut self, word: u8) -> nb::Result<(), Self::Error> { + todo!("{}", word) + } +} + +#[derive(Clone, Copy, PartialEq, Eq)] +pub enum FrameFormat { + Standard, + Dual, + Quad, + Octal, +} +#[derive(Clone, Copy, PartialEq, Eq)] +#[repr(u32)] +pub enum Endian { + Little = 0, + Big = 1, +} + +#[inline] +fn hal_mode_to_pac(mode: Mode) -> crate::pac::spi0::ctrlr0::WORK_MODE_A { + use crate::pac::spi0::ctrlr0::WORK_MODE_A; + use {Polarity::*, Phase::*}; + match (mode.polarity, mode.phase) { + (IdleLow, CaptureOnFirstTransition) => WORK_MODE_A::MODE0, + (IdleLow, CaptureOnSecondTransition) => WORK_MODE_A::MODE1, + (IdleHigh, CaptureOnFirstTransition) => WORK_MODE_A::MODE2, + (IdleHigh, CaptureOnSecondTransition) => WORK_MODE_A::MODE3, + } +} + +#[inline] +fn frame_format_to_pac(frame_format: FrameFormat) -> crate::pac::spi0::ctrlr0::FRAME_FORMAT_A { + use crate::pac::spi0::ctrlr0::FRAME_FORMAT_A; + match frame_format { + FrameFormat::Standard => FRAME_FORMAT_A::STANDARD, + FrameFormat::Dual => FRAME_FORMAT_A::DUAL, + FrameFormat::Quad => FRAME_FORMAT_A::QUAD, + FrameFormat::Octal => FRAME_FORMAT_A::OCTAL, + } +} diff --git a/tools/k210-hal/src/stdout.rs b/tools/k210-hal/src/stdout.rs new file mode 100644 index 0000000..8483cc4 --- /dev/null +++ b/tools/k210-hal/src/stdout.rs @@ -0,0 +1,31 @@ +//! Stdout +pub use core::fmt::Write; +use nb::block; + +/// Stdout implements the core::fmt::Write trait for hal::serial::Write +/// implementations. +pub struct Stdout<'p, T>(pub &'p mut T); + +impl<'p, T> Write for Stdout<'p, T> + where + T: embedded_hal::serial::Write, +{ + fn write_str(&mut self, s: &str) -> core::fmt::Result { + for byte in s.as_bytes() { + if *byte == b'\n' { + let res = block!(self.0.try_write(b'\r')); + + if res.is_err() { + return Err(core::fmt::Error); + } + } + + let res = block!(self.0.try_write(*byte)); + + if res.is_err() { + return Err(core::fmt::Error); + } + } + Ok(()) + } +} diff --git a/tools/k210-hal/src/sysctl.rs b/tools/k210-hal/src/sysctl.rs new file mode 100644 index 0000000..f2e6649 --- /dev/null +++ b/tools/k210-hal/src/sysctl.rs @@ -0,0 +1,61 @@ +//! (TODO) System Controller (SYSCTL) + +use crate::pac::{sysctl, SYSCTL}; + +pub(crate) fn sysctl<'a>() -> &'a sysctl::RegisterBlock { + unsafe { &*(SYSCTL::ptr()) } +} + +pub(crate) fn clk_en_cent<'a>() -> &'a sysctl::CLK_EN_CENT { + &sysctl().clk_en_cent +} + +pub(crate) fn clk_en_peri<'a>() -> &'a sysctl::CLK_EN_PERI { + &sysctl().clk_en_peri +} + +pub(crate) fn peri_reset<'a>() -> &'a sysctl::PERI_RESET { + &sysctl().peri_reset +} + +pub trait SysctlExt { + fn constrain(self) -> Parts; +} + +impl SysctlExt for SYSCTL { + fn constrain(self) -> Parts { + Parts { + apb0: APB0 { _ownership: () }, + } + } +} + +// ref: sysctl.c +pub struct Parts { + // todo: PLL0, PLL1, PLL2 + // todo: CPU, SRAM, APB-bus, ROM, DMA, AI + pub apb0: APB0, + // pub apb1: APB1, + // pub apb2: APB2, +} + +pub struct APB0 { + _ownership: () +} + +impl APB0 { + pub(crate) fn enable(&mut self) { + clk_en_cent().modify( + |_r, w| + w.apb0_clk_en().set_bit() + ); + } +} + +// pub struct APB1 { +// _ownership: () +// } + +// pub struct APB2 { +// _ownership: () +// } diff --git a/tools/k210-hal/src/time.rs b/tools/k210-hal/src/time.rs new file mode 100644 index 0000000..c21a86f --- /dev/null +++ b/tools/k210-hal/src/time.rs @@ -0,0 +1,68 @@ +//! Time units + +/// Bits per second +#[derive(Clone, Copy)] +pub struct Bps(pub u32); + +/// Hertz +#[derive(Clone, Copy)] +pub struct Hertz(pub u32); + +/// KiloHertz +#[derive(Clone, Copy)] +pub struct KiloHertz(pub u32); + +/// MegaHertz +#[derive(Clone, Copy)] +pub struct MegaHertz(pub u32); + +/// Extension trait that adds convenience methods to the `u32` type +pub trait U32Ext { + /// Wrap in `Bps` + fn bps(self) -> Bps; + + /// Wrap in `Hertz` + fn hz(self) -> Hertz; + + /// Wrap in `KiloHertz` + fn khz(self) -> KiloHertz; + + /// Wrap in `MegaHertz` + fn mhz(self) -> MegaHertz; +} + +impl U32Ext for u32 { + fn bps(self) -> Bps { + Bps(self) + } + + fn hz(self) -> Hertz { + Hertz(self) + } + + fn khz(self) -> KiloHertz { + KiloHertz(self) + } + + fn mhz(self) -> MegaHertz { + MegaHertz(self) + } +} + +impl Into for KiloHertz { + fn into(self) -> Hertz { + Hertz(self.0 * 1_000) + } +} + +impl Into for MegaHertz { + fn into(self) -> Hertz { + Hertz(self.0 * 1_000_000) + } +} + +impl Into for MegaHertz { + fn into(self) -> KiloHertz { + KiloHertz(self.0 * 1_000) + } +} diff --git a/tools/k210-pac/.travis.yml b/tools/k210-pac/.travis.yml new file mode 100644 index 0000000..6fbe7e6 --- /dev/null +++ b/tools/k210-pac/.travis.yml @@ -0,0 +1,28 @@ +language: rust + +env: + - TARGET=x86_64-unknown-linux-gnu + - TARGET=riscv64gc-unknown-none-elf + +rust: + - nightly + - stable + +if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master) + + +install: + - ci/install.sh + +script: + - ci/script.sh + +branches: + only: + - master + - staging + - trying + +notifications: + email: + on_success: never diff --git a/tools/k210-pac/CODE_OF_CONDUCT.md b/tools/k210-pac/CODE_OF_CONDUCT.md new file mode 100644 index 0000000..fccadf9 --- /dev/null +++ b/tools/k210-pac/CODE_OF_CONDUCT.md @@ -0,0 +1,37 @@ +# The Rust Code of Conduct + +## Conduct + +**Contact**: [RISC-V team](https://github.com/rust-embedded/wg#the-riscv-team) + +* We are committed to providing a friendly, safe and welcoming environment for all, regardless of level of experience, gender identity and expression, sexual orientation, disability, personal appearance, body size, race, ethnicity, age, religion, nationality, or other similar characteristic. +* On IRC, please avoid using overtly sexual nicknames or other nicknames that might detract from a friendly, safe and welcoming environment for all. +* Please be kind and courteous. There's no need to be mean or rude. +* Respect that people have differences of opinion and that every design or implementation choice carries a trade-off and numerous costs. There is seldom a right answer. +* Please keep unstructured critique to a minimum. If you have solid ideas you want to experiment with, make a fork and see how it works. +* We will exclude you from interaction if you insult, demean or harass anyone. That is not welcome behavior. We interpret the term "harassment" as including the definition in the [Citizen Code of Conduct](http://citizencodeofconduct.org/); if you have any lack of clarity about what might be included in that concept, please read their definition. In particular, we don't tolerate behavior that excludes people in socially marginalized groups. +* Private harassment is also unacceptable. No matter who you are, if you feel you have been or are being harassed or made uncomfortable by a community member, please contact one of the channel ops or any of the [RISC-V team][team] immediately. Whether you're a regular contributor or a newcomer, we care about making this community a safe place for you and we've got your back. +* Likewise any spamming, trolling, flaming, baiting or other attention-stealing behavior is not welcome. + +## Moderation + +These are the policies for upholding our community's standards of conduct. + +1. Remarks that violate the Rust standards of conduct, including hateful, hurtful, oppressive, or exclusionary remarks, are not allowed. (Cursing is allowed, but never targeting another user, and never in a hateful manner.) +2. Remarks that moderators find inappropriate, whether listed in the code of conduct or not, are also not allowed. +3. Moderators will first respond to such remarks with a warning. +4. If the warning is unheeded, the user will be "kicked," i.e., kicked out of the communication channel to cool off. +5. If the user comes back and continues to make trouble, they will be banned, i.e., indefinitely excluded. +6. Moderators may choose at their discretion to un-ban the user if it was a first offense and they offer the offended party a genuine apology. +7. If a moderator bans someone and you think it was unjustified, please take it up with that moderator, or with a different moderator, **in private**. Complaints about bans in-channel are not allowed. +8. Moderators are held to a higher standard than other community members. If a moderator creates an inappropriate situation, they should expect less leeway than others. + +In the Rust community we strive to go the extra step to look out for each other. Don't just aim to be technically unimpeachable, try to be your best self. In particular, avoid flirting with offensive or sensitive issues, particularly if they're off-topic; this all too often leads to unnecessary fights, hurt feelings, and damaged trust; worse, it can drive people away from the community entirely. + +And if someone takes issue with something you said or did, resist the urge to be defensive. Just stop doing what it was they complained about and apologize. Even if you feel you were misinterpreted or unfairly accused, chances are good there was something you could've communicated better — remember that it's your responsibility to make your fellow Rustaceans comfortable. Everyone wants to get along and we are all here first and foremost because we want to talk about cool technology. You will find that people will be eager to assume good intent and forgive as long as you earn their trust. + +The enforcement policies listed above apply to all official embedded WG venues; including official IRC channels (#rust-embedded); GitHub repositories under rust-embedded; and all forums under rust-embedded.org (forum.rust-embedded.org). + +*Adapted from the [Node.js Policy on Trolling](http://blog.izs.me/post/30036893703/policy-on-trolling) as well as the [Contributor Covenant v1.3.0](https://www.contributor-covenant.org/version/1/3/0/).* + +[team]: https://github.com/rust-embedded/wg#the-riscv-team diff --git a/tools/k210-pac/Cargo.toml b/tools/k210-pac/Cargo.toml new file mode 100644 index 0000000..66080af --- /dev/null +++ b/tools/k210-pac/Cargo.toml @@ -0,0 +1,19 @@ +[package] +name = "k210-pac" +version = "0.2.0" +authors = ["The RISC-V Team "] +categories = ["embedded", "hardware-support", "no-std"] +description = "Peripheral access API for K210 SoC" +repository = "https://github.com/riscv-rust/k210-pac" +keywords = ["riscv", "k210", "register", "peripheral"] +license = "ISC" +edition = "2018" + +[dependencies] +bare-metal = "0.2.4" +riscv = "0.6.0" +riscv-rt = { version = "0.8", optional = true } +vcell = "0.1.2" + +[features] +rt = ["riscv-rt"] diff --git a/tools/k210-pac/README.md b/tools/k210-pac/README.md new file mode 100644 index 0000000..eccb942 --- /dev/null +++ b/tools/k210-pac/README.md @@ -0,0 +1,36 @@ +[![crates.io](https://img.shields.io/crates/d/k210-pac.svg)](https://crates.io/crates/k210-pac) +[![crates.io](https://img.shields.io/crates/v/k210-pac.svg)](https://crates.io/crates/k210-pac) +[![Build Status](https://travis-ci.org/riscv-rust/k210-pac.svg?branch=master)](https://travis-ci.org/riscv-rust/k210-pac) + +# `k210-pac` + +> Peripheral access API for K210 SoC + +This project is developed and maintained by the [RISC-V team][team]. + +## [Documentation](https://docs.rs/crate/k210-pac) + +## License + +Copyright 2019 [RISC-V team][team] + +Permission to use, copy, modify, and/or distribute this software for any +purpose with or without fee is hereby granted, provided that the above +copyright notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +## Code of Conduct + +Contribution to this crate is organized under the terms of the [Rust Code of +Conduct][CoC], the maintainer of this crate, the [RISC-V team][team], promises +to intervene to uphold that code of conduct. + +[CoC]: CODE_OF_CONDUCT.md +[team]: https://github.com/rust-embedded/wg#the-risc-v-team diff --git a/tools/k210-pac/build.rs b/tools/k210-pac/build.rs new file mode 100644 index 0000000..41ec77f --- /dev/null +++ b/tools/k210-pac/build.rs @@ -0,0 +1,15 @@ +use std::io::Write; +use std::path::PathBuf; +use std::{env, fs}; + +fn main() { + // Put the linker script somewhere the linker can find it + let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap()); + println!("cargo:rustc-link-search={}", out_dir.display()); + + fs::File::create(out_dir.join("memory-k210.x")) + .unwrap() + .write_all(include_bytes!("memory-k210.x")) + .unwrap(); + println!("cargo:rerun-if-changed=memory-k210.x"); +} diff --git a/tools/k210-pac/ci/install.sh b/tools/k210-pac/ci/install.sh new file mode 100755 index 0000000..ce4ea1e --- /dev/null +++ b/tools/k210-pac/ci/install.sh @@ -0,0 +1,5 @@ +#!/bin/bash + +set -euxo pipefail + +rustup target add $TARGET diff --git a/tools/k210-pac/ci/script.sh b/tools/k210-pac/ci/script.sh new file mode 100755 index 0000000..70fa0f4 --- /dev/null +++ b/tools/k210-pac/ci/script.sh @@ -0,0 +1,6 @@ +#!/bin/bash + +set -euxo pipefail + +cargo check --target $TARGET +cargo check --target $TARGET --features rt diff --git a/tools/k210-pac/k210.svd b/tools/k210-pac/k210.svd new file mode 100644 index 0000000..c2f9933 --- /dev/null +++ b/tools/k210-pac/k210.svd @@ -0,0 +1,7718 @@ + + + Canaan Inc. + K210 + 1.0 + Kendryte K210 64-bit RISC-V CPU + + 8 + 64 + 32 + read-write + + + 0x00000000 + 0xFFFFFFFF + + + + + CLINT + Core Local Interruptor + CLINT + 0x02000000 + + + 2 + 0x04 + msip[%s] + Hart software interrupt register + 0x0000 + + + 0 + 1 + + + + + 64 + 2 + 0x08 + mtimecmp[%s] + Hart time comparator register + 0x4000 + + + 64 + mtime + Timer register + 0xBFF8 + + + + + + + + PLIC + Platform-Level Interrupt Controller + PLIC + 0x0C000000 + + + 1024 + 0x04 + priority[%s] + Interrupt Source Priority Register + 0x000000 + + + + + 32 + 0x04 + pending[%s] + Interrupt Pending Register + 0x001000 + + + target_enables[%s] + Target Interrupt Enables + 0x002000 + 4 + 0x80 + + 32 + 0x04 + enable[%s] + Interrupt Enable Register + 0 + + + + targets[%s] + Target Configuration + 0x200000 + 4 + 0x1000 + + threshold + Priority Threshold Register + 0x0 + + + priority + 20 + + Priority + + Never + Never interrupt + 0 + + + P1 + Priority 1 + 1 + + + P2 + Priority 2 + 2 + + + P3 + Priority 3 + 3 + + + P4 + Priority 4 + 4 + + + P5 + Priority 5 + 5 + + + P6 + Priority 6 + 6 + + + P7 + Priority 7 + 7 + + + + + + + claim + Claim/Complete Register + 0x4 + + 0x00000000 + 0xFFFFFFFF + + + + _reserved + Padding to make sure targets is an array + 0xffc + + + + + + + + + UARTHS + High-speed UART + UARTHS + 0x38000000 + + + txdata + Transmit Data Register + 0x00 + + + data + Transmit data + [7:0] + + + full + Transmit FIFO full + [31:31] + + + + + + rxdata + Receive Data Register + 0x04 + + + data + Received data + [7:0] + + + empty + Receive FIFO empty + [31:31] + + + + + + txctrl + Transmit Control Register + 0x08 + + + txen + Transmit enable + [0:0] + + + nstop + Number of stop bits + [1:1] + + + txcnt + Transmit watermark level + [18:16] + + + + + + rxctrl + Receive Control Register + 0x0C + + + rxen + Receive enable + [0:0] + + + rxcnt + Receive watermark level + [18:16] + + + + + + ie + Interrupt Enable Register + 0x10 + + + txwm + Transmit watermark interrupt enable + [0:0] + + + rxwm + Receive watermark interrupt enable + [1:1] + + + + + + ip + Interrupt Pending Register + 0x14 + + + txwm + Transmit watermark interrupt pending + [0:0] + + + rxwm + Receive watermark interrupt pending + [1:1] + + + + + + div + Baud Rate Divisor Register + 0x18 + + + div + Baud rate divisor + [15:0] + + + + + + UARTHS + 33 + + + + + + + GPIOHS + High-speed GPIO + GPIOHS + 0x38001000 + + + input_val + Input Value Register + 0x000 + + + pin%s + 0 + 0 + 32 + 1 + + + + + input_en + Pin Input Enable Register + 0x004 + + + pin%s + 0 + 0 + 32 + 1 + + + + + output_en + Pin Output Enable Register + 0x008 + + + pin%s + 0 + 0 + 32 + 1 + + + + + output_val + Output Value Register + 0x00C + + + pin%s + 0 + 0 + 32 + 1 + + + + + pullup_en + Internal Pull-Up Enable Register + 0x010 + + + pin%s + 0 + 0 + 32 + 1 + + + + + drive + Drive Strength Register + 0x014 + + + pin%s + 0 + 0 + 32 + 1 + + + + + rise_ie + Rise Interrupt Enable Register + 0x018 + + + pin%s + 0 + 0 + 32 + 1 + + + + + rise_ip + Rise Interrupt Pending Register + 0x01C + + + pin%s + 0 + 0 + 32 + 1 + + + + + fall_ie + Fall Interrupt Enable Register + 0x020 + + + pin%s + 0 + 0 + 32 + 1 + + + + + fall_ip + Fall Interrupt Pending Register + 0x024 + + + pin%s + 0 + 0 + 32 + 1 + + + + + high_ie + High Interrupt Enable Register + 0x028 + + + pin%s + 0 + 0 + 32 + 1 + + + + + high_ip + High Interrupt Pending Register + 0x02C + + + pin%s + 0 + 0 + 32 + 1 + + + + + low_ie + Low Interrupt Enable Register + 0x030 + + + pin%s + 0 + 0 + 32 + 1 + + + + + low_ip + Low Interrupt Pending Register + 0x034 + + + pin%s + 0 + 0 + 32 + 1 + + + + + iof_en + HW I/O Function Enable Register + 0x038 + + + pin%s + 0 + 0 + 32 + 1 + + + + + iof_sel + HW I/O Function Select Register + 0x03C + + + pin%s + 0 + 0 + 32 + 1 + + + + + output_xor + Output XOR (invert) Register + 0x040 + + + pin%s + 0 + 0 + 32 + 1 + + + + + + GPIOHS0 + 34 + + + GPIOHS1 + 35 + + + GPIOHS2 + 36 + + + GPIOHS3 + 37 + + + GPIOHS4 + 38 + + + GPIOHS5 + 39 + + + GPIOHS6 + 40 + + + GPIOHS7 + 41 + + + GPIOHS8 + 42 + + + GPIOHS9 + 43 + + + GPIOHS10 + 44 + + + GPIOHS11 + 45 + + + GPIOHS12 + 46 + + + GPIOHS13 + 47 + + + GPIOHS14 + 48 + + + GPIOHS15 + 49 + + + GPIOHS16 + 50 + + + GPIOHS17 + 51 + + + GPIOHS18 + 52 + + + GPIOHS19 + 53 + + + GPIOHS20 + 54 + + + GPIOHS21 + 55 + + + GPIOHS22 + 56 + + + GPIOHS23 + 57 + + + GPIOHS24 + 58 + + + GPIOHS25 + 59 + + + GPIOHS26 + 60 + + + GPIOHS27 + 61 + + + GPIOHS28 + 62 + + + GPIOHS29 + 63 + + + GPIOHS30 + 64 + + + GPIOHS31 + 65 + + + + + + + KPU + Neural Network Accelerator + KPU + 0x40800000 + + + + layer_argument_fifo + Layer arguments FIFO: each layer is defined by writing 12 successive argument values to this register + 0x00 + 64 + + + interrupt_status + Interrupt status + 0x08 + 64 + + + calc_done + Interrupt raised when calculation is done + [0:0] + + + layer_cfg_almost_empty + Interrupt raised when layer arguments FIFO almost empty + [1:1] + + + layer_cfg_almost_full + Interrupt raised when layer arguments FIFO almost full + [2:2] + + + + + interrupt_raw + Interrupt raw + 0x10 + 64 + + + interrupt_mask + Interrupt mask: 0 enables the interrupt, 1 masks the interrupt + 0x18 + 64 + + + interrupt_clear + Interrupt clear: write 1 to a bit to clear interrupt + 0x20 + 64 + + + fifo_threshold + FIFO threshold + 0x28 + 64 + + + full_threshold + FIFO full threshold + [3:0] + + + empty_threshold + FIFO empty threshold + [7:4] + + + + + fifo_data_out + FIFO data output + 0x30 + 64 + + + fifo_ctrl + FIFO control + 0x38 + 64 + + + dma_fifo_flush_n + Flush DMA FIFO + [0:0] + + + gs_fifo_flush_n + Flush GS FIFO + [1:1] + + + cfg_fifo_flush_n + Flush configuration FIFO + [2:2] + + + cmd_fifo_flush_n + Flush command FIFO + [3:3] + + + resp_fifo_flush_n + Flush response FIFO + [4:4] + + + + + eight_bit_mode + Eight bit mode + 0x40 + 64 + + + eight_bit_mode + Use 8-bit instead of 16-bit precision if set + [0:0] + + + + + + KPU + 25 + + + + + + + FFT + Fast Fourier Transform Accelerator + FFT + 0x42000000 + + + input_fifo + FFT input data fifo + 0x00 + 64 + + + ctrl + FFT control register + 0x08 + 64 + + + point + FFT calculation data length + [2:0] + + + p512 + 512 point + 0 + + + p256 + 256 point + 1 + + + p128 + 128 point + 2 + + + p64 + 64 point + 3 + + + + + mode + FFT mode + [3:3] + + + fft + FFT mode + 0 + + + ifft + Inverse FFT mode + 1 + + + + + shift + Corresponding to the nine layer butterfly shift operation, 0x0: does not shift; 0x1: shift 1st layer. ... + [12:4] + + + enable + FFT enable + [13:13] + + + dma_send + FFT DMA enable + [14:14] + + + input_mode + Input data arrangement + [16:15] + + + riri + RIRI (real imaginary interleaved) + 0 + + + rrrr + RRRR (only real part) + 1 + + + rrii + First input the real part and then input the imaginary part + 2 + + + + + data_mode + Effective width of input data + [17:17] + + + width_64 + 64 bit effective + 0 + + + width_128 + 128 bit effective + 1 + + + + + + + + fifo_ctrl + FIFO control + 0x10 + 64 + + + resp_fifo_flush + Response memory initialization flag + [0:0] + + + cmd_fifo_flush + Command memory initialization flag + [1:1] + + + gs_fifo_flush + Output interface memory initialization flag + [2:2] + + + + + + intr_mask + interrupt mask + 0x18 + 64 + + + fft_done + FFT done + [0:0] + + + + + + intr_clear + Interrupt clear + 0x20 + 64 + + + fft_done + FFT done + [0:0] + + + + + + status + FFT status register + 0x28 + 64 + + + fft_done + FFT done + [0:0] + + + + + + status_raw + FFT status raw + 0x30 + 64 + + + fft_done + FFT done + [0:0] + + + fft_work + FFT work + [1:1] + + + + + + output_fifo + FFT output FIFO + 0x38 + 64 + + + + FFT + 26 + + + + + + + DMAC + Direct Memory Access Controller + DMAC + 0x50000000 + + + + id + ID Register + 0x00 + 64 + + + compver + COMPVER Register + 0x08 + 64 + + + cfg + Configure Register + 0x10 + 64 + + + dmac_en + Enable DMAC + [0:0] + + + int_en + Globally enable interrupt generation + [1:1] + + + + + + chen + Channel Enable Register + 0x18 + 64 + + + ch%s_en + Enable channel %s + [0:0] + 6 + 1 + 1-6 + + + + ch%s_en_we + Write enable channel %s + [8:8] + 6 + 1 + 1-6 + + + + ch%s_susp + Suspend request channel %s + [16:16] + 6 + 1 + 1-6 + + + + ch%s_susp_we + Enable write to ch%s_susp bit + [24:24] + 6 + 1 + 1-6 + + + + ch%s_abort + Abort request channel %s + [32:32] + 6 + 1 + 1-6 + + + + ch%s_abort_we + Enable write to ch%s_abort bit + [40:40] + 6 + 1 + 1-6 + + + + + + + intstatus + Interrupt Status Register + 0x30 + 64 + + + ch%s_intstat + Channel %s interrupt bit + [0:0] + 6 + 1 + 1-6 + + + + commonreg_intstat + Common register status bit + [16:16] + + + + + + com_intclear + Common Interrupt Clear Register + 0x38 + 64 + + + slvif_dec_err + Clear slvif_dec_err interrupt in com_intstatus + [0:0] + + + slvif_wr2ro_err + Clear slvif_wr2ro_err interrupt in com_intstatus + [1:1] + + + slvif_rd2wo_err + Clear slvif_rd2wo_err interrupt in com_intstatus + [2:2] + + + slvif_wronhold_err + Clear slvif_wronhold_err interrupt in com_intstatus + [3:3] + + + + slvif_undefinedreg_dec_err + Clear slvif_undefinedreg_dec_err in com_intstatus + [8:8] + + + + + + com_intstatus_en + Common Interrupt Status Enable Register + 0x40 + 64 + + + slvif_dec_err + Slave Interface Common Register Decode Error + [0:0] + + + slvif_wr2ro_err + Slave Interface Common Register Write to Read only Error + [1:1] + + + slvif_rd2wo_err + Slave Interface Common Register Read to Write-only Error + [2:2] + + + slvif_wronhold_err + Slave Interface Common Register Write On Hold Error + [3:3] + + + + slvif_undefinedreg_dec_err + Slave Interface Undefined Register Decode Error + [8:8] + + + + + + com_intsignal_en + Common Interrupt Signal Enable Register + 0x48 + 64 + + + slvif_dec_err + Slave Interface Common Register Decode Error + [0:0] + + + slvif_wr2ro_err + Slave Interface Common Register Write to Read only Error + [1:1] + + + slvif_rd2wo_err + Slave Interface Common Register Read to Write-only Error + [2:2] + + + slvif_wronhold_err + Slave Interface Common Register Write On Hold Error + [3:3] + + + + slvif_undefinedreg_dec_err + Slave Interface Undefined Register Decode Error + [8:8] + + + + + + com_intstatus + Common Interrupt Status + 0x50 + 64 + + + slvif_dec_err + Slave Interface Common Register Decode Error + [0:0] + + + slvif_wr2ro_err + Slave Interface Common Register Write to Read only Error + [1:1] + + + slvif_rd2wo_err + Slave Interface Common Register Read to Write-only Error + [2:2] + + + slvif_wronhold_err + Slave Interface Common Register Write On Hold Error + [3:3] + + + + slvif_undefinedreg_dec_err + Slave Interface Undefined Register Decode Error + [8:8] + + + + + + reset + Reset register + 0x58 + 64 + + + rst + DMAC reset request bit + [0:0] + + + + + + + channel[%s] + Channel configuration + 6 + 0x100 + 0x100 + 64 + + sar + SAR Address Register + 0x00 + + + dar + DAR Address Register + 0x08 + + + block_ts + Block Transfer Size Register + 0x10 + + + block_ts + Block transfer size + [21:0] + + + + + + ctl + Control Register + 0x18 + + + sms + Source master select + [0:0] + + MASTER_SELECT + + axi_master_1 + AXI master 1 + 0 + + + axi_master_2 + AXI master 2 + 1 + + + + + + dms + Destination master select + [2:2] + + + + + sinc + Source address increment + [4:4] + + INCREMENT + + increment + Increment address + 0 + + + nochange + Don't increment address + 1 + + + + + + dinc + Destination address increment + [6:6] + + + + + src_tr_width + Source transfer width + [10:8] + + TRANSFER_WIDTH + + width_8 + 8 bits + 0 + + + width_16 + 16 bits + 1 + + + width_32 + 32 bits + 2 + + + width_64 + 64 bits + 3 + + + width_128 + 128 bits + 4 + + + width_256 + 256 bits + 5 + + + width_512 + 512 bits + 6 + + + + + dst_tr_width + Destination transfer width + [13:11] + + + + src_msize + Source burst transaction length + [17:14] + + BURST_LENGTH + + length_1 + 1 data item + 0 + + + length_4 + 4 data items + 1 + + + length_8 + 8 data items + 2 + + + length_16 + 16 data items + 3 + + + length_32 + 32 data items + 4 + + + length_64 + 64 data items + 5 + + + length_128 + 128 data items + 6 + + + length_256 + 256 data items + 7 + + + length_512 + 512 data items + 8 + + + length_1024 + 1024 data items + 9 + + + + + dst_msize + Destination burst transaction length + [21:18] + + + + + nonposted_lastwrite_en + Non Posted Last Write Enable (posted writes may be used till the end of the block) + [30:30] + + + + arlen_en + Source burst length enable + [38:38] + + + arlen + Source burst length + [46:39] + + + awlen_en + Destination burst length enable + [47:47] + + + awlen + Destination burst length + [55:48] + + + src_stat_en + Source status enable + [56:56] + + + dst_stat_en + Destination status enable + [57:57] + + + ioc_blktfr + Interrupt completion of block transfer + [58:58] + + + + shadowreg_or_lli_last + Last shadow linked list item (indicates shadowreg/LLI content is the last one) + [62:62] + + + shadowreg_or_lli_valid + last shadow linked list item valid (indicate shadowreg/LLI content is valid) + [63:63] + + + + + cfg + Configure Register + 0x20 + + + src_multblk_type + Source multi-block transfer type + [1:0] + + MULTIBLK_TRANSFER_TYPE + + contiguous + Continuous multi-block type + 0 + + + reload + Reload multi-block type + 1 + + + shadow_register + Shadow register based multi-block type + 2 + + + linked_list + Linked list based multi-block type + 3 + + + + + dst_multblk_type + Destination multi-block transfer type + [3:2] + + + + + tt_fc + Transfer type and flow control + [34:32] + + + mem2mem_dma + Transfer memory to memory and flow controller is DMAC + 0 + + + mem2prf_dma + Transfer memory to peripheral and flow controller is DMAC + 1 + + + prf2mem_dma + Transfer peripheral to memory and flow controller is DMAC + 2 + + + prf2prf_dma + Transfer peripheral to peripheral and flow controller is DMAC + 3 + + + prf2mem_prf + Transfer peripheral to memory and flow controller is source peripheral + 4 + + + prf2prf_srcprf + Transfer peripheral to peripheral and flow controller is source peripheral + 5 + + + mem2prf_prf + Transfer memory to peripheral and flow controller is destination peripheral + 6 + + + prf2prf_dstprf + Transfer peripheral to peripheral and flow controller is destination peripheral + 7 + + + + + hs_sel_src + Source software or hardware handshaking select + [35:35] + + HANDSHAKING + + hardware + Hardware handshaking is used + 0 + + + software + Software handshaking is used + 1 + + + + + hs_sel_dst + Destination software or hardware handshaking select + [36:36] + + + + src_hwhs_pol + Source hardware handshaking interface polarity + [37:37] + + POLARITY + + active_high + Active high + 0 + + + active_low + Active low + 1 + + + + + dst_hwhs_pol + Destination hardware handshaking interface polarity + [38:38] + + + + src_per + Assign a hardware handshaking interface to source of channel + [42:39] + + + + dst_per + Assign a hardware handshaking interface to destination of channel + [47:44] + + + + ch_prior + Channel priority (7 is highest, 0 is lowest) + [51:49] + + + lock_ch + Channel lock bit + [52:52] + + + lock_ch_l + Channel lock level + [54:53] + + + dma_transfer + Duration of channel is locked for entire DMA transfer + 0 + + + block_transfer + Duration of channel is locked for current block transfer + 1 + + + transaction + Duration of channel is locked for current transaction + 2 + + + + + src_osr_lmt + Source outstanding request limit + [58:55] + + + dst_osr_lmt + Destination outstanding request limit + [62:59] + + + + + + llp + Linked List Pointer register + 0x28 + + + lms + LLI master select + [0:0] + + + + + loc + Starting address memeory of LLI block + [63:6] + + + + + status + Channel Status Register + 0x30 + + + cmpltd_blk_size + Completed block transfer size + [21:0] + + + + + + swhssrc + Channel Software handshake Source Register + 0x38 + + + req + Software handshake request for channel source + [0:0] + + + req_we + Write enable bit for software handshake request + [1:1] + + + sglreq + Software handshake single request for channel source + [2:2] + + + sglreq_we + Write enable bit for software handshake + [3:3] + + + lst + Software handshake last request for channel source + [4:4] + + + lst_we + Write enable bit for software handshake last request + [5:5] + + + + + + swhsdst + Channel Software handshake Destination Register + 0x40 + + + req + Software handshake request for channel destination + [0:0] + + + req_we + Write enable bit for software handshake request + [1:1] + + + sglreq + Software handshake single request for channel destination + [2:2] + + + sglreq_we + Write enable bit for software handshake + [3:3] + + + lst + Software handshake last request for channel destination + [4:4] + + + lst_we + Write enable bit for software handshake last request + [5:5] + + + + + + blk_tfr + Channel Block Transfer Resume Request Register + 0x48 + + + resumereq + Block transfer resume request + [0:0] + + + + + + axi_id + Channel AXI ID Register + 0x50 + + + axi_qos + AXI QOS Register + 0x58 + + + + intstatus_en + Interrupt Status Enable Register + 0x80 + + + block_tfr_done + Block transfer done + [0:0] + + + tfr_done + Transfer done + [1:1] + + + + src_transcomp + Source transaction complete + [3:3] + + + dst_transcomp + Destination transaction complete + [4:4] + + + src_dec_err + Source Decode Error + [5:5] + + + dst_dec_err + Destination Decode Error + [6:6] + + + src_slv_err + Source Slave Error + [7:7] + + + dst_slv_err + Destination Slave Error + [8:8] + + + lli_rd_dec_err + LLI Read Decode Error Status Enable + [9:9] + + + lli_wr_dec_err + LLI WRITE Decode Error + [10:10] + + + lli_rd_slv_err + LLI Read Slave Error + [11:11] + + + lli_wr_slv_err + LLI WRITE Slave Error + [12:12] + + + + + + intstatus + Channel Interrupt Status Register + 0x88 + + + block_tfr_done + Block transfer done + [0:0] + + + tfr_done + Transfer done + [1:1] + + + + src_transcomp + Source transaction complete + [3:3] + + + dst_transcomp + Destination transaction complete + [4:4] + + + src_dec_err + Source Decode Error + [5:5] + + + dst_dec_err + Destination Decode Error + [6:6] + + + src_slv_err + Source Slave Error + [7:7] + + + dst_slv_err + Destination Slave Error + [8:8] + + + lli_rd_dec_err + LLI Read Decode Error Status Enable + [9:9] + + + lli_wr_dec_err + LLI WRITE Decode Error + [10:10] + + + lli_rd_slv_err + LLI Read Slave Error + [11:11] + + + lli_wr_slv_err + LLI WRITE Slave Error + [12:12] + + + + + + intsignal_en + Interrupt Signal Enable Register + 0x90 + + + block_tfr_done + Block transfer done + [0:0] + + + tfr_done + Transfer done + [1:1] + + + + src_transcomp + Source transaction complete + [3:3] + + + dst_transcomp + Destination transaction complete + [4:4] + + + src_dec_err + Source Decode Error + [5:5] + + + dst_dec_err + Destination Decode Error + [6:6] + + + src_slv_err + Source Slave Error + [7:7] + + + dst_slv_err + Destination Slave Error + [8:8] + + + lli_rd_dec_err + LLI Read Decode Error Status Enable + [9:9] + + + lli_wr_dec_err + LLI WRITE Decode Error + [10:10] + + + lli_rd_slv_err + LLI Read Slave Error + [11:11] + + + lli_wr_slv_err + LLI WRITE Slave Error + [12:12] + + + + + + intclear + Interrupt Clear Register + 0x98 + + + block_tfr_done + Block transfer done + [0:0] + + + tfr_done + Transfer done + [1:1] + + + + src_transcomp + Source transaction complete + [3:3] + + + dst_transcomp + Destination transaction complete + [4:4] + + + src_dec_err + Source Decode Error + [5:5] + + + dst_dec_err + Destination Decode Error + [6:6] + + + src_slv_err + Source Slave Error + [7:7] + + + dst_slv_err + Destination Slave Error + [8:8] + + + lli_rd_dec_err + LLI Read Decode Error Status Enable + [9:9] + + + lli_wr_dec_err + LLI WRITE Decode Error + [10:10] + + + lli_rd_slv_err + LLI Read Slave Error + [11:11] + + + lli_wr_slv_err + LLI WRITE Slave Error + [12:12] + + + + + + + _reserved + Padding to make structure size 256 bytes so that channels[] is an array + 0xf8 + + + + + DMA0 + 27 + + + DMA1 + 28 + + + DMA2 + 29 + + + DMA3 + 30 + + + DMA4 + 31 + + + DMA5 + 32 + + + + + + + GPIO + General Purpose Input/Output Interface + GPIO + 0x50200000 + + + data_output + Data (output) registers + 0x00 + + + pin%s + 0 + 0 + 8 + 1 + + + + + direction + Data direction registers + 0x04 + + + pin%s + 0 + 0 + 8 + 1 + + DIRECTION + + input + Pin is input + 0 + + + output + Pin is output + 1 + + + + + + + source + Data source registers + 0x08 + + + interrupt_enable + Interrupt enable/disable registers + 0x30 + + + interrupt_mask + Interrupt mask registers + 0x34 + + + interrupt_level + Interrupt level registers + 0x38 + + + interrupt_polarity + Interrupt polarity registers + 0x3c + + + interrupt_status + Interrupt status registers + 0x40 + + + interrupt_status_raw + Raw interrupt status registers + 0x44 + + + interrupt_debounce + Interrupt debounce registers + 0x48 + + + interrupt_clear + Registers for clearing interrupts + 0x4c + + + data_input + External port (data input) registers + 0x50 + + + pin%s + 0 + 0 + 8 + 1 + + + + + sync_level + Sync level registers + 0x60 + + + id_code + ID code + 0x64 + + + interrupt_bothedge + Interrupt both edge type + 0x68 + + + + APB_GPIO + 23 + + + + + + + UART1 + Universal Asynchronous Receiver-Transmitter 1 + UART + 0x50210000 + + + rbr_dll_thr + Receive Buffer Register / Divisor Latch (Low) / Transmit Holding Register (depending on context and R/W) + 0x00 + + + dlh_ier + Divisor Latch (High) / Interrupt Enable Register + 0x04 + + + fcr_iir + FIFO Control Register / Interrupt Identification Register + 0x08 + + + lcr + Line Control Register + 0x0c + + + mcr + Modem Control Register + 0x10 + + + lsr + Line Status Register + 0x14 + + + msr + Modem Status Register + 0x18 + + + scr + Scratchpad Register + 0x1c + + + lpdll + Low Power Divisor Latch (Low) Register + 0x20 + + + lpdlh + Low Power Divisor Latch (High) Register + 0x24 + + + srbr_sthr[%s] + 16 + 4 + Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W) + 0x30 + + + far + FIFO Access Register + 0x70 + + + tfr + Transmit FIFO Read Register + 0x74 + + + rfw + Receive FIFO Write Register + 0x78 + + + usr + UART Status Register + 0x7c + + + tfl + Transmit FIFO Level + 0x80 + + + rfl + Receive FIFO Level + 0x84 + + + srr + Software Reset Register + 0x88 + + + srts + Shadow Request to Send Register + 0x8c + + + sbcr + Shadow Break Control Register + 0x90 + + + sdmam + Shadow DMA Mode + 0x94 + + + sfe + Shadow FIFO Enable + 0x98 + + + srt + Shadow RCVR Trigger Register + 0x9c + + + stet + Shadow TX Empty Trigger Register + 0xa0 + + + htx + Halt TX Regster + 0xa4 + + + dmasa + DMA Software Acknowledge Register + 0xa8 + + + tcr + Transfer Control Register + 0xac + + + de_en + DE Enable Register + 0xb0 + + + re_en + RE Enable Register + 0xb4 + + + det + DE Assertion Time Register + 0xb8 + + + tat + Turn-Around Time Register + 0xbc + + + dlf + Divisor Latch (Fractional) Register + 0xc0 + + + rar + Receive-Mode Address Register + 0xc4 + + + tar + Transmit-Mode Address Register + 0xc8 + + + lcr_ext + Line Control Register (Extended) + 0xcc + + + cpr + Component Parameter Register + 0xf4 + + + ucv + UART Component Version + 0xf8 + + + ctr + Component Type Register + 0xfc + + + + UART1 + 11 + + + + + + + UART2 + Universal Asynchronous Receiver-Transmitter 2 + 0x50220000 + + UART2 + 12 + + + + + + + UART3 + Universal Asynchronous Receiver-Transmitter 3 + 0x50230000 + + UART3 + 13 + + + + + + + SPI0 + Serial Peripheral Interface 0 (master) + SPI + 0x52000000 + + + + ctrlr0 + Control Register 0 + 0x00 + + + work_mode + WORK_MODE + [7:6] + + + mode0 + MODE_0 + 0 + + + mode1 + MODE_1 + 1 + + + mode2 + MODE_2 + 2 + + + mode3 + MODE_3 + 3 + + + + + tmod + TRANSFER_MODE + [9:8] + + + trans_recv + TRANS_RECV + 0 + + + trans + TRANS + 1 + + + recv + RECV + 2 + + + eerom + EEROM + 3 + + + + + frame_format + FRAME_FORMAT + [22:21] + + + standard + STANDARD + 0 + + + dual + DUAL + 1 + + + quad + QUAD + 2 + + + octal + OCTAL + 3 + + + + + data_length + DATA_BIT_LENGTH + [20:16] + 331 + + + + + + ctrlr1 + Control Register 1 + 0x04 + + + + ssienr + Enable Register + 0x08 + + + + mwcr + Microwire Control Register + 0x0c + + + + ser + Slave Enable Register + 0x10 + + + + baudr + Baud Rate Select + 0x14 + + + + txftlr + Transmit FIFO Threshold Level + 0x18 + + + + rxftlr + Receive FIFO Threshold Level + 0x1c + + + + txflr + Transmit FIFO Level Register + 0x20 + + + + rxflr + Receive FIFO Level Register + 0x24 + + + + sr + Status Register + 0x28 + + + + imr + Interrupt Mask Register + 0x2c + + + + isr + Interrupt Status Register + 0x30 + + + risr + Raw Interrupt Status Register + 0x34 + + + + txoicr + Transmit FIFO Overflow Interrupt Clear Register + 0x38 + + + + rxoicr + Receive FIFO Overflow Interrupt Clear Register + 0x3c + + + + rxuicr + Receive FIFO Underflow Interrupt Clear Register + 0x40 + + + + msticr + Multi-Master Interrupt Clear Register + 0x44 + + + + icr + Interrupt Clear Register + 0x48 + + + + dmacr + DMA Control Register + 0x4c + + + + dmatdlr + DMA Transmit Data Level + 0x50 + + + + dmardlr + DMA Receive Data Level + 0x54 + + + + idr + Identification Register + 0x58 + + + + ssic_version_id + DWC_ssi component version + 0x5c + + + + dr%s + Data Register + 0x60 + 36 + 0-35 + 0x4 + + + + rx_sample_delay + RX Sample Delay Register + 0xf0 + + + + spi_ctrlr0 + SPI Control Register + 0xf4 + + + aitm + instruction_address_trans_mode + [1:0] + + + standard + STANDARD + 0 + + + addr_standard + ADDR_STANDARD + 1 + + + as_frame_format + AS_FRAME_FORMAT + 2 + + + + + addr_length + ADDR_LENGTH + [5:2] + + + inst_length + INSTRUCTION_LENGTH + [9:8] + + + wait_cycles + WAIT_CYCLES + [15:11] + 031 + + + + + + xip_mode_bits + XIP Mode bits + 0xfc + + + xip_incr_inst + XIP INCR transfer opcode + 0x100 + + + + xip_wrap_inst + XIP WRAP transfer opcode + 0x104 + + + xip_ctrl + XIP Control Register + 0x108 + + + + xip_ser + XIP Slave Enable Register + 0x10c + + + + xrxoicr + XIP Receive FIFO Overflow Interrupt Clear Register + 0x110 + + + + xip_cnt_time_out + XIP time out register for continuous transfers + 0x114 + + + + endian + ENDIAN + 0x118 + + + + SPI0 + 1 + + + + + + + SPI1 + Serial Peripheral Interface 1 (master) + 0x53000000 + + SPI1 + 2 + + + + + + + SPI2 + Serial Peripheral Interface 2 (slave) + 0x50240000 + + + + dummy + Dummy register: this peripheral is not implemented yet + 0x00 + + + + SPI_SLAVE + 3 + + + + + + + SPI3 + Serial Peripheral Interface 3 (master) + 0x54000000 + + + + ctrlr0 + Control Register 0 + 0x00 + + + data_length + DATA_BIT_LENGTH + [4:0] + 331 + + + work_mode + WORK_MODE + [9:8] + + + mode0 + MODE_0 + 0 + + + mode1 + MODE_1 + 1 + + + mode2 + MODE_2 + 2 + + + mode3 + MODE_3 + 3 + + + + + tmod + TRANSFER_MODE + [11:10] + + + trans_recv + TRANS_RECV + 0 + + + trans + TRANS + 1 + + + recv + RECV + 2 + + + eerom + EEROM + 3 + + + + + frame_format + FRAME_FORMAT + [23:22] + + + standard + STANDARD + 0 + + + dual + DUAL + 1 + + + quad + QUAD + 2 + + + octal + OCTAL + 3 + + + + + + + + ctrlr1 + Control Register 1 + 0x04 + + + + ssienr + Enable Register + 0x08 + + + + mwcr + Microwire Control Register + 0x0c + + + + ser + Slave Enable Register + 0x10 + + + + baudr + Baud Rate Select + 0x14 + + + + txftlr + Transmit FIFO Threshold Level + 0x18 + + + + rxftlr + Receive FIFO Threshold Level + 0x1c + + + + txflr + Transmit FIFO Level Register + 0x20 + + + + rxflr + Receive FIFO Level Register + 0x24 + + + + sr + Status Register + 0x28 + + + + imr + Interrupt Mask Register + 0x2c + + + + isr + Interrupt Status Register + 0x30 + + + risr + Raw Interrupt Status Register + 0x34 + + + + txoicr + Transmit FIFO Overflow Interrupt Clear Register + 0x38 + + + + rxoicr + Receive FIFO Overflow Interrupt Clear Register + 0x3c + + + + rxuicr + Receive FIFO Underflow Interrupt Clear Register + 0x40 + + + + msticr + Multi-Master Interrupt Clear Register + 0x44 + + + + icr + Interrupt Clear Register + 0x48 + + + + dmacr + DMA Control Register + 0x4c + + + + dmatdlr + DMA Transmit Data Level + 0x50 + + + + dmardlr + DMA Receive Data Level + 0x54 + + + + idr + Identification Register + 0x58 + + + + ssic_version_id + DWC_ssi component version + 0x5c + + + + dr%s + Data Register + 0x60 + 36 + 0-35 + 0x4 + + + + rx_sample_delay + RX Sample Delay Register + 0xf0 + + + + spi_ctrlr0 + SPI Control Register + 0xf4 + + + aitm + instruction_address_trans_mode + [1:0] + + + standard + STANDARD + 0 + + + addr_standard + ADDR_STANDARD + 1 + + + as_frame_format + AS_FRAME_FORMAT + 2 + + + + + addr_length + ADDR_LENGTH + [5:2] + + + inst_length + INSTRUCTION_LENGTH + [9:8] + + + wait_cycles + WAIT_CYCLES + [15:11] + 031 + + + + + + xip_mode_bits + XIP Mode bits + 0xfc + + + xip_incr_inst + XIP INCR transfer opcode + 0x100 + + + + xip_wrap_inst + XIP WRAP transfer opcode + 0x104 + + + xip_ctrl + XIP Control Register + 0x108 + + + + xip_ser + XIP Slave Enable Register + 0x10c + + + + xrxoicr + XIP Receive FIFO Overflow Interrupt Clear Register + 0x110 + + + + xip_cnt_time_out + XIP time out register for continuous transfers + 0x114 + + + + endian + ENDIAN + 0x118 + + + + SPI3 + 4 + + + + + + + I2S0 + Inter-Integrated Sound Interface 0 + I2S + 0x50250000 + + + + ier + Enable Register + 0x00 + + + ien + I2S Enable + [0:0] + + + + + irer + Receiver Block Enable Register + 0x04 + + + rxen + Receiver block enable + [0:0] + + + + + iter + Transmitter Block Enable Register + 0x08 + + + txen + Transmitter block enable + [0:0] + + + + + cer + Clock Generation enable + 0x0c + + + clken + Transmitter block enable + [0:0] + + + + + ccr + Clock Configuration Register + 0x10 + + + clk_gate + Gating of sclk + [2:0] + + + no + Clock gating is disabled + 0 + + + cycles12 + Gating after 12 sclk cycles + 1 + + + cycles16 + Gating after 16 sclk cycles + 2 + + + cycles20 + Gating after 20 sclk cycles + 3 + + + cycles24 + Gating after 24 sclk cycles + 4 + + + + + clk_word_size + The number of sclk cycles for which the word select line stayd in the left aligned or right aligned mode + [4:3] + + + cycles16 + 16 sclk cycles + 0 + + + cycles24 + 24 sclk cycles + 1 + + + cycles32 + 32 sclk cycles + 2 + + + + + align_mode + Alignment mode setting + [7:5] + + + standard + Standard I2S format + 1 + + + right + Right aligned format + 2 + + + left + Left aligned format + 4 + + + + + dma_tx_en + DMA transmit enable control + [8:8] + + + dma_rx_en + DMA receive enable control + [9:9] + + + dma_divide_16 + Split 32bit data to two 16 bit data and filled in left and right channel. Used with dma_tx_en or dma_rx_en + [10:10] + + + sign_expand_en + SIGN_EXPAND_EN + [11:11] + + + + + rxffr + Receiver Block FIFO Reset Register + 0x14 + + + rxffr + Receiver FIFO reset + [0:0] + + FLUSH + + not_flush + Not flush FIFO + 0 + + + flush + Flush FIFO + 1 + + + + + + + txffr + Transmitter Block FIFO Reset Register + 0x18 + + + rxffr + Transmitter FIFO reset + [0:0] + + + + + + + channel%s + Channel cluster + 0x20 + 4 + 0-3 + 0x40 + + + left_rxtx + Left Receive or Left Transmit Register + 0x00 + + + right_rxtx + + Right Receive or Right Transmit Register + 0x04 + + + rer + Receive Enable Register + 0x08 + + + rxchenx + Receive channel enable/disable + [0:0] + + + + + ter + Transmit Enable Register + 0x0c + + + txchenx + Transmit channel enable/disable + [0:0] + + + + + rcr + Receive Configuration Register + 0x10 + + + wlen + Desired data resolution of receiver + [2:0] + + WLEN + + ignore + Ignore the word length + 0 + + + resolution12 + 12-bit data resolution of the receiver + 1 + + + resolution16 + 16-bit data resolution of the receiver + 2 + + + resolution20 + 20-bit data resolution of the receiver + 3 + + + resolution24 + 24-bit data resolution of the receiver + 4 + + + resolution32 + 32-bit data resolution of the receiver + 5 + + + + + + + tcr + Transmit Configuration Register + 0x14 + + + wlen + Desired data resolution of transmitter + [2:0] + + + + + + + isr + Interrupt Status Register + 0x18 + read-only + + + rxda + Status of receiver data avaliable interrupt + [0:0] + + + rxfo + Status of data overrun interrupt for RX channel + [1:1] + + + txfe + Status of transmit empty triger interrupt + [4:4] + + + txfo + Status of data overrun interrupt for the TX channel + [5:5] + + + + + imr + Interrupt Mask Register + 0x1c + + + rxdam + Mask RX FIFO data avaliable interrupt + [0:0] + + + rxfom + Mask RX FIFO overrun interrupt + [1:1] + + + txfem + Mask TX FIFO empty interrupt + [4:4] + + + txfom + Mask TX FIFO overrun interrupt + [5:5] + + + + + ror + Receive Overrun Register + 0x20 + read-only + + + rxcho + Read this bit to clear RX FIFO data overrun interrupt. 0x0 for RX FIFO write valid, 0x1 for RX FIFO write overrun + [0:0] + + + + + tor + Transmit Overrun Register + 0x24 + read-only + + + txcho + Read this bit to clear TX FIFO data overrun interrupt. 0x0 for TX FIFO write valid, 0x1 for TX FIFO write overrun + [0:0] + + + + + rfcr + Receive FIFO Configuration Register + 0x28 + + + rxchdt + Trigger level in the RX FIFO at which the receiver data available interrupt generate + [3:0] + + LEVEL + + level1 + Interrupt trigger when FIFO level is 1 + 0 + + + level2 + Interrupt trigger when FIFO level is 2 + 1 + + + level3 + Interrupt trigger when FIFO level is 3 + 2 + + + level4 + Interrupt trigger when FIFO level is 4 + 3 + + + level5 + Interrupt trigger when FIFO level is 5 + 4 + + + level6 + Interrupt trigger when FIFO level is 6 + 5 + + + level7 + Interrupt trigger when FIFO level is 7 + 6 + + + level8 + Interrupt trigger when FIFO level is 8 + 7 + + + level9 + Interrupt trigger when FIFO level is 9 + 8 + + + level10 + Interrupt trigger when FIFO level is 10 + 9 + + + level11 + Interrupt trigger when FIFO level is 11 + 10 + + + level12 + Interrupt trigger when FIFO level is 12 + 11 + + + level13 + Interrupt trigger when FIFO level is 13 + 12 + + + level14 + Interrupt trigger when FIFO level is 14 + 13 + + + level15 + Interrupt trigger when FIFO level is 15 + 14 + + + level16 + Interrupt trigger when FIFO level is 16 + 15 + + + + + + + tfcr + Transmit FIFO Configuration Register + 0x2c + + + txchet + Trigger level in the TX FIFO at which the transmitter data available interrupt generate + [3:0] + + + + + + + rff + Receive FIFO Flush Register + 0x30 + + + rxchfr + Receiver channel FIFO reset + [0:0] + + FLUSH + + not_flush + Not flush an individual FIFO + 0 + + + flush + Flush an indiviadual FIFO + 1 + + + + + + + tff + Transmit FIFO Flush Register + 0x34 + + + rtxchfr + Transmit channel FIFO reset + [0:0] + + + + + + + _reserved%s + _RESERVED0 + 0x38 + 2 + 0-1 + 0x4 + + + + + rxdma + Receiver Block DMA Register + 0x1c0 + + + + rrxdma + Reset Receiver Block DMA Register + 0x1c4 + + + + txdma + Transmitter Block DMA Register + 0x1c8 + + + + rtxdma + Reset Transmitter Block DMA Register + 0x1cc + + + i2s_comp_param_2 + Component Parameter Register 2 + 0x1f0 + + + i2s_comp_param_1 + Component Parameter Register 1 + 0x1f4 + + + i2s_comp_version_1 + Component Version Register + 0x1f8 + + + i2s_comp_type + Component Type Register + 0x1fc + + + + I2S0 + 5 + + + + + + + APU + Audio Processor + APU + 0x50250200 + + + ch_cfg + Channel Config Register + 0x00 + + + sound_ch_en + BF unit sound channel enable control bits + [7:0] + + + target_dir + Target direction select for valid voice output + [11:8] + + + audio_gain + Audio sample gain factor + [22:12] + + + + data_src_mode + Audio data source configure parameter + [24:24] + + + + we_sound_ch_en + Write enable for sound_ch_en parameter + [28:28] + write-only + + + we_target_dir + Write enable for target_dir parameter + [29:29] + write-only + + + we_audio_gain + Write enable for audio_gain parameter + [30:30] + write-only + + + we_data_src_mode + Write enable for data_out_mode parameter + [31:31] + write-only + + + + + ctl + Control Register + 0x04 + + + dir_search_en + Sound direction searching enable bit + [0:0] + + + search_path_reset + Reset all control logic on direction search processing path + [1:1] + + + + stream_gen_en + Valid voice sample stream generation enable bit + [4:4] + + + voice_gen_path_reset + Reset all control logic on voice stream generating path + [5:5] + + + update_voice_dir + Switch to a new voice source direction + [6:6] + + + + we_dir_search_en + Write enable for we_dir_search_en parameter + [8:8] + write-only + + + we_search_path_rst + Write enable for we_search_path_rst parameter + [9:9] + write-only + + + we_stream_gen + Write enable for we_stream_gen parameter + [10:10] + write-only + + + we_voice_gen_path_rst + Write enable for we_voice_gen_path_rst parameter + [11:11] + write-only + + + we_update_voice_dir + Write enable for we_update_voice_dir parameter + [12:12] + write-only + + + + + + dir_bidx[%s] + Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices) + 0x08 + 32 + 0x04 + + + rd_idx%s + rd_idx%s + [5:0] + 4 + 8 + + + + + + pre_fir0_coef[%s] + FIR0 pre-filter coefficients + 0x88 + 9 + 0x04 + + + tap0 + Tap 0 + [15:0] + + + tap1 + Tap 1 + [31:16] + + + + + post_fir0_coef[%s] + FIR0 post-filter coefficients + 0xac + 9 + 0x04 + + + tap0 + Tap 0 + [15:0] + + + tap1 + Tap 1 + [31:16] + + + + + pre_fir1_coef[%s] + FIR1 pre-filter coeffecients + 0xd0 + 9 + 0x04 + + + tap0 + Tap 0 + [15:0] + + + tap1 + Tap 1 + [31:16] + + + + + post_fir1_coef[%s] + FIR1 post-filter coefficients + 0xf4 + 9 + 0x04 + + + tap0 + Tap 0 + [15:0] + + + tap1 + Tap 1 + [31:16] + + + + + dwsz_cfg + Downsize Config Register + 0x118 + + + dir_dwn_siz_rate + Down-sizing ratio used for direction searching + [3:0] + + + voc_dwn_siz_rate + Down-sizing ratio used for voice stream generation + [7:4] + + + smpl_shift_bits + Sample precision reduction when the source sound sample precision is 20/24/32 bits + [12:8] + + + + + + fft_cfg + FFT Config Register + 0x11c + + fft_shift_factor + FFT shift factor + [8:0] + + + + fft_enable + FFT enable + [12:12] + + + + + sobuf_dma_rdata + Read register for DMA to sample-out buffers + 0x120 + + + vobuf_dma_rdata + Read register for DMA to voice-out buffers + 0x124 + + + int_stat + Interrupt Status Register + 0x128 + + + dir_search_data_rdy + Sound direction searching data ready interrupt event + [0:0] + + + voc_buf_data_rdy + Voice output stream buffer data ready interrupt event + [1:1] + + + + + + int_mask + Interrupt Mask Register + 0x12c + + + dir_search_data_rdy + Sound direction searching data ready interrupt event + [0:0] + + + voc_buf_data_rdy + Voice output stream buffer data ready interrupt event + [1:1] + + + + + + sat_counter + Saturation Counter + 0x130 + + + counter + Counter + [15:0] + + + total + Total + [31:16] + + + + + sat_limits + Saturation Limits + 0x134 + + + upper + Upper limit + [15:0] + + + bottom + Bottom limit + [31:16] + + + + + + + + + + I2S1 + Inter-Integrated Sound Interface 1 + 0x50260000 + + I2S1 + 6 + + + + + + + I2S2 + Inter-Integrated Sound Interface 2 + 0x50270000 + + I2S2 + 7 + + + + + + + I2C0 + Inter-Integrated Circuit Bus 0 + I2C + 0x50280000 + + + con + Control Register + 0x00 + + + master_mode + Master Mode + [0:0] + + + speed + Speed + [2:1] + + + standard + STANDARD + 0 + + + fast + FAST + 1 + + + highspeed + HIGHSPEED + 2 + + + + + addr_slave_width + Slave address width + [3:3] + + + b7 + 7-bit address + 0 + + + b10 + 10-bit address + 1 + + + + + restart_en + Enable Restart + [5:5] + + + slave_disable + Disable Slave + [6:6] + + + stop_det + STOP_DET_IFADDRESSED + [7:7] + + + tx_empty + TX_EMPTY_CTRL + [8:8] + + + + + tar + Target Address Register + 0x04 + + + address + Target Address + [9:0] + + + gc + GC_OR_START + [10:10] + + + special + SPECIAL + [11:11] + + + addr_master_width + Master Address + [12:12] + + + b7 + 7-bit address + 0 + + + b10 + 10-bit address + 1 + + + + + + + sar + Slave Address Register + 0x08 + + + address + Slave Address + [9:0] + + + + + data_cmd + Data Buffer and Command Register + 0x10 + + + cmd + CMD + [8:8] + + + data + Data + [7:0] + + + + + ss_scl_hcnt + Standard Speed Clock SCL High Count Register + 0x14 + + + count + COUNT + [15:0] + + + + + ss_scl_lcnt + Standard Speed Clock SCL Low Count Register + 0x18 + + + count + COUNT + [15:0] + + + + + intr_stat + Interrupt Status Register + 0x2c + read-only + + + rx_under + RX_UNDER + [0:0] + + + rx_over + RX_OVER + [1:1] + + + rx_full + RX_FULL + [2:2] + + + tx_over + TX_OVER + [3:3] + + + tx_empty + TX_EMPTY + [4:4] + + + rd_req + RD_REQ + [5:5] + + + tx_abrt + TX_ABRT + [6:6] + + + rx_done + RX_DONE + [7:7] + + + activity + ACTIVITY + [8:8] + + + stop_det + STOP_DET + [9:9] + + + start_det + START_DET + [10:10] + + + gen_call + GEN_CALL + [11:11] + + + + + intr_mask + Interrupt Mask Register + 0x30 + + + rx_under + RX_UNDER + [0:0] + + + rx_over + RX_OVER + [1:1] + + + rx_full + RX_FULL + [2:2] + + + tx_over + TX_OVER + [3:3] + + + tx_empty + TX_EMPTY + [4:4] + + + rd_req + RD_REQ + [5:5] + + + tx_abrt + TX_ABRT + [6:6] + + + rx_done + RX_DONE + [7:7] + + + activity + ACTIVITY + [8:8] + + + stop_det + STOP_DET + [9:9] + + + start_det + START_DET + [10:10] + + + gen_call + GEN_CALL + [11:11] + + + + + raw_intr_stat + Raw Interrupt Status Register + 0x34 + + + rx_under + RX_UNDER + [0:0] + + + rx_over + RX_OVER + [1:1] + + + rx_full + RX_FULL + [2:2] + + + tx_over + TX_OVER + [3:3] + + + tx_empty + TX_EMPTY + [4:4] + + + rd_req + RD_REQ + [5:5] + + + tx_abrt + TX_ABRT + [6:6] + + + rx_done + RX_DONE + [7:7] + + + activity + ACTIVITY + [8:8] + + + stop_det + STOP_DET + [9:9] + + + start_det + START_DET + [10:10] + + + gen_call + GEN_CALL + [11:11] + + + + + rx_tl + Receive FIFO Threshold Register + 0x38 + + + value + VALUE + [2:0] + + + + + tx_tl + Transmit FIFO Threshold Register + 0x3c + + + value + VALUE + [2:0] + + + + + clr_intr + Clear Combined and Individual Interrupt Register + 0x40 + read-only + + + clr + CLR + [0:0] + + + + + clr_rx_under + Clear RX_UNDER Interrupt Register + 0x44 + read-only + + + clr + CLR + [0:0] + + + + + clr_rx_over + Clear RX_OVER Interrupt Register + 0x48 + read-only + + + clr + CLR + [0:0] + + + + + clr_tx_over + Clear TX_OVER Interrupt Register + 0x4c + read-only + + + clr + CLR + [0:0] + + + + + clr_rd_req + Clear RD_REQ Interrupt Register + 0x50 + read-only + + + clr + CLR + [0:0] + + + + + clr_tx_abrt + Clear TX_ABRT Interrupt Register + 0x54 + read-only + + + clr + CLR + [0:0] + + + + + clr_rx_done + Clear RX_DONE Interrupt Register + 0x58 + read-only + + + clr + CLR + [0:0] + + + + + clr_activity + Clear ACTIVITY Interrupt Register + 0x5c + read-only + + + clr + CLR + [0:0] + + + + + clr_stop_det + Clear STOP_DET Interrupt Register + 0x60 + read-only + + + clr + CLR + [0:0] + + + + + clr_start_det + Clear START_DET Interrupt Register + 0x64 + read-only + + + clr + CLR + [0:0] + + + + + clr_gen_call + I2C Clear GEN_CALL Interrupt Register + 0x68 + read-only + + + clr + CLR + [0:0] + + + + + enable + Enable Register + 0x6c + + + enable + ENABLE + [0:0] + + + abort + ABORT + [1:1] + + + tx_cmd_block + TX_CMD_BLOCK + [2:2] + + + + + status + Status Register + 0x70 + read-only + + + activity + ACTIVITY + [0:0] + + + tfnf + TFNF + [1:1] + + + tfe + TFE + [2:2] + + + rfne + RFNE + [3:3] + + + rff + RFF + [4:4] + + + mst_activity + MST_ACTIVITY + [5:5] + + + slv_activity + SLV_ACTIVITY + [6:6] + + + + + txflr + Transmit FIFO Level Register + 0x74 + + + value + VALUE + [2:0] + + + + + rxflr + Receive FIFO Level Register + 0x78 + + + value + VALUE + [2:0] + + + + + sda_hold + SDA Hold Time Length Register + 0x7c + + + tx + TX + [15:0] + + + rx + RX + [23:16] + + + + + tx_abrt_source + Transmit Abort Source Register + 0x80 + + + addr7_noack + 7B_ADDR_NOACK + [0:0] + + + addr1_10_noack + 10B_ADDR1_NOACK + [1:1] + + + addr2_10_noack + 10B_ADDR2_NOACK + [2:2] + + + txdata_noack + TXDATA_NOACK + [3:3] + + + gcall_noack + GCALL_NOACK + [4:4] + + + gcall_read + GCALL_READ + [5:5] + + + hs_ackdet + HS_ACKDET + [6:6] + + + sbyte_ackdet + SBYTE_ACKDET + [7:7] + + + hs_norstrt + HS_NORSTRT + [8:8] + + + sbyte_norstrt + SBYTE_NORSTRT + [9:9] + + + rd_10_norstrt + 10B_RD_NORSTRT + [10:10] + + + master_dis + MASTER_DIS + [11:11] + + + mst_arblost + MST_ARBLOST + [12:12] + + + slvflush_txfifo + SLVFLUSH_TXFIFO + [13:13] + + + slv_arblost + SLV_ARBLOST + [14:14] + + + slvrd_intx + SLVRD_INTX + [15:15] + + + user_abrt + USER_ABRT + [16:16] + + + + + dma_cr + I2C DMA Control Register + 0x88 + + + RDMAE + RDMAE + [0:0] + + + TDMAE + TDMAE + [1:1] + + + + + dma_tdlr + DMA Transmit Data Level Register + 0x8c + + + value + VALUE + [2:0] + + + + + dma_rdlr + DMA Receive Data Level Register + 0x90 + + + value + VALUE + [2:0] + + + + + sda_setup + SDA Setup Register + 0x94 + + + value + VALUE + [7:0] + + + + + general_call + ACK General Call Register + 0x98 + + + call_enable + CALL_ENABLE + [0:0] + + + + + enable_status + Enable Status Register + 0x9c + read-only + + + ic_enable + IC_ENABLE + [0:0] + + + slv_dis_busy + SLV_DIS_BUSY + [1:1] + + + slv_rx_data_lost + SLV_RX_DATA_LOST + [2:2] + + + + + fs_spklen + SS, FS or FM+ spike suppression limit + 0xa0 + + + value + VALUE + [7:0] + + + + + comp_param_1 + Component Parameter Register 1 + 0xf4 + read-only + + + apb_data_width + APB_DATA_WIDTH + [1:0] + + + max_speed_mode + MAX_SPEED_MODE + [3:2] + + + hc_count_values + HC_COUNT_VALUES + [4:4] + + + intr_io + INTR_IO + [5:5] + + + has_dma + HAS_DMA + [6:6] + + + encoded_params + ENCODED_PARAMS + [7:7] + + + rx_buffer_depth + RX_BUFFER_DEPTH + [15:8] + + + tx_buffer_depth + TX_BUFFER_DEPTH + [23:16] + + + + + comp_version + Component Version Register + 0xf8 + read-only + + + value + VALUE + [31:0] + + + + + comp_type + Component Type Register + 0xfc + read-only + + + value + VALUE + [31:0] + + + + + + I2C0 + 8 + + + + + + + I2C1 + Inter-Integrated Circuit Bus 1 + 0x50290000 + + I2C1 + 9 + + + + + + + I2C2 + Inter-Integrated Circuit Bus 2 + 0x502A0000 + + I2C2 + 10 + + + + + + + FPIOA + Field Programmable IO Array + FPIOA + 0x502B0000 + + + 48 + 0x04 + io[%s] + FPIOA GPIO multiplexer io array + 0x00 + + + ch_sel + Channel select from 256 input + [7:0] + + + ds + Driving selector + [11:8] + + + oe_en + Static output enable, will AND with OE_INV + [12:12] + + + oe_inv + Invert output enable + [13:13] + + + do_sel + Data output select: 0 for DO, 1 for OE + [14:14] + + + do_inv + Invert the result of data output select (DO_SEL) + [15:15] + + + pu + Pull up enable. 0 for nothing, 1 for pull up + [16:16] + + + pd + Pull down enable. 0 for nothing, 1 for pull down + [17:17] + + + sl + Slew rate control enable + [19:19] + + + ie_en + Static input enable, will AND with IE_INV + [20:20] + + + ie_inv + Invert input enable + [21:21] + + + di_inv + Invert Data input + [22:22] + + + st + Schmitt trigger + [23:23] + + + pad_di + Read current IO's data input + [31:31] + + + + + 8 + 0x04 + tie_en[%s] + FPIOA GPIO multiplexer tie enable array + 0xC0 + + + 8 + 0x04 + tie_val[%s] + FPIOA GPIO multiplexer tie value array + 0xE0 + + + + + + + + SHA256 + SHA256 Accelerator + SHA256 + 0x502C0000 + + + 8 + 0x4 + result[%s] + Calculated SHA256 return value + 0x00 + + + data_in + SHA256 input data is written to this register + 0x20 + + + num_reg + Counters register + 0x28 + + + data_cnt + The total amount of data calculated by SHA256 is set by this register, and the smallest unit is 512bit + [15:0] + + + data_num + Currently calculated block number. 512bit=1block + [31:16] + + + + + function_reg_0 + Function configuration register 0 + 0x2C + + + en + write:SHA256 enable register. read:Calculation completed flag + [0:0] + + + overflow + SHA256 calculation overflow flag + [8:8] + + + endian + Endian setting + [16:16] + + + le + Little endian + 0 + + + be + Big endian + 1 + + + + + + + function_reg_1 + Function configuration register 1 + 0x34 + + + dma_en + SHA and DMA handshake signals enable. 1:enable; 0:disable + [0:0] + + + fifo_in_full + 1:SHA256 input fifo is full; 0:not full + [8:8] + + + + + + + + + + TIMER0 + Timer 0 + TIMER + 0x502D0000 + + + channel%s + Channel cluster: load_count, current_value, control, eoi and intr_stat registers + 0x0 + 4 + 0-3 + 0x14 + + + load_count + Load Count Register + 0x00 + + + + current_value + Current Value Register + 0x04 + + + control + Control Register + 0x08 + + + enable + ENABLE + [0:0] + + + mode + MODE + [1:1] + + + free + FREE_MODE + 0 + + + user + USER_MODE + 1 + + + + + interrupt + INTERRUPT_MASK + [2:2] + + + pwm_enable + PWM_ENABLE + [3:3] + + + + + + eoi + Interrupt Clear Register + 0x0c + + + + intr_stat + Interrupt Status Register + 0x10 + + + + + intr_stat + Interrupt Status Register + 0xa0 + + + + eoi + Interrupt Clear Register + 0xa4 + + + + raw_intr_stat + Raw Interrupt Status Register + 0xa8 + + + + comp_version + Component Version Register + 0xac + + + + load_count2%s + Load Count2 Register + 0xb0 + 4 + 0-3 + 0x4 + + + + TIMER0A + 14 + TIMER0 channel 0 or 1 interrupt + + + TIMER0B + 15 + TIMER0 channel 2 or 3 interrupt + + + + + + + TIMER1 + Timer 1 + 0x502E0000 + + TIMER1A + 16 + TIMER1 channel 0 or 1 interrupt + + + TIMER1B + 17 + TIMER1 channel 2 or 3 interrupt + + + + + + + TIMER2 + Timer 2 + 0x502F0000 + + TIMER2A + 18 + TIMER2 channel 0 or 1 interrupt + + + TIMER2B + 19 + TIMER2 channel 2 or 3 interrupt + + + + + + + WDT0 + Watchdog Timer 0 + WDT + 0x50400000 + + + cr + Control Register + 0x00 + + + enable + enable + [0:0] + + + rmod + rmod + [1:1] + + + reset + RESET + 0 + + + interrupt + INTERRUPT + 1 + + + + + rpl + rpl + [4:2] + + + + + torr + Timeout Range Register + 0x04 + + + top0 + top (lower half) + [3:0] + + + top1 + top (upper half) + [7:4] + + + + + ccvr + Current Counter Value Register + 0x08 + + + crr + Counter Restart Register + 0x0c + + + stat + Interrupt Status Register + 0x10 + + + stat + stat + [0:0] + + + + + eoi + Interrupt Clear Register + 0x14 + + + eoi + eoi + [0:0] + + + + + + prot_level + Protection level Register + 0x1c + + + prot_level + prot_level + [2:0] + + + + + + comp_param_5 + Component Parameters Register 5 + 0xe4 + + + user_top_max + user_top_max + [31:0] + + + + + comp_param_4 + Component Parameters Register 4 + 0xe8 + + + user_top_init_max + user_top_init_max + [31:0] + + + + + comp_param_3 + Component Parameters Register 3 + 0xec + + + top_rst + top_rst + [31:0] + + + + + comp_param_2 + Component Parameters Register 2 + 0xf0 + + + cnt_rst + cnt_rst + [31:0] + + + + + comp_param_1 + Component Parameters Register 1 + 0xf4 + + + always_en + always_en + [0:0] + + + dflt_rmod + dflt_rmod + [1:1] + + + dual_top + dual_top + [2:2] + + + hc_rmod + hc_rmod + [3:3] + + + hc_rpl + hc_rpl + [4:4] + + + hc_top + hc_top + [5:5] + + + use_fix_top + use_fix_top + [6:6] + + + pause + pause + [7:7] + + + apb_data_width + apb_data_width + [9:8] + + + dflt_rpl + dflt_rpl + [12:10] + + + + dflt_top + dflt_top + [19:16] + + + dflt_top_init + dflt_top_init + [23:20] + + + cnt_width + cnt_width + [28:24] + + + + + + comp_version + Component Version Register + 0xf8 + + + comp_type + Component Type Register + 0xfc + + + + WDT0 + 21 + + + + + + + WDT1 + Watchdog Timer 1 + 0x50410000 + + WDT1 + 22 + + + + + + + OTP + One-Time Programmable Memory Controller + OTP + 0x50420000 + + + + dummy + Dummy register: this peripheral is not implemented yet + 0x00 + + + + + + + + DVP + Digital Video Port + DVP + 0x50430000 + + + + dvp_cfg + Config Register + 0x00 + + + start_int_enable + START_INT_ENABLE + [0:0] + + + finish_int_enable + FINISH_INT_ENABLE + [1:1] + + + ai_output_enable + AI_OUTPUT_ENABLE + [2:2] + + + display_output_enable + DISPLAY_OUTPUT_ENABLE + [3:3] + + + auto_enable + AUTO_ENABLE + [4:4] + + + burst_size_4beats + BURST_SIZE_4BEATS + [8:8] + + + format + FORMAT + [10:9] + + + rgb + RGB_FORMAT + 0 + + + yuv + YUV_FORMAT + 1 + + + y + Y_FORMAT + 3 + + + + + href_burst_num + HREF_BURST_NUM + [19:12] + + + line_num + LINE_NUM + [29:20] + + + + + r_addr + R_ADDR + 0x04 + + + g_addr + G_ADDR + 0x08 + + + b_addr + B_ADDR + 0x0c + + + cmos_cfg + CMOS Config Register + 0x10 + + + clk_div + CLK_DIV + [7:0] + + + clk_enable + CLK_ENABLE + [8:8] + + + reset + RESET + [16:16] + + + power_down + POWER_DOWN + [24:24] + + + + + sccb_cfg + SCCB Config Register + 0x14 + + + byte_num + BYTE_NUM + [1:0] + + + num2 + BYTE_NUM_2 + 1 + + + num3 + BYTE_NUM_3 + 2 + + + num4 + BYTE_NUM_4 + 3 + + + + + scl_lcnt + SCL_LCNT + [15:8] + + + scl_hcnt + SCL_HCNT + [23:16] + + + rdata + RDATA + [31:24] + read-only + + + + + sccb_ctl + SCCB Control Register + 0x18 + + + + device_address + DEVICE_ADDRESS + [7:0] + + + reg_address + REG_ADDRESS + [15:8] + + + wdata_byte0 + WDATA_BYTE0 + [23:16] + + + wdata_byte1 + WDATA_BYTE1 + [31:24] + + + + + axi + AXI Register + 0x1c + + + gm_mlen + GM_MLEN + [7:0] + + + byte1 + GM_MLEN_1BYTE + 0 + + + byte4 + GM_MLEN_4BYTE + 3 + + + + + + + sts + STS Register + 0x20 + + + frame_start + FRAME_START + [0:0] + + + frame_start_we + FRAME_START_WE + [1:1] + + + frame_finish + FRAME_FINISH + [8:8] + + + frame_finish_we + FRAME_FINISH_WE + [9:9] + + + dvp_en + DVP_EN + [16:16] + + + dvp_en_we + DVP_EN_WE + [17:17] + + + sccb_en + SCCB_EN + [24:24] + + + sccb_en_we + SCCB_EN_WE + [25:25] + + + + + reverse + REVERSE + 0x24 + + + rgb_addr + RGB_ADDR + 0x28 + + + + DVP + 24 + + + + + + + SYSCTL + System Controller + SYSCTL + 0x50440000 + + + git_id + Git short commit id + 0x00 + + + clk_freq + System clock base frequency + 0x04 + + + pll0 + PLL0 controller + 0x08 + + + clkr + [3:0] + + + clkf + [9:4] + + + clkod + [13:10] + + + bwadj + [19:14] + + + reset + [20:20] + + + pwrd + [21:21] + + + intfb + [22:22] + + + bypass + [23:23] + + + test + [24:24] + + + out_en + [25:25] + + + test_en + [26:26] + + + + + pll1 + PLL1 controller + 0x0c + + + clkr + [3:0] + + + clkf + [9:4] + + + clkod + [13:10] + + + bwadj + [19:14] + + + reset + [20:20] + + + pwrd + [21:21] + + + intfb + [22:22] + + + bypass + [23:23] + + + test + [24:24] + + + out_en + [25:25] + + + + + pll2 + PLL2 controller + 0x10 + + + clkr + [3:0] + + + clkf + [9:4] + + + clkod + [13:10] + + + bwadj + [19:14] + + + reset + [20:20] + + + pwrd + [21:21] + + + intfb + [22:22] + + + bypass + [23:23] + + + test + [24:24] + + + out_en + [25:25] + + + ckin_sel + [27:26] + + + + + pll_lock + PLL lock tester + 0x18 + + + pll_lock0 + [1:0] + + + pll_slip_clear0 + [2:2] + + + test_clk_out0 + [3:3] + + + pll_lock1 + [9:8] + + + pll_slip_clear1 + [10:10] + + + test_clk_out1 + [11:11] + + + pll_lock2 + [17:16] + + + pll_slip_clear2 + [18:18] + + + test_clk_out2 + [19:19] + + + + + rom_error + AXI ROM detector + 0x1c + + + rom_mul_error + [0:0] + + + rom_one_error + [1:1] + + + + + clk_sel0 + Clock select controller 0 + 0x20 + + + aclk_sel + [0:0] + + + aclk_divider_sel + [2:1] + + + apb0_clk_sel + [5:3] + + + apb1_clk_sel + [8:6] + + + apb2_clk_sel + [11:9] + + + spi3_clk_sel + [12:12] + + + timer0_clk_sel + [13:13] + + + timer1_clk_sel + [14:14] + + + timer2_clk_sel + [15:15] + + + + + clk_sel1 + Clock select controller 1 + 0x24 + + + spi3_sample_clk_sel + [0:0] + + + + + clk_en_cent + Central clock enable + 0x28 + + + cpu_clk_en + [0:0] + + + sram0_clk_en + [1:1] + + + sram1_clk_en + [2:2] + + + apb0_clk_en + [3:3] + + + apb1_clk_en + [4:4] + + + apb2_clk_en + [5:5] + + + + + clk_en_peri + Peripheral clock enable + 0x2c + + + rom_clk_en + [0:0] + + + dma_clk_en + [1:1] + + + ai_clk_en + [2:2] + + + dvp_clk_en + [3:3] + + + fft_clk_en + [4:4] + + + gpio_clk_en + [5:5] + + + spi0_clk_en + [6:6] + + + spi1_clk_en + [7:7] + + + spi2_clk_en + [8:8] + + + spi3_clk_en + [9:9] + + + i2s0_clk_en + [10:10] + + + i2s1_clk_en + [11:11] + + + i2s2_clk_en + [12:12] + + + i2c0_clk_en + [13:13] + + + i2c1_clk_en + [14:14] + + + i2c2_clk_en + [15:15] + + + uart1_clk_en + [16:16] + + + uart2_clk_en + [17:17] + + + uart3_clk_en + [18:18] + + + aes_clk_en + [19:19] + + + fpioa_clk_en + [20:20] + + + timer0_clk_en + [21:21] + + + timer1_clk_en + [22:22] + + + timer2_clk_en + [23:23] + + + wdt0_clk_en + [24:24] + + + wdt1_clk_en + [25:25] + + + sha_clk_en + [26:26] + + + otp_clk_en + [27:27] + + + rtc_clk_en + [29:29] + + + + + soft_reset + Soft reset ctrl + 0x30 + + + soft_reset + [0:0] + + + + + peri_reset + Peripheral reset controller + 0x34 + + + rom_reset + [0:0] + + + dma_reset + [1:1] + + + ai_reset + [2:2] + + + dvp_reset + [3:3] + + + fft_reset + [4:4] + + + gpio_reset + [5:5] + + + spi0_reset + [6:6] + + + spi1_reset + [7:7] + + + spi2_reset + [8:8] + + + spi3_reset + [9:9] + + + i2s0_reset + [10:10] + + + i2s1_reset + [11:11] + + + i2s2_reset + [12:12] + + + i2c0_reset + [13:13] + + + i2c1_reset + [14:14] + + + i2c2_reset + [15:15] + + + uart1_reset + [16:16] + + + uart2_reset + [17:17] + + + uart3_reset + [18:18] + + + aes_reset + [19:19] + + + fpioa_reset + [20:20] + + + timer0_reset + [21:21] + + + timer1_reset + [22:22] + + + timer2_reset + [23:23] + + + wdt0_reset + [24:24] + + + wdt1_reset + [25:25] + + + sha_reset + [26:26] + + + rtc_reset + [29:29] + + + + + clk_th0 + Clock threshold controller 0 + 0x38 + + + sram0_gclk + [3:0] + + + sram1_gclk + [7:4] + + + ai_gclk + [11:8] + + + dvp_gclk + [15:12] + + + rom_gclk + [19:16] + + + + + clk_th1 + Clock threshold controller 1 + 0x3c + + + spi0_clk + [7:0] + + + spi1_clk + [15:8] + + + spi2_clk + [23:16] + + + spi3_clk + [31:24] + + + + + clk_th2 + Clock threshold controller 2 + 0x40 + + + timer0_clk + [7:0] + + + timer1_clk + [15:8] + + + timer2_clk + [23:16] + + + + + clk_th3 + Clock threshold controller 3 + 0x44 + + + i2s0_clk + [15:0] + + + i2s1_clk + [31:16] + + + + + clk_th4 + Clock threshold controller 4 + 0x48 + + + i2s2_clk + [15:0] + + + i2s0_mclk + [23:16] + + + i2s1_mclk + [31:24] + + + + + clk_th5 + Clock threshold controller 5 + 0x4c + + + i2s2_mclk + [7:0] + + + i2c0_clk + [15:8] + + + i2c1_clk + [23:16] + + + i2c2_clk + [31:24] + + + + + clk_th6 + Clock threshold controller 6 + 0x50 + + + wdt0_clk + [7:0] + + + wdt1_clk + [15:8] + + + + + misc + Miscellaneous controller + 0x54 + + + debug_sel + [5:0] + + + spi_dvp_data_enable + [10:10] + + + + + peri + Peripheral controller + 0x58 + + + timer0_pause + [0:0] + + + timer1_pause + [1:1] + + + timer2_pause + [2:2] + + + timer3_pause + [3:3] + + + timer4_pause + [4:4] + + + timer5_pause + [5:5] + + + timer6_pause + [6:6] + + + timer7_pause + [7:7] + + + timer8_pause + [8:8] + + + timer9_pause + [9:9] + + + timer10_pause + [10:10] + + + timer11_pause + [11:11] + + + spi0_xip_en + [12:12] + + + spi1_xip_en + [13:13] + + + spi2_xip_en + [14:14] + + + spi3_xip_en + [15:15] + + + spi0_clk_bypass + [16:16] + + + spi1_clk_bypass + [17:17] + + + spi2_clk_bypass + [18:18] + + + i2s0_clk_bypass + [19:19] + + + i2s1_clk_bypass + [20:20] + + + i2s2_clk_bypass + [21:21] + + + jtag_clk_bypass + [22:22] + + + dvp_clk_bypass + [23:23] + + + debug_clk_bypass + [24:24] + + + + + spi_sleep + SPI sleep controller + 0x5c + + + ssi0_sleep + [0:0] + + + ssi1_sleep + [1:1] + + + ssi2_sleep + [2:2] + + + ssi3_sleep + [3:3] + + + + + reset_status + Reset source status + 0x60 + + + reset_sts_clr + [0:0] + + + pin_reset_sts + [1:1] + + + wdt0_reset_sts + [2:2] + + + wdt1_reset_sts + [3:3] + + + soft_reset_sts + [4:4] + + + + + dma_sel0 + DMA handshake selector + 0x64 + + + dma_sel0 + [5:0] + + DMASELECT + ssi0_rx_req0 + ssi0_tx_req1 + ssi1_rx_req2 + ssi1_tx_req3 + ssi2_rx_req4 + ssi2_tx_req5 + ssi3_rx_req6 + ssi3_tx_req7 + i2c0_rx_req8 + i2c0_tx_req9 + i2c1_rx_req10 + i2c1_tx_req11 + i2c2_rx_req12 + i2c2_tx_req13 + uart1_rx_req14 + uart1_tx_req15 + uart2_rx_req16 + uart2_tx_req17 + uart3_rx_req18 + uart3_tx_req19 + aes_req20 + sha_rx_req21 + ai_rx_req22 + fft_rx_req23 + fft_tx_req24 + i2s0_tx_req25 + i2s0_rx_req26 + i2s1_tx_req27 + i2s1_rx_req28 + i2s2_tx_req29 + i2s2_rx_req30 + i2s0_bf_dir_req31 + i2s0_bf_voice_req32 + + + + dma_sel1 + [11:6] + + + + + dma_sel2 + [17:12] + + + + + dma_sel3 + [23:18] + + + + + dma_sel4 + [29:24] + + + + + + + dma_sel1 + DMA handshake selector + 0x68 + + + dma_sel5 + [5:0] + + + + + + + power_sel + IO Power Mode Select controller + 0x6c + + + power_mode_sel0 + [0:0] + + + power_mode_sel1 + [1:1] + + + power_mode_sel2 + [2:2] + + + power_mode_sel3 + [3:3] + + + power_mode_sel4 + [4:4] + + + power_mode_sel5 + [5:5] + + + power_mode_sel6 + [6:6] + + + power_mode_sel7 + [7:7] + + + + + + + + + + AES + AES Accelerator + AES + 0x50450000 + + + 4 + 0x04 + key[%s] + 1st-4th word of key + 0x00 + + + encrypt_sel + Encryption or decryption select + 0x10 + + + encrypt_sel + Select encryption or decryption mode + [0:0] + + + encryption + Sets encryption mode + 0 + + + decryption + Sets decryption mode + 1 + + + + + + + mode_ctl + AES mode register + 0x14 + + + cipher_mode + Cipher mode + [2:0] + + + ECB + Electronic Codebook + 0 + + + CBC + Cipher Block Chaining + 1 + + + GCM + Galois/Counter Mode + 2 + + + + + key_mode + Key mode + [4:3] + + + AES128 + AES-128 + 0 + + + AES192 + AES-192 + 1 + + + AES256 + AES-256 + 2 + + + + + key_order + Input key order + [5:5] + + ENDIAN + + be + Big Endian + 0 + + + le + Little Endian + 1 + + + + + input_order + Input data order + [7:7] + + + + + output_order + Output data order + [9:9] + + + + + + + 4 + 0x04 + iv[%s] + Initialisation Vector (96 bit for GCM, 128 bit for CBC) + 0x18 + + + endian + Endian control + 0x28 + + + endian + Input data endian + [0:0] + + + + + + + finish + Finished status + 0x2C + + + finish + AES operation finished status + [0:0] + + + not_finished + Operation not finished + 0 + + + finished + Operation finished + 1 + + + + + + + dma_sel + DMA select + 0x30 + + + dma_sel + Output to DMA if set, to CPU otherwise + [0:0] + + + + + aad_num + GCM additional authenticated data count in bytes, minus one + 0x34 + + + pc_num + Plaintext/ciphertext input data count in bytes, minus one + 0x3c + + + text_data + Plaintext/ciphertext input data + 0x40 + + + aad_data + Additional authenticated data + 0x44 + + + tag_chk + Tag check status + 0x48 + + + tag_chk + Tag check status + [1:0] + + + busy + Check not finished + 0 + + + fail + Check failed + 1 + + + success + Check success + 2 + + + + + + + data_in_flag + Data can input flag + 0x4c + + + data_in_flag + Data can be written to text_data or aad_data when this flag is set + [0:0] + + CAN_INPUT + + cannot_input + Cannot input + 0 + + + can_input + Can input + 1 + + + + + + + 4 + 0x04 + gcm_in_tag[%s] + GCM input tag for comparison with the calculated tag + 0x50 + + + out_data + Plaintext/ciphertext output data + 0x60 + + + en + AES module enable + 0x64 + + + en + AES module enable + [0:0] + + + disable + Disable module + 0 + + + enable + Enable module + 1 + + + + + + + data_out_flag + Data can output flag + 0x68 + + + data_out_flag + Data can be read from out_data when this flag is set + [0:0] + + + cannot_output + Data cannot output + 0 + + + can_output + Data can output + 1 + + + + + + + tag_in_flag + Can input tag (when using GCM) + 0x6c + + + tag_in_flag + GCM tag can be written to gcm_in_tag when this flag is set + [0:0] + + + + + + + tag_clear + Tag clear (a write to this register clears the tag_chk status) + 0x70 + + + 4 + 0x04 + gcm_out_tag[%s] + Computed GCM output tag + 0x74 + + + 4 + 0x04 + key_ext[%s] + 5th-8th word of key + 0x84 + + + + + + + + RTC + Real Time Clock + RTC + 0x50460000 + + + date + Timer date information + 0x00 + + + week + Week. Range [0,6]. 0 is Sunday. + [2:0] + 06 + + + day + Day. Range [1,31] or [1,30] or [1,29] or [1,28] + [12:8] + 131 + + + month + Month. Range [1,12] + [19:16] + 112 + + + year + Year. Range [0,99] + [31:20] + 099 + + + + + time + Timer time information + 0x04 + + + second + Second. Range [0,59] + [15:10] + 059 + + + minute + Minute. Range [0,59] + [21:16] + 059 + + + hour + Hour. Range [0,23] + [28:24] + 023 + + + + + alarm_date + Alarm date information + 0x08 + + + week + Week. Range [0,6]. 0 is Sunday. + [2:0] + 06 + + + day + Day. Range [1,31] or [1,30] or [1,29] or [1,28] + [12:8] + 131 + + + month + Month. Range [1,12] + [19:16] + 112 + + + year + Year. Range [0,99] + [31:20] + 099 + + + + + alarm_time + Alarm time information + 0x0c + + + second + Second. Range [0,59] + [15:10] + 059 + + + minute + Minute. Range [0,59] + [21:16] + 059 + + + hour + Hour. Range [0,23] + [28:24] + 023 + + + + + initial_count + Timer counter initial value + 0x10 + + + count + RTC counter initial value + [31:0] + + + + + current_count + Timer counter current value + 0x14 + + + count + RTC counter current value + [31:0] + + + + + interrupt_ctrl + RTC interrupt settings + 0x18 + + + tick_enable + TICK_ENABLE + [0:0] + + + alarm_enable + Alarm interrupt enable + [1:1] + + + tick_int_mode + Tick interrupt enable + [3:2] + + + alarm_compare_mask + Alarm compare mask for interrupt + [31:24] + + + + + register_ctrl + RTC register settings + 0x1c + + + read_enable + RTC timer read enable + [0:0] + + + write_enable + RTC timer write enable + [1:1] + + + timer_mask + RTC timer mask + [20:13] + + + alarm_mask + RTC alarm mask + [28:21] + + + initial_count_mask + RTC counter initial count value mask + [29:29] + + + interrupt_register_mask + RTC interrupt register mask + [30:30] + + + + + extended + Timer extended information + 0x28 + + + century + Century. Range [0,31] + [4:0] + 031 + + + leap_year + Is leap year. 1 is leap year, 0 is not leap year + [5:5] + + + not_leap + 0 is not leap year + 0 + + + leap + 1 is leap year + 1 + + + + + + + + RTC + 20 + + + + + diff --git a/tools/k210-pac/memory-k210.x b/tools/k210-pac/memory-k210.x new file mode 100644 index 0000000..2770e46 --- /dev/null +++ b/tools/k210-pac/memory-k210.x @@ -0,0 +1,9 @@ +_max_hart_id = 1; + +MEMORY +{ + SRAM : ORIGIN = 0x80000000, LENGTH = 6M + AI_SRAM : ORIGIN = 0x80600000, LENGTH = 2M + SRAM_NOCACHE : ORIGIN = 0x40000000, LENGTH = 6M + AI_SRAM_NOCACHE : ORIGIN = 0x40600000, LENGTH = 2M +} diff --git a/tools/k210-pac/src/lib.rs b/tools/k210-pac/src/lib.rs new file mode 100644 index 0000000..f5befa0 --- /dev/null +++ b/tools/k210-pac/src/lib.rs @@ -0,0 +1,46139 @@ +#![doc = "Peripheral access API for K210 microcontrollers (generated using svd2rust v0.17.0)\n\nYou can find an overview of the API [here].\n\n[here]: https://docs.rs/svd2rust/0.17.0/svd2rust/#peripheral-api"] +#![deny(const_err)] +#![deny(dead_code)] +#![deny(improper_ctypes)] +#![deny(missing_docs)] +#![deny(no_mangle_generic_items)] +#![deny(non_shorthand_field_patterns)] +#![deny(overflowing_literals)] +#![deny(path_statements)] +#![deny(patterns_in_fns_without_body)] +#![deny(private_in_public)] +#![deny(unconditional_recursion)] +#![deny(unused_allocation)] +#![deny(unused_comparisons)] +#![deny(unused_parens)] +#![deny(while_true)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![no_std] +extern crate bare_metal; +extern crate riscv; +#[cfg(feature = "rt")] +extern crate riscv_rt; +extern crate vcell; +use core::marker::PhantomData; +use core::ops::Deref; +#[doc(hidden)] +pub mod interrupt { + #[doc = r"Enumeration of all the interrupts"] + #[derive(Copy, Clone, Debug)] + #[repr(u8)] + pub enum Interrupt { + #[doc = "1 - SPI0"] + SPI0 = 1, + #[doc = "2 - SPI1"] + SPI1 = 2, + #[doc = "3 - SPI_SLAVE"] + SPI_SLAVE = 3, + #[doc = "4 - SPI3"] + SPI3 = 4, + #[doc = "5 - I2S0"] + I2S0 = 5, + #[doc = "6 - I2S1"] + I2S1 = 6, + #[doc = "7 - I2S2"] + I2S2 = 7, + #[doc = "8 - I2C0"] + I2C0 = 8, + #[doc = "9 - I2C1"] + I2C1 = 9, + #[doc = "10 - I2C2"] + I2C2 = 10, + #[doc = "11 - UART1"] + UART1 = 11, + #[doc = "12 - UART2"] + UART2 = 12, + #[doc = "13 - UART3"] + UART3 = 13, + #[doc = "14 - TIMER0 channel 0 or 1 interrupt"] + TIMER0A = 14, + #[doc = "15 - TIMER0 channel 2 or 3 interrupt"] + TIMER0B = 15, + #[doc = "16 - TIMER1 channel 0 or 1 interrupt"] + TIMER1A = 16, + #[doc = "17 - TIMER1 channel 2 or 3 interrupt"] + TIMER1B = 17, + #[doc = "18 - TIMER2 channel 0 or 1 interrupt"] + TIMER2A = 18, + #[doc = "19 - TIMER2 channel 2 or 3 interrupt"] + TIMER2B = 19, + #[doc = "20 - RTC"] + RTC = 20, + #[doc = "21 - WDT0"] + WDT0 = 21, + #[doc = "22 - WDT1"] + WDT1 = 22, + #[doc = "23 - APB_GPIO"] + APB_GPIO = 23, + #[doc = "24 - DVP"] + DVP = 24, + #[doc = "25 - KPU"] + KPU = 25, + #[doc = "26 - FFT"] + FFT = 26, + #[doc = "27 - DMA0"] + DMA0 = 27, + #[doc = "28 - DMA1"] + DMA1 = 28, + #[doc = "29 - DMA2"] + DMA2 = 29, + #[doc = "30 - DMA3"] + DMA3 = 30, + #[doc = "31 - DMA4"] + DMA4 = 31, + #[doc = "32 - DMA5"] + DMA5 = 32, + #[doc = "33 - UARTHS"] + UARTHS = 33, + #[doc = "34 - GPIOHS0"] + GPIOHS0 = 34, + #[doc = "35 - GPIOHS1"] + GPIOHS1 = 35, + #[doc = "36 - GPIOHS2"] + GPIOHS2 = 36, + #[doc = "37 - GPIOHS3"] + GPIOHS3 = 37, + #[doc = "38 - GPIOHS4"] + GPIOHS4 = 38, + #[doc = "39 - GPIOHS5"] + GPIOHS5 = 39, + #[doc = "40 - GPIOHS6"] + GPIOHS6 = 40, + #[doc = "41 - GPIOHS7"] + GPIOHS7 = 41, + #[doc = "42 - GPIOHS8"] + GPIOHS8 = 42, + #[doc = "43 - GPIOHS9"] + GPIOHS9 = 43, + #[doc = "44 - GPIOHS10"] + GPIOHS10 = 44, + #[doc = "45 - GPIOHS11"] + GPIOHS11 = 45, + #[doc = "46 - GPIOHS12"] + GPIOHS12 = 46, + #[doc = "47 - GPIOHS13"] + GPIOHS13 = 47, + #[doc = "48 - GPIOHS14"] + GPIOHS14 = 48, + #[doc = "49 - GPIOHS15"] + GPIOHS15 = 49, + #[doc = "50 - GPIOHS16"] + GPIOHS16 = 50, + #[doc = "51 - GPIOHS17"] + GPIOHS17 = 51, + #[doc = "52 - GPIOHS18"] + GPIOHS18 = 52, + #[doc = "53 - GPIOHS19"] + GPIOHS19 = 53, + #[doc = "54 - GPIOHS20"] + GPIOHS20 = 54, + #[doc = "55 - GPIOHS21"] + GPIOHS21 = 55, + #[doc = "56 - GPIOHS22"] + GPIOHS22 = 56, + #[doc = "57 - GPIOHS23"] + GPIOHS23 = 57, + #[doc = "58 - GPIOHS24"] + GPIOHS24 = 58, + #[doc = "59 - GPIOHS25"] + GPIOHS25 = 59, + #[doc = "60 - GPIOHS26"] + GPIOHS26 = 60, + #[doc = "61 - GPIOHS27"] + GPIOHS27 = 61, + #[doc = "62 - GPIOHS28"] + GPIOHS28 = 62, + #[doc = "63 - GPIOHS29"] + GPIOHS29 = 63, + #[doc = "64 - GPIOHS30"] + GPIOHS30 = 64, + #[doc = "65 - GPIOHS31"] + GPIOHS31 = 65, + } + unsafe impl bare_metal::Nr for Interrupt { + #[inline(always)] + fn nr(&self) -> u8 { + *self as u8 + } + } + #[derive(Debug, Copy, Clone)] + pub struct TryFromInterruptError(()); + impl Interrupt { + #[inline] + pub fn try_from(value: u8) -> Result { + match value { + 1 => Ok(Interrupt::SPI0), + 2 => Ok(Interrupt::SPI1), + 3 => Ok(Interrupt::SPI_SLAVE), + 4 => Ok(Interrupt::SPI3), + 5 => Ok(Interrupt::I2S0), + 6 => Ok(Interrupt::I2S1), + 7 => Ok(Interrupt::I2S2), + 8 => Ok(Interrupt::I2C0), + 9 => Ok(Interrupt::I2C1), + 10 => Ok(Interrupt::I2C2), + 11 => Ok(Interrupt::UART1), + 12 => Ok(Interrupt::UART2), + 13 => Ok(Interrupt::UART3), + 14 => Ok(Interrupt::TIMER0A), + 15 => Ok(Interrupt::TIMER0B), + 16 => Ok(Interrupt::TIMER1A), + 17 => Ok(Interrupt::TIMER1B), + 18 => Ok(Interrupt::TIMER2A), + 19 => Ok(Interrupt::TIMER2B), + 20 => Ok(Interrupt::RTC), + 21 => Ok(Interrupt::WDT0), + 22 => Ok(Interrupt::WDT1), + 23 => Ok(Interrupt::APB_GPIO), + 24 => Ok(Interrupt::DVP), + 25 => Ok(Interrupt::KPU), + 26 => Ok(Interrupt::FFT), + 27 => Ok(Interrupt::DMA0), + 28 => Ok(Interrupt::DMA1), + 29 => Ok(Interrupt::DMA2), + 30 => Ok(Interrupt::DMA3), + 31 => Ok(Interrupt::DMA4), + 32 => Ok(Interrupt::DMA5), + 33 => Ok(Interrupt::UARTHS), + 34 => Ok(Interrupt::GPIOHS0), + 35 => Ok(Interrupt::GPIOHS1), + 36 => Ok(Interrupt::GPIOHS2), + 37 => Ok(Interrupt::GPIOHS3), + 38 => Ok(Interrupt::GPIOHS4), + 39 => Ok(Interrupt::GPIOHS5), + 40 => Ok(Interrupt::GPIOHS6), + 41 => Ok(Interrupt::GPIOHS7), + 42 => Ok(Interrupt::GPIOHS8), + 43 => Ok(Interrupt::GPIOHS9), + 44 => Ok(Interrupt::GPIOHS10), + 45 => Ok(Interrupt::GPIOHS11), + 46 => Ok(Interrupt::GPIOHS12), + 47 => Ok(Interrupt::GPIOHS13), + 48 => Ok(Interrupt::GPIOHS14), + 49 => Ok(Interrupt::GPIOHS15), + 50 => Ok(Interrupt::GPIOHS16), + 51 => Ok(Interrupt::GPIOHS17), + 52 => Ok(Interrupt::GPIOHS18), + 53 => Ok(Interrupt::GPIOHS19), + 54 => Ok(Interrupt::GPIOHS20), + 55 => Ok(Interrupt::GPIOHS21), + 56 => Ok(Interrupt::GPIOHS22), + 57 => Ok(Interrupt::GPIOHS23), + 58 => Ok(Interrupt::GPIOHS24), + 59 => Ok(Interrupt::GPIOHS25), + 60 => Ok(Interrupt::GPIOHS26), + 61 => Ok(Interrupt::GPIOHS27), + 62 => Ok(Interrupt::GPIOHS28), + 63 => Ok(Interrupt::GPIOHS29), + 64 => Ok(Interrupt::GPIOHS30), + 65 => Ok(Interrupt::GPIOHS31), + _ => Err(TryFromInterruptError(())), + } + } + } + #[cfg(feature = "rt")] + #[macro_export] + #[doc = r" Assigns a handler to an interrupt"] + #[doc = r""] + #[doc = r" This macro takes two arguments: the name of an interrupt and the path to the"] + #[doc = r" function that will be used as the handler of that interrupt. That function"] + #[doc = r" must have signature `fn()`."] + #[doc = r""] + #[doc = r" Optionally, a third argument may be used to declare interrupt local data."] + #[doc = r" The handler will have exclusive access to these *local* variables on each"] + #[doc = r" invocation. If the third argument is used then the signature of the handler"] + #[doc = r" function must be `fn(&mut $NAME::Locals)` where `$NAME` is the first argument"] + #[doc = r" passed to the macro."] + #[doc = r""] + #[doc = r" # Example"] + #[doc = r""] + #[doc = r" ``` ignore"] + #[doc = r" interrupt!(TIM2, periodic);"] + #[doc = r""] + #[doc = r" fn periodic() {"] + #[doc = r#" print!(".");"#] + #[doc = r" }"] + #[doc = r""] + #[doc = r" interrupt!(TIM3, tick, locals: {"] + #[doc = r" tick: bool = false;"] + #[doc = r" });"] + #[doc = r""] + #[doc = r" fn tick(locals: &mut TIM3::Locals) {"] + #[doc = r" locals.tick = !locals.tick;"] + #[doc = r""] + #[doc = r" if locals.tick {"] + #[doc = r#" println!("Tick");"#] + #[doc = r" } else {"] + #[doc = r#" println!("Tock");"#] + #[doc = r" }"] + #[doc = r" }"] + #[doc = r" ```"] + macro_rules ! interrupt { ( $ NAME : ident , $ path : path , locals : { $ ( $ lvar : ident : $ lty : ty = $ lval : expr ; ) * } ) => { # [ allow ( non_snake_case ) ] +mod $ NAME { pub struct Locals { $ ( pub $ lvar : $ lty , ) * } } # [ allow ( non_snake_case ) ] +# [ no_mangle ] +pub extern "C" fn $ NAME ( ) { let _ = $ crate :: interrupt :: Interrupt :: $ NAME ; static mut LOCALS : self :: $ NAME :: Locals = self :: $ NAME :: Locals { $ ( $ lvar : $ lval , ) * } ; let f : fn ( & mut self :: $ NAME :: Locals ) = $ path ; f ( unsafe { & mut LOCALS } ) ; } } ; ( $ NAME : ident , $ path : path ) => { # [ allow ( non_snake_case ) ] +# [ no_mangle ] +pub extern "C" fn $ NAME ( ) { let _ = $ crate :: interrupt :: Interrupt :: $ NAME ; let f : fn ( ) = $ path ; f ( ) ; } } } +} +pub use self::interrupt::Interrupt; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic { + use core::marker; + #[doc = " Trait implemented by readable registers to enable the `read` method."] + #[doc = ""] + #[doc = " Registers marked with `Writable` can be also `modify`'ed."] + pub trait Readable {} + #[doc = " Trait implemented by writeable registers."] + #[doc = ""] + #[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] + #[doc = ""] + #[doc = " Registers marked with `Readable` can be also `modify`'ed."] + pub trait Writable {} + #[doc = " Reset value of the register."] + #[doc = ""] + #[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] + #[doc = " register by using the `reset` method."] + pub trait ResetValue { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Type; + #[doc = " Reset value of the register."] + fn reset_value() -> Self::Type; + } + #[doc = " This structure provides volatile access to registers."] + pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, + } + unsafe impl Send for Reg {} + impl Reg + where + Self: Readable, + U: Copy, + { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> R { + R { + bits: self.register.get(), + _reg: marker::PhantomData, + } + } + } + impl Reg + where + Self: ResetValue + Writable, + U: Copy, + { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(Self::reset_value()) + } + } + impl Reg + where + Self: ResetValue + Writable, + U: Copy, + { + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut W) -> &mut W, + { + self.register.set( + f(&mut W { + bits: Self::reset_value(), + _reg: marker::PhantomData, + }) + .bits, + ); + } + } + impl Reg + where + Self: Writable, + U: Copy + Default, + { + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[inline(always)] + pub fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut W) -> &mut W, + { + self.register.set( + f(&mut W { + bits: U::default(), + _reg: marker::PhantomData, + }) + .bits, + ); + } + } + impl Reg + where + Self: Readable + Writable, + U: Copy, + { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + &R { + bits, + _reg: marker::PhantomData, + }, + &mut W { + bits, + _reg: marker::PhantomData, + }, + ) + .bits, + ); + } + } + #[doc = " Register/field reader."] + #[doc = ""] + #[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] + #[doc = " method."] + pub struct R { + pub(crate) bits: U, + _reg: marker::PhantomData, + } + impl R + where + U: Copy, + { + #[doc = " Creates a new instance of the reader."] + #[inline(always)] + pub(crate) fn new(bits: U) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } + #[doc = " Reads raw bits from register/field."] + #[inline(always)] + pub fn bits(&self) -> U { + self.bits + } + } + impl PartialEq for R + where + U: PartialEq, + FI: Copy + Into, + { + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } + } + impl R { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub fn bit_is_set(&self) -> bool { + self.bit() + } + } + #[doc = " Register writer."] + #[doc = ""] + #[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] + pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: U, + _reg: marker::PhantomData, + } + impl W { + #[doc = " Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: U) -> &mut Self { + self.bits = bits; + self + } + } + #[doc = " Used if enumerated values cover not the whole range."] + #[derive(Clone, Copy, PartialEq)] + pub enum Variant { + #[doc = " Expected variant."] + Val(T), + #[doc = " Raw bits."] + Res(U), + } +} +#[doc = "Core Local Interruptor"] +pub struct CLINT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CLINT {} +impl CLINT { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const clint::RegisterBlock { + 0x0200_0000 as *const _ + } +} +impl Deref for CLINT { + type Target = clint::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*CLINT::ptr() } + } +} +#[doc = "Core Local Interruptor"] +pub mod clint { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Hart software interrupt register"] + pub msip: [MSIP; 2], + _reserved1: [u8; 16376usize], + #[doc = "0x4000 - Hart time comparator register"] + pub mtimecmp: [MTIMECMP; 2], + _reserved2: [u8; 32744usize], + #[doc = "0xbff8 - Timer register"] + pub mtime: MTIME, + } + #[doc = "Hart software interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msip](msip) module"] + pub type MSIP = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _MSIP; + #[doc = "`read()` method returns [msip::R](msip::R) reader structure"] + impl crate::Readable for MSIP {} + #[doc = "`write(|w| ..)` method takes [msip::W](msip::W) writer structure"] + impl crate::Writable for MSIP {} + #[doc = "Hart software interrupt register"] + pub mod msip { + #[doc = "Reader of register msip[%s]"] + pub type R = crate::R; + #[doc = "Writer for register msip[%s]"] + pub type W = crate::W; + #[doc = "Register msip[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::MSIP { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Hart time comparator register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mtimecmp](mtimecmp) module"] + pub type MTIMECMP = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _MTIMECMP; + #[doc = "`read()` method returns [mtimecmp::R](mtimecmp::R) reader structure"] + impl crate::Readable for MTIMECMP {} + #[doc = "`write(|w| ..)` method takes [mtimecmp::W](mtimecmp::W) writer structure"] + impl crate::Writable for MTIMECMP {} + #[doc = "Hart time comparator register"] + pub mod mtimecmp { + #[doc = "Reader of register mtimecmp[%s]"] + pub type R = crate::R; + #[doc = "Writer for register mtimecmp[%s]"] + pub type W = crate::W; + #[doc = "Register mtimecmp[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::MTIMECMP { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Timer register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mtime](mtime) module"] + pub type MTIME = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _MTIME; + #[doc = "`read()` method returns [mtime::R](mtime::R) reader structure"] + impl crate::Readable for MTIME {} + #[doc = "`write(|w| ..)` method takes [mtime::W](mtime::W) writer structure"] + impl crate::Writable for MTIME {} + #[doc = "Timer register"] + pub mod mtime { + #[doc = "Reader of register mtime"] + pub type R = crate::R; + #[doc = "Writer for register mtime"] + pub type W = crate::W; + #[doc = "Register mtime `reset()`'s with value 0"] + impl crate::ResetValue for super::MTIME { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Platform-Level Interrupt Controller"] +pub struct PLIC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PLIC {} +impl PLIC { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const plic::RegisterBlock { + 0x0c00_0000 as *const _ + } +} +impl Deref for PLIC { + type Target = plic::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*PLIC::ptr() } + } +} +#[doc = "Platform-Level Interrupt Controller"] +pub mod plic { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Source Priority Register"] + pub priority: [PRIORITY; 1024], + #[doc = "0x1000 - Interrupt Pending Register"] + pub pending: [PENDING; 32], + _reserved2: [u8; 3968usize], + #[doc = "0x2000 - Target Interrupt Enables"] + pub target_enables: [TARGET_ENABLES; 4], + _reserved3: [u8; 2088448usize], + #[doc = "0x200000 - Target Configuration"] + pub targets: [TARGETS; 4], + } + #[doc = r"Register block"] + #[repr(C)] + pub struct TARGET_ENABLES { + #[doc = "0x00 - Interrupt Enable Register"] + pub enable: [self::target_enables::ENABLE; 32], + } + #[doc = r"Register block"] + #[doc = "Target Interrupt Enables"] + pub mod target_enables { + #[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](enable) module"] + pub type ENABLE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ENABLE; + #[doc = "`read()` method returns [enable::R](enable::R) reader structure"] + impl crate::Readable for ENABLE {} + #[doc = "`write(|w| ..)` method takes [enable::W](enable::W) writer structure"] + impl crate::Writable for ENABLE {} + #[doc = "Interrupt Enable Register"] + pub mod enable { + #[doc = "Reader of register enable[%s]"] + pub type R = crate::R; + #[doc = "Writer for register enable[%s]"] + pub type W = crate::W; + #[doc = "Register enable[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::ENABLE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + } + #[doc = r"Register block"] + #[repr(C)] + pub struct TARGETS { + #[doc = "0x00 - Priority Threshold Register"] + pub threshold: self::targets::THRESHOLD, + #[doc = "0x04 - Claim/Complete Register"] + pub claim: self::targets::CLAIM, + _reserved2: [u8; 4084usize], + #[doc = "0xffc - Padding to make sure targets is an array"] + pub _reserved: self::targets::_RESERVED, + } + #[doc = r"Register block"] + #[doc = "Target Configuration"] + pub mod targets { + #[doc = "Priority Threshold Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [threshold](threshold) module"] + pub type THRESHOLD = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _THRESHOLD; + #[doc = "`read()` method returns [threshold::R](threshold::R) reader structure"] + impl crate::Readable for THRESHOLD {} + #[doc = "`write(|w| ..)` method takes [threshold::W](threshold::W) writer structure"] + impl crate::Writable for THRESHOLD {} + #[doc = "Priority Threshold Register"] + pub mod threshold { + #[doc = "Reader of register threshold"] + pub type R = crate::R; + #[doc = "Writer for register threshold"] + pub type W = crate::W; + #[doc = "Register threshold `reset()`'s with value 0"] + impl crate::ResetValue for super::THRESHOLD { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum PRIORITY_A { + #[doc = "0: Never interrupt"] + NEVER = 0, + #[doc = "1: Priority 1"] + P1 = 1, + #[doc = "2: Priority 2"] + P2 = 2, + #[doc = "3: Priority 3"] + P3 = 3, + #[doc = "4: Priority 4"] + P4 = 4, + #[doc = "5: Priority 5"] + P5 = 5, + #[doc = "6: Priority 6"] + P6 = 6, + #[doc = "7: Priority 7"] + P7 = 7, + } + impl From for u8 { + #[inline(always)] + fn from(variant: PRIORITY_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `priority`"] + pub type PRIORITY_R = crate::R; + impl PRIORITY_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRIORITY_A { + match self.bits { + 0 => PRIORITY_A::NEVER, + 1 => PRIORITY_A::P1, + 2 => PRIORITY_A::P2, + 3 => PRIORITY_A::P3, + 4 => PRIORITY_A::P4, + 5 => PRIORITY_A::P5, + 6 => PRIORITY_A::P6, + 7 => PRIORITY_A::P7, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NEVER`"] + #[inline(always)] + pub fn is_never(&self) -> bool { + *self == PRIORITY_A::NEVER + } + #[doc = "Checks if the value of the field is `P1`"] + #[inline(always)] + pub fn is_p1(&self) -> bool { + *self == PRIORITY_A::P1 + } + #[doc = "Checks if the value of the field is `P2`"] + #[inline(always)] + pub fn is_p2(&self) -> bool { + *self == PRIORITY_A::P2 + } + #[doc = "Checks if the value of the field is `P3`"] + #[inline(always)] + pub fn is_p3(&self) -> bool { + *self == PRIORITY_A::P3 + } + #[doc = "Checks if the value of the field is `P4`"] + #[inline(always)] + pub fn is_p4(&self) -> bool { + *self == PRIORITY_A::P4 + } + #[doc = "Checks if the value of the field is `P5`"] + #[inline(always)] + pub fn is_p5(&self) -> bool { + *self == PRIORITY_A::P5 + } + #[doc = "Checks if the value of the field is `P6`"] + #[inline(always)] + pub fn is_p6(&self) -> bool { + *self == PRIORITY_A::P6 + } + #[doc = "Checks if the value of the field is `P7`"] + #[inline(always)] + pub fn is_p7(&self) -> bool { + *self == PRIORITY_A::P7 + } + } + #[doc = "Write proxy for field `priority`"] + pub struct PRIORITY_W<'a> { + w: &'a mut W, + } + impl<'a> PRIORITY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRIORITY_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "Never interrupt"] + #[inline(always)] + pub fn never(self) -> &'a mut W { + self.variant(PRIORITY_A::NEVER) + } + #[doc = "Priority 1"] + #[inline(always)] + pub fn p1(self) -> &'a mut W { + self.variant(PRIORITY_A::P1) + } + #[doc = "Priority 2"] + #[inline(always)] + pub fn p2(self) -> &'a mut W { + self.variant(PRIORITY_A::P2) + } + #[doc = "Priority 3"] + #[inline(always)] + pub fn p3(self) -> &'a mut W { + self.variant(PRIORITY_A::P3) + } + #[doc = "Priority 4"] + #[inline(always)] + pub fn p4(self) -> &'a mut W { + self.variant(PRIORITY_A::P4) + } + #[doc = "Priority 5"] + #[inline(always)] + pub fn p5(self) -> &'a mut W { + self.variant(PRIORITY_A::P5) + } + #[doc = "Priority 6"] + #[inline(always)] + pub fn p6(self) -> &'a mut W { + self.variant(PRIORITY_A::P6) + } + #[doc = "Priority 7"] + #[inline(always)] + pub fn p7(self) -> &'a mut W { + self.variant(PRIORITY_A::P7) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + impl R { + #[doc = "Bits 0:2"] + #[inline(always)] + pub fn priority(&self) -> PRIORITY_R { + PRIORITY_R::new((self.bits & 0x07) as u8) + } + } + impl W { + #[doc = "Bits 0:2"] + #[inline(always)] + pub fn priority(&mut self) -> PRIORITY_W { + PRIORITY_W { w: self } + } + } + } + #[doc = "Claim/Complete Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claim](claim) module"] + pub type CLAIM = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLAIM; + #[doc = "`read()` method returns [claim::R](claim::R) reader structure"] + impl crate::Readable for CLAIM {} + #[doc = "`write(|w| ..)` method takes [claim::W](claim::W) writer structure"] + impl crate::Writable for CLAIM {} + #[doc = "Claim/Complete Register"] + pub mod claim { + #[doc = "Reader of register claim"] + pub type R = crate::R; + #[doc = "Writer for register claim"] + pub type W = crate::W; + #[doc = "Register claim `reset()`'s with value 0"] + impl crate::ResetValue for super::CLAIM { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Padding to make sure targets is an array\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_reserved](_reserved) module"] + pub type _RESERVED = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct __RESERVED; + #[doc = "`read()` method returns [_reserved::R](_reserved::R) reader structure"] + impl crate::Readable for _RESERVED {} + #[doc = "`write(|w| ..)` method takes [_reserved::W](_reserved::W) writer structure"] + impl crate::Writable for _RESERVED {} + #[doc = "Padding to make sure targets is an array"] + pub mod _reserved { + #[doc = "Reader of register _reserved"] + pub type R = crate::R; + #[doc = "Writer for register _reserved"] + pub type W = crate::W; + #[doc = "Register _reserved `reset()`'s with value 0"] + impl crate::ResetValue for super::_RESERVED { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + } + #[doc = "Interrupt Source Priority Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [priority](priority) module"] + pub type PRIORITY = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PRIORITY; + #[doc = "`read()` method returns [priority::R](priority::R) reader structure"] + impl crate::Readable for PRIORITY {} + #[doc = "`write(|w| ..)` method takes [priority::W](priority::W) writer structure"] + impl crate::Writable for PRIORITY {} + #[doc = "Interrupt Source Priority Register"] + pub mod priority { + #[doc = "Reader of register priority[%s]"] + pub type R = crate::R; + #[doc = "Writer for register priority[%s]"] + pub type W = crate::W; + #[doc = "Register priority[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::PRIORITY { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Pending Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pending](pending) module"] + pub type PENDING = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PENDING; + #[doc = "`read()` method returns [pending::R](pending::R) reader structure"] + impl crate::Readable for PENDING {} + #[doc = "`write(|w| ..)` method takes [pending::W](pending::W) writer structure"] + impl crate::Writable for PENDING {} + #[doc = "Interrupt Pending Register"] + pub mod pending { + #[doc = "Reader of register pending[%s]"] + pub type R = crate::R; + #[doc = "Writer for register pending[%s]"] + pub type W = crate::W; + #[doc = "Register pending[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::PENDING { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "High-speed UART"] +pub struct UARTHS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UARTHS {} +impl UARTHS { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uarths::RegisterBlock { + 0x3800_0000 as *const _ + } +} +impl Deref for UARTHS { + type Target = uarths::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*UARTHS::ptr() } + } +} +#[doc = "High-speed UART"] +pub mod uarths { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Transmit Data Register"] + pub txdata: TXDATA, + #[doc = "0x04 - Receive Data Register"] + pub rxdata: RXDATA, + #[doc = "0x08 - Transmit Control Register"] + pub txctrl: TXCTRL, + #[doc = "0x0c - Receive Control Register"] + pub rxctrl: RXCTRL, + #[doc = "0x10 - Interrupt Enable Register"] + pub ie: IE, + #[doc = "0x14 - Interrupt Pending Register"] + pub ip: IP, + #[doc = "0x18 - Baud Rate Divisor Register"] + pub div: DIV, + } + #[doc = "Transmit Data Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txdata](txdata) module"] + pub type TXDATA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TXDATA; + #[doc = "`read()` method returns [txdata::R](txdata::R) reader structure"] + impl crate::Readable for TXDATA {} + #[doc = "`write(|w| ..)` method takes [txdata::W](txdata::W) writer structure"] + impl crate::Writable for TXDATA {} + #[doc = "Transmit Data Register"] + pub mod txdata { + #[doc = "Reader of register txdata"] + pub type R = crate::R; + #[doc = "Writer for register txdata"] + pub type W = crate::W; + #[doc = "Register txdata `reset()`'s with value 0"] + impl crate::ResetValue for super::TXDATA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `data`"] + pub type DATA_R = crate::R; + #[doc = "Write proxy for field `data`"] + pub struct DATA_W<'a> { + w: &'a mut W, + } + impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + #[doc = "Reader of field `full`"] + pub type FULL_R = crate::R; + #[doc = "Write proxy for field `full`"] + pub struct FULL_W<'a> { + w: &'a mut W, + } + impl<'a> FULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31); + self.w + } + } + impl R { + #[doc = "Bits 0:7 - Transmit data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31 - Transmit FIFO full"] + #[inline(always)] + pub fn full(&self) -> FULL_R { + FULL_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:7 - Transmit data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Bit 31 - Transmit FIFO full"] + #[inline(always)] + pub fn full(&mut self) -> FULL_W { + FULL_W { w: self } + } + } + } + #[doc = "Receive Data Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxdata](rxdata) module"] + pub type RXDATA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXDATA; + #[doc = "`read()` method returns [rxdata::R](rxdata::R) reader structure"] + impl crate::Readable for RXDATA {} + #[doc = "`write(|w| ..)` method takes [rxdata::W](rxdata::W) writer structure"] + impl crate::Writable for RXDATA {} + #[doc = "Receive Data Register"] + pub mod rxdata { + #[doc = "Reader of register rxdata"] + pub type R = crate::R; + #[doc = "Writer for register rxdata"] + pub type W = crate::W; + #[doc = "Register rxdata `reset()`'s with value 0"] + impl crate::ResetValue for super::RXDATA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `data`"] + pub type DATA_R = crate::R; + #[doc = "Write proxy for field `data`"] + pub struct DATA_W<'a> { + w: &'a mut W, + } + impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + #[doc = "Reader of field `empty`"] + pub type EMPTY_R = crate::R; + #[doc = "Write proxy for field `empty`"] + pub struct EMPTY_W<'a> { + w: &'a mut W, + } + impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31); + self.w + } + } + impl R { + #[doc = "Bits 0:7 - Received data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31 - Receive FIFO empty"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:7 - Received data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Bit 31 - Receive FIFO empty"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + } + } + #[doc = "Transmit Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txctrl](txctrl) module"] + pub type TXCTRL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TXCTRL; + #[doc = "`read()` method returns [txctrl::R](txctrl::R) reader structure"] + impl crate::Readable for TXCTRL {} + #[doc = "`write(|w| ..)` method takes [txctrl::W](txctrl::W) writer structure"] + impl crate::Writable for TXCTRL {} + #[doc = "Transmit Control Register"] + pub mod txctrl { + #[doc = "Reader of register txctrl"] + pub type R = crate::R; + #[doc = "Writer for register txctrl"] + pub type W = crate::W; + #[doc = "Register txctrl `reset()`'s with value 0"] + impl crate::ResetValue for super::TXCTRL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `txen`"] + pub type TXEN_R = crate::R; + #[doc = "Write proxy for field `txen`"] + pub struct TXEN_W<'a> { + w: &'a mut W, + } + impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `nstop`"] + pub type NSTOP_R = crate::R; + #[doc = "Write proxy for field `nstop`"] + pub struct NSTOP_W<'a> { + w: &'a mut W, + } + impl<'a> NSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `txcnt`"] + pub type TXCNT_R = crate::R; + #[doc = "Write proxy for field `txcnt`"] + pub struct TXCNT_W<'a> { + w: &'a mut W, + } + impl<'a> TXCNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | (((value as u32) & 0x07) << 16); + self.w + } + } + impl R { + #[doc = "Bit 0 - Transmit enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Number of stop bits"] + #[inline(always)] + pub fn nstop(&self) -> NSTOP_R { + NSTOP_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 16:18 - Transmit watermark level"] + #[inline(always)] + pub fn txcnt(&self) -> TXCNT_R { + TXCNT_R::new(((self.bits >> 16) & 0x07) as u8) + } + } + impl W { + #[doc = "Bit 0 - Transmit enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 1 - Number of stop bits"] + #[inline(always)] + pub fn nstop(&mut self) -> NSTOP_W { + NSTOP_W { w: self } + } + #[doc = "Bits 16:18 - Transmit watermark level"] + #[inline(always)] + pub fn txcnt(&mut self) -> TXCNT_W { + TXCNT_W { w: self } + } + } + } + #[doc = "Receive Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxctrl](rxctrl) module"] + pub type RXCTRL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXCTRL; + #[doc = "`read()` method returns [rxctrl::R](rxctrl::R) reader structure"] + impl crate::Readable for RXCTRL {} + #[doc = "`write(|w| ..)` method takes [rxctrl::W](rxctrl::W) writer structure"] + impl crate::Writable for RXCTRL {} + #[doc = "Receive Control Register"] + pub mod rxctrl { + #[doc = "Reader of register rxctrl"] + pub type R = crate::R; + #[doc = "Writer for register rxctrl"] + pub type W = crate::W; + #[doc = "Register rxctrl `reset()`'s with value 0"] + impl crate::ResetValue for super::RXCTRL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `rxen`"] + pub type RXEN_R = crate::R; + #[doc = "Write proxy for field `rxen`"] + pub struct RXEN_W<'a> { + w: &'a mut W, + } + impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `rxcnt`"] + pub type RXCNT_R = crate::R; + #[doc = "Write proxy for field `rxcnt`"] + pub struct RXCNT_W<'a> { + w: &'a mut W, + } + impl<'a> RXCNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | (((value as u32) & 0x07) << 16); + self.w + } + } + impl R { + #[doc = "Bit 0 - Receive enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 16:18 - Receive watermark level"] + #[inline(always)] + pub fn rxcnt(&self) -> RXCNT_R { + RXCNT_R::new(((self.bits >> 16) & 0x07) as u8) + } + } + impl W { + #[doc = "Bit 0 - Receive enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Bits 16:18 - Receive watermark level"] + #[inline(always)] + pub fn rxcnt(&mut self) -> RXCNT_W { + RXCNT_W { w: self } + } + } + } + #[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ie](ie) module"] + pub type IE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IE; + #[doc = "`read()` method returns [ie::R](ie::R) reader structure"] + impl crate::Readable for IE {} + #[doc = "`write(|w| ..)` method takes [ie::W](ie::W) writer structure"] + impl crate::Writable for IE {} + #[doc = "Interrupt Enable Register"] + pub mod ie { + #[doc = "Reader of register ie"] + pub type R = crate::R; + #[doc = "Writer for register ie"] + pub type W = crate::W; + #[doc = "Register ie `reset()`'s with value 0"] + impl crate::ResetValue for super::IE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `txwm`"] + pub type TXWM_R = crate::R; + #[doc = "Write proxy for field `txwm`"] + pub struct TXWM_W<'a> { + w: &'a mut W, + } + impl<'a> TXWM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `rxwm`"] + pub type RXWM_R = crate::R; + #[doc = "Write proxy for field `rxwm`"] + pub struct RXWM_W<'a> { + w: &'a mut W, + } + impl<'a> RXWM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + impl R { + #[doc = "Bit 0 - Transmit watermark interrupt enable"] + #[inline(always)] + pub fn txwm(&self) -> TXWM_R { + TXWM_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Receive watermark interrupt enable"] + #[inline(always)] + pub fn rxwm(&self) -> RXWM_R { + RXWM_R::new(((self.bits >> 1) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Transmit watermark interrupt enable"] + #[inline(always)] + pub fn txwm(&mut self) -> TXWM_W { + TXWM_W { w: self } + } + #[doc = "Bit 1 - Receive watermark interrupt enable"] + #[inline(always)] + pub fn rxwm(&mut self) -> RXWM_W { + RXWM_W { w: self } + } + } + } + #[doc = "Interrupt Pending Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ip](ip) module"] + pub type IP = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IP; + #[doc = "`read()` method returns [ip::R](ip::R) reader structure"] + impl crate::Readable for IP {} + #[doc = "`write(|w| ..)` method takes [ip::W](ip::W) writer structure"] + impl crate::Writable for IP {} + #[doc = "Interrupt Pending Register"] + pub mod ip { + #[doc = "Reader of register ip"] + pub type R = crate::R; + #[doc = "Writer for register ip"] + pub type W = crate::W; + #[doc = "Register ip `reset()`'s with value 0"] + impl crate::ResetValue for super::IP { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `txwm`"] + pub type TXWM_R = crate::R; + #[doc = "Write proxy for field `txwm`"] + pub struct TXWM_W<'a> { + w: &'a mut W, + } + impl<'a> TXWM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `rxwm`"] + pub type RXWM_R = crate::R; + #[doc = "Write proxy for field `rxwm`"] + pub struct RXWM_W<'a> { + w: &'a mut W, + } + impl<'a> RXWM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + impl R { + #[doc = "Bit 0 - Transmit watermark interrupt pending"] + #[inline(always)] + pub fn txwm(&self) -> TXWM_R { + TXWM_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Receive watermark interrupt pending"] + #[inline(always)] + pub fn rxwm(&self) -> RXWM_R { + RXWM_R::new(((self.bits >> 1) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Transmit watermark interrupt pending"] + #[inline(always)] + pub fn txwm(&mut self) -> TXWM_W { + TXWM_W { w: self } + } + #[doc = "Bit 1 - Receive watermark interrupt pending"] + #[inline(always)] + pub fn rxwm(&mut self) -> RXWM_W { + RXWM_W { w: self } + } + } + } + #[doc = "Baud Rate Divisor Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [div](div) module"] + pub type DIV = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DIV; + #[doc = "`read()` method returns [div::R](div::R) reader structure"] + impl crate::Readable for DIV {} + #[doc = "`write(|w| ..)` method takes [div::W](div::W) writer structure"] + impl crate::Writable for DIV {} + #[doc = "Baud Rate Divisor Register"] + pub mod div { + #[doc = "Reader of register div"] + pub type R = crate::R; + #[doc = "Writer for register div"] + pub type W = crate::W; + #[doc = "Register div `reset()`'s with value 0"] + impl crate::ResetValue for super::DIV { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `div`"] + pub type DIV_R = crate::R; + #[doc = "Write proxy for field `div`"] + pub struct DIV_W<'a> { + w: &'a mut W, + } + impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + impl R { + #[doc = "Bits 0:15 - Baud rate divisor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new((self.bits & 0xffff) as u16) + } + } + impl W { + #[doc = "Bits 0:15 - Baud rate divisor"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + } + } +} +#[doc = "High-speed GPIO"] +pub struct GPIOHS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GPIOHS {} +impl GPIOHS { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gpiohs::RegisterBlock { + 0x3800_1000 as *const _ + } +} +impl Deref for GPIOHS { + type Target = gpiohs::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*GPIOHS::ptr() } + } +} +#[doc = "High-speed GPIO"] +pub mod gpiohs { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Input Value Register"] + pub input_val: INPUT_VAL, + #[doc = "0x04 - Pin Input Enable Register"] + pub input_en: INPUT_EN, + #[doc = "0x08 - Pin Output Enable Register"] + pub output_en: OUTPUT_EN, + #[doc = "0x0c - Output Value Register"] + pub output_val: OUTPUT_VAL, + #[doc = "0x10 - Internal Pull-Up Enable Register"] + pub pullup_en: PULLUP_EN, + #[doc = "0x14 - Drive Strength Register"] + pub drive: DRIVE, + #[doc = "0x18 - Rise Interrupt Enable Register"] + pub rise_ie: RISE_IE, + #[doc = "0x1c - Rise Interrupt Pending Register"] + pub rise_ip: RISE_IP, + #[doc = "0x20 - Fall Interrupt Enable Register"] + pub fall_ie: FALL_IE, + #[doc = "0x24 - Fall Interrupt Pending Register"] + pub fall_ip: FALL_IP, + #[doc = "0x28 - High Interrupt Enable Register"] + pub high_ie: HIGH_IE, + #[doc = "0x2c - High Interrupt Pending Register"] + pub high_ip: HIGH_IP, + #[doc = "0x30 - Low Interrupt Enable Register"] + pub low_ie: LOW_IE, + #[doc = "0x34 - Low Interrupt Pending Register"] + pub low_ip: LOW_IP, + #[doc = "0x38 - HW I/O Function Enable Register"] + pub iof_en: IOF_EN, + #[doc = "0x3c - HW I/O Function Select Register"] + pub iof_sel: IOF_SEL, + #[doc = "0x40 - Output XOR (invert) Register"] + pub output_xor: OUTPUT_XOR, + } + #[doc = "Input Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [input_val](input_val) module"] + pub type INPUT_VAL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INPUT_VAL; + #[doc = "`read()` method returns [input_val::R](input_val::R) reader structure"] + impl crate::Readable for INPUT_VAL {} + #[doc = "`write(|w| ..)` method takes [input_val::W](input_val::W) writer structure"] + impl crate::Writable for INPUT_VAL {} + #[doc = "Input Value Register"] + pub mod input_val { + #[doc = "Reader of register input_val"] + pub type R = crate::R; + #[doc = "Writer for register input_val"] + pub type W = crate::W; + #[doc = "Register input_val `reset()`'s with value 0"] + impl crate::ResetValue for super::INPUT_VAL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Pin Input Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [input_en](input_en) module"] + pub type INPUT_EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INPUT_EN; + #[doc = "`read()` method returns [input_en::R](input_en::R) reader structure"] + impl crate::Readable for INPUT_EN {} + #[doc = "`write(|w| ..)` method takes [input_en::W](input_en::W) writer structure"] + impl crate::Writable for INPUT_EN {} + #[doc = "Pin Input Enable Register"] + pub mod input_en { + #[doc = "Reader of register input_en"] + pub type R = crate::R; + #[doc = "Writer for register input_en"] + pub type W = crate::W; + #[doc = "Register input_en `reset()`'s with value 0"] + impl crate::ResetValue for super::INPUT_EN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Pin Output Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [output_en](output_en) module"] + pub type OUTPUT_EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _OUTPUT_EN; + #[doc = "`read()` method returns [output_en::R](output_en::R) reader structure"] + impl crate::Readable for OUTPUT_EN {} + #[doc = "`write(|w| ..)` method takes [output_en::W](output_en::W) writer structure"] + impl crate::Writable for OUTPUT_EN {} + #[doc = "Pin Output Enable Register"] + pub mod output_en { + #[doc = "Reader of register output_en"] + pub type R = crate::R; + #[doc = "Writer for register output_en"] + pub type W = crate::W; + #[doc = "Register output_en `reset()`'s with value 0"] + impl crate::ResetValue for super::OUTPUT_EN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Output Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [output_val](output_val) module"] + pub type OUTPUT_VAL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _OUTPUT_VAL; + #[doc = "`read()` method returns [output_val::R](output_val::R) reader structure"] + impl crate::Readable for OUTPUT_VAL {} + #[doc = "`write(|w| ..)` method takes [output_val::W](output_val::W) writer structure"] + impl crate::Writable for OUTPUT_VAL {} + #[doc = "Output Value Register"] + pub mod output_val { + #[doc = "Reader of register output_val"] + pub type R = crate::R; + #[doc = "Writer for register output_val"] + pub type W = crate::W; + #[doc = "Register output_val `reset()`'s with value 0"] + impl crate::ResetValue for super::OUTPUT_VAL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Internal Pull-Up Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pullup_en](pullup_en) module"] + pub type PULLUP_EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PULLUP_EN; + #[doc = "`read()` method returns [pullup_en::R](pullup_en::R) reader structure"] + impl crate::Readable for PULLUP_EN {} + #[doc = "`write(|w| ..)` method takes [pullup_en::W](pullup_en::W) writer structure"] + impl crate::Writable for PULLUP_EN {} + #[doc = "Internal Pull-Up Enable Register"] + pub mod pullup_en { + #[doc = "Reader of register pullup_en"] + pub type R = crate::R; + #[doc = "Writer for register pullup_en"] + pub type W = crate::W; + #[doc = "Register pullup_en `reset()`'s with value 0"] + impl crate::ResetValue for super::PULLUP_EN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Drive Strength Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drive](drive) module"] + pub type DRIVE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DRIVE; + #[doc = "`read()` method returns [drive::R](drive::R) reader structure"] + impl crate::Readable for DRIVE {} + #[doc = "`write(|w| ..)` method takes [drive::W](drive::W) writer structure"] + impl crate::Writable for DRIVE {} + #[doc = "Drive Strength Register"] + pub mod drive { + #[doc = "Reader of register drive"] + pub type R = crate::R; + #[doc = "Writer for register drive"] + pub type W = crate::W; + #[doc = "Register drive `reset()`'s with value 0"] + impl crate::ResetValue for super::DRIVE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Rise Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rise_ie](rise_ie) module"] + pub type RISE_IE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RISE_IE; + #[doc = "`read()` method returns [rise_ie::R](rise_ie::R) reader structure"] + impl crate::Readable for RISE_IE {} + #[doc = "`write(|w| ..)` method takes [rise_ie::W](rise_ie::W) writer structure"] + impl crate::Writable for RISE_IE {} + #[doc = "Rise Interrupt Enable Register"] + pub mod rise_ie { + #[doc = "Reader of register rise_ie"] + pub type R = crate::R; + #[doc = "Writer for register rise_ie"] + pub type W = crate::W; + #[doc = "Register rise_ie `reset()`'s with value 0"] + impl crate::ResetValue for super::RISE_IE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Rise Interrupt Pending Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rise_ip](rise_ip) module"] + pub type RISE_IP = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RISE_IP; + #[doc = "`read()` method returns [rise_ip::R](rise_ip::R) reader structure"] + impl crate::Readable for RISE_IP {} + #[doc = "`write(|w| ..)` method takes [rise_ip::W](rise_ip::W) writer structure"] + impl crate::Writable for RISE_IP {} + #[doc = "Rise Interrupt Pending Register"] + pub mod rise_ip { + #[doc = "Reader of register rise_ip"] + pub type R = crate::R; + #[doc = "Writer for register rise_ip"] + pub type W = crate::W; + #[doc = "Register rise_ip `reset()`'s with value 0"] + impl crate::ResetValue for super::RISE_IP { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Fall Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fall_ie](fall_ie) module"] + pub type FALL_IE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FALL_IE; + #[doc = "`read()` method returns [fall_ie::R](fall_ie::R) reader structure"] + impl crate::Readable for FALL_IE {} + #[doc = "`write(|w| ..)` method takes [fall_ie::W](fall_ie::W) writer structure"] + impl crate::Writable for FALL_IE {} + #[doc = "Fall Interrupt Enable Register"] + pub mod fall_ie { + #[doc = "Reader of register fall_ie"] + pub type R = crate::R; + #[doc = "Writer for register fall_ie"] + pub type W = crate::W; + #[doc = "Register fall_ie `reset()`'s with value 0"] + impl crate::ResetValue for super::FALL_IE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Fall Interrupt Pending Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fall_ip](fall_ip) module"] + pub type FALL_IP = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FALL_IP; + #[doc = "`read()` method returns [fall_ip::R](fall_ip::R) reader structure"] + impl crate::Readable for FALL_IP {} + #[doc = "`write(|w| ..)` method takes [fall_ip::W](fall_ip::W) writer structure"] + impl crate::Writable for FALL_IP {} + #[doc = "Fall Interrupt Pending Register"] + pub mod fall_ip { + #[doc = "Reader of register fall_ip"] + pub type R = crate::R; + #[doc = "Writer for register fall_ip"] + pub type W = crate::W; + #[doc = "Register fall_ip `reset()`'s with value 0"] + impl crate::ResetValue for super::FALL_IP { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "High Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [high_ie](high_ie) module"] + pub type HIGH_IE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _HIGH_IE; + #[doc = "`read()` method returns [high_ie::R](high_ie::R) reader structure"] + impl crate::Readable for HIGH_IE {} + #[doc = "`write(|w| ..)` method takes [high_ie::W](high_ie::W) writer structure"] + impl crate::Writable for HIGH_IE {} + #[doc = "High Interrupt Enable Register"] + pub mod high_ie { + #[doc = "Reader of register high_ie"] + pub type R = crate::R; + #[doc = "Writer for register high_ie"] + pub type W = crate::W; + #[doc = "Register high_ie `reset()`'s with value 0"] + impl crate::ResetValue for super::HIGH_IE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "High Interrupt Pending Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [high_ip](high_ip) module"] + pub type HIGH_IP = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _HIGH_IP; + #[doc = "`read()` method returns [high_ip::R](high_ip::R) reader structure"] + impl crate::Readable for HIGH_IP {} + #[doc = "`write(|w| ..)` method takes [high_ip::W](high_ip::W) writer structure"] + impl crate::Writable for HIGH_IP {} + #[doc = "High Interrupt Pending Register"] + pub mod high_ip { + #[doc = "Reader of register high_ip"] + pub type R = crate::R; + #[doc = "Writer for register high_ip"] + pub type W = crate::W; + #[doc = "Register high_ip `reset()`'s with value 0"] + impl crate::ResetValue for super::HIGH_IP { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Low Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [low_ie](low_ie) module"] + pub type LOW_IE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LOW_IE; + #[doc = "`read()` method returns [low_ie::R](low_ie::R) reader structure"] + impl crate::Readable for LOW_IE {} + #[doc = "`write(|w| ..)` method takes [low_ie::W](low_ie::W) writer structure"] + impl crate::Writable for LOW_IE {} + #[doc = "Low Interrupt Enable Register"] + pub mod low_ie { + #[doc = "Reader of register low_ie"] + pub type R = crate::R; + #[doc = "Writer for register low_ie"] + pub type W = crate::W; + #[doc = "Register low_ie `reset()`'s with value 0"] + impl crate::ResetValue for super::LOW_IE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Low Interrupt Pending Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [low_ip](low_ip) module"] + pub type LOW_IP = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LOW_IP; + #[doc = "`read()` method returns [low_ip::R](low_ip::R) reader structure"] + impl crate::Readable for LOW_IP {} + #[doc = "`write(|w| ..)` method takes [low_ip::W](low_ip::W) writer structure"] + impl crate::Writable for LOW_IP {} + #[doc = "Low Interrupt Pending Register"] + pub mod low_ip { + #[doc = "Reader of register low_ip"] + pub type R = crate::R; + #[doc = "Writer for register low_ip"] + pub type W = crate::W; + #[doc = "Register low_ip `reset()`'s with value 0"] + impl crate::ResetValue for super::LOW_IP { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "HW I/O Function Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iof_en](iof_en) module"] + pub type IOF_EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IOF_EN; + #[doc = "`read()` method returns [iof_en::R](iof_en::R) reader structure"] + impl crate::Readable for IOF_EN {} + #[doc = "`write(|w| ..)` method takes [iof_en::W](iof_en::W) writer structure"] + impl crate::Writable for IOF_EN {} + #[doc = "HW I/O Function Enable Register"] + pub mod iof_en { + #[doc = "Reader of register iof_en"] + pub type R = crate::R; + #[doc = "Writer for register iof_en"] + pub type W = crate::W; + #[doc = "Register iof_en `reset()`'s with value 0"] + impl crate::ResetValue for super::IOF_EN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "HW I/O Function Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iof_sel](iof_sel) module"] + pub type IOF_SEL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IOF_SEL; + #[doc = "`read()` method returns [iof_sel::R](iof_sel::R) reader structure"] + impl crate::Readable for IOF_SEL {} + #[doc = "`write(|w| ..)` method takes [iof_sel::W](iof_sel::W) writer structure"] + impl crate::Writable for IOF_SEL {} + #[doc = "HW I/O Function Select Register"] + pub mod iof_sel { + #[doc = "Reader of register iof_sel"] + pub type R = crate::R; + #[doc = "Writer for register iof_sel"] + pub type W = crate::W; + #[doc = "Register iof_sel `reset()`'s with value 0"] + impl crate::ResetValue for super::IOF_SEL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Output XOR (invert) Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [output_xor](output_xor) module"] + pub type OUTPUT_XOR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _OUTPUT_XOR; + #[doc = "`read()` method returns [output_xor::R](output_xor::R) reader structure"] + impl crate::Readable for OUTPUT_XOR {} + #[doc = "`write(|w| ..)` method takes [output_xor::W](output_xor::W) writer structure"] + impl crate::Writable for OUTPUT_XOR {} + #[doc = "Output XOR (invert) Register"] + pub mod output_xor { + #[doc = "Reader of register output_xor"] + pub type R = crate::R; + #[doc = "Writer for register output_xor"] + pub type W = crate::W; + #[doc = "Register output_xor `reset()`'s with value 0"] + impl crate::ResetValue for super::OUTPUT_XOR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } +} +#[doc = "Neural Network Accelerator"] +pub struct KPU { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for KPU {} +impl KPU { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const kpu::RegisterBlock { + 0x4080_0000 as *const _ + } +} +impl Deref for KPU { + type Target = kpu::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*KPU::ptr() } + } +} +#[doc = "Neural Network Accelerator"] +pub mod kpu { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Layer arguments FIFO: each layer is defined by writing 12 successive argument values to this register"] + pub layer_argument_fifo: LAYER_ARGUMENT_FIFO, + #[doc = "0x08 - Interrupt status"] + pub interrupt_status: INTERRUPT_STATUS, + #[doc = "0x10 - Interrupt raw"] + pub interrupt_raw: INTERRUPT_RAW, + #[doc = "0x18 - Interrupt mask: 0 enables the interrupt, 1 masks the interrupt"] + pub interrupt_mask: INTERRUPT_MASK, + #[doc = "0x20 - Interrupt clear: write 1 to a bit to clear interrupt"] + pub interrupt_clear: INTERRUPT_CLEAR, + #[doc = "0x28 - FIFO threshold"] + pub fifo_threshold: FIFO_THRESHOLD, + #[doc = "0x30 - FIFO data output"] + pub fifo_data_out: FIFO_DATA_OUT, + #[doc = "0x38 - FIFO control"] + pub fifo_ctrl: FIFO_CTRL, + #[doc = "0x40 - Eight bit mode"] + pub eight_bit_mode: EIGHT_BIT_MODE, + } + #[doc = "Layer arguments FIFO: each layer is defined by writing 12 successive argument values to this register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [layer_argument_fifo](layer_argument_fifo) module"] + pub type LAYER_ARGUMENT_FIFO = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LAYER_ARGUMENT_FIFO; + #[doc = "`read()` method returns [layer_argument_fifo::R](layer_argument_fifo::R) reader structure"] + impl crate::Readable for LAYER_ARGUMENT_FIFO {} + #[doc = "`write(|w| ..)` method takes [layer_argument_fifo::W](layer_argument_fifo::W) writer structure"] + impl crate::Writable for LAYER_ARGUMENT_FIFO {} + #[doc = "Layer arguments FIFO: each layer is defined by writing 12 successive argument values to this register"] + pub mod layer_argument_fifo { + #[doc = "Reader of register layer_argument_fifo"] + pub type R = crate::R; + #[doc = "Writer for register layer_argument_fifo"] + pub type W = crate::W; + #[doc = "Register layer_argument_fifo `reset()`'s with value 0"] + impl crate::ResetValue for super::LAYER_ARGUMENT_FIFO { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_status](interrupt_status) module"] + pub type INTERRUPT_STATUS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_STATUS; + #[doc = "`read()` method returns [interrupt_status::R](interrupt_status::R) reader structure"] + impl crate::Readable for INTERRUPT_STATUS {} + #[doc = "`write(|w| ..)` method takes [interrupt_status::W](interrupt_status::W) writer structure"] + impl crate::Writable for INTERRUPT_STATUS {} + #[doc = "Interrupt status"] + pub mod interrupt_status { + #[doc = "Reader of register interrupt_status"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_status"] + pub type W = crate::W; + #[doc = "Register interrupt_status `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_STATUS { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `calc_done`"] + pub type CALC_DONE_R = crate::R; + #[doc = "Write proxy for field `calc_done`"] + pub struct CALC_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> CALC_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `layer_cfg_almost_empty`"] + pub type LAYER_CFG_ALMOST_EMPTY_R = crate::R; + #[doc = "Write proxy for field `layer_cfg_almost_empty`"] + pub struct LAYER_CFG_ALMOST_EMPTY_W<'a> { + w: &'a mut W, + } + impl<'a> LAYER_CFG_ALMOST_EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `layer_cfg_almost_full`"] + pub type LAYER_CFG_ALMOST_FULL_R = crate::R; + #[doc = "Write proxy for field `layer_cfg_almost_full`"] + pub struct LAYER_CFG_ALMOST_FULL_W<'a> { + w: &'a mut W, + } + impl<'a> LAYER_CFG_ALMOST_FULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + impl R { + #[doc = "Bit 0 - Interrupt raised when calculation is done"] + #[inline(always)] + pub fn calc_done(&self) -> CALC_DONE_R { + CALC_DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Interrupt raised when layer arguments FIFO almost empty"] + #[inline(always)] + pub fn layer_cfg_almost_empty(&self) -> LAYER_CFG_ALMOST_EMPTY_R { + LAYER_CFG_ALMOST_EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Interrupt raised when layer arguments FIFO almost full"] + #[inline(always)] + pub fn layer_cfg_almost_full(&self) -> LAYER_CFG_ALMOST_FULL_R { + LAYER_CFG_ALMOST_FULL_R::new(((self.bits >> 2) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Interrupt raised when calculation is done"] + #[inline(always)] + pub fn calc_done(&mut self) -> CALC_DONE_W { + CALC_DONE_W { w: self } + } + #[doc = "Bit 1 - Interrupt raised when layer arguments FIFO almost empty"] + #[inline(always)] + pub fn layer_cfg_almost_empty(&mut self) -> LAYER_CFG_ALMOST_EMPTY_W { + LAYER_CFG_ALMOST_EMPTY_W { w: self } + } + #[doc = "Bit 2 - Interrupt raised when layer arguments FIFO almost full"] + #[inline(always)] + pub fn layer_cfg_almost_full(&mut self) -> LAYER_CFG_ALMOST_FULL_W { + LAYER_CFG_ALMOST_FULL_W { w: self } + } + } + } + #[doc = "Interrupt raw\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_raw](interrupt_raw) module"] + pub type INTERRUPT_RAW = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_RAW; + #[doc = "`read()` method returns [interrupt_raw::R](interrupt_raw::R) reader structure"] + impl crate::Readable for INTERRUPT_RAW {} + #[doc = "`write(|w| ..)` method takes [interrupt_raw::W](interrupt_raw::W) writer structure"] + impl crate::Writable for INTERRUPT_RAW {} + #[doc = "Interrupt raw"] + pub mod interrupt_raw { + #[doc = "Reader of register interrupt_raw"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_raw"] + pub type W = crate::W; + #[doc = "Register interrupt_raw `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_RAW { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `calc_done`"] + pub type CALC_DONE_R = crate::R; + #[doc = "Write proxy for field `calc_done`"] + pub struct CALC_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> CALC_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `layer_cfg_almost_empty`"] + pub type LAYER_CFG_ALMOST_EMPTY_R = crate::R; + #[doc = "Write proxy for field `layer_cfg_almost_empty`"] + pub struct LAYER_CFG_ALMOST_EMPTY_W<'a> { + w: &'a mut W, + } + impl<'a> LAYER_CFG_ALMOST_EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `layer_cfg_almost_full`"] + pub type LAYER_CFG_ALMOST_FULL_R = crate::R; + #[doc = "Write proxy for field `layer_cfg_almost_full`"] + pub struct LAYER_CFG_ALMOST_FULL_W<'a> { + w: &'a mut W, + } + impl<'a> LAYER_CFG_ALMOST_FULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + impl R { + #[doc = "Bit 0 - Interrupt raised when calculation is done"] + #[inline(always)] + pub fn calc_done(&self) -> CALC_DONE_R { + CALC_DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Interrupt raised when layer arguments FIFO almost empty"] + #[inline(always)] + pub fn layer_cfg_almost_empty(&self) -> LAYER_CFG_ALMOST_EMPTY_R { + LAYER_CFG_ALMOST_EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Interrupt raised when layer arguments FIFO almost full"] + #[inline(always)] + pub fn layer_cfg_almost_full(&self) -> LAYER_CFG_ALMOST_FULL_R { + LAYER_CFG_ALMOST_FULL_R::new(((self.bits >> 2) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Interrupt raised when calculation is done"] + #[inline(always)] + pub fn calc_done(&mut self) -> CALC_DONE_W { + CALC_DONE_W { w: self } + } + #[doc = "Bit 1 - Interrupt raised when layer arguments FIFO almost empty"] + #[inline(always)] + pub fn layer_cfg_almost_empty(&mut self) -> LAYER_CFG_ALMOST_EMPTY_W { + LAYER_CFG_ALMOST_EMPTY_W { w: self } + } + #[doc = "Bit 2 - Interrupt raised when layer arguments FIFO almost full"] + #[inline(always)] + pub fn layer_cfg_almost_full(&mut self) -> LAYER_CFG_ALMOST_FULL_W { + LAYER_CFG_ALMOST_FULL_W { w: self } + } + } + } + #[doc = "Interrupt mask: 0 enables the interrupt, 1 masks the interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_mask](interrupt_mask) module"] + pub type INTERRUPT_MASK = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_MASK; + #[doc = "`read()` method returns [interrupt_mask::R](interrupt_mask::R) reader structure"] + impl crate::Readable for INTERRUPT_MASK {} + #[doc = "`write(|w| ..)` method takes [interrupt_mask::W](interrupt_mask::W) writer structure"] + impl crate::Writable for INTERRUPT_MASK {} + #[doc = "Interrupt mask: 0 enables the interrupt, 1 masks the interrupt"] + pub mod interrupt_mask { + #[doc = "Reader of register interrupt_mask"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_mask"] + pub type W = crate::W; + #[doc = "Register interrupt_mask `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_MASK { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `calc_done`"] + pub type CALC_DONE_R = crate::R; + #[doc = "Write proxy for field `calc_done`"] + pub struct CALC_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> CALC_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `layer_cfg_almost_empty`"] + pub type LAYER_CFG_ALMOST_EMPTY_R = crate::R; + #[doc = "Write proxy for field `layer_cfg_almost_empty`"] + pub struct LAYER_CFG_ALMOST_EMPTY_W<'a> { + w: &'a mut W, + } + impl<'a> LAYER_CFG_ALMOST_EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `layer_cfg_almost_full`"] + pub type LAYER_CFG_ALMOST_FULL_R = crate::R; + #[doc = "Write proxy for field `layer_cfg_almost_full`"] + pub struct LAYER_CFG_ALMOST_FULL_W<'a> { + w: &'a mut W, + } + impl<'a> LAYER_CFG_ALMOST_FULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + impl R { + #[doc = "Bit 0 - Interrupt raised when calculation is done"] + #[inline(always)] + pub fn calc_done(&self) -> CALC_DONE_R { + CALC_DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Interrupt raised when layer arguments FIFO almost empty"] + #[inline(always)] + pub fn layer_cfg_almost_empty(&self) -> LAYER_CFG_ALMOST_EMPTY_R { + LAYER_CFG_ALMOST_EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Interrupt raised when layer arguments FIFO almost full"] + #[inline(always)] + pub fn layer_cfg_almost_full(&self) -> LAYER_CFG_ALMOST_FULL_R { + LAYER_CFG_ALMOST_FULL_R::new(((self.bits >> 2) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Interrupt raised when calculation is done"] + #[inline(always)] + pub fn calc_done(&mut self) -> CALC_DONE_W { + CALC_DONE_W { w: self } + } + #[doc = "Bit 1 - Interrupt raised when layer arguments FIFO almost empty"] + #[inline(always)] + pub fn layer_cfg_almost_empty(&mut self) -> LAYER_CFG_ALMOST_EMPTY_W { + LAYER_CFG_ALMOST_EMPTY_W { w: self } + } + #[doc = "Bit 2 - Interrupt raised when layer arguments FIFO almost full"] + #[inline(always)] + pub fn layer_cfg_almost_full(&mut self) -> LAYER_CFG_ALMOST_FULL_W { + LAYER_CFG_ALMOST_FULL_W { w: self } + } + } + } + #[doc = "Interrupt clear: write 1 to a bit to clear interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_clear](interrupt_clear) module"] + pub type INTERRUPT_CLEAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_CLEAR; + #[doc = "`read()` method returns [interrupt_clear::R](interrupt_clear::R) reader structure"] + impl crate::Readable for INTERRUPT_CLEAR {} + #[doc = "`write(|w| ..)` method takes [interrupt_clear::W](interrupt_clear::W) writer structure"] + impl crate::Writable for INTERRUPT_CLEAR {} + #[doc = "Interrupt clear: write 1 to a bit to clear interrupt"] + pub mod interrupt_clear { + #[doc = "Reader of register interrupt_clear"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_clear"] + pub type W = crate::W; + #[doc = "Register interrupt_clear `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_CLEAR { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `calc_done`"] + pub type CALC_DONE_R = crate::R; + #[doc = "Write proxy for field `calc_done`"] + pub struct CALC_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> CALC_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `layer_cfg_almost_empty`"] + pub type LAYER_CFG_ALMOST_EMPTY_R = crate::R; + #[doc = "Write proxy for field `layer_cfg_almost_empty`"] + pub struct LAYER_CFG_ALMOST_EMPTY_W<'a> { + w: &'a mut W, + } + impl<'a> LAYER_CFG_ALMOST_EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `layer_cfg_almost_full`"] + pub type LAYER_CFG_ALMOST_FULL_R = crate::R; + #[doc = "Write proxy for field `layer_cfg_almost_full`"] + pub struct LAYER_CFG_ALMOST_FULL_W<'a> { + w: &'a mut W, + } + impl<'a> LAYER_CFG_ALMOST_FULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + impl R { + #[doc = "Bit 0 - Interrupt raised when calculation is done"] + #[inline(always)] + pub fn calc_done(&self) -> CALC_DONE_R { + CALC_DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Interrupt raised when layer arguments FIFO almost empty"] + #[inline(always)] + pub fn layer_cfg_almost_empty(&self) -> LAYER_CFG_ALMOST_EMPTY_R { + LAYER_CFG_ALMOST_EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Interrupt raised when layer arguments FIFO almost full"] + #[inline(always)] + pub fn layer_cfg_almost_full(&self) -> LAYER_CFG_ALMOST_FULL_R { + LAYER_CFG_ALMOST_FULL_R::new(((self.bits >> 2) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Interrupt raised when calculation is done"] + #[inline(always)] + pub fn calc_done(&mut self) -> CALC_DONE_W { + CALC_DONE_W { w: self } + } + #[doc = "Bit 1 - Interrupt raised when layer arguments FIFO almost empty"] + #[inline(always)] + pub fn layer_cfg_almost_empty(&mut self) -> LAYER_CFG_ALMOST_EMPTY_W { + LAYER_CFG_ALMOST_EMPTY_W { w: self } + } + #[doc = "Bit 2 - Interrupt raised when layer arguments FIFO almost full"] + #[inline(always)] + pub fn layer_cfg_almost_full(&mut self) -> LAYER_CFG_ALMOST_FULL_W { + LAYER_CFG_ALMOST_FULL_W { w: self } + } + } + } + #[doc = "FIFO threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo_threshold](fifo_threshold) module"] + pub type FIFO_THRESHOLD = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FIFO_THRESHOLD; + #[doc = "`read()` method returns [fifo_threshold::R](fifo_threshold::R) reader structure"] + impl crate::Readable for FIFO_THRESHOLD {} + #[doc = "`write(|w| ..)` method takes [fifo_threshold::W](fifo_threshold::W) writer structure"] + impl crate::Writable for FIFO_THRESHOLD {} + #[doc = "FIFO threshold"] + pub mod fifo_threshold { + #[doc = "Reader of register fifo_threshold"] + pub type R = crate::R; + #[doc = "Writer for register fifo_threshold"] + pub type W = crate::W; + #[doc = "Register fifo_threshold `reset()`'s with value 0"] + impl crate::ResetValue for super::FIFO_THRESHOLD { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `full_threshold`"] + pub type FULL_THRESHOLD_R = crate::R; + #[doc = "Write proxy for field `full_threshold`"] + pub struct FULL_THRESHOLD_W<'a> { + w: &'a mut W, + } + impl<'a> FULL_THRESHOLD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | ((value as u64) & 0x0f); + self.w + } + } + #[doc = "Reader of field `empty_threshold`"] + pub type EMPTY_THRESHOLD_R = crate::R; + #[doc = "Write proxy for field `empty_threshold`"] + pub struct EMPTY_THRESHOLD_W<'a> { + w: &'a mut W, + } + impl<'a> EMPTY_THRESHOLD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u64) & 0x0f) << 4); + self.w + } + } + impl R { + #[doc = "Bits 0:3 - FIFO full threshold"] + #[inline(always)] + pub fn full_threshold(&self) -> FULL_THRESHOLD_R { + FULL_THRESHOLD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - FIFO empty threshold"] + #[inline(always)] + pub fn empty_threshold(&self) -> EMPTY_THRESHOLD_R { + EMPTY_THRESHOLD_R::new(((self.bits >> 4) & 0x0f) as u8) + } + } + impl W { + #[doc = "Bits 0:3 - FIFO full threshold"] + #[inline(always)] + pub fn full_threshold(&mut self) -> FULL_THRESHOLD_W { + FULL_THRESHOLD_W { w: self } + } + #[doc = "Bits 4:7 - FIFO empty threshold"] + #[inline(always)] + pub fn empty_threshold(&mut self) -> EMPTY_THRESHOLD_W { + EMPTY_THRESHOLD_W { w: self } + } + } + } + #[doc = "FIFO data output\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo_data_out](fifo_data_out) module"] + pub type FIFO_DATA_OUT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FIFO_DATA_OUT; + #[doc = "`read()` method returns [fifo_data_out::R](fifo_data_out::R) reader structure"] + impl crate::Readable for FIFO_DATA_OUT {} + #[doc = "`write(|w| ..)` method takes [fifo_data_out::W](fifo_data_out::W) writer structure"] + impl crate::Writable for FIFO_DATA_OUT {} + #[doc = "FIFO data output"] + pub mod fifo_data_out { + #[doc = "Reader of register fifo_data_out"] + pub type R = crate::R; + #[doc = "Writer for register fifo_data_out"] + pub type W = crate::W; + #[doc = "Register fifo_data_out `reset()`'s with value 0"] + impl crate::ResetValue for super::FIFO_DATA_OUT { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "FIFO control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo_ctrl](fifo_ctrl) module"] + pub type FIFO_CTRL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FIFO_CTRL; + #[doc = "`read()` method returns [fifo_ctrl::R](fifo_ctrl::R) reader structure"] + impl crate::Readable for FIFO_CTRL {} + #[doc = "`write(|w| ..)` method takes [fifo_ctrl::W](fifo_ctrl::W) writer structure"] + impl crate::Writable for FIFO_CTRL {} + #[doc = "FIFO control"] + pub mod fifo_ctrl { + #[doc = "Reader of register fifo_ctrl"] + pub type R = crate::R; + #[doc = "Writer for register fifo_ctrl"] + pub type W = crate::W; + #[doc = "Register fifo_ctrl `reset()`'s with value 0"] + impl crate::ResetValue for super::FIFO_CTRL { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `dma_fifo_flush_n`"] + pub type DMA_FIFO_FLUSH_N_R = crate::R; + #[doc = "Write proxy for field `dma_fifo_flush_n`"] + pub struct DMA_FIFO_FLUSH_N_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_FIFO_FLUSH_N_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `gs_fifo_flush_n`"] + pub type GS_FIFO_FLUSH_N_R = crate::R; + #[doc = "Write proxy for field `gs_fifo_flush_n`"] + pub struct GS_FIFO_FLUSH_N_W<'a> { + w: &'a mut W, + } + impl<'a> GS_FIFO_FLUSH_N_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `cfg_fifo_flush_n`"] + pub type CFG_FIFO_FLUSH_N_R = crate::R; + #[doc = "Write proxy for field `cfg_fifo_flush_n`"] + pub struct CFG_FIFO_FLUSH_N_W<'a> { + w: &'a mut W, + } + impl<'a> CFG_FIFO_FLUSH_N_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `cmd_fifo_flush_n`"] + pub type CMD_FIFO_FLUSH_N_R = crate::R; + #[doc = "Write proxy for field `cmd_fifo_flush_n`"] + pub struct CMD_FIFO_FLUSH_N_W<'a> { + w: &'a mut W, + } + impl<'a> CMD_FIFO_FLUSH_N_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `resp_fifo_flush_n`"] + pub type RESP_FIFO_FLUSH_N_R = crate::R; + #[doc = "Write proxy for field `resp_fifo_flush_n`"] + pub struct RESP_FIFO_FLUSH_N_W<'a> { + w: &'a mut W, + } + impl<'a> RESP_FIFO_FLUSH_N_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u64) & 0x01) << 4); + self.w + } + } + impl R { + #[doc = "Bit 0 - Flush DMA FIFO"] + #[inline(always)] + pub fn dma_fifo_flush_n(&self) -> DMA_FIFO_FLUSH_N_R { + DMA_FIFO_FLUSH_N_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Flush GS FIFO"] + #[inline(always)] + pub fn gs_fifo_flush_n(&self) -> GS_FIFO_FLUSH_N_R { + GS_FIFO_FLUSH_N_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Flush configuration FIFO"] + #[inline(always)] + pub fn cfg_fifo_flush_n(&self) -> CFG_FIFO_FLUSH_N_R { + CFG_FIFO_FLUSH_N_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Flush command FIFO"] + #[inline(always)] + pub fn cmd_fifo_flush_n(&self) -> CMD_FIFO_FLUSH_N_R { + CMD_FIFO_FLUSH_N_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Flush response FIFO"] + #[inline(always)] + pub fn resp_fifo_flush_n(&self) -> RESP_FIFO_FLUSH_N_R { + RESP_FIFO_FLUSH_N_R::new(((self.bits >> 4) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Flush DMA FIFO"] + #[inline(always)] + pub fn dma_fifo_flush_n(&mut self) -> DMA_FIFO_FLUSH_N_W { + DMA_FIFO_FLUSH_N_W { w: self } + } + #[doc = "Bit 1 - Flush GS FIFO"] + #[inline(always)] + pub fn gs_fifo_flush_n(&mut self) -> GS_FIFO_FLUSH_N_W { + GS_FIFO_FLUSH_N_W { w: self } + } + #[doc = "Bit 2 - Flush configuration FIFO"] + #[inline(always)] + pub fn cfg_fifo_flush_n(&mut self) -> CFG_FIFO_FLUSH_N_W { + CFG_FIFO_FLUSH_N_W { w: self } + } + #[doc = "Bit 3 - Flush command FIFO"] + #[inline(always)] + pub fn cmd_fifo_flush_n(&mut self) -> CMD_FIFO_FLUSH_N_W { + CMD_FIFO_FLUSH_N_W { w: self } + } + #[doc = "Bit 4 - Flush response FIFO"] + #[inline(always)] + pub fn resp_fifo_flush_n(&mut self) -> RESP_FIFO_FLUSH_N_W { + RESP_FIFO_FLUSH_N_W { w: self } + } + } + } + #[doc = "Eight bit mode\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [eight_bit_mode](eight_bit_mode) module"] + pub type EIGHT_BIT_MODE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _EIGHT_BIT_MODE; + #[doc = "`read()` method returns [eight_bit_mode::R](eight_bit_mode::R) reader structure"] + impl crate::Readable for EIGHT_BIT_MODE {} + #[doc = "`write(|w| ..)` method takes [eight_bit_mode::W](eight_bit_mode::W) writer structure"] + impl crate::Writable for EIGHT_BIT_MODE {} + #[doc = "Eight bit mode"] + pub mod eight_bit_mode { + #[doc = "Reader of register eight_bit_mode"] + pub type R = crate::R; + #[doc = "Writer for register eight_bit_mode"] + pub type W = crate::W; + #[doc = "Register eight_bit_mode `reset()`'s with value 0"] + impl crate::ResetValue for super::EIGHT_BIT_MODE { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `eight_bit_mode`"] + pub type EIGHT_BIT_MODE_R = crate::R; + #[doc = "Write proxy for field `eight_bit_mode`"] + pub struct EIGHT_BIT_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> EIGHT_BIT_MODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Use 8-bit instead of 16-bit precision if set"] + #[inline(always)] + pub fn eight_bit_mode(&self) -> EIGHT_BIT_MODE_R { + EIGHT_BIT_MODE_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Use 8-bit instead of 16-bit precision if set"] + #[inline(always)] + pub fn eight_bit_mode(&mut self) -> EIGHT_BIT_MODE_W { + EIGHT_BIT_MODE_W { w: self } + } + } + } +} +#[doc = "Fast Fourier Transform Accelerator"] +pub struct FFT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for FFT {} +impl FFT { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const fft::RegisterBlock { + 0x4200_0000 as *const _ + } +} +impl Deref for FFT { + type Target = fft::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*FFT::ptr() } + } +} +#[doc = "Fast Fourier Transform Accelerator"] +pub mod fft { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - FFT input data fifo"] + pub input_fifo: INPUT_FIFO, + #[doc = "0x08 - FFT control register"] + pub ctrl: CTRL, + #[doc = "0x10 - FIFO control"] + pub fifo_ctrl: FIFO_CTRL, + #[doc = "0x18 - intr_mask"] + pub interruptmask: INTERRUPTMASK, + #[doc = "0x20 - Interrupt clear"] + pub intr_clear: INTR_CLEAR, + #[doc = "0x28 - FFT status register"] + pub status: STATUS, + #[doc = "0x30 - FFT status raw"] + pub status_raw: STATUS_RAW, + #[doc = "0x38 - FFT output FIFO"] + pub output_fifo: OUTPUT_FIFO, + } + #[doc = "FFT input data fifo\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [input_fifo](input_fifo) module"] + pub type INPUT_FIFO = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INPUT_FIFO; + #[doc = "`read()` method returns [input_fifo::R](input_fifo::R) reader structure"] + impl crate::Readable for INPUT_FIFO {} + #[doc = "`write(|w| ..)` method takes [input_fifo::W](input_fifo::W) writer structure"] + impl crate::Writable for INPUT_FIFO {} + #[doc = "FFT input data fifo"] + pub mod input_fifo { + #[doc = "Reader of register input_fifo"] + pub type R = crate::R; + #[doc = "Writer for register input_fifo"] + pub type W = crate::W; + #[doc = "Register input_fifo `reset()`'s with value 0"] + impl crate::ResetValue for super::INPUT_FIFO { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "FFT control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](ctrl) module"] + pub type CTRL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CTRL; + #[doc = "`read()` method returns [ctrl::R](ctrl::R) reader structure"] + impl crate::Readable for CTRL {} + #[doc = "`write(|w| ..)` method takes [ctrl::W](ctrl::W) writer structure"] + impl crate::Writable for CTRL {} + #[doc = "FFT control register"] + pub mod ctrl { + #[doc = "Reader of register ctrl"] + pub type R = crate::R; + #[doc = "Writer for register ctrl"] + pub type W = crate::W; + #[doc = "Register ctrl `reset()`'s with value 0"] + impl crate::ResetValue for super::CTRL { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "FFT calculation data length\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum POINT_A { + #[doc = "0: 512 point"] + P512 = 0, + #[doc = "1: 256 point"] + P256 = 1, + #[doc = "2: 128 point"] + P128 = 2, + #[doc = "3: 64 point"] + P64 = 3, + } + impl From for u8 { + #[inline(always)] + fn from(variant: POINT_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `point`"] + pub type POINT_R = crate::R; + impl POINT_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(POINT_A::P512), + 1 => Val(POINT_A::P256), + 2 => Val(POINT_A::P128), + 3 => Val(POINT_A::P64), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `P512`"] + #[inline(always)] + pub fn is_p512(&self) -> bool { + *self == POINT_A::P512 + } + #[doc = "Checks if the value of the field is `P256`"] + #[inline(always)] + pub fn is_p256(&self) -> bool { + *self == POINT_A::P256 + } + #[doc = "Checks if the value of the field is `P128`"] + #[inline(always)] + pub fn is_p128(&self) -> bool { + *self == POINT_A::P128 + } + #[doc = "Checks if the value of the field is `P64`"] + #[inline(always)] + pub fn is_p64(&self) -> bool { + *self == POINT_A::P64 + } + } + #[doc = "Write proxy for field `point`"] + pub struct POINT_W<'a> { + w: &'a mut W, + } + impl<'a> POINT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: POINT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "512 point"] + #[inline(always)] + pub fn p512(self) -> &'a mut W { + self.variant(POINT_A::P512) + } + #[doc = "256 point"] + #[inline(always)] + pub fn p256(self) -> &'a mut W { + self.variant(POINT_A::P256) + } + #[doc = "128 point"] + #[inline(always)] + pub fn p128(self) -> &'a mut W { + self.variant(POINT_A::P128) + } + #[doc = "64 point"] + #[inline(always)] + pub fn p64(self) -> &'a mut W { + self.variant(POINT_A::P64) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u64) & 0x07); + self.w + } + } + #[doc = "FFT mode\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum MODE_A { + #[doc = "0: FFT mode"] + FFT = 0, + #[doc = "1: Inverse FFT mode"] + IFFT = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `mode`"] + pub type MODE_R = crate::R; + impl MODE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MODE_A { + match self.bits { + false => MODE_A::FFT, + true => MODE_A::IFFT, + } + } + #[doc = "Checks if the value of the field is `FFT`"] + #[inline(always)] + pub fn is_fft(&self) -> bool { + *self == MODE_A::FFT + } + #[doc = "Checks if the value of the field is `IFFT`"] + #[inline(always)] + pub fn is_ifft(&self) -> bool { + *self == MODE_A::IFFT + } + } + #[doc = "Write proxy for field `mode`"] + pub struct MODE_W<'a> { + w: &'a mut W, + } + impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "FFT mode"] + #[inline(always)] + pub fn fft(self) -> &'a mut W { + self.variant(MODE_A::FFT) + } + #[doc = "Inverse FFT mode"] + #[inline(always)] + pub fn ifft(self) -> &'a mut W { + self.variant(MODE_A::IFFT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `shift`"] + pub type SHIFT_R = crate::R; + #[doc = "Write proxy for field `shift`"] + pub struct SHIFT_W<'a> { + w: &'a mut W, + } + impl<'a> SHIFT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff << 4)) | (((value as u64) & 0x01ff) << 4); + self.w + } + } + #[doc = "Reader of field `enable`"] + pub type ENABLE_R = crate::R; + #[doc = "Write proxy for field `enable`"] + pub struct ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u64) & 0x01) << 13); + self.w + } + } + #[doc = "Reader of field `dma_send`"] + pub type DMA_SEND_R = crate::R; + #[doc = "Write proxy for field `dma_send`"] + pub struct DMA_SEND_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_SEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u64) & 0x01) << 14); + self.w + } + } + #[doc = "Input data arrangement\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum INPUT_MODE_A { + #[doc = "0: RIRI (real imaginary interleaved)"] + RIRI = 0, + #[doc = "1: RRRR (only real part)"] + RRRR = 1, + #[doc = "2: First input the real part and then input the imaginary part"] + RRII = 2, + } + impl From for u8 { + #[inline(always)] + fn from(variant: INPUT_MODE_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `input_mode`"] + pub type INPUT_MODE_R = crate::R; + impl INPUT_MODE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(INPUT_MODE_A::RIRI), + 1 => Val(INPUT_MODE_A::RRRR), + 2 => Val(INPUT_MODE_A::RRII), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `RIRI`"] + #[inline(always)] + pub fn is_riri(&self) -> bool { + *self == INPUT_MODE_A::RIRI + } + #[doc = "Checks if the value of the field is `RRRR`"] + #[inline(always)] + pub fn is_rrrr(&self) -> bool { + *self == INPUT_MODE_A::RRRR + } + #[doc = "Checks if the value of the field is `RRII`"] + #[inline(always)] + pub fn is_rrii(&self) -> bool { + *self == INPUT_MODE_A::RRII + } + } + #[doc = "Write proxy for field `input_mode`"] + pub struct INPUT_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> INPUT_MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INPUT_MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "RIRI (real imaginary interleaved)"] + #[inline(always)] + pub fn riri(self) -> &'a mut W { + self.variant(INPUT_MODE_A::RIRI) + } + #[doc = "RRRR (only real part)"] + #[inline(always)] + pub fn rrrr(self) -> &'a mut W { + self.variant(INPUT_MODE_A::RRRR) + } + #[doc = "First input the real part and then input the imaginary part"] + #[inline(always)] + pub fn rrii(self) -> &'a mut W { + self.variant(INPUT_MODE_A::RRII) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 15)) | (((value as u64) & 0x03) << 15); + self.w + } + } + #[doc = "Effective width of input data\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum DATA_MODE_A { + #[doc = "0: 64 bit effective"] + WIDTH_64 = 0, + #[doc = "1: 128 bit effective"] + WIDTH_128 = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: DATA_MODE_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `data_mode`"] + pub type DATA_MODE_R = crate::R; + impl DATA_MODE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DATA_MODE_A { + match self.bits { + false => DATA_MODE_A::WIDTH_64, + true => DATA_MODE_A::WIDTH_128, + } + } + #[doc = "Checks if the value of the field is `WIDTH_64`"] + #[inline(always)] + pub fn is_width_64(&self) -> bool { + *self == DATA_MODE_A::WIDTH_64 + } + #[doc = "Checks if the value of the field is `WIDTH_128`"] + #[inline(always)] + pub fn is_width_128(&self) -> bool { + *self == DATA_MODE_A::WIDTH_128 + } + } + #[doc = "Write proxy for field `data_mode`"] + pub struct DATA_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> DATA_MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DATA_MODE_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "64 bit effective"] + #[inline(always)] + pub fn width_64(self) -> &'a mut W { + self.variant(DATA_MODE_A::WIDTH_64) + } + #[doc = "128 bit effective"] + #[inline(always)] + pub fn width_128(self) -> &'a mut W { + self.variant(DATA_MODE_A::WIDTH_128) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u64) & 0x01) << 17); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - FFT calculation data length"] + #[inline(always)] + pub fn point(&self) -> POINT_R { + POINT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - FFT mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:12 - Corresponding to the nine layer butterfly shift operation, 0x0: does not shift; 0x1: shift 1st layer. ..."] + #[inline(always)] + pub fn shift(&self) -> SHIFT_R { + SHIFT_R::new(((self.bits >> 4) & 0x01ff) as u16) + } + #[doc = "Bit 13 - FFT enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - FFT DMA enable"] + #[inline(always)] + pub fn dma_send(&self) -> DMA_SEND_R { + DMA_SEND_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bits 15:16 - Input data arrangement"] + #[inline(always)] + pub fn input_mode(&self) -> INPUT_MODE_R { + INPUT_MODE_R::new(((self.bits >> 15) & 0x03) as u8) + } + #[doc = "Bit 17 - Effective width of input data"] + #[inline(always)] + pub fn data_mode(&self) -> DATA_MODE_R { + DATA_MODE_R::new(((self.bits >> 17) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:2 - FFT calculation data length"] + #[inline(always)] + pub fn point(&mut self) -> POINT_W { + POINT_W { w: self } + } + #[doc = "Bit 3 - FFT mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:12 - Corresponding to the nine layer butterfly shift operation, 0x0: does not shift; 0x1: shift 1st layer. ..."] + #[inline(always)] + pub fn shift(&mut self) -> SHIFT_W { + SHIFT_W { w: self } + } + #[doc = "Bit 13 - FFT enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 14 - FFT DMA enable"] + #[inline(always)] + pub fn dma_send(&mut self) -> DMA_SEND_W { + DMA_SEND_W { w: self } + } + #[doc = "Bits 15:16 - Input data arrangement"] + #[inline(always)] + pub fn input_mode(&mut self) -> INPUT_MODE_W { + INPUT_MODE_W { w: self } + } + #[doc = "Bit 17 - Effective width of input data"] + #[inline(always)] + pub fn data_mode(&mut self) -> DATA_MODE_W { + DATA_MODE_W { w: self } + } + } + } + #[doc = "FIFO control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo_ctrl](fifo_ctrl) module"] + pub type FIFO_CTRL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FIFO_CTRL; + #[doc = "`read()` method returns [fifo_ctrl::R](fifo_ctrl::R) reader structure"] + impl crate::Readable for FIFO_CTRL {} + #[doc = "`write(|w| ..)` method takes [fifo_ctrl::W](fifo_ctrl::W) writer structure"] + impl crate::Writable for FIFO_CTRL {} + #[doc = "FIFO control"] + pub mod fifo_ctrl { + #[doc = "Reader of register fifo_ctrl"] + pub type R = crate::R; + #[doc = "Writer for register fifo_ctrl"] + pub type W = crate::W; + #[doc = "Register fifo_ctrl `reset()`'s with value 0"] + impl crate::ResetValue for super::FIFO_CTRL { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `resp_fifo_flush`"] + pub type RESP_FIFO_FLUSH_R = crate::R; + #[doc = "Write proxy for field `resp_fifo_flush`"] + pub struct RESP_FIFO_FLUSH_W<'a> { + w: &'a mut W, + } + impl<'a> RESP_FIFO_FLUSH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `cmd_fifo_flush`"] + pub type CMD_FIFO_FLUSH_R = crate::R; + #[doc = "Write proxy for field `cmd_fifo_flush`"] + pub struct CMD_FIFO_FLUSH_W<'a> { + w: &'a mut W, + } + impl<'a> CMD_FIFO_FLUSH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `gs_fifo_flush`"] + pub type GS_FIFO_FLUSH_R = crate::R; + #[doc = "Write proxy for field `gs_fifo_flush`"] + pub struct GS_FIFO_FLUSH_W<'a> { + w: &'a mut W, + } + impl<'a> GS_FIFO_FLUSH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + impl R { + #[doc = "Bit 0 - Response memory initialization flag"] + #[inline(always)] + pub fn resp_fifo_flush(&self) -> RESP_FIFO_FLUSH_R { + RESP_FIFO_FLUSH_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Command memory initialization flag"] + #[inline(always)] + pub fn cmd_fifo_flush(&self) -> CMD_FIFO_FLUSH_R { + CMD_FIFO_FLUSH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Output interface memory initialization flag"] + #[inline(always)] + pub fn gs_fifo_flush(&self) -> GS_FIFO_FLUSH_R { + GS_FIFO_FLUSH_R::new(((self.bits >> 2) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Response memory initialization flag"] + #[inline(always)] + pub fn resp_fifo_flush(&mut self) -> RESP_FIFO_FLUSH_W { + RESP_FIFO_FLUSH_W { w: self } + } + #[doc = "Bit 1 - Command memory initialization flag"] + #[inline(always)] + pub fn cmd_fifo_flush(&mut self) -> CMD_FIFO_FLUSH_W { + CMD_FIFO_FLUSH_W { w: self } + } + #[doc = "Bit 2 - Output interface memory initialization flag"] + #[inline(always)] + pub fn gs_fifo_flush(&mut self) -> GS_FIFO_FLUSH_W { + GS_FIFO_FLUSH_W { w: self } + } + } + } + #[doc = "intr_mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interruptmask](interruptmask) module"] + pub type INTERRUPTMASK = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPTMASK; + #[doc = "`read()` method returns [interruptmask::R](interruptmask::R) reader structure"] + impl crate::Readable for INTERRUPTMASK {} + #[doc = "`write(|w| ..)` method takes [interruptmask::W](interruptmask::W) writer structure"] + impl crate::Writable for INTERRUPTMASK {} + #[doc = "intr_mask"] + pub mod interruptmask { + #[doc = "Reader of register interrupt mask"] + pub type R = crate::R; + #[doc = "Writer for register interrupt mask"] + pub type W = crate::W; + #[doc = "Register interrupt mask `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPTMASK { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `fft_done`"] + pub type FFT_DONE_R = crate::R; + #[doc = "Write proxy for field `fft_done`"] + pub struct FFT_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> FFT_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - FFT done"] + #[inline(always)] + pub fn fft_done(&self) -> FFT_DONE_R { + FFT_DONE_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - FFT done"] + #[inline(always)] + pub fn fft_done(&mut self) -> FFT_DONE_W { + FFT_DONE_W { w: self } + } + } + } + #[doc = "Interrupt clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intr_clear](intr_clear) module"] + pub type INTR_CLEAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTR_CLEAR; + #[doc = "`read()` method returns [intr_clear::R](intr_clear::R) reader structure"] + impl crate::Readable for INTR_CLEAR {} + #[doc = "`write(|w| ..)` method takes [intr_clear::W](intr_clear::W) writer structure"] + impl crate::Writable for INTR_CLEAR {} + #[doc = "Interrupt clear"] + pub mod intr_clear { + #[doc = "Reader of register intr_clear"] + pub type R = crate::R; + #[doc = "Writer for register intr_clear"] + pub type W = crate::W; + #[doc = "Register intr_clear `reset()`'s with value 0"] + impl crate::ResetValue for super::INTR_CLEAR { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `fft_done`"] + pub type FFT_DONE_R = crate::R; + #[doc = "Write proxy for field `fft_done`"] + pub struct FFT_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> FFT_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - FFT done"] + #[inline(always)] + pub fn fft_done(&self) -> FFT_DONE_R { + FFT_DONE_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - FFT done"] + #[inline(always)] + pub fn fft_done(&mut self) -> FFT_DONE_W { + FFT_DONE_W { w: self } + } + } + } + #[doc = "FFT status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](status) module"] + pub type STATUS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _STATUS; + #[doc = "`read()` method returns [status::R](status::R) reader structure"] + impl crate::Readable for STATUS {} + #[doc = "`write(|w| ..)` method takes [status::W](status::W) writer structure"] + impl crate::Writable for STATUS {} + #[doc = "FFT status register"] + pub mod status { + #[doc = "Reader of register status"] + pub type R = crate::R; + #[doc = "Writer for register status"] + pub type W = crate::W; + #[doc = "Register status `reset()`'s with value 0"] + impl crate::ResetValue for super::STATUS { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `fft_done`"] + pub type FFT_DONE_R = crate::R; + #[doc = "Write proxy for field `fft_done`"] + pub struct FFT_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> FFT_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - FFT done"] + #[inline(always)] + pub fn fft_done(&self) -> FFT_DONE_R { + FFT_DONE_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - FFT done"] + #[inline(always)] + pub fn fft_done(&mut self) -> FFT_DONE_W { + FFT_DONE_W { w: self } + } + } + } + #[doc = "FFT status raw\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status_raw](status_raw) module"] + pub type STATUS_RAW = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _STATUS_RAW; + #[doc = "`read()` method returns [status_raw::R](status_raw::R) reader structure"] + impl crate::Readable for STATUS_RAW {} + #[doc = "`write(|w| ..)` method takes [status_raw::W](status_raw::W) writer structure"] + impl crate::Writable for STATUS_RAW {} + #[doc = "FFT status raw"] + pub mod status_raw { + #[doc = "Reader of register status_raw"] + pub type R = crate::R; + #[doc = "Writer for register status_raw"] + pub type W = crate::W; + #[doc = "Register status_raw `reset()`'s with value 0"] + impl crate::ResetValue for super::STATUS_RAW { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `fft_done`"] + pub type FFT_DONE_R = crate::R; + #[doc = "Write proxy for field `fft_done`"] + pub struct FFT_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> FFT_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `fft_work`"] + pub type FFT_WORK_R = crate::R; + #[doc = "Write proxy for field `fft_work`"] + pub struct FFT_WORK_W<'a> { + w: &'a mut W, + } + impl<'a> FFT_WORK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + impl R { + #[doc = "Bit 0 - FFT done"] + #[inline(always)] + pub fn fft_done(&self) -> FFT_DONE_R { + FFT_DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - FFT work"] + #[inline(always)] + pub fn fft_work(&self) -> FFT_WORK_R { + FFT_WORK_R::new(((self.bits >> 1) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - FFT done"] + #[inline(always)] + pub fn fft_done(&mut self) -> FFT_DONE_W { + FFT_DONE_W { w: self } + } + #[doc = "Bit 1 - FFT work"] + #[inline(always)] + pub fn fft_work(&mut self) -> FFT_WORK_W { + FFT_WORK_W { w: self } + } + } + } + #[doc = "FFT output FIFO\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [output_fifo](output_fifo) module"] + pub type OUTPUT_FIFO = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _OUTPUT_FIFO; + #[doc = "`read()` method returns [output_fifo::R](output_fifo::R) reader structure"] + impl crate::Readable for OUTPUT_FIFO {} + #[doc = "`write(|w| ..)` method takes [output_fifo::W](output_fifo::W) writer structure"] + impl crate::Writable for OUTPUT_FIFO {} + #[doc = "FFT output FIFO"] + pub mod output_fifo { + #[doc = "Reader of register output_fifo"] + pub type R = crate::R; + #[doc = "Writer for register output_fifo"] + pub type W = crate::W; + #[doc = "Register output_fifo `reset()`'s with value 0"] + impl crate::ResetValue for super::OUTPUT_FIFO { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Direct Memory Access Controller"] +pub struct DMAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DMAC {} +impl DMAC { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dmac::RegisterBlock { + 0x5000_0000 as *const _ + } +} +impl Deref for DMAC { + type Target = dmac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*DMAC::ptr() } + } +} +#[doc = "Direct Memory Access Controller"] +pub mod dmac { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - ID Register"] + pub id: ID, + #[doc = "0x08 - COMPVER Register"] + pub compver: COMPVER, + #[doc = "0x10 - Configure Register"] + pub cfg: CFG, + #[doc = "0x18 - Channel Enable Register"] + pub chen: CHEN, + _reserved4: [u8; 16usize], + #[doc = "0x30 - Interrupt Status Register"] + pub intstatus: INTSTATUS, + #[doc = "0x38 - Common Interrupt Clear Register"] + pub com_intclear: COM_INTCLEAR, + #[doc = "0x40 - Common Interrupt Status Enable Register"] + pub com_intstatus_en: COM_INTSTATUS_EN, + #[doc = "0x48 - Common Interrupt Signal Enable Register"] + pub com_intsignal_en: COM_INTSIGNAL_EN, + #[doc = "0x50 - Common Interrupt Status"] + pub com_intstatus: COM_INTSTATUS, + #[doc = "0x58 - Reset register"] + pub reset: RESET, + _reserved10: [u8; 160usize], + #[doc = "0x100 - Channel configuration"] + pub channel: [CHANNEL; 6], + } + #[doc = r"Register block"] + #[repr(C)] + pub struct CHANNEL { + #[doc = "0x00 - SAR Address Register"] + pub sar: self::channel::SAR, + #[doc = "0x08 - DAR Address Register"] + pub dar: self::channel::DAR, + #[doc = "0x10 - Block Transfer Size Register"] + pub block_ts: self::channel::BLOCK_TS, + #[doc = "0x18 - Control Register"] + pub ctl: self::channel::CTL, + #[doc = "0x20 - Configure Register"] + pub cfg: self::channel::CFG, + #[doc = "0x28 - Linked List Pointer register"] + pub llp: self::channel::LLP, + #[doc = "0x30 - Channel Status Register"] + pub status: self::channel::STATUS, + #[doc = "0x38 - Channel Software handshake Source Register"] + pub swhssrc: self::channel::SWHSSRC, + #[doc = "0x40 - Channel Software handshake Destination Register"] + pub swhsdst: self::channel::SWHSDST, + #[doc = "0x48 - Channel Block Transfer Resume Request Register"] + pub blk_tfr: self::channel::BLK_TFR, + #[doc = "0x50 - Channel AXI ID Register"] + pub axi_id: self::channel::AXI_ID, + #[doc = "0x58 - AXI QOS Register"] + pub axi_qos: self::channel::AXI_QOS, + _reserved12: [u8; 32usize], + #[doc = "0x80 - Interrupt Status Enable Register"] + pub intstatus_en: self::channel::INTSTATUS_EN, + #[doc = "0x88 - Channel Interrupt Status Register"] + pub intstatus: self::channel::INTSTATUS, + #[doc = "0x90 - Interrupt Signal Enable Register"] + pub intsignal_en: self::channel::INTSIGNAL_EN, + #[doc = "0x98 - Interrupt Clear Register"] + pub intclear: self::channel::INTCLEAR, + _reserved16: [u8; 88usize], + #[doc = "0xf8 - Padding to make structure size 256 bytes so that channels\\[\\] +is an array"] + pub _reserved: self::channel::_RESERVED, + } + #[doc = r"Register block"] + #[doc = "Channel configuration"] + pub mod channel { + #[doc = "SAR Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sar](sar) module"] + pub type SAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SAR; + #[doc = "`read()` method returns [sar::R](sar::R) reader structure"] + impl crate::Readable for SAR {} + #[doc = "`write(|w| ..)` method takes [sar::W](sar::W) writer structure"] + impl crate::Writable for SAR {} + #[doc = "SAR Address Register"] + pub mod sar { + #[doc = "Reader of register sar"] + pub type R = crate::R; + #[doc = "Writer for register sar"] + pub type W = crate::W; + #[doc = "Register sar `reset()`'s with value 0"] + impl crate::ResetValue for super::SAR { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DAR Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dar](dar) module"] + pub type DAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DAR; + #[doc = "`read()` method returns [dar::R](dar::R) reader structure"] + impl crate::Readable for DAR {} + #[doc = "`write(|w| ..)` method takes [dar::W](dar::W) writer structure"] + impl crate::Writable for DAR {} + #[doc = "DAR Address Register"] + pub mod dar { + #[doc = "Reader of register dar"] + pub type R = crate::R; + #[doc = "Writer for register dar"] + pub type W = crate::W; + #[doc = "Register dar `reset()`'s with value 0"] + impl crate::ResetValue for super::DAR { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Block Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [block_ts](block_ts) module"] + pub type BLOCK_TS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _BLOCK_TS; + #[doc = "`read()` method returns [block_ts::R](block_ts::R) reader structure"] + impl crate::Readable for BLOCK_TS {} + #[doc = "`write(|w| ..)` method takes [block_ts::W](block_ts::W) writer structure"] + impl crate::Writable for BLOCK_TS {} + #[doc = "Block Transfer Size Register"] + pub mod block_ts { + #[doc = "Reader of register block_ts"] + pub type R = crate::R; + #[doc = "Writer for register block_ts"] + pub type W = crate::W; + #[doc = "Register block_ts `reset()`'s with value 0"] + impl crate::ResetValue for super::BLOCK_TS { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `block_ts`"] + pub type BLOCK_TS_R = crate::R; + #[doc = "Write proxy for field `block_ts`"] + pub struct BLOCK_TS_W<'a> { + w: &'a mut W, + } + impl<'a> BLOCK_TS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x003f_ffff) | ((value as u64) & 0x003f_ffff); + self.w + } + } + impl R { + #[doc = "Bits 0:21 - Block transfer size"] + #[inline(always)] + pub fn block_ts(&self) -> BLOCK_TS_R { + BLOCK_TS_R::new((self.bits & 0x003f_ffff) as u32) + } + } + impl W { + #[doc = "Bits 0:21 - Block transfer size"] + #[inline(always)] + pub fn block_ts(&mut self) -> BLOCK_TS_W { + BLOCK_TS_W { w: self } + } + } + } + #[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl](ctl) module"] + pub type CTL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CTL; + #[doc = "`read()` method returns [ctl::R](ctl::R) reader structure"] + impl crate::Readable for CTL {} + #[doc = "`write(|w| ..)` method takes [ctl::W](ctl::W) writer structure"] + impl crate::Writable for CTL {} + #[doc = "Control Register"] + pub mod ctl { + #[doc = "Reader of register ctl"] + pub type R = crate::R; + #[doc = "Writer for register ctl"] + pub type W = crate::W; + #[doc = "Register ctl `reset()`'s with value 0"] + impl crate::ResetValue for super::CTL { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Source master select\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum SMS_A { + #[doc = "0: AXI master 1"] + AXI_MASTER_1 = 0, + #[doc = "1: AXI master 2"] + AXI_MASTER_2 = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: SMS_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `sms`"] + pub type SMS_R = crate::R; + impl SMS_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SMS_A { + match self.bits { + false => SMS_A::AXI_MASTER_1, + true => SMS_A::AXI_MASTER_2, + } + } + #[doc = "Checks if the value of the field is `AXI_MASTER_1`"] + #[inline(always)] + pub fn is_axi_master_1(&self) -> bool { + *self == SMS_A::AXI_MASTER_1 + } + #[doc = "Checks if the value of the field is `AXI_MASTER_2`"] + #[inline(always)] + pub fn is_axi_master_2(&self) -> bool { + *self == SMS_A::AXI_MASTER_2 + } + } + #[doc = "Write proxy for field `sms`"] + pub struct SMS_W<'a> { + w: &'a mut W, + } + impl<'a> SMS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SMS_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "AXI master 1"] + #[inline(always)] + pub fn axi_master_1(self) -> &'a mut W { + self.variant(SMS_A::AXI_MASTER_1) + } + #[doc = "AXI master 2"] + #[inline(always)] + pub fn axi_master_2(self) -> &'a mut W { + self.variant(SMS_A::AXI_MASTER_2) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Destination master select"] + pub type DMS_A = SMS_A; + #[doc = "Reader of field `dms`"] + pub type DMS_R = crate::R; + #[doc = "Write proxy for field `dms`"] + pub struct DMS_W<'a> { + w: &'a mut W, + } + impl<'a> DMS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DMS_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "AXI master 1"] + #[inline(always)] + pub fn axi_master_1(self) -> &'a mut W { + self.variant(DMS_A::AXI_MASTER_1) + } + #[doc = "AXI master 2"] + #[inline(always)] + pub fn axi_master_2(self) -> &'a mut W { + self.variant(DMS_A::AXI_MASTER_2) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + #[doc = "Source address increment\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum SINC_A { + #[doc = "0: Increment address"] + INCREMENT = 0, + #[doc = "1: Don't increment address"] + NOCHANGE = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: SINC_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `sinc`"] + pub type SINC_R = crate::R; + impl SINC_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SINC_A { + match self.bits { + false => SINC_A::INCREMENT, + true => SINC_A::NOCHANGE, + } + } + #[doc = "Checks if the value of the field is `INCREMENT`"] + #[inline(always)] + pub fn is_increment(&self) -> bool { + *self == SINC_A::INCREMENT + } + #[doc = "Checks if the value of the field is `NOCHANGE`"] + #[inline(always)] + pub fn is_nochange(&self) -> bool { + *self == SINC_A::NOCHANGE + } + } + #[doc = "Write proxy for field `sinc`"] + pub struct SINC_W<'a> { + w: &'a mut W, + } + impl<'a> SINC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SINC_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Increment address"] + #[inline(always)] + pub fn increment(self) -> &'a mut W { + self.variant(SINC_A::INCREMENT) + } + #[doc = "Don't increment address"] + #[inline(always)] + pub fn nochange(self) -> &'a mut W { + self.variant(SINC_A::NOCHANGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u64) & 0x01) << 4); + self.w + } + } + #[doc = "Destination address increment"] + pub type DINC_A = SINC_A; + #[doc = "Reader of field `dinc`"] + pub type DINC_R = crate::R; + #[doc = "Write proxy for field `dinc`"] + pub struct DINC_W<'a> { + w: &'a mut W, + } + impl<'a> DINC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DINC_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Increment address"] + #[inline(always)] + pub fn increment(self) -> &'a mut W { + self.variant(DINC_A::INCREMENT) + } + #[doc = "Don't increment address"] + #[inline(always)] + pub fn nochange(self) -> &'a mut W { + self.variant(DINC_A::NOCHANGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u64) & 0x01) << 6); + self.w + } + } + #[doc = "Source transfer width\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum SRC_TR_WIDTH_A { + #[doc = "0: 8 bits"] + WIDTH_8 = 0, + #[doc = "1: 16 bits"] + WIDTH_16 = 1, + #[doc = "2: 32 bits"] + WIDTH_32 = 2, + #[doc = "3: 64 bits"] + WIDTH_64 = 3, + #[doc = "4: 128 bits"] + WIDTH_128 = 4, + #[doc = "5: 256 bits"] + WIDTH_256 = 5, + #[doc = "6: 512 bits"] + WIDTH_512 = 6, + } + impl From for u8 { + #[inline(always)] + fn from(variant: SRC_TR_WIDTH_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `src_tr_width`"] + pub type SRC_TR_WIDTH_R = crate::R; + impl SRC_TR_WIDTH_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(SRC_TR_WIDTH_A::WIDTH_8), + 1 => Val(SRC_TR_WIDTH_A::WIDTH_16), + 2 => Val(SRC_TR_WIDTH_A::WIDTH_32), + 3 => Val(SRC_TR_WIDTH_A::WIDTH_64), + 4 => Val(SRC_TR_WIDTH_A::WIDTH_128), + 5 => Val(SRC_TR_WIDTH_A::WIDTH_256), + 6 => Val(SRC_TR_WIDTH_A::WIDTH_512), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `WIDTH_8`"] + #[inline(always)] + pub fn is_width_8(&self) -> bool { + *self == SRC_TR_WIDTH_A::WIDTH_8 + } + #[doc = "Checks if the value of the field is `WIDTH_16`"] + #[inline(always)] + pub fn is_width_16(&self) -> bool { + *self == SRC_TR_WIDTH_A::WIDTH_16 + } + #[doc = "Checks if the value of the field is `WIDTH_32`"] + #[inline(always)] + pub fn is_width_32(&self) -> bool { + *self == SRC_TR_WIDTH_A::WIDTH_32 + } + #[doc = "Checks if the value of the field is `WIDTH_64`"] + #[inline(always)] + pub fn is_width_64(&self) -> bool { + *self == SRC_TR_WIDTH_A::WIDTH_64 + } + #[doc = "Checks if the value of the field is `WIDTH_128`"] + #[inline(always)] + pub fn is_width_128(&self) -> bool { + *self == SRC_TR_WIDTH_A::WIDTH_128 + } + #[doc = "Checks if the value of the field is `WIDTH_256`"] + #[inline(always)] + pub fn is_width_256(&self) -> bool { + *self == SRC_TR_WIDTH_A::WIDTH_256 + } + #[doc = "Checks if the value of the field is `WIDTH_512`"] + #[inline(always)] + pub fn is_width_512(&self) -> bool { + *self == SRC_TR_WIDTH_A::WIDTH_512 + } + } + #[doc = "Write proxy for field `src_tr_width`"] + pub struct SRC_TR_WIDTH_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_TR_WIDTH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_TR_WIDTH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn width_8(self) -> &'a mut W { + self.variant(SRC_TR_WIDTH_A::WIDTH_8) + } + #[doc = "16 bits"] + #[inline(always)] + pub fn width_16(self) -> &'a mut W { + self.variant(SRC_TR_WIDTH_A::WIDTH_16) + } + #[doc = "32 bits"] + #[inline(always)] + pub fn width_32(self) -> &'a mut W { + self.variant(SRC_TR_WIDTH_A::WIDTH_32) + } + #[doc = "64 bits"] + #[inline(always)] + pub fn width_64(self) -> &'a mut W { + self.variant(SRC_TR_WIDTH_A::WIDTH_64) + } + #[doc = "128 bits"] + #[inline(always)] + pub fn width_128(self) -> &'a mut W { + self.variant(SRC_TR_WIDTH_A::WIDTH_128) + } + #[doc = "256 bits"] + #[inline(always)] + pub fn width_256(self) -> &'a mut W { + self.variant(SRC_TR_WIDTH_A::WIDTH_256) + } + #[doc = "512 bits"] + #[inline(always)] + pub fn width_512(self) -> &'a mut W { + self.variant(SRC_TR_WIDTH_A::WIDTH_512) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | (((value as u64) & 0x07) << 8); + self.w + } + } + #[doc = "Destination transfer width"] + pub type DST_TR_WIDTH_A = SRC_TR_WIDTH_A; + #[doc = "Reader of field `dst_tr_width`"] + pub type DST_TR_WIDTH_R = crate::R; + #[doc = "Write proxy for field `dst_tr_width`"] + pub struct DST_TR_WIDTH_W<'a> { + w: &'a mut W, + } + impl<'a> DST_TR_WIDTH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DST_TR_WIDTH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn width_8(self) -> &'a mut W { + self.variant(DST_TR_WIDTH_A::WIDTH_8) + } + #[doc = "16 bits"] + #[inline(always)] + pub fn width_16(self) -> &'a mut W { + self.variant(DST_TR_WIDTH_A::WIDTH_16) + } + #[doc = "32 bits"] + #[inline(always)] + pub fn width_32(self) -> &'a mut W { + self.variant(DST_TR_WIDTH_A::WIDTH_32) + } + #[doc = "64 bits"] + #[inline(always)] + pub fn width_64(self) -> &'a mut W { + self.variant(DST_TR_WIDTH_A::WIDTH_64) + } + #[doc = "128 bits"] + #[inline(always)] + pub fn width_128(self) -> &'a mut W { + self.variant(DST_TR_WIDTH_A::WIDTH_128) + } + #[doc = "256 bits"] + #[inline(always)] + pub fn width_256(self) -> &'a mut W { + self.variant(DST_TR_WIDTH_A::WIDTH_256) + } + #[doc = "512 bits"] + #[inline(always)] + pub fn width_512(self) -> &'a mut W { + self.variant(DST_TR_WIDTH_A::WIDTH_512) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 11)) | (((value as u64) & 0x07) << 11); + self.w + } + } + #[doc = "Source burst transaction length\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum SRC_MSIZE_A { + #[doc = "0: 1 data item"] + LENGTH_1 = 0, + #[doc = "1: 4 data items"] + LENGTH_4 = 1, + #[doc = "2: 8 data items"] + LENGTH_8 = 2, + #[doc = "3: 16 data items"] + LENGTH_16 = 3, + #[doc = "4: 32 data items"] + LENGTH_32 = 4, + #[doc = "5: 64 data items"] + LENGTH_64 = 5, + #[doc = "6: 128 data items"] + LENGTH_128 = 6, + #[doc = "7: 256 data items"] + LENGTH_256 = 7, + #[doc = "8: 512 data items"] + LENGTH_512 = 8, + #[doc = "9: 1024 data items"] + LENGTH_1024 = 9, + } + impl From for u8 { + #[inline(always)] + fn from(variant: SRC_MSIZE_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `src_msize`"] + pub type SRC_MSIZE_R = crate::R; + impl SRC_MSIZE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(SRC_MSIZE_A::LENGTH_1), + 1 => Val(SRC_MSIZE_A::LENGTH_4), + 2 => Val(SRC_MSIZE_A::LENGTH_8), + 3 => Val(SRC_MSIZE_A::LENGTH_16), + 4 => Val(SRC_MSIZE_A::LENGTH_32), + 5 => Val(SRC_MSIZE_A::LENGTH_64), + 6 => Val(SRC_MSIZE_A::LENGTH_128), + 7 => Val(SRC_MSIZE_A::LENGTH_256), + 8 => Val(SRC_MSIZE_A::LENGTH_512), + 9 => Val(SRC_MSIZE_A::LENGTH_1024), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `LENGTH_1`"] + #[inline(always)] + pub fn is_length_1(&self) -> bool { + *self == SRC_MSIZE_A::LENGTH_1 + } + #[doc = "Checks if the value of the field is `LENGTH_4`"] + #[inline(always)] + pub fn is_length_4(&self) -> bool { + *self == SRC_MSIZE_A::LENGTH_4 + } + #[doc = "Checks if the value of the field is `LENGTH_8`"] + #[inline(always)] + pub fn is_length_8(&self) -> bool { + *self == SRC_MSIZE_A::LENGTH_8 + } + #[doc = "Checks if the value of the field is `LENGTH_16`"] + #[inline(always)] + pub fn is_length_16(&self) -> bool { + *self == SRC_MSIZE_A::LENGTH_16 + } + #[doc = "Checks if the value of the field is `LENGTH_32`"] + #[inline(always)] + pub fn is_length_32(&self) -> bool { + *self == SRC_MSIZE_A::LENGTH_32 + } + #[doc = "Checks if the value of the field is `LENGTH_64`"] + #[inline(always)] + pub fn is_length_64(&self) -> bool { + *self == SRC_MSIZE_A::LENGTH_64 + } + #[doc = "Checks if the value of the field is `LENGTH_128`"] + #[inline(always)] + pub fn is_length_128(&self) -> bool { + *self == SRC_MSIZE_A::LENGTH_128 + } + #[doc = "Checks if the value of the field is `LENGTH_256`"] + #[inline(always)] + pub fn is_length_256(&self) -> bool { + *self == SRC_MSIZE_A::LENGTH_256 + } + #[doc = "Checks if the value of the field is `LENGTH_512`"] + #[inline(always)] + pub fn is_length_512(&self) -> bool { + *self == SRC_MSIZE_A::LENGTH_512 + } + #[doc = "Checks if the value of the field is `LENGTH_1024`"] + #[inline(always)] + pub fn is_length_1024(&self) -> bool { + *self == SRC_MSIZE_A::LENGTH_1024 + } + } + #[doc = "Write proxy for field `src_msize`"] + pub struct SRC_MSIZE_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_MSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_MSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1 data item"] + #[inline(always)] + pub fn length_1(self) -> &'a mut W { + self.variant(SRC_MSIZE_A::LENGTH_1) + } + #[doc = "4 data items"] + #[inline(always)] + pub fn length_4(self) -> &'a mut W { + self.variant(SRC_MSIZE_A::LENGTH_4) + } + #[doc = "8 data items"] + #[inline(always)] + pub fn length_8(self) -> &'a mut W { + self.variant(SRC_MSIZE_A::LENGTH_8) + } + #[doc = "16 data items"] + #[inline(always)] + pub fn length_16(self) -> &'a mut W { + self.variant(SRC_MSIZE_A::LENGTH_16) + } + #[doc = "32 data items"] + #[inline(always)] + pub fn length_32(self) -> &'a mut W { + self.variant(SRC_MSIZE_A::LENGTH_32) + } + #[doc = "64 data items"] + #[inline(always)] + pub fn length_64(self) -> &'a mut W { + self.variant(SRC_MSIZE_A::LENGTH_64) + } + #[doc = "128 data items"] + #[inline(always)] + pub fn length_128(self) -> &'a mut W { + self.variant(SRC_MSIZE_A::LENGTH_128) + } + #[doc = "256 data items"] + #[inline(always)] + pub fn length_256(self) -> &'a mut W { + self.variant(SRC_MSIZE_A::LENGTH_256) + } + #[doc = "512 data items"] + #[inline(always)] + pub fn length_512(self) -> &'a mut W { + self.variant(SRC_MSIZE_A::LENGTH_512) + } + #[doc = "1024 data items"] + #[inline(always)] + pub fn length_1024(self) -> &'a mut W { + self.variant(SRC_MSIZE_A::LENGTH_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 14)) | (((value as u64) & 0x0f) << 14); + self.w + } + } + #[doc = "Destination burst transaction length"] + pub type DST_MSIZE_A = SRC_MSIZE_A; + #[doc = "Reader of field `dst_msize`"] + pub type DST_MSIZE_R = crate::R; + #[doc = "Write proxy for field `dst_msize`"] + pub struct DST_MSIZE_W<'a> { + w: &'a mut W, + } + impl<'a> DST_MSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DST_MSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1 data item"] + #[inline(always)] + pub fn length_1(self) -> &'a mut W { + self.variant(DST_MSIZE_A::LENGTH_1) + } + #[doc = "4 data items"] + #[inline(always)] + pub fn length_4(self) -> &'a mut W { + self.variant(DST_MSIZE_A::LENGTH_4) + } + #[doc = "8 data items"] + #[inline(always)] + pub fn length_8(self) -> &'a mut W { + self.variant(DST_MSIZE_A::LENGTH_8) + } + #[doc = "16 data items"] + #[inline(always)] + pub fn length_16(self) -> &'a mut W { + self.variant(DST_MSIZE_A::LENGTH_16) + } + #[doc = "32 data items"] + #[inline(always)] + pub fn length_32(self) -> &'a mut W { + self.variant(DST_MSIZE_A::LENGTH_32) + } + #[doc = "64 data items"] + #[inline(always)] + pub fn length_64(self) -> &'a mut W { + self.variant(DST_MSIZE_A::LENGTH_64) + } + #[doc = "128 data items"] + #[inline(always)] + pub fn length_128(self) -> &'a mut W { + self.variant(DST_MSIZE_A::LENGTH_128) + } + #[doc = "256 data items"] + #[inline(always)] + pub fn length_256(self) -> &'a mut W { + self.variant(DST_MSIZE_A::LENGTH_256) + } + #[doc = "512 data items"] + #[inline(always)] + pub fn length_512(self) -> &'a mut W { + self.variant(DST_MSIZE_A::LENGTH_512) + } + #[doc = "1024 data items"] + #[inline(always)] + pub fn length_1024(self) -> &'a mut W { + self.variant(DST_MSIZE_A::LENGTH_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 18)) | (((value as u64) & 0x0f) << 18); + self.w + } + } + #[doc = "Reader of field `nonposted_lastwrite_en`"] + pub type NONPOSTED_LASTWRITE_EN_R = crate::R; + #[doc = "Write proxy for field `nonposted_lastwrite_en`"] + pub struct NONPOSTED_LASTWRITE_EN_W<'a> { + w: &'a mut W, + } + impl<'a> NONPOSTED_LASTWRITE_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u64) & 0x01) << 30); + self.w + } + } + #[doc = "Reader of field `arlen_en`"] + pub type ARLEN_EN_R = crate::R; + #[doc = "Write proxy for field `arlen_en`"] + pub struct ARLEN_EN_W<'a> { + w: &'a mut W, + } + impl<'a> ARLEN_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 38)) | (((value as u64) & 0x01) << 38); + self.w + } + } + #[doc = "Reader of field `arlen`"] + pub type ARLEN_R = crate::R; + #[doc = "Write proxy for field `arlen`"] + pub struct ARLEN_W<'a> { + w: &'a mut W, + } + impl<'a> ARLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 39)) | (((value as u64) & 0xff) << 39); + self.w + } + } + #[doc = "Reader of field `awlen_en`"] + pub type AWLEN_EN_R = crate::R; + #[doc = "Write proxy for field `awlen_en`"] + pub struct AWLEN_EN_W<'a> { + w: &'a mut W, + } + impl<'a> AWLEN_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 47)) | (((value as u64) & 0x01) << 47); + self.w + } + } + #[doc = "Reader of field `awlen`"] + pub type AWLEN_R = crate::R; + #[doc = "Write proxy for field `awlen`"] + pub struct AWLEN_W<'a> { + w: &'a mut W, + } + impl<'a> AWLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 48)) | (((value as u64) & 0xff) << 48); + self.w + } + } + #[doc = "Reader of field `src_stat_en`"] + pub type SRC_STAT_EN_R = crate::R; + #[doc = "Write proxy for field `src_stat_en`"] + pub struct SRC_STAT_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_STAT_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 56)) | (((value as u64) & 0x01) << 56); + self.w + } + } + #[doc = "Reader of field `dst_stat_en`"] + pub type DST_STAT_EN_R = crate::R; + #[doc = "Write proxy for field `dst_stat_en`"] + pub struct DST_STAT_EN_W<'a> { + w: &'a mut W, + } + impl<'a> DST_STAT_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 57)) | (((value as u64) & 0x01) << 57); + self.w + } + } + #[doc = "Reader of field `ioc_blktfr`"] + pub type IOC_BLKTFR_R = crate::R; + #[doc = "Write proxy for field `ioc_blktfr`"] + pub struct IOC_BLKTFR_W<'a> { + w: &'a mut W, + } + impl<'a> IOC_BLKTFR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 58)) | (((value as u64) & 0x01) << 58); + self.w + } + } + #[doc = "Reader of field `shadowreg_or_lli_last`"] + pub type SHADOWREG_OR_LLI_LAST_R = crate::R; + #[doc = "Write proxy for field `shadowreg_or_lli_last`"] + pub struct SHADOWREG_OR_LLI_LAST_W<'a> { + w: &'a mut W, + } + impl<'a> SHADOWREG_OR_LLI_LAST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 62)) | (((value as u64) & 0x01) << 62); + self.w + } + } + #[doc = "Reader of field `shadowreg_or_lli_valid`"] + pub type SHADOWREG_OR_LLI_VALID_R = crate::R; + #[doc = "Write proxy for field `shadowreg_or_lli_valid`"] + pub struct SHADOWREG_OR_LLI_VALID_W<'a> { + w: &'a mut W, + } + impl<'a> SHADOWREG_OR_LLI_VALID_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 63)) | (((value as u64) & 0x01) << 63); + self.w + } + } + impl R { + #[doc = "Bit 0 - Source master select"] + #[inline(always)] + pub fn sms(&self) -> SMS_R { + SMS_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Destination master select"] + #[inline(always)] + pub fn dms(&self) -> DMS_R { + DMS_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - Source address increment"] + #[inline(always)] + pub fn sinc(&self) -> SINC_R { + SINC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Destination address increment"] + #[inline(always)] + pub fn dinc(&self) -> DINC_R { + DINC_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Source transfer width"] + #[inline(always)] + pub fn src_tr_width(&self) -> SRC_TR_WIDTH_R { + SRC_TR_WIDTH_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bits 11:13 - Destination transfer width"] + #[inline(always)] + pub fn dst_tr_width(&self) -> DST_TR_WIDTH_R { + DST_TR_WIDTH_R::new(((self.bits >> 11) & 0x07) as u8) + } + #[doc = "Bits 14:17 - Source burst transaction length"] + #[inline(always)] + pub fn src_msize(&self) -> SRC_MSIZE_R { + SRC_MSIZE_R::new(((self.bits >> 14) & 0x0f) as u8) + } + #[doc = "Bits 18:21 - Destination burst transaction length"] + #[inline(always)] + pub fn dst_msize(&self) -> DST_MSIZE_R { + DST_MSIZE_R::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bit 30 - Non Posted Last Write Enable (posted writes may be used till the end of the block)"] + #[inline(always)] + pub fn nonposted_lastwrite_en(&self) -> NONPOSTED_LASTWRITE_EN_R { + NONPOSTED_LASTWRITE_EN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 38 - Source burst length enable"] + #[inline(always)] + pub fn arlen_en(&self) -> ARLEN_EN_R { + ARLEN_EN_R::new(((self.bits >> 38) & 0x01) != 0) + } + #[doc = "Bits 39:46 - Source burst length"] + #[inline(always)] + pub fn arlen(&self) -> ARLEN_R { + ARLEN_R::new(((self.bits >> 39) & 0xff) as u8) + } + #[doc = "Bit 47 - Destination burst length enable"] + #[inline(always)] + pub fn awlen_en(&self) -> AWLEN_EN_R { + AWLEN_EN_R::new(((self.bits >> 47) & 0x01) != 0) + } + #[doc = "Bits 48:55 - Destination burst length"] + #[inline(always)] + pub fn awlen(&self) -> AWLEN_R { + AWLEN_R::new(((self.bits >> 48) & 0xff) as u8) + } + #[doc = "Bit 56 - Source status enable"] + #[inline(always)] + pub fn src_stat_en(&self) -> SRC_STAT_EN_R { + SRC_STAT_EN_R::new(((self.bits >> 56) & 0x01) != 0) + } + #[doc = "Bit 57 - Destination status enable"] + #[inline(always)] + pub fn dst_stat_en(&self) -> DST_STAT_EN_R { + DST_STAT_EN_R::new(((self.bits >> 57) & 0x01) != 0) + } + #[doc = "Bit 58 - Interrupt completion of block transfer"] + #[inline(always)] + pub fn ioc_blktfr(&self) -> IOC_BLKTFR_R { + IOC_BLKTFR_R::new(((self.bits >> 58) & 0x01) != 0) + } + #[doc = "Bit 62 - Last shadow linked list item (indicates shadowreg/LLI content is the last one)"] + #[inline(always)] + pub fn shadowreg_or_lli_last(&self) -> SHADOWREG_OR_LLI_LAST_R { + SHADOWREG_OR_LLI_LAST_R::new(((self.bits >> 62) & 0x01) != 0) + } + #[doc = "Bit 63 - last shadow linked list item valid (indicate shadowreg/LLI content is valid)"] + #[inline(always)] + pub fn shadowreg_or_lli_valid(&self) -> SHADOWREG_OR_LLI_VALID_R { + SHADOWREG_OR_LLI_VALID_R::new(((self.bits >> 63) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Source master select"] + #[inline(always)] + pub fn sms(&mut self) -> SMS_W { + SMS_W { w: self } + } + #[doc = "Bit 2 - Destination master select"] + #[inline(always)] + pub fn dms(&mut self) -> DMS_W { + DMS_W { w: self } + } + #[doc = "Bit 4 - Source address increment"] + #[inline(always)] + pub fn sinc(&mut self) -> SINC_W { + SINC_W { w: self } + } + #[doc = "Bit 6 - Destination address increment"] + #[inline(always)] + pub fn dinc(&mut self) -> DINC_W { + DINC_W { w: self } + } + #[doc = "Bits 8:10 - Source transfer width"] + #[inline(always)] + pub fn src_tr_width(&mut self) -> SRC_TR_WIDTH_W { + SRC_TR_WIDTH_W { w: self } + } + #[doc = "Bits 11:13 - Destination transfer width"] + #[inline(always)] + pub fn dst_tr_width(&mut self) -> DST_TR_WIDTH_W { + DST_TR_WIDTH_W { w: self } + } + #[doc = "Bits 14:17 - Source burst transaction length"] + #[inline(always)] + pub fn src_msize(&mut self) -> SRC_MSIZE_W { + SRC_MSIZE_W { w: self } + } + #[doc = "Bits 18:21 - Destination burst transaction length"] + #[inline(always)] + pub fn dst_msize(&mut self) -> DST_MSIZE_W { + DST_MSIZE_W { w: self } + } + #[doc = "Bit 30 - Non Posted Last Write Enable (posted writes may be used till the end of the block)"] + #[inline(always)] + pub fn nonposted_lastwrite_en(&mut self) -> NONPOSTED_LASTWRITE_EN_W { + NONPOSTED_LASTWRITE_EN_W { w: self } + } + #[doc = "Bit 38 - Source burst length enable"] + #[inline(always)] + pub fn arlen_en(&mut self) -> ARLEN_EN_W { + ARLEN_EN_W { w: self } + } + #[doc = "Bits 39:46 - Source burst length"] + #[inline(always)] + pub fn arlen(&mut self) -> ARLEN_W { + ARLEN_W { w: self } + } + #[doc = "Bit 47 - Destination burst length enable"] + #[inline(always)] + pub fn awlen_en(&mut self) -> AWLEN_EN_W { + AWLEN_EN_W { w: self } + } + #[doc = "Bits 48:55 - Destination burst length"] + #[inline(always)] + pub fn awlen(&mut self) -> AWLEN_W { + AWLEN_W { w: self } + } + #[doc = "Bit 56 - Source status enable"] + #[inline(always)] + pub fn src_stat_en(&mut self) -> SRC_STAT_EN_W { + SRC_STAT_EN_W { w: self } + } + #[doc = "Bit 57 - Destination status enable"] + #[inline(always)] + pub fn dst_stat_en(&mut self) -> DST_STAT_EN_W { + DST_STAT_EN_W { w: self } + } + #[doc = "Bit 58 - Interrupt completion of block transfer"] + #[inline(always)] + pub fn ioc_blktfr(&mut self) -> IOC_BLKTFR_W { + IOC_BLKTFR_W { w: self } + } + #[doc = "Bit 62 - Last shadow linked list item (indicates shadowreg/LLI content is the last one)"] + #[inline(always)] + pub fn shadowreg_or_lli_last(&mut self) -> SHADOWREG_OR_LLI_LAST_W { + SHADOWREG_OR_LLI_LAST_W { w: self } + } + #[doc = "Bit 63 - last shadow linked list item valid (indicate shadowreg/LLI content is valid)"] + #[inline(always)] + pub fn shadowreg_or_lli_valid(&mut self) -> SHADOWREG_OR_LLI_VALID_W { + SHADOWREG_OR_LLI_VALID_W { w: self } + } + } + } + #[doc = "Configure Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] + pub type CFG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CFG; + #[doc = "`read()` method returns [cfg::R](cfg::R) reader structure"] + impl crate::Readable for CFG {} + #[doc = "`write(|w| ..)` method takes [cfg::W](cfg::W) writer structure"] + impl crate::Writable for CFG {} + #[doc = "Configure Register"] + pub mod cfg { + #[doc = "Reader of register cfg"] + pub type R = crate::R; + #[doc = "Writer for register cfg"] + pub type W = crate::W; + #[doc = "Register cfg `reset()`'s with value 0"] + impl crate::ResetValue for super::CFG { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Source multi-block transfer type\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum SRC_MULTBLK_TYPE_A { + #[doc = "0: Continuous multi-block type"] + CONTIGUOUS = 0, + #[doc = "1: Reload multi-block type"] + RELOAD = 1, + #[doc = "2: Shadow register based multi-block type"] + SHADOW_REGISTER = 2, + #[doc = "3: Linked list based multi-block type"] + LINKED_LIST = 3, + } + impl From for u8 { + #[inline(always)] + fn from(variant: SRC_MULTBLK_TYPE_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `src_multblk_type`"] + pub type SRC_MULTBLK_TYPE_R = crate::R; + impl SRC_MULTBLK_TYPE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_MULTBLK_TYPE_A { + match self.bits { + 0 => SRC_MULTBLK_TYPE_A::CONTIGUOUS, + 1 => SRC_MULTBLK_TYPE_A::RELOAD, + 2 => SRC_MULTBLK_TYPE_A::SHADOW_REGISTER, + 3 => SRC_MULTBLK_TYPE_A::LINKED_LIST, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CONTIGUOUS`"] + #[inline(always)] + pub fn is_contiguous(&self) -> bool { + *self == SRC_MULTBLK_TYPE_A::CONTIGUOUS + } + #[doc = "Checks if the value of the field is `RELOAD`"] + #[inline(always)] + pub fn is_reload(&self) -> bool { + *self == SRC_MULTBLK_TYPE_A::RELOAD + } + #[doc = "Checks if the value of the field is `SHADOW_REGISTER`"] + #[inline(always)] + pub fn is_shadow_register(&self) -> bool { + *self == SRC_MULTBLK_TYPE_A::SHADOW_REGISTER + } + #[doc = "Checks if the value of the field is `LINKED_LIST`"] + #[inline(always)] + pub fn is_linked_list(&self) -> bool { + *self == SRC_MULTBLK_TYPE_A::LINKED_LIST + } + } + #[doc = "Write proxy for field `src_multblk_type`"] + pub struct SRC_MULTBLK_TYPE_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_MULTBLK_TYPE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_MULTBLK_TYPE_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "Continuous multi-block type"] + #[inline(always)] + pub fn contiguous(self) -> &'a mut W { + self.variant(SRC_MULTBLK_TYPE_A::CONTIGUOUS) + } + #[doc = "Reload multi-block type"] + #[inline(always)] + pub fn reload(self) -> &'a mut W { + self.variant(SRC_MULTBLK_TYPE_A::RELOAD) + } + #[doc = "Shadow register based multi-block type"] + #[inline(always)] + pub fn shadow_register(self) -> &'a mut W { + self.variant(SRC_MULTBLK_TYPE_A::SHADOW_REGISTER) + } + #[doc = "Linked list based multi-block type"] + #[inline(always)] + pub fn linked_list(self) -> &'a mut W { + self.variant(SRC_MULTBLK_TYPE_A::LINKED_LIST) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | ((value as u64) & 0x03); + self.w + } + } + #[doc = "Destination multi-block transfer type"] + pub type DST_MULTBLK_TYPE_A = SRC_MULTBLK_TYPE_A; + #[doc = "Reader of field `dst_multblk_type`"] + pub type DST_MULTBLK_TYPE_R = crate::R; + #[doc = "Write proxy for field `dst_multblk_type`"] + pub struct DST_MULTBLK_TYPE_W<'a> { + w: &'a mut W, + } + impl<'a> DST_MULTBLK_TYPE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DST_MULTBLK_TYPE_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "Continuous multi-block type"] + #[inline(always)] + pub fn contiguous(self) -> &'a mut W { + self.variant(DST_MULTBLK_TYPE_A::CONTIGUOUS) + } + #[doc = "Reload multi-block type"] + #[inline(always)] + pub fn reload(self) -> &'a mut W { + self.variant(DST_MULTBLK_TYPE_A::RELOAD) + } + #[doc = "Shadow register based multi-block type"] + #[inline(always)] + pub fn shadow_register(self) -> &'a mut W { + self.variant(DST_MULTBLK_TYPE_A::SHADOW_REGISTER) + } + #[doc = "Linked list based multi-block type"] + #[inline(always)] + pub fn linked_list(self) -> &'a mut W { + self.variant(DST_MULTBLK_TYPE_A::LINKED_LIST) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u64) & 0x03) << 2); + self.w + } + } + #[doc = "Transfer type and flow control\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum TT_FC_A { + #[doc = "0: Transfer memory to memory and flow controller is DMAC"] + MEM2MEM_DMA = 0, + #[doc = "1: Transfer memory to peripheral and flow controller is DMAC"] + MEM2PRF_DMA = 1, + #[doc = "2: Transfer peripheral to memory and flow controller is DMAC"] + PRF2MEM_DMA = 2, + #[doc = "3: Transfer peripheral to peripheral and flow controller is DMAC"] + PRF2PRF_DMA = 3, + #[doc = "4: Transfer peripheral to memory and flow controller is source peripheral"] + PRF2MEM_PRF = 4, + #[doc = "5: Transfer peripheral to peripheral and flow controller is source peripheral"] + PRF2PRF_SRCPRF = 5, + #[doc = "6: Transfer memory to peripheral and flow controller is destination peripheral"] + MEM2PRF_PRF = 6, + #[doc = "7: Transfer peripheral to peripheral and flow controller is destination peripheral"] + PRF2PRF_DSTPRF = 7, + } + impl From for u8 { + #[inline(always)] + fn from(variant: TT_FC_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `tt_fc`"] + pub type TT_FC_R = crate::R; + impl TT_FC_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TT_FC_A { + match self.bits { + 0 => TT_FC_A::MEM2MEM_DMA, + 1 => TT_FC_A::MEM2PRF_DMA, + 2 => TT_FC_A::PRF2MEM_DMA, + 3 => TT_FC_A::PRF2PRF_DMA, + 4 => TT_FC_A::PRF2MEM_PRF, + 5 => TT_FC_A::PRF2PRF_SRCPRF, + 6 => TT_FC_A::MEM2PRF_PRF, + 7 => TT_FC_A::PRF2PRF_DSTPRF, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `MEM2MEM_DMA`"] + #[inline(always)] + pub fn is_mem2mem_dma(&self) -> bool { + *self == TT_FC_A::MEM2MEM_DMA + } + #[doc = "Checks if the value of the field is `MEM2PRF_DMA`"] + #[inline(always)] + pub fn is_mem2prf_dma(&self) -> bool { + *self == TT_FC_A::MEM2PRF_DMA + } + #[doc = "Checks if the value of the field is `PRF2MEM_DMA`"] + #[inline(always)] + pub fn is_prf2mem_dma(&self) -> bool { + *self == TT_FC_A::PRF2MEM_DMA + } + #[doc = "Checks if the value of the field is `PRF2PRF_DMA`"] + #[inline(always)] + pub fn is_prf2prf_dma(&self) -> bool { + *self == TT_FC_A::PRF2PRF_DMA + } + #[doc = "Checks if the value of the field is `PRF2MEM_PRF`"] + #[inline(always)] + pub fn is_prf2mem_prf(&self) -> bool { + *self == TT_FC_A::PRF2MEM_PRF + } + #[doc = "Checks if the value of the field is `PRF2PRF_SRCPRF`"] + #[inline(always)] + pub fn is_prf2prf_srcprf(&self) -> bool { + *self == TT_FC_A::PRF2PRF_SRCPRF + } + #[doc = "Checks if the value of the field is `MEM2PRF_PRF`"] + #[inline(always)] + pub fn is_mem2prf_prf(&self) -> bool { + *self == TT_FC_A::MEM2PRF_PRF + } + #[doc = "Checks if the value of the field is `PRF2PRF_DSTPRF`"] + #[inline(always)] + pub fn is_prf2prf_dstprf(&self) -> bool { + *self == TT_FC_A::PRF2PRF_DSTPRF + } + } + #[doc = "Write proxy for field `tt_fc`"] + pub struct TT_FC_W<'a> { + w: &'a mut W, + } + impl<'a> TT_FC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TT_FC_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "Transfer memory to memory and flow controller is DMAC"] + #[inline(always)] + pub fn mem2mem_dma(self) -> &'a mut W { + self.variant(TT_FC_A::MEM2MEM_DMA) + } + #[doc = "Transfer memory to peripheral and flow controller is DMAC"] + #[inline(always)] + pub fn mem2prf_dma(self) -> &'a mut W { + self.variant(TT_FC_A::MEM2PRF_DMA) + } + #[doc = "Transfer peripheral to memory and flow controller is DMAC"] + #[inline(always)] + pub fn prf2mem_dma(self) -> &'a mut W { + self.variant(TT_FC_A::PRF2MEM_DMA) + } + #[doc = "Transfer peripheral to peripheral and flow controller is DMAC"] + #[inline(always)] + pub fn prf2prf_dma(self) -> &'a mut W { + self.variant(TT_FC_A::PRF2PRF_DMA) + } + #[doc = "Transfer peripheral to memory and flow controller is source peripheral"] + #[inline(always)] + pub fn prf2mem_prf(self) -> &'a mut W { + self.variant(TT_FC_A::PRF2MEM_PRF) + } + #[doc = "Transfer peripheral to peripheral and flow controller is source peripheral"] + #[inline(always)] + pub fn prf2prf_srcprf(self) -> &'a mut W { + self.variant(TT_FC_A::PRF2PRF_SRCPRF) + } + #[doc = "Transfer memory to peripheral and flow controller is destination peripheral"] + #[inline(always)] + pub fn mem2prf_prf(self) -> &'a mut W { + self.variant(TT_FC_A::MEM2PRF_PRF) + } + #[doc = "Transfer peripheral to peripheral and flow controller is destination peripheral"] + #[inline(always)] + pub fn prf2prf_dstprf(self) -> &'a mut W { + self.variant(TT_FC_A::PRF2PRF_DSTPRF) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 32)) | (((value as u64) & 0x07) << 32); + self.w + } + } + #[doc = "Source software or hardware handshaking select\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum HS_SEL_SRC_A { + #[doc = "0: Hardware handshaking is used"] + HARDWARE = 0, + #[doc = "1: Software handshaking is used"] + SOFTWARE = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: HS_SEL_SRC_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `hs_sel_src`"] + pub type HS_SEL_SRC_R = crate::R; + impl HS_SEL_SRC_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HS_SEL_SRC_A { + match self.bits { + false => HS_SEL_SRC_A::HARDWARE, + true => HS_SEL_SRC_A::SOFTWARE, + } + } + #[doc = "Checks if the value of the field is `HARDWARE`"] + #[inline(always)] + pub fn is_hardware(&self) -> bool { + *self == HS_SEL_SRC_A::HARDWARE + } + #[doc = "Checks if the value of the field is `SOFTWARE`"] + #[inline(always)] + pub fn is_software(&self) -> bool { + *self == HS_SEL_SRC_A::SOFTWARE + } + } + #[doc = "Write proxy for field `hs_sel_src`"] + pub struct HS_SEL_SRC_W<'a> { + w: &'a mut W, + } + impl<'a> HS_SEL_SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HS_SEL_SRC_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Hardware handshaking is used"] + #[inline(always)] + pub fn hardware(self) -> &'a mut W { + self.variant(HS_SEL_SRC_A::HARDWARE) + } + #[doc = "Software handshaking is used"] + #[inline(always)] + pub fn software(self) -> &'a mut W { + self.variant(HS_SEL_SRC_A::SOFTWARE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 35)) | (((value as u64) & 0x01) << 35); + self.w + } + } + #[doc = "Destination software or hardware handshaking select"] + pub type HS_SEL_DST_A = HS_SEL_SRC_A; + #[doc = "Reader of field `hs_sel_dst`"] + pub type HS_SEL_DST_R = crate::R; + #[doc = "Write proxy for field `hs_sel_dst`"] + pub struct HS_SEL_DST_W<'a> { + w: &'a mut W, + } + impl<'a> HS_SEL_DST_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HS_SEL_DST_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Hardware handshaking is used"] + #[inline(always)] + pub fn hardware(self) -> &'a mut W { + self.variant(HS_SEL_DST_A::HARDWARE) + } + #[doc = "Software handshaking is used"] + #[inline(always)] + pub fn software(self) -> &'a mut W { + self.variant(HS_SEL_DST_A::SOFTWARE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 36)) | (((value as u64) & 0x01) << 36); + self.w + } + } + #[doc = "Source hardware handshaking interface polarity\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum SRC_HWHS_POL_A { + #[doc = "0: Active high"] + ACTIVE_HIGH = 0, + #[doc = "1: Active low"] + ACTIVE_LOW = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: SRC_HWHS_POL_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `src_hwhs_pol`"] + pub type SRC_HWHS_POL_R = crate::R; + impl SRC_HWHS_POL_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_HWHS_POL_A { + match self.bits { + false => SRC_HWHS_POL_A::ACTIVE_HIGH, + true => SRC_HWHS_POL_A::ACTIVE_LOW, + } + } + #[doc = "Checks if the value of the field is `ACTIVE_HIGH`"] + #[inline(always)] + pub fn is_active_high(&self) -> bool { + *self == SRC_HWHS_POL_A::ACTIVE_HIGH + } + #[doc = "Checks if the value of the field is `ACTIVE_LOW`"] + #[inline(always)] + pub fn is_active_low(&self) -> bool { + *self == SRC_HWHS_POL_A::ACTIVE_LOW + } + } + #[doc = "Write proxy for field `src_hwhs_pol`"] + pub struct SRC_HWHS_POL_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_HWHS_POL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_HWHS_POL_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Active high"] + #[inline(always)] + pub fn active_high(self) -> &'a mut W { + self.variant(SRC_HWHS_POL_A::ACTIVE_HIGH) + } + #[doc = "Active low"] + #[inline(always)] + pub fn active_low(self) -> &'a mut W { + self.variant(SRC_HWHS_POL_A::ACTIVE_LOW) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 37)) | (((value as u64) & 0x01) << 37); + self.w + } + } + #[doc = "Destination hardware handshaking interface polarity"] + pub type DST_HWHS_POL_A = SRC_HWHS_POL_A; + #[doc = "Reader of field `dst_hwhs_pol`"] + pub type DST_HWHS_POL_R = crate::R; + #[doc = "Write proxy for field `dst_hwhs_pol`"] + pub struct DST_HWHS_POL_W<'a> { + w: &'a mut W, + } + impl<'a> DST_HWHS_POL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DST_HWHS_POL_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Active high"] + #[inline(always)] + pub fn active_high(self) -> &'a mut W { + self.variant(DST_HWHS_POL_A::ACTIVE_HIGH) + } + #[doc = "Active low"] + #[inline(always)] + pub fn active_low(self) -> &'a mut W { + self.variant(DST_HWHS_POL_A::ACTIVE_LOW) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 38)) | (((value as u64) & 0x01) << 38); + self.w + } + } + #[doc = "Reader of field `src_per`"] + pub type SRC_PER_R = crate::R; + #[doc = "Write proxy for field `src_per`"] + pub struct SRC_PER_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 39)) | (((value as u64) & 0x0f) << 39); + self.w + } + } + #[doc = "Reader of field `dst_per`"] + pub type DST_PER_R = crate::R; + #[doc = "Write proxy for field `dst_per`"] + pub struct DST_PER_W<'a> { + w: &'a mut W, + } + impl<'a> DST_PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 44)) | (((value as u64) & 0x0f) << 44); + self.w + } + } + #[doc = "Reader of field `ch_prior`"] + pub type CH_PRIOR_R = crate::R; + #[doc = "Write proxy for field `ch_prior`"] + pub struct CH_PRIOR_W<'a> { + w: &'a mut W, + } + impl<'a> CH_PRIOR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 49)) | (((value as u64) & 0x07) << 49); + self.w + } + } + #[doc = "Reader of field `lock_ch`"] + pub type LOCK_CH_R = crate::R; + #[doc = "Write proxy for field `lock_ch`"] + pub struct LOCK_CH_W<'a> { + w: &'a mut W, + } + impl<'a> LOCK_CH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 52)) | (((value as u64) & 0x01) << 52); + self.w + } + } + #[doc = "Channel lock level\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum LOCK_CH_L_A { + #[doc = "0: Duration of channel is locked for entire DMA transfer"] + DMA_TRANSFER = 0, + #[doc = "1: Duration of channel is locked for current block transfer"] + BLOCK_TRANSFER = 1, + #[doc = "2: Duration of channel is locked for current transaction"] + TRANSACTION = 2, + } + impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_CH_L_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `lock_ch_l`"] + pub type LOCK_CH_L_R = crate::R; + impl LOCK_CH_L_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(LOCK_CH_L_A::DMA_TRANSFER), + 1 => Val(LOCK_CH_L_A::BLOCK_TRANSFER), + 2 => Val(LOCK_CH_L_A::TRANSACTION), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `DMA_TRANSFER`"] + #[inline(always)] + pub fn is_dma_transfer(&self) -> bool { + *self == LOCK_CH_L_A::DMA_TRANSFER + } + #[doc = "Checks if the value of the field is `BLOCK_TRANSFER`"] + #[inline(always)] + pub fn is_block_transfer(&self) -> bool { + *self == LOCK_CH_L_A::BLOCK_TRANSFER + } + #[doc = "Checks if the value of the field is `TRANSACTION`"] + #[inline(always)] + pub fn is_transaction(&self) -> bool { + *self == LOCK_CH_L_A::TRANSACTION + } + } + #[doc = "Write proxy for field `lock_ch_l`"] + pub struct LOCK_CH_L_W<'a> { + w: &'a mut W, + } + impl<'a> LOCK_CH_L_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LOCK_CH_L_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Duration of channel is locked for entire DMA transfer"] + #[inline(always)] + pub fn dma_transfer(self) -> &'a mut W { + self.variant(LOCK_CH_L_A::DMA_TRANSFER) + } + #[doc = "Duration of channel is locked for current block transfer"] + #[inline(always)] + pub fn block_transfer(self) -> &'a mut W { + self.variant(LOCK_CH_L_A::BLOCK_TRANSFER) + } + #[doc = "Duration of channel is locked for current transaction"] + #[inline(always)] + pub fn transaction(self) -> &'a mut W { + self.variant(LOCK_CH_L_A::TRANSACTION) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 53)) | (((value as u64) & 0x03) << 53); + self.w + } + } + #[doc = "Reader of field `src_osr_lmt`"] + pub type SRC_OSR_LMT_R = crate::R; + #[doc = "Write proxy for field `src_osr_lmt`"] + pub struct SRC_OSR_LMT_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_OSR_LMT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 55)) | (((value as u64) & 0x0f) << 55); + self.w + } + } + #[doc = "Reader of field `dst_osr_lmt`"] + pub type DST_OSR_LMT_R = crate::R; + #[doc = "Write proxy for field `dst_osr_lmt`"] + pub struct DST_OSR_LMT_W<'a> { + w: &'a mut W, + } + impl<'a> DST_OSR_LMT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 59)) | (((value as u64) & 0x0f) << 59); + self.w + } + } + impl R { + #[doc = "Bits 0:1 - Source multi-block transfer type"] + #[inline(always)] + pub fn src_multblk_type(&self) -> SRC_MULTBLK_TYPE_R { + SRC_MULTBLK_TYPE_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Destination multi-block transfer type"] + #[inline(always)] + pub fn dst_multblk_type(&self) -> DST_MULTBLK_TYPE_R { + DST_MULTBLK_TYPE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 32:34 - Transfer type and flow control"] + #[inline(always)] + pub fn tt_fc(&self) -> TT_FC_R { + TT_FC_R::new(((self.bits >> 32) & 0x07) as u8) + } + #[doc = "Bit 35 - Source software or hardware handshaking select"] + #[inline(always)] + pub fn hs_sel_src(&self) -> HS_SEL_SRC_R { + HS_SEL_SRC_R::new(((self.bits >> 35) & 0x01) != 0) + } + #[doc = "Bit 36 - Destination software or hardware handshaking select"] + #[inline(always)] + pub fn hs_sel_dst(&self) -> HS_SEL_DST_R { + HS_SEL_DST_R::new(((self.bits >> 36) & 0x01) != 0) + } + #[doc = "Bit 37 - Source hardware handshaking interface polarity"] + #[inline(always)] + pub fn src_hwhs_pol(&self) -> SRC_HWHS_POL_R { + SRC_HWHS_POL_R::new(((self.bits >> 37) & 0x01) != 0) + } + #[doc = "Bit 38 - Destination hardware handshaking interface polarity"] + #[inline(always)] + pub fn dst_hwhs_pol(&self) -> DST_HWHS_POL_R { + DST_HWHS_POL_R::new(((self.bits >> 38) & 0x01) != 0) + } + #[doc = "Bits 39:42 - Assign a hardware handshaking interface to source of channel"] + #[inline(always)] + pub fn src_per(&self) -> SRC_PER_R { + SRC_PER_R::new(((self.bits >> 39) & 0x0f) as u8) + } + #[doc = "Bits 44:47 - Assign a hardware handshaking interface to destination of channel"] + #[inline(always)] + pub fn dst_per(&self) -> DST_PER_R { + DST_PER_R::new(((self.bits >> 44) & 0x0f) as u8) + } + #[doc = "Bits 49:51 - Channel priority (7 is highest, 0 is lowest)"] + #[inline(always)] + pub fn ch_prior(&self) -> CH_PRIOR_R { + CH_PRIOR_R::new(((self.bits >> 49) & 0x07) as u8) + } + #[doc = "Bit 52 - Channel lock bit"] + #[inline(always)] + pub fn lock_ch(&self) -> LOCK_CH_R { + LOCK_CH_R::new(((self.bits >> 52) & 0x01) != 0) + } + #[doc = "Bits 53:54 - Channel lock level"] + #[inline(always)] + pub fn lock_ch_l(&self) -> LOCK_CH_L_R { + LOCK_CH_L_R::new(((self.bits >> 53) & 0x03) as u8) + } + #[doc = "Bits 55:58 - Source outstanding request limit"] + #[inline(always)] + pub fn src_osr_lmt(&self) -> SRC_OSR_LMT_R { + SRC_OSR_LMT_R::new(((self.bits >> 55) & 0x0f) as u8) + } + #[doc = "Bits 59:62 - Destination outstanding request limit"] + #[inline(always)] + pub fn dst_osr_lmt(&self) -> DST_OSR_LMT_R { + DST_OSR_LMT_R::new(((self.bits >> 59) & 0x0f) as u8) + } + } + impl W { + #[doc = "Bits 0:1 - Source multi-block transfer type"] + #[inline(always)] + pub fn src_multblk_type(&mut self) -> SRC_MULTBLK_TYPE_W { + SRC_MULTBLK_TYPE_W { w: self } + } + #[doc = "Bits 2:3 - Destination multi-block transfer type"] + #[inline(always)] + pub fn dst_multblk_type(&mut self) -> DST_MULTBLK_TYPE_W { + DST_MULTBLK_TYPE_W { w: self } + } + #[doc = "Bits 32:34 - Transfer type and flow control"] + #[inline(always)] + pub fn tt_fc(&mut self) -> TT_FC_W { + TT_FC_W { w: self } + } + #[doc = "Bit 35 - Source software or hardware handshaking select"] + #[inline(always)] + pub fn hs_sel_src(&mut self) -> HS_SEL_SRC_W { + HS_SEL_SRC_W { w: self } + } + #[doc = "Bit 36 - Destination software or hardware handshaking select"] + #[inline(always)] + pub fn hs_sel_dst(&mut self) -> HS_SEL_DST_W { + HS_SEL_DST_W { w: self } + } + #[doc = "Bit 37 - Source hardware handshaking interface polarity"] + #[inline(always)] + pub fn src_hwhs_pol(&mut self) -> SRC_HWHS_POL_W { + SRC_HWHS_POL_W { w: self } + } + #[doc = "Bit 38 - Destination hardware handshaking interface polarity"] + #[inline(always)] + pub fn dst_hwhs_pol(&mut self) -> DST_HWHS_POL_W { + DST_HWHS_POL_W { w: self } + } + #[doc = "Bits 39:42 - Assign a hardware handshaking interface to source of channel"] + #[inline(always)] + pub fn src_per(&mut self) -> SRC_PER_W { + SRC_PER_W { w: self } + } + #[doc = "Bits 44:47 - Assign a hardware handshaking interface to destination of channel"] + #[inline(always)] + pub fn dst_per(&mut self) -> DST_PER_W { + DST_PER_W { w: self } + } + #[doc = "Bits 49:51 - Channel priority (7 is highest, 0 is lowest)"] + #[inline(always)] + pub fn ch_prior(&mut self) -> CH_PRIOR_W { + CH_PRIOR_W { w: self } + } + #[doc = "Bit 52 - Channel lock bit"] + #[inline(always)] + pub fn lock_ch(&mut self) -> LOCK_CH_W { + LOCK_CH_W { w: self } + } + #[doc = "Bits 53:54 - Channel lock level"] + #[inline(always)] + pub fn lock_ch_l(&mut self) -> LOCK_CH_L_W { + LOCK_CH_L_W { w: self } + } + #[doc = "Bits 55:58 - Source outstanding request limit"] + #[inline(always)] + pub fn src_osr_lmt(&mut self) -> SRC_OSR_LMT_W { + SRC_OSR_LMT_W { w: self } + } + #[doc = "Bits 59:62 - Destination outstanding request limit"] + #[inline(always)] + pub fn dst_osr_lmt(&mut self) -> DST_OSR_LMT_W { + DST_OSR_LMT_W { w: self } + } + } + } + #[doc = "Linked List Pointer register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [llp](llp) module"] + pub type LLP = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LLP; + #[doc = "`read()` method returns [llp::R](llp::R) reader structure"] + impl crate::Readable for LLP {} + #[doc = "`write(|w| ..)` method takes [llp::W](llp::W) writer structure"] + impl crate::Writable for LLP {} + #[doc = "Linked List Pointer register"] + pub mod llp { + #[doc = "Reader of register llp"] + pub type R = crate::R; + #[doc = "Writer for register llp"] + pub type W = crate::W; + #[doc = "Register llp `reset()`'s with value 0"] + impl crate::ResetValue for super::LLP { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "LLI master select"] + pub type LMS_A = super::ctl::SMS_A; + #[doc = "Reader of field `lms`"] + pub type LMS_R = crate::R; + #[doc = "Write proxy for field `lms`"] + pub struct LMS_W<'a> { + w: &'a mut W, + } + impl<'a> LMS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LMS_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "AXI master 1"] + #[inline(always)] + pub fn axi_master_1(self) -> &'a mut W { + self.variant(LMS_A::AXI_MASTER_1) + } + #[doc = "AXI master 2"] + #[inline(always)] + pub fn axi_master_2(self) -> &'a mut W { + self.variant(LMS_A::AXI_MASTER_2) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `loc`"] + pub type LOC_R = crate::R; + #[doc = "Write proxy for field `loc`"] + pub struct LOC_W<'a> { + w: &'a mut W, + } + impl<'a> LOC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u64) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff_ffff_ffff_ffff << 6)) + | (((value as u64) & 0x03ff_ffff_ffff_ffff) << 6); + self.w + } + } + impl R { + #[doc = "Bit 0 - LLI master select"] + #[inline(always)] + pub fn lms(&self) -> LMS_R { + LMS_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 6:63 - Starting address memeory of LLI block"] + #[inline(always)] + pub fn loc(&self) -> LOC_R { + LOC_R::new(((self.bits >> 6) & 0x03ff_ffff_ffff_ffff) as u64) + } + } + impl W { + #[doc = "Bit 0 - LLI master select"] + #[inline(always)] + pub fn lms(&mut self) -> LMS_W { + LMS_W { w: self } + } + #[doc = "Bits 6:63 - Starting address memeory of LLI block"] + #[inline(always)] + pub fn loc(&mut self) -> LOC_W { + LOC_W { w: self } + } + } + } + #[doc = "Channel Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](status) module"] + pub type STATUS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _STATUS; + #[doc = "`read()` method returns [status::R](status::R) reader structure"] + impl crate::Readable for STATUS {} + #[doc = "`write(|w| ..)` method takes [status::W](status::W) writer structure"] + impl crate::Writable for STATUS {} + #[doc = "Channel Status Register"] + pub mod status { + #[doc = "Reader of register status"] + pub type R = crate::R; + #[doc = "Writer for register status"] + pub type W = crate::W; + #[doc = "Register status `reset()`'s with value 0"] + impl crate::ResetValue for super::STATUS { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `cmpltd_blk_size`"] + pub type CMPLTD_BLK_SIZE_R = crate::R; + #[doc = "Write proxy for field `cmpltd_blk_size`"] + pub struct CMPLTD_BLK_SIZE_W<'a> { + w: &'a mut W, + } + impl<'a> CMPLTD_BLK_SIZE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x003f_ffff) | ((value as u64) & 0x003f_ffff); + self.w + } + } + impl R { + #[doc = "Bits 0:21 - Completed block transfer size"] + #[inline(always)] + pub fn cmpltd_blk_size(&self) -> CMPLTD_BLK_SIZE_R { + CMPLTD_BLK_SIZE_R::new((self.bits & 0x003f_ffff) as u32) + } + } + impl W { + #[doc = "Bits 0:21 - Completed block transfer size"] + #[inline(always)] + pub fn cmpltd_blk_size(&mut self) -> CMPLTD_BLK_SIZE_W { + CMPLTD_BLK_SIZE_W { w: self } + } + } + } + #[doc = "Channel Software handshake Source Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swhssrc](swhssrc) module"] + pub type SWHSSRC = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SWHSSRC; + #[doc = "`read()` method returns [swhssrc::R](swhssrc::R) reader structure"] + impl crate::Readable for SWHSSRC {} + #[doc = "`write(|w| ..)` method takes [swhssrc::W](swhssrc::W) writer structure"] + impl crate::Writable for SWHSSRC {} + #[doc = "Channel Software handshake Source Register"] + pub mod swhssrc { + #[doc = "Reader of register swhssrc"] + pub type R = crate::R; + #[doc = "Writer for register swhssrc"] + pub type W = crate::W; + #[doc = "Register swhssrc `reset()`'s with value 0"] + impl crate::ResetValue for super::SWHSSRC { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `req`"] + pub type REQ_R = crate::R; + #[doc = "Write proxy for field `req`"] + pub struct REQ_W<'a> { + w: &'a mut W, + } + impl<'a> REQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `req_we`"] + pub type REQ_WE_R = crate::R; + #[doc = "Write proxy for field `req_we`"] + pub struct REQ_WE_W<'a> { + w: &'a mut W, + } + impl<'a> REQ_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `sglreq`"] + pub type SGLREQ_R = crate::R; + #[doc = "Write proxy for field `sglreq`"] + pub struct SGLREQ_W<'a> { + w: &'a mut W, + } + impl<'a> SGLREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `sglreq_we`"] + pub type SGLREQ_WE_R = crate::R; + #[doc = "Write proxy for field `sglreq_we`"] + pub struct SGLREQ_WE_W<'a> { + w: &'a mut W, + } + impl<'a> SGLREQ_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `lst`"] + pub type LST_R = crate::R; + #[doc = "Write proxy for field `lst`"] + pub struct LST_W<'a> { + w: &'a mut W, + } + impl<'a> LST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u64) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `lst_we`"] + pub type LST_WE_R = crate::R; + #[doc = "Write proxy for field `lst_we`"] + pub struct LST_WE_W<'a> { + w: &'a mut W, + } + impl<'a> LST_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u64) & 0x01) << 5); + self.w + } + } + impl R { + #[doc = "Bit 0 - Software handshake request for channel source"] + #[inline(always)] + pub fn req(&self) -> REQ_R { + REQ_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Write enable bit for software handshake request"] + #[inline(always)] + pub fn req_we(&self) -> REQ_WE_R { + REQ_WE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Software handshake single request for channel source"] + #[inline(always)] + pub fn sglreq(&self) -> SGLREQ_R { + SGLREQ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Write enable bit for software handshake"] + #[inline(always)] + pub fn sglreq_we(&self) -> SGLREQ_WE_R { + SGLREQ_WE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Software handshake last request for channel source"] + #[inline(always)] + pub fn lst(&self) -> LST_R { + LST_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Write enable bit for software handshake last request"] + #[inline(always)] + pub fn lst_we(&self) -> LST_WE_R { + LST_WE_R::new(((self.bits >> 5) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Software handshake request for channel source"] + #[inline(always)] + pub fn req(&mut self) -> REQ_W { + REQ_W { w: self } + } + #[doc = "Bit 1 - Write enable bit for software handshake request"] + #[inline(always)] + pub fn req_we(&mut self) -> REQ_WE_W { + REQ_WE_W { w: self } + } + #[doc = "Bit 2 - Software handshake single request for channel source"] + #[inline(always)] + pub fn sglreq(&mut self) -> SGLREQ_W { + SGLREQ_W { w: self } + } + #[doc = "Bit 3 - Write enable bit for software handshake"] + #[inline(always)] + pub fn sglreq_we(&mut self) -> SGLREQ_WE_W { + SGLREQ_WE_W { w: self } + } + #[doc = "Bit 4 - Software handshake last request for channel source"] + #[inline(always)] + pub fn lst(&mut self) -> LST_W { + LST_W { w: self } + } + #[doc = "Bit 5 - Write enable bit for software handshake last request"] + #[inline(always)] + pub fn lst_we(&mut self) -> LST_WE_W { + LST_WE_W { w: self } + } + } + } + #[doc = "Channel Software handshake Destination Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swhsdst](swhsdst) module"] + pub type SWHSDST = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SWHSDST; + #[doc = "`read()` method returns [swhsdst::R](swhsdst::R) reader structure"] + impl crate::Readable for SWHSDST {} + #[doc = "`write(|w| ..)` method takes [swhsdst::W](swhsdst::W) writer structure"] + impl crate::Writable for SWHSDST {} + #[doc = "Channel Software handshake Destination Register"] + pub mod swhsdst { + #[doc = "Reader of register swhsdst"] + pub type R = crate::R; + #[doc = "Writer for register swhsdst"] + pub type W = crate::W; + #[doc = "Register swhsdst `reset()`'s with value 0"] + impl crate::ResetValue for super::SWHSDST { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `req`"] + pub type REQ_R = crate::R; + #[doc = "Write proxy for field `req`"] + pub struct REQ_W<'a> { + w: &'a mut W, + } + impl<'a> REQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `req_we`"] + pub type REQ_WE_R = crate::R; + #[doc = "Write proxy for field `req_we`"] + pub struct REQ_WE_W<'a> { + w: &'a mut W, + } + impl<'a> REQ_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `sglreq`"] + pub type SGLREQ_R = crate::R; + #[doc = "Write proxy for field `sglreq`"] + pub struct SGLREQ_W<'a> { + w: &'a mut W, + } + impl<'a> SGLREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `sglreq_we`"] + pub type SGLREQ_WE_R = crate::R; + #[doc = "Write proxy for field `sglreq_we`"] + pub struct SGLREQ_WE_W<'a> { + w: &'a mut W, + } + impl<'a> SGLREQ_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `lst`"] + pub type LST_R = crate::R; + #[doc = "Write proxy for field `lst`"] + pub struct LST_W<'a> { + w: &'a mut W, + } + impl<'a> LST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u64) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `lst_we`"] + pub type LST_WE_R = crate::R; + #[doc = "Write proxy for field `lst_we`"] + pub struct LST_WE_W<'a> { + w: &'a mut W, + } + impl<'a> LST_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u64) & 0x01) << 5); + self.w + } + } + impl R { + #[doc = "Bit 0 - Software handshake request for channel destination"] + #[inline(always)] + pub fn req(&self) -> REQ_R { + REQ_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Write enable bit for software handshake request"] + #[inline(always)] + pub fn req_we(&self) -> REQ_WE_R { + REQ_WE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Software handshake single request for channel destination"] + #[inline(always)] + pub fn sglreq(&self) -> SGLREQ_R { + SGLREQ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Write enable bit for software handshake"] + #[inline(always)] + pub fn sglreq_we(&self) -> SGLREQ_WE_R { + SGLREQ_WE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Software handshake last request for channel destination"] + #[inline(always)] + pub fn lst(&self) -> LST_R { + LST_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Write enable bit for software handshake last request"] + #[inline(always)] + pub fn lst_we(&self) -> LST_WE_R { + LST_WE_R::new(((self.bits >> 5) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Software handshake request for channel destination"] + #[inline(always)] + pub fn req(&mut self) -> REQ_W { + REQ_W { w: self } + } + #[doc = "Bit 1 - Write enable bit for software handshake request"] + #[inline(always)] + pub fn req_we(&mut self) -> REQ_WE_W { + REQ_WE_W { w: self } + } + #[doc = "Bit 2 - Software handshake single request for channel destination"] + #[inline(always)] + pub fn sglreq(&mut self) -> SGLREQ_W { + SGLREQ_W { w: self } + } + #[doc = "Bit 3 - Write enable bit for software handshake"] + #[inline(always)] + pub fn sglreq_we(&mut self) -> SGLREQ_WE_W { + SGLREQ_WE_W { w: self } + } + #[doc = "Bit 4 - Software handshake last request for channel destination"] + #[inline(always)] + pub fn lst(&mut self) -> LST_W { + LST_W { w: self } + } + #[doc = "Bit 5 - Write enable bit for software handshake last request"] + #[inline(always)] + pub fn lst_we(&mut self) -> LST_WE_W { + LST_WE_W { w: self } + } + } + } + #[doc = "Channel Block Transfer Resume Request Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [blk_tfr](blk_tfr) module"] + pub type BLK_TFR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _BLK_TFR; + #[doc = "`read()` method returns [blk_tfr::R](blk_tfr::R) reader structure"] + impl crate::Readable for BLK_TFR {} + #[doc = "`write(|w| ..)` method takes [blk_tfr::W](blk_tfr::W) writer structure"] + impl crate::Writable for BLK_TFR {} + #[doc = "Channel Block Transfer Resume Request Register"] + pub mod blk_tfr { + #[doc = "Reader of register blk_tfr"] + pub type R = crate::R; + #[doc = "Writer for register blk_tfr"] + pub type W = crate::W; + #[doc = "Register blk_tfr `reset()`'s with value 0"] + impl crate::ResetValue for super::BLK_TFR { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `resumereq`"] + pub type RESUMEREQ_R = crate::R; + #[doc = "Write proxy for field `resumereq`"] + pub struct RESUMEREQ_W<'a> { + w: &'a mut W, + } + impl<'a> RESUMEREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Block transfer resume request"] + #[inline(always)] + pub fn resumereq(&self) -> RESUMEREQ_R { + RESUMEREQ_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Block transfer resume request"] + #[inline(always)] + pub fn resumereq(&mut self) -> RESUMEREQ_W { + RESUMEREQ_W { w: self } + } + } + } + #[doc = "Channel AXI ID Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [axi_id](axi_id) module"] + pub type AXI_ID = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _AXI_ID; + #[doc = "`read()` method returns [axi_id::R](axi_id::R) reader structure"] + impl crate::Readable for AXI_ID {} + #[doc = "`write(|w| ..)` method takes [axi_id::W](axi_id::W) writer structure"] + impl crate::Writable for AXI_ID {} + #[doc = "Channel AXI ID Register"] + pub mod axi_id { + #[doc = "Reader of register axi_id"] + pub type R = crate::R; + #[doc = "Writer for register axi_id"] + pub type W = crate::W; + #[doc = "Register axi_id `reset()`'s with value 0"] + impl crate::ResetValue for super::AXI_ID { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "AXI QOS Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [axi_qos](axi_qos) module"] + pub type AXI_QOS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _AXI_QOS; + #[doc = "`read()` method returns [axi_qos::R](axi_qos::R) reader structure"] + impl crate::Readable for AXI_QOS {} + #[doc = "`write(|w| ..)` method takes [axi_qos::W](axi_qos::W) writer structure"] + impl crate::Writable for AXI_QOS {} + #[doc = "AXI QOS Register"] + pub mod axi_qos { + #[doc = "Reader of register axi_qos"] + pub type R = crate::R; + #[doc = "Writer for register axi_qos"] + pub type W = crate::W; + #[doc = "Register axi_qos `reset()`'s with value 0"] + impl crate::ResetValue for super::AXI_QOS { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Status Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstatus_en](intstatus_en) module"] + pub type INTSTATUS_EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTSTATUS_EN; + #[doc = "`read()` method returns [intstatus_en::R](intstatus_en::R) reader structure"] + impl crate::Readable for INTSTATUS_EN {} + #[doc = "`write(|w| ..)` method takes [intstatus_en::W](intstatus_en::W) writer structure"] + impl crate::Writable for INTSTATUS_EN {} + #[doc = "Interrupt Status Enable Register"] + pub mod intstatus_en { + #[doc = "Reader of register intstatus_en"] + pub type R = crate::R; + #[doc = "Writer for register intstatus_en"] + pub type W = crate::W; + #[doc = "Register intstatus_en `reset()`'s with value 0"] + impl crate::ResetValue for super::INTSTATUS_EN { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `block_tfr_done`"] + pub type BLOCK_TFR_DONE_R = crate::R; + #[doc = "Write proxy for field `block_tfr_done`"] + pub struct BLOCK_TFR_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> BLOCK_TFR_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `tfr_done`"] + pub type TFR_DONE_R = crate::R; + #[doc = "Write proxy for field `tfr_done`"] + pub struct TFR_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> TFR_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `src_transcomp`"] + pub type SRC_TRANSCOMP_R = crate::R; + #[doc = "Write proxy for field `src_transcomp`"] + pub struct SRC_TRANSCOMP_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_TRANSCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `dst_transcomp`"] + pub type DST_TRANSCOMP_R = crate::R; + #[doc = "Write proxy for field `dst_transcomp`"] + pub struct DST_TRANSCOMP_W<'a> { + w: &'a mut W, + } + impl<'a> DST_TRANSCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u64) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `src_dec_err`"] + pub type SRC_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `src_dec_err`"] + pub struct SRC_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u64) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `dst_dec_err`"] + pub type DST_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `dst_dec_err`"] + pub struct DST_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> DST_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u64) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `src_slv_err`"] + pub type SRC_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `src_slv_err`"] + pub struct SRC_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u64) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `dst_slv_err`"] + pub type DST_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `dst_slv_err`"] + pub struct DST_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> DST_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u64) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `lli_rd_dec_err`"] + pub type LLI_RD_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_rd_dec_err`"] + pub struct LLI_RD_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_RD_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u64) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `lli_wr_dec_err`"] + pub type LLI_WR_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_wr_dec_err`"] + pub struct LLI_WR_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_WR_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u64) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `lli_rd_slv_err`"] + pub type LLI_RD_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_rd_slv_err`"] + pub struct LLI_RD_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_RD_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u64) & 0x01) << 11); + self.w + } + } + #[doc = "Reader of field `lli_wr_slv_err`"] + pub type LLI_WR_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_wr_slv_err`"] + pub struct LLI_WR_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_WR_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u64) & 0x01) << 12); + self.w + } + } + impl R { + #[doc = "Bit 0 - Block transfer done"] + #[inline(always)] + pub fn block_tfr_done(&self) -> BLOCK_TFR_DONE_R { + BLOCK_TFR_DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer done"] + #[inline(always)] + pub fn tfr_done(&self) -> TFR_DONE_R { + TFR_DONE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Source transaction complete"] + #[inline(always)] + pub fn src_transcomp(&self) -> SRC_TRANSCOMP_R { + SRC_TRANSCOMP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Destination transaction complete"] + #[inline(always)] + pub fn dst_transcomp(&self) -> DST_TRANSCOMP_R { + DST_TRANSCOMP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Source Decode Error"] + #[inline(always)] + pub fn src_dec_err(&self) -> SRC_DEC_ERR_R { + SRC_DEC_ERR_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Destination Decode Error"] + #[inline(always)] + pub fn dst_dec_err(&self) -> DST_DEC_ERR_R { + DST_DEC_ERR_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Source Slave Error"] + #[inline(always)] + pub fn src_slv_err(&self) -> SRC_SLV_ERR_R { + SRC_SLV_ERR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Destination Slave Error"] + #[inline(always)] + pub fn dst_slv_err(&self) -> DST_SLV_ERR_R { + DST_SLV_ERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - LLI Read Decode Error Status Enable"] + #[inline(always)] + pub fn lli_rd_dec_err(&self) -> LLI_RD_DEC_ERR_R { + LLI_RD_DEC_ERR_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - LLI WRITE Decode Error"] + #[inline(always)] + pub fn lli_wr_dec_err(&self) -> LLI_WR_DEC_ERR_R { + LLI_WR_DEC_ERR_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - LLI Read Slave Error"] + #[inline(always)] + pub fn lli_rd_slv_err(&self) -> LLI_RD_SLV_ERR_R { + LLI_RD_SLV_ERR_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - LLI WRITE Slave Error"] + #[inline(always)] + pub fn lli_wr_slv_err(&self) -> LLI_WR_SLV_ERR_R { + LLI_WR_SLV_ERR_R::new(((self.bits >> 12) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Block transfer done"] + #[inline(always)] + pub fn block_tfr_done(&mut self) -> BLOCK_TFR_DONE_W { + BLOCK_TFR_DONE_W { w: self } + } + #[doc = "Bit 1 - Transfer done"] + #[inline(always)] + pub fn tfr_done(&mut self) -> TFR_DONE_W { + TFR_DONE_W { w: self } + } + #[doc = "Bit 3 - Source transaction complete"] + #[inline(always)] + pub fn src_transcomp(&mut self) -> SRC_TRANSCOMP_W { + SRC_TRANSCOMP_W { w: self } + } + #[doc = "Bit 4 - Destination transaction complete"] + #[inline(always)] + pub fn dst_transcomp(&mut self) -> DST_TRANSCOMP_W { + DST_TRANSCOMP_W { w: self } + } + #[doc = "Bit 5 - Source Decode Error"] + #[inline(always)] + pub fn src_dec_err(&mut self) -> SRC_DEC_ERR_W { + SRC_DEC_ERR_W { w: self } + } + #[doc = "Bit 6 - Destination Decode Error"] + #[inline(always)] + pub fn dst_dec_err(&mut self) -> DST_DEC_ERR_W { + DST_DEC_ERR_W { w: self } + } + #[doc = "Bit 7 - Source Slave Error"] + #[inline(always)] + pub fn src_slv_err(&mut self) -> SRC_SLV_ERR_W { + SRC_SLV_ERR_W { w: self } + } + #[doc = "Bit 8 - Destination Slave Error"] + #[inline(always)] + pub fn dst_slv_err(&mut self) -> DST_SLV_ERR_W { + DST_SLV_ERR_W { w: self } + } + #[doc = "Bit 9 - LLI Read Decode Error Status Enable"] + #[inline(always)] + pub fn lli_rd_dec_err(&mut self) -> LLI_RD_DEC_ERR_W { + LLI_RD_DEC_ERR_W { w: self } + } + #[doc = "Bit 10 - LLI WRITE Decode Error"] + #[inline(always)] + pub fn lli_wr_dec_err(&mut self) -> LLI_WR_DEC_ERR_W { + LLI_WR_DEC_ERR_W { w: self } + } + #[doc = "Bit 11 - LLI Read Slave Error"] + #[inline(always)] + pub fn lli_rd_slv_err(&mut self) -> LLI_RD_SLV_ERR_W { + LLI_RD_SLV_ERR_W { w: self } + } + #[doc = "Bit 12 - LLI WRITE Slave Error"] + #[inline(always)] + pub fn lli_wr_slv_err(&mut self) -> LLI_WR_SLV_ERR_W { + LLI_WR_SLV_ERR_W { w: self } + } + } + } + #[doc = "Channel Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstatus](intstatus) module"] + pub type INTSTATUS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTSTATUS; + #[doc = "`read()` method returns [intstatus::R](intstatus::R) reader structure"] + impl crate::Readable for INTSTATUS {} + #[doc = "`write(|w| ..)` method takes [intstatus::W](intstatus::W) writer structure"] + impl crate::Writable for INTSTATUS {} + #[doc = "Channel Interrupt Status Register"] + pub mod intstatus { + #[doc = "Reader of register intstatus"] + pub type R = crate::R; + #[doc = "Writer for register intstatus"] + pub type W = crate::W; + #[doc = "Register intstatus `reset()`'s with value 0"] + impl crate::ResetValue for super::INTSTATUS { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `block_tfr_done`"] + pub type BLOCK_TFR_DONE_R = crate::R; + #[doc = "Write proxy for field `block_tfr_done`"] + pub struct BLOCK_TFR_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> BLOCK_TFR_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `tfr_done`"] + pub type TFR_DONE_R = crate::R; + #[doc = "Write proxy for field `tfr_done`"] + pub struct TFR_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> TFR_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `src_transcomp`"] + pub type SRC_TRANSCOMP_R = crate::R; + #[doc = "Write proxy for field `src_transcomp`"] + pub struct SRC_TRANSCOMP_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_TRANSCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `dst_transcomp`"] + pub type DST_TRANSCOMP_R = crate::R; + #[doc = "Write proxy for field `dst_transcomp`"] + pub struct DST_TRANSCOMP_W<'a> { + w: &'a mut W, + } + impl<'a> DST_TRANSCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u64) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `src_dec_err`"] + pub type SRC_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `src_dec_err`"] + pub struct SRC_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u64) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `dst_dec_err`"] + pub type DST_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `dst_dec_err`"] + pub struct DST_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> DST_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u64) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `src_slv_err`"] + pub type SRC_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `src_slv_err`"] + pub struct SRC_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u64) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `dst_slv_err`"] + pub type DST_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `dst_slv_err`"] + pub struct DST_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> DST_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u64) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `lli_rd_dec_err`"] + pub type LLI_RD_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_rd_dec_err`"] + pub struct LLI_RD_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_RD_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u64) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `lli_wr_dec_err`"] + pub type LLI_WR_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_wr_dec_err`"] + pub struct LLI_WR_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_WR_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u64) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `lli_rd_slv_err`"] + pub type LLI_RD_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_rd_slv_err`"] + pub struct LLI_RD_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_RD_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u64) & 0x01) << 11); + self.w + } + } + #[doc = "Reader of field `lli_wr_slv_err`"] + pub type LLI_WR_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_wr_slv_err`"] + pub struct LLI_WR_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_WR_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u64) & 0x01) << 12); + self.w + } + } + impl R { + #[doc = "Bit 0 - Block transfer done"] + #[inline(always)] + pub fn block_tfr_done(&self) -> BLOCK_TFR_DONE_R { + BLOCK_TFR_DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer done"] + #[inline(always)] + pub fn tfr_done(&self) -> TFR_DONE_R { + TFR_DONE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Source transaction complete"] + #[inline(always)] + pub fn src_transcomp(&self) -> SRC_TRANSCOMP_R { + SRC_TRANSCOMP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Destination transaction complete"] + #[inline(always)] + pub fn dst_transcomp(&self) -> DST_TRANSCOMP_R { + DST_TRANSCOMP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Source Decode Error"] + #[inline(always)] + pub fn src_dec_err(&self) -> SRC_DEC_ERR_R { + SRC_DEC_ERR_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Destination Decode Error"] + #[inline(always)] + pub fn dst_dec_err(&self) -> DST_DEC_ERR_R { + DST_DEC_ERR_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Source Slave Error"] + #[inline(always)] + pub fn src_slv_err(&self) -> SRC_SLV_ERR_R { + SRC_SLV_ERR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Destination Slave Error"] + #[inline(always)] + pub fn dst_slv_err(&self) -> DST_SLV_ERR_R { + DST_SLV_ERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - LLI Read Decode Error Status Enable"] + #[inline(always)] + pub fn lli_rd_dec_err(&self) -> LLI_RD_DEC_ERR_R { + LLI_RD_DEC_ERR_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - LLI WRITE Decode Error"] + #[inline(always)] + pub fn lli_wr_dec_err(&self) -> LLI_WR_DEC_ERR_R { + LLI_WR_DEC_ERR_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - LLI Read Slave Error"] + #[inline(always)] + pub fn lli_rd_slv_err(&self) -> LLI_RD_SLV_ERR_R { + LLI_RD_SLV_ERR_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - LLI WRITE Slave Error"] + #[inline(always)] + pub fn lli_wr_slv_err(&self) -> LLI_WR_SLV_ERR_R { + LLI_WR_SLV_ERR_R::new(((self.bits >> 12) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Block transfer done"] + #[inline(always)] + pub fn block_tfr_done(&mut self) -> BLOCK_TFR_DONE_W { + BLOCK_TFR_DONE_W { w: self } + } + #[doc = "Bit 1 - Transfer done"] + #[inline(always)] + pub fn tfr_done(&mut self) -> TFR_DONE_W { + TFR_DONE_W { w: self } + } + #[doc = "Bit 3 - Source transaction complete"] + #[inline(always)] + pub fn src_transcomp(&mut self) -> SRC_TRANSCOMP_W { + SRC_TRANSCOMP_W { w: self } + } + #[doc = "Bit 4 - Destination transaction complete"] + #[inline(always)] + pub fn dst_transcomp(&mut self) -> DST_TRANSCOMP_W { + DST_TRANSCOMP_W { w: self } + } + #[doc = "Bit 5 - Source Decode Error"] + #[inline(always)] + pub fn src_dec_err(&mut self) -> SRC_DEC_ERR_W { + SRC_DEC_ERR_W { w: self } + } + #[doc = "Bit 6 - Destination Decode Error"] + #[inline(always)] + pub fn dst_dec_err(&mut self) -> DST_DEC_ERR_W { + DST_DEC_ERR_W { w: self } + } + #[doc = "Bit 7 - Source Slave Error"] + #[inline(always)] + pub fn src_slv_err(&mut self) -> SRC_SLV_ERR_W { + SRC_SLV_ERR_W { w: self } + } + #[doc = "Bit 8 - Destination Slave Error"] + #[inline(always)] + pub fn dst_slv_err(&mut self) -> DST_SLV_ERR_W { + DST_SLV_ERR_W { w: self } + } + #[doc = "Bit 9 - LLI Read Decode Error Status Enable"] + #[inline(always)] + pub fn lli_rd_dec_err(&mut self) -> LLI_RD_DEC_ERR_W { + LLI_RD_DEC_ERR_W { w: self } + } + #[doc = "Bit 10 - LLI WRITE Decode Error"] + #[inline(always)] + pub fn lli_wr_dec_err(&mut self) -> LLI_WR_DEC_ERR_W { + LLI_WR_DEC_ERR_W { w: self } + } + #[doc = "Bit 11 - LLI Read Slave Error"] + #[inline(always)] + pub fn lli_rd_slv_err(&mut self) -> LLI_RD_SLV_ERR_W { + LLI_RD_SLV_ERR_W { w: self } + } + #[doc = "Bit 12 - LLI WRITE Slave Error"] + #[inline(always)] + pub fn lli_wr_slv_err(&mut self) -> LLI_WR_SLV_ERR_W { + LLI_WR_SLV_ERR_W { w: self } + } + } + } + #[doc = "Interrupt Signal Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intsignal_en](intsignal_en) module"] + pub type INTSIGNAL_EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTSIGNAL_EN; + #[doc = "`read()` method returns [intsignal_en::R](intsignal_en::R) reader structure"] + impl crate::Readable for INTSIGNAL_EN {} + #[doc = "`write(|w| ..)` method takes [intsignal_en::W](intsignal_en::W) writer structure"] + impl crate::Writable for INTSIGNAL_EN {} + #[doc = "Interrupt Signal Enable Register"] + pub mod intsignal_en { + #[doc = "Reader of register intsignal_en"] + pub type R = crate::R; + #[doc = "Writer for register intsignal_en"] + pub type W = crate::W; + #[doc = "Register intsignal_en `reset()`'s with value 0"] + impl crate::ResetValue for super::INTSIGNAL_EN { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `block_tfr_done`"] + pub type BLOCK_TFR_DONE_R = crate::R; + #[doc = "Write proxy for field `block_tfr_done`"] + pub struct BLOCK_TFR_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> BLOCK_TFR_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `tfr_done`"] + pub type TFR_DONE_R = crate::R; + #[doc = "Write proxy for field `tfr_done`"] + pub struct TFR_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> TFR_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `src_transcomp`"] + pub type SRC_TRANSCOMP_R = crate::R; + #[doc = "Write proxy for field `src_transcomp`"] + pub struct SRC_TRANSCOMP_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_TRANSCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `dst_transcomp`"] + pub type DST_TRANSCOMP_R = crate::R; + #[doc = "Write proxy for field `dst_transcomp`"] + pub struct DST_TRANSCOMP_W<'a> { + w: &'a mut W, + } + impl<'a> DST_TRANSCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u64) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `src_dec_err`"] + pub type SRC_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `src_dec_err`"] + pub struct SRC_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u64) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `dst_dec_err`"] + pub type DST_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `dst_dec_err`"] + pub struct DST_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> DST_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u64) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `src_slv_err`"] + pub type SRC_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `src_slv_err`"] + pub struct SRC_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u64) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `dst_slv_err`"] + pub type DST_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `dst_slv_err`"] + pub struct DST_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> DST_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u64) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `lli_rd_dec_err`"] + pub type LLI_RD_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_rd_dec_err`"] + pub struct LLI_RD_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_RD_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u64) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `lli_wr_dec_err`"] + pub type LLI_WR_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_wr_dec_err`"] + pub struct LLI_WR_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_WR_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u64) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `lli_rd_slv_err`"] + pub type LLI_RD_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_rd_slv_err`"] + pub struct LLI_RD_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_RD_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u64) & 0x01) << 11); + self.w + } + } + #[doc = "Reader of field `lli_wr_slv_err`"] + pub type LLI_WR_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_wr_slv_err`"] + pub struct LLI_WR_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_WR_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u64) & 0x01) << 12); + self.w + } + } + impl R { + #[doc = "Bit 0 - Block transfer done"] + #[inline(always)] + pub fn block_tfr_done(&self) -> BLOCK_TFR_DONE_R { + BLOCK_TFR_DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer done"] + #[inline(always)] + pub fn tfr_done(&self) -> TFR_DONE_R { + TFR_DONE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Source transaction complete"] + #[inline(always)] + pub fn src_transcomp(&self) -> SRC_TRANSCOMP_R { + SRC_TRANSCOMP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Destination transaction complete"] + #[inline(always)] + pub fn dst_transcomp(&self) -> DST_TRANSCOMP_R { + DST_TRANSCOMP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Source Decode Error"] + #[inline(always)] + pub fn src_dec_err(&self) -> SRC_DEC_ERR_R { + SRC_DEC_ERR_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Destination Decode Error"] + #[inline(always)] + pub fn dst_dec_err(&self) -> DST_DEC_ERR_R { + DST_DEC_ERR_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Source Slave Error"] + #[inline(always)] + pub fn src_slv_err(&self) -> SRC_SLV_ERR_R { + SRC_SLV_ERR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Destination Slave Error"] + #[inline(always)] + pub fn dst_slv_err(&self) -> DST_SLV_ERR_R { + DST_SLV_ERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - LLI Read Decode Error Status Enable"] + #[inline(always)] + pub fn lli_rd_dec_err(&self) -> LLI_RD_DEC_ERR_R { + LLI_RD_DEC_ERR_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - LLI WRITE Decode Error"] + #[inline(always)] + pub fn lli_wr_dec_err(&self) -> LLI_WR_DEC_ERR_R { + LLI_WR_DEC_ERR_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - LLI Read Slave Error"] + #[inline(always)] + pub fn lli_rd_slv_err(&self) -> LLI_RD_SLV_ERR_R { + LLI_RD_SLV_ERR_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - LLI WRITE Slave Error"] + #[inline(always)] + pub fn lli_wr_slv_err(&self) -> LLI_WR_SLV_ERR_R { + LLI_WR_SLV_ERR_R::new(((self.bits >> 12) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Block transfer done"] + #[inline(always)] + pub fn block_tfr_done(&mut self) -> BLOCK_TFR_DONE_W { + BLOCK_TFR_DONE_W { w: self } + } + #[doc = "Bit 1 - Transfer done"] + #[inline(always)] + pub fn tfr_done(&mut self) -> TFR_DONE_W { + TFR_DONE_W { w: self } + } + #[doc = "Bit 3 - Source transaction complete"] + #[inline(always)] + pub fn src_transcomp(&mut self) -> SRC_TRANSCOMP_W { + SRC_TRANSCOMP_W { w: self } + } + #[doc = "Bit 4 - Destination transaction complete"] + #[inline(always)] + pub fn dst_transcomp(&mut self) -> DST_TRANSCOMP_W { + DST_TRANSCOMP_W { w: self } + } + #[doc = "Bit 5 - Source Decode Error"] + #[inline(always)] + pub fn src_dec_err(&mut self) -> SRC_DEC_ERR_W { + SRC_DEC_ERR_W { w: self } + } + #[doc = "Bit 6 - Destination Decode Error"] + #[inline(always)] + pub fn dst_dec_err(&mut self) -> DST_DEC_ERR_W { + DST_DEC_ERR_W { w: self } + } + #[doc = "Bit 7 - Source Slave Error"] + #[inline(always)] + pub fn src_slv_err(&mut self) -> SRC_SLV_ERR_W { + SRC_SLV_ERR_W { w: self } + } + #[doc = "Bit 8 - Destination Slave Error"] + #[inline(always)] + pub fn dst_slv_err(&mut self) -> DST_SLV_ERR_W { + DST_SLV_ERR_W { w: self } + } + #[doc = "Bit 9 - LLI Read Decode Error Status Enable"] + #[inline(always)] + pub fn lli_rd_dec_err(&mut self) -> LLI_RD_DEC_ERR_W { + LLI_RD_DEC_ERR_W { w: self } + } + #[doc = "Bit 10 - LLI WRITE Decode Error"] + #[inline(always)] + pub fn lli_wr_dec_err(&mut self) -> LLI_WR_DEC_ERR_W { + LLI_WR_DEC_ERR_W { w: self } + } + #[doc = "Bit 11 - LLI Read Slave Error"] + #[inline(always)] + pub fn lli_rd_slv_err(&mut self) -> LLI_RD_SLV_ERR_W { + LLI_RD_SLV_ERR_W { w: self } + } + #[doc = "Bit 12 - LLI WRITE Slave Error"] + #[inline(always)] + pub fn lli_wr_slv_err(&mut self) -> LLI_WR_SLV_ERR_W { + LLI_WR_SLV_ERR_W { w: self } + } + } + } + #[doc = "Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intclear](intclear) module"] + pub type INTCLEAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTCLEAR; + #[doc = "`read()` method returns [intclear::R](intclear::R) reader structure"] + impl crate::Readable for INTCLEAR {} + #[doc = "`write(|w| ..)` method takes [intclear::W](intclear::W) writer structure"] + impl crate::Writable for INTCLEAR {} + #[doc = "Interrupt Clear Register"] + pub mod intclear { + #[doc = "Reader of register intclear"] + pub type R = crate::R; + #[doc = "Writer for register intclear"] + pub type W = crate::W; + #[doc = "Register intclear `reset()`'s with value 0"] + impl crate::ResetValue for super::INTCLEAR { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `block_tfr_done`"] + pub type BLOCK_TFR_DONE_R = crate::R; + #[doc = "Write proxy for field `block_tfr_done`"] + pub struct BLOCK_TFR_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> BLOCK_TFR_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `tfr_done`"] + pub type TFR_DONE_R = crate::R; + #[doc = "Write proxy for field `tfr_done`"] + pub struct TFR_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> TFR_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `src_transcomp`"] + pub type SRC_TRANSCOMP_R = crate::R; + #[doc = "Write proxy for field `src_transcomp`"] + pub struct SRC_TRANSCOMP_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_TRANSCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `dst_transcomp`"] + pub type DST_TRANSCOMP_R = crate::R; + #[doc = "Write proxy for field `dst_transcomp`"] + pub struct DST_TRANSCOMP_W<'a> { + w: &'a mut W, + } + impl<'a> DST_TRANSCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u64) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `src_dec_err`"] + pub type SRC_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `src_dec_err`"] + pub struct SRC_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u64) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `dst_dec_err`"] + pub type DST_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `dst_dec_err`"] + pub struct DST_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> DST_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u64) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `src_slv_err`"] + pub type SRC_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `src_slv_err`"] + pub struct SRC_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u64) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `dst_slv_err`"] + pub type DST_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `dst_slv_err`"] + pub struct DST_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> DST_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u64) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `lli_rd_dec_err`"] + pub type LLI_RD_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_rd_dec_err`"] + pub struct LLI_RD_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_RD_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u64) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `lli_wr_dec_err`"] + pub type LLI_WR_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_wr_dec_err`"] + pub struct LLI_WR_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_WR_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u64) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `lli_rd_slv_err`"] + pub type LLI_RD_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_rd_slv_err`"] + pub struct LLI_RD_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_RD_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u64) & 0x01) << 11); + self.w + } + } + #[doc = "Reader of field `lli_wr_slv_err`"] + pub type LLI_WR_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_wr_slv_err`"] + pub struct LLI_WR_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_WR_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u64) & 0x01) << 12); + self.w + } + } + impl R { + #[doc = "Bit 0 - Block transfer done"] + #[inline(always)] + pub fn block_tfr_done(&self) -> BLOCK_TFR_DONE_R { + BLOCK_TFR_DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer done"] + #[inline(always)] + pub fn tfr_done(&self) -> TFR_DONE_R { + TFR_DONE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Source transaction complete"] + #[inline(always)] + pub fn src_transcomp(&self) -> SRC_TRANSCOMP_R { + SRC_TRANSCOMP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Destination transaction complete"] + #[inline(always)] + pub fn dst_transcomp(&self) -> DST_TRANSCOMP_R { + DST_TRANSCOMP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Source Decode Error"] + #[inline(always)] + pub fn src_dec_err(&self) -> SRC_DEC_ERR_R { + SRC_DEC_ERR_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Destination Decode Error"] + #[inline(always)] + pub fn dst_dec_err(&self) -> DST_DEC_ERR_R { + DST_DEC_ERR_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Source Slave Error"] + #[inline(always)] + pub fn src_slv_err(&self) -> SRC_SLV_ERR_R { + SRC_SLV_ERR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Destination Slave Error"] + #[inline(always)] + pub fn dst_slv_err(&self) -> DST_SLV_ERR_R { + DST_SLV_ERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - LLI Read Decode Error Status Enable"] + #[inline(always)] + pub fn lli_rd_dec_err(&self) -> LLI_RD_DEC_ERR_R { + LLI_RD_DEC_ERR_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - LLI WRITE Decode Error"] + #[inline(always)] + pub fn lli_wr_dec_err(&self) -> LLI_WR_DEC_ERR_R { + LLI_WR_DEC_ERR_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - LLI Read Slave Error"] + #[inline(always)] + pub fn lli_rd_slv_err(&self) -> LLI_RD_SLV_ERR_R { + LLI_RD_SLV_ERR_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - LLI WRITE Slave Error"] + #[inline(always)] + pub fn lli_wr_slv_err(&self) -> LLI_WR_SLV_ERR_R { + LLI_WR_SLV_ERR_R::new(((self.bits >> 12) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Block transfer done"] + #[inline(always)] + pub fn block_tfr_done(&mut self) -> BLOCK_TFR_DONE_W { + BLOCK_TFR_DONE_W { w: self } + } + #[doc = "Bit 1 - Transfer done"] + #[inline(always)] + pub fn tfr_done(&mut self) -> TFR_DONE_W { + TFR_DONE_W { w: self } + } + #[doc = "Bit 3 - Source transaction complete"] + #[inline(always)] + pub fn src_transcomp(&mut self) -> SRC_TRANSCOMP_W { + SRC_TRANSCOMP_W { w: self } + } + #[doc = "Bit 4 - Destination transaction complete"] + #[inline(always)] + pub fn dst_transcomp(&mut self) -> DST_TRANSCOMP_W { + DST_TRANSCOMP_W { w: self } + } + #[doc = "Bit 5 - Source Decode Error"] + #[inline(always)] + pub fn src_dec_err(&mut self) -> SRC_DEC_ERR_W { + SRC_DEC_ERR_W { w: self } + } + #[doc = "Bit 6 - Destination Decode Error"] + #[inline(always)] + pub fn dst_dec_err(&mut self) -> DST_DEC_ERR_W { + DST_DEC_ERR_W { w: self } + } + #[doc = "Bit 7 - Source Slave Error"] + #[inline(always)] + pub fn src_slv_err(&mut self) -> SRC_SLV_ERR_W { + SRC_SLV_ERR_W { w: self } + } + #[doc = "Bit 8 - Destination Slave Error"] + #[inline(always)] + pub fn dst_slv_err(&mut self) -> DST_SLV_ERR_W { + DST_SLV_ERR_W { w: self } + } + #[doc = "Bit 9 - LLI Read Decode Error Status Enable"] + #[inline(always)] + pub fn lli_rd_dec_err(&mut self) -> LLI_RD_DEC_ERR_W { + LLI_RD_DEC_ERR_W { w: self } + } + #[doc = "Bit 10 - LLI WRITE Decode Error"] + #[inline(always)] + pub fn lli_wr_dec_err(&mut self) -> LLI_WR_DEC_ERR_W { + LLI_WR_DEC_ERR_W { w: self } + } + #[doc = "Bit 11 - LLI Read Slave Error"] + #[inline(always)] + pub fn lli_rd_slv_err(&mut self) -> LLI_RD_SLV_ERR_W { + LLI_RD_SLV_ERR_W { w: self } + } + #[doc = "Bit 12 - LLI WRITE Slave Error"] + #[inline(always)] + pub fn lli_wr_slv_err(&mut self) -> LLI_WR_SLV_ERR_W { + LLI_WR_SLV_ERR_W { w: self } + } + } + } + #[doc = "Padding to make structure size 256 bytes so that channels\\[\\] +is an array\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_reserved](_reserved) module"] + pub type _RESERVED = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct __RESERVED; + #[doc = "`read()` method returns [_reserved::R](_reserved::R) reader structure"] + impl crate::Readable for _RESERVED {} + #[doc = "`write(|w| ..)` method takes [_reserved::W](_reserved::W) writer structure"] + impl crate::Writable for _RESERVED {} + #[doc = "Padding to make structure size 256 bytes so that channels\\[\\] +is an array"] + pub mod _reserved { + #[doc = "Reader of register _reserved"] + pub type R = crate::R; + #[doc = "Writer for register _reserved"] + pub type W = crate::W; + #[doc = "Register _reserved `reset()`'s with value 0"] + impl crate::ResetValue for super::_RESERVED { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + } + #[doc = "ID Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id](id) module"] + pub type ID = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ID; + #[doc = "`read()` method returns [id::R](id::R) reader structure"] + impl crate::Readable for ID {} + #[doc = "`write(|w| ..)` method takes [id::W](id::W) writer structure"] + impl crate::Writable for ID {} + #[doc = "ID Register"] + pub mod id { + #[doc = "Reader of register id"] + pub type R = crate::R; + #[doc = "Writer for register id"] + pub type W = crate::W; + #[doc = "Register id `reset()`'s with value 0"] + impl crate::ResetValue for super::ID { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "COMPVER Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [compver](compver) module"] + pub type COMPVER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMPVER; + #[doc = "`read()` method returns [compver::R](compver::R) reader structure"] + impl crate::Readable for COMPVER {} + #[doc = "`write(|w| ..)` method takes [compver::W](compver::W) writer structure"] + impl crate::Writable for COMPVER {} + #[doc = "COMPVER Register"] + pub mod compver { + #[doc = "Reader of register compver"] + pub type R = crate::R; + #[doc = "Writer for register compver"] + pub type W = crate::W; + #[doc = "Register compver `reset()`'s with value 0"] + impl crate::ResetValue for super::COMPVER { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Configure Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] + pub type CFG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CFG; + #[doc = "`read()` method returns [cfg::R](cfg::R) reader structure"] + impl crate::Readable for CFG {} + #[doc = "`write(|w| ..)` method takes [cfg::W](cfg::W) writer structure"] + impl crate::Writable for CFG {} + #[doc = "Configure Register"] + pub mod cfg { + #[doc = "Reader of register cfg"] + pub type R = crate::R; + #[doc = "Writer for register cfg"] + pub type W = crate::W; + #[doc = "Register cfg `reset()`'s with value 0"] + impl crate::ResetValue for super::CFG { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `dmac_en`"] + pub type DMAC_EN_R = crate::R; + #[doc = "Write proxy for field `dmac_en`"] + pub struct DMAC_EN_W<'a> { + w: &'a mut W, + } + impl<'a> DMAC_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `int_en`"] + pub type INT_EN_R = crate::R; + #[doc = "Write proxy for field `int_en`"] + pub struct INT_EN_W<'a> { + w: &'a mut W, + } + impl<'a> INT_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + impl R { + #[doc = "Bit 0 - Enable DMAC"] + #[inline(always)] + pub fn dmac_en(&self) -> DMAC_EN_R { + DMAC_EN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Globally enable interrupt generation"] + #[inline(always)] + pub fn int_en(&self) -> INT_EN_R { + INT_EN_R::new(((self.bits >> 1) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Enable DMAC"] + #[inline(always)] + pub fn dmac_en(&mut self) -> DMAC_EN_W { + DMAC_EN_W { w: self } + } + #[doc = "Bit 1 - Globally enable interrupt generation"] + #[inline(always)] + pub fn int_en(&mut self) -> INT_EN_W { + INT_EN_W { w: self } + } + } + } + #[doc = "Channel Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chen](chen) module"] + pub type CHEN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CHEN; + #[doc = "`read()` method returns [chen::R](chen::R) reader structure"] + impl crate::Readable for CHEN {} + #[doc = "`write(|w| ..)` method takes [chen::W](chen::W) writer structure"] + impl crate::Writable for CHEN {} + #[doc = "Channel Enable Register"] + pub mod chen { + #[doc = "Reader of register chen"] + pub type R = crate::R; + #[doc = "Writer for register chen"] + pub type W = crate::W; + #[doc = "Register chen `reset()`'s with value 0"] + impl crate::ResetValue for super::CHEN { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `ch(1-6)_en`"] + pub type CH_EN_R = crate::R; + #[doc = "Write proxy for fields `ch(1-6)_en`"] + pub struct CH_EN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> CH_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u64) & 0x01) << self.offset); + self.w + } + } + #[doc = "Reader of fields `ch(1-6)_en_we`"] + pub type CH_EN_WE_R = crate::R; + #[doc = "Write proxy for fields `ch(1-6)_en_we`"] + pub struct CH_EN_WE_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> CH_EN_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u64) & 0x01) << self.offset); + self.w + } + } + #[doc = "Reader of fields `ch(1-6)_susp`"] + pub type CH_SUSP_R = crate::R; + #[doc = "Write proxy for fields `ch(1-6)_susp`"] + pub struct CH_SUSP_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> CH_SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u64) & 0x01) << self.offset); + self.w + } + } + #[doc = "Reader of fields `ch(1-6)_susp_we`"] + pub type CH_SUSP_WE_R = crate::R; + #[doc = "Write proxy for fields `ch(1-6)_susp_we`"] + pub struct CH_SUSP_WE_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> CH_SUSP_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u64) & 0x01) << self.offset); + self.w + } + } + #[doc = "Reader of fields `ch(1-6)_abort`"] + pub type CH_ABORT_R = crate::R; + #[doc = "Write proxy for fields `ch(1-6)_abort`"] + pub struct CH_ABORT_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> CH_ABORT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u64) & 0x01) << self.offset); + self.w + } + } + #[doc = "Reader of fields `ch(1-6)_abort_we`"] + pub type CH_ABORT_WE_R = crate::R; + #[doc = "Write proxy for fields `ch(1-6)_abort_we`"] + pub struct CH_ABORT_WE_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> CH_ABORT_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u64) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = "Enable channel (1-6)"] + #[inline(always)] + pub unsafe fn ch_en(&self, n: usize) -> CH_EN_R { + CH_EN_R::new(((self.bits >> n - 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Enable channel 1"] + #[inline(always)] + pub fn ch1_en(&self) -> CH_EN_R { + CH_EN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable channel 2"] + #[inline(always)] + pub fn ch2_en(&self) -> CH_EN_R { + CH_EN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Enable channel 3"] + #[inline(always)] + pub fn ch3_en(&self) -> CH_EN_R { + CH_EN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Enable channel 4"] + #[inline(always)] + pub fn ch4_en(&self) -> CH_EN_R { + CH_EN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Enable channel 5"] + #[inline(always)] + pub fn ch5_en(&self) -> CH_EN_R { + CH_EN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Enable channel 6"] + #[inline(always)] + pub fn ch6_en(&self) -> CH_EN_R { + CH_EN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Write enable channel (1-6)"] + #[inline(always)] + pub unsafe fn ch_en_we(&self, n: usize) -> CH_EN_WE_R { + CH_EN_WE_R::new(((self.bits >> n - 1 + 8) & 0x01) != 0) + } + #[doc = "Bit 8 - Write enable channel 1"] + #[inline(always)] + pub fn ch1_en_we(&self) -> CH_EN_WE_R { + CH_EN_WE_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Write enable channel 2"] + #[inline(always)] + pub fn ch2_en_we(&self) -> CH_EN_WE_R { + CH_EN_WE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Write enable channel 3"] + #[inline(always)] + pub fn ch3_en_we(&self) -> CH_EN_WE_R { + CH_EN_WE_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Write enable channel 4"] + #[inline(always)] + pub fn ch4_en_we(&self) -> CH_EN_WE_R { + CH_EN_WE_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Write enable channel 5"] + #[inline(always)] + pub fn ch5_en_we(&self) -> CH_EN_WE_R { + CH_EN_WE_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Write enable channel 6"] + #[inline(always)] + pub fn ch6_en_we(&self) -> CH_EN_WE_R { + CH_EN_WE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Suspend request channel (1-6)"] + #[inline(always)] + pub unsafe fn ch_susp(&self, n: usize) -> CH_SUSP_R { + CH_SUSP_R::new(((self.bits >> n - 1 + 16) & 0x01) != 0) + } + #[doc = "Bit 16 - Suspend request channel 1"] + #[inline(always)] + pub fn ch1_susp(&self) -> CH_SUSP_R { + CH_SUSP_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Suspend request channel 2"] + #[inline(always)] + pub fn ch2_susp(&self) -> CH_SUSP_R { + CH_SUSP_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Suspend request channel 3"] + #[inline(always)] + pub fn ch3_susp(&self) -> CH_SUSP_R { + CH_SUSP_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Suspend request channel 4"] + #[inline(always)] + pub fn ch4_susp(&self) -> CH_SUSP_R { + CH_SUSP_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Suspend request channel 5"] + #[inline(always)] + pub fn ch5_susp(&self) -> CH_SUSP_R { + CH_SUSP_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Suspend request channel 6"] + #[inline(always)] + pub fn ch6_susp(&self) -> CH_SUSP_R { + CH_SUSP_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Enable write to ch(1-6)_susp bit"] + #[inline(always)] + pub unsafe fn ch_susp_we(&self, n: usize) -> CH_SUSP_WE_R { + CH_SUSP_WE_R::new(((self.bits >> n - 1 + 24) & 0x01) != 0) + } + #[doc = "Bit 24 - Enable write to ch1_susp bit"] + #[inline(always)] + pub fn ch1_susp_we(&self) -> CH_SUSP_WE_R { + CH_SUSP_WE_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Enable write to ch2_susp bit"] + #[inline(always)] + pub fn ch2_susp_we(&self) -> CH_SUSP_WE_R { + CH_SUSP_WE_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Enable write to ch3_susp bit"] + #[inline(always)] + pub fn ch3_susp_we(&self) -> CH_SUSP_WE_R { + CH_SUSP_WE_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Enable write to ch4_susp bit"] + #[inline(always)] + pub fn ch4_susp_we(&self) -> CH_SUSP_WE_R { + CH_SUSP_WE_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Enable write to ch5_susp bit"] + #[inline(always)] + pub fn ch5_susp_we(&self) -> CH_SUSP_WE_R { + CH_SUSP_WE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Enable write to ch6_susp bit"] + #[inline(always)] + pub fn ch6_susp_we(&self) -> CH_SUSP_WE_R { + CH_SUSP_WE_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Abort request channel (1-6)"] + #[inline(always)] + pub unsafe fn ch_abort(&self, n: usize) -> CH_ABORT_R { + CH_ABORT_R::new(((self.bits >> n - 1 + 32) & 0x01) != 0) + } + #[doc = "Bit 32 - Abort request channel 1"] + #[inline(always)] + pub fn ch1_abort(&self) -> CH_ABORT_R { + CH_ABORT_R::new(((self.bits >> 32) & 0x01) != 0) + } + #[doc = "Bit 33 - Abort request channel 2"] + #[inline(always)] + pub fn ch2_abort(&self) -> CH_ABORT_R { + CH_ABORT_R::new(((self.bits >> 33) & 0x01) != 0) + } + #[doc = "Bit 34 - Abort request channel 3"] + #[inline(always)] + pub fn ch3_abort(&self) -> CH_ABORT_R { + CH_ABORT_R::new(((self.bits >> 34) & 0x01) != 0) + } + #[doc = "Bit 35 - Abort request channel 4"] + #[inline(always)] + pub fn ch4_abort(&self) -> CH_ABORT_R { + CH_ABORT_R::new(((self.bits >> 35) & 0x01) != 0) + } + #[doc = "Bit 36 - Abort request channel 5"] + #[inline(always)] + pub fn ch5_abort(&self) -> CH_ABORT_R { + CH_ABORT_R::new(((self.bits >> 36) & 0x01) != 0) + } + #[doc = "Bit 37 - Abort request channel 6"] + #[inline(always)] + pub fn ch6_abort(&self) -> CH_ABORT_R { + CH_ABORT_R::new(((self.bits >> 37) & 0x01) != 0) + } + #[doc = "Enable write to ch(1-6)_abort bit"] + #[inline(always)] + pub unsafe fn ch_abort_we(&self, n: usize) -> CH_ABORT_WE_R { + CH_ABORT_WE_R::new(((self.bits >> n - 1 + 40) & 0x01) != 0) + } + #[doc = "Bit 40 - Enable write to ch1_abort bit"] + #[inline(always)] + pub fn ch1_abort_we(&self) -> CH_ABORT_WE_R { + CH_ABORT_WE_R::new(((self.bits >> 40) & 0x01) != 0) + } + #[doc = "Bit 41 - Enable write to ch2_abort bit"] + #[inline(always)] + pub fn ch2_abort_we(&self) -> CH_ABORT_WE_R { + CH_ABORT_WE_R::new(((self.bits >> 41) & 0x01) != 0) + } + #[doc = "Bit 42 - Enable write to ch3_abort bit"] + #[inline(always)] + pub fn ch3_abort_we(&self) -> CH_ABORT_WE_R { + CH_ABORT_WE_R::new(((self.bits >> 42) & 0x01) != 0) + } + #[doc = "Bit 43 - Enable write to ch4_abort bit"] + #[inline(always)] + pub fn ch4_abort_we(&self) -> CH_ABORT_WE_R { + CH_ABORT_WE_R::new(((self.bits >> 43) & 0x01) != 0) + } + #[doc = "Bit 44 - Enable write to ch5_abort bit"] + #[inline(always)] + pub fn ch5_abort_we(&self) -> CH_ABORT_WE_R { + CH_ABORT_WE_R::new(((self.bits >> 44) & 0x01) != 0) + } + #[doc = "Bit 45 - Enable write to ch6_abort bit"] + #[inline(always)] + pub fn ch6_abort_we(&self) -> CH_ABORT_WE_R { + CH_ABORT_WE_R::new(((self.bits >> 45) & 0x01) != 0) + } + } + impl W { + #[doc = "Enable channel (1-6)"] + #[inline(always)] + pub unsafe fn ch_en(&mut self, n: usize) -> CH_EN_W { + CH_EN_W { + w: self, + offset: n - 1, + } + } + #[doc = "Bit 0 - Enable channel 1"] + #[inline(always)] + pub fn ch1_en(&mut self) -> CH_EN_W { + CH_EN_W { w: self, offset: 0 } + } + #[doc = "Bit 1 - Enable channel 2"] + #[inline(always)] + pub fn ch2_en(&mut self) -> CH_EN_W { + CH_EN_W { w: self, offset: 1 } + } + #[doc = "Bit 2 - Enable channel 3"] + #[inline(always)] + pub fn ch3_en(&mut self) -> CH_EN_W { + CH_EN_W { w: self, offset: 2 } + } + #[doc = "Bit 3 - Enable channel 4"] + #[inline(always)] + pub fn ch4_en(&mut self) -> CH_EN_W { + CH_EN_W { w: self, offset: 3 } + } + #[doc = "Bit 4 - Enable channel 5"] + #[inline(always)] + pub fn ch5_en(&mut self) -> CH_EN_W { + CH_EN_W { w: self, offset: 4 } + } + #[doc = "Bit 5 - Enable channel 6"] + #[inline(always)] + pub fn ch6_en(&mut self) -> CH_EN_W { + CH_EN_W { w: self, offset: 5 } + } + #[doc = "Write enable channel (1-6)"] + #[inline(always)] + pub unsafe fn ch_en_we(&mut self, n: usize) -> CH_EN_WE_W { + CH_EN_WE_W { + w: self, + offset: n - 1 + 8, + } + } + #[doc = "Bit 8 - Write enable channel 1"] + #[inline(always)] + pub fn ch1_en_we(&mut self) -> CH_EN_WE_W { + CH_EN_WE_W { w: self, offset: 8 } + } + #[doc = "Bit 9 - Write enable channel 2"] + #[inline(always)] + pub fn ch2_en_we(&mut self) -> CH_EN_WE_W { + CH_EN_WE_W { w: self, offset: 9 } + } + #[doc = "Bit 10 - Write enable channel 3"] + #[inline(always)] + pub fn ch3_en_we(&mut self) -> CH_EN_WE_W { + CH_EN_WE_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11 - Write enable channel 4"] + #[inline(always)] + pub fn ch4_en_we(&mut self) -> CH_EN_WE_W { + CH_EN_WE_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12 - Write enable channel 5"] + #[inline(always)] + pub fn ch5_en_we(&mut self) -> CH_EN_WE_W { + CH_EN_WE_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13 - Write enable channel 6"] + #[inline(always)] + pub fn ch6_en_we(&mut self) -> CH_EN_WE_W { + CH_EN_WE_W { + w: self, + offset: 13, + } + } + #[doc = "Suspend request channel (1-6)"] + #[inline(always)] + pub unsafe fn ch_susp(&mut self, n: usize) -> CH_SUSP_W { + CH_SUSP_W { + w: self, + offset: n - 1 + 16, + } + } + #[doc = "Bit 16 - Suspend request channel 1"] + #[inline(always)] + pub fn ch1_susp(&mut self) -> CH_SUSP_W { + CH_SUSP_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17 - Suspend request channel 2"] + #[inline(always)] + pub fn ch2_susp(&mut self) -> CH_SUSP_W { + CH_SUSP_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18 - Suspend request channel 3"] + #[inline(always)] + pub fn ch3_susp(&mut self) -> CH_SUSP_W { + CH_SUSP_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19 - Suspend request channel 4"] + #[inline(always)] + pub fn ch4_susp(&mut self) -> CH_SUSP_W { + CH_SUSP_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20 - Suspend request channel 5"] + #[inline(always)] + pub fn ch5_susp(&mut self) -> CH_SUSP_W { + CH_SUSP_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21 - Suspend request channel 6"] + #[inline(always)] + pub fn ch6_susp(&mut self) -> CH_SUSP_W { + CH_SUSP_W { + w: self, + offset: 21, + } + } + #[doc = "Enable write to ch(1-6)_susp bit"] + #[inline(always)] + pub unsafe fn ch_susp_we(&mut self, n: usize) -> CH_SUSP_WE_W { + CH_SUSP_WE_W { + w: self, + offset: n - 1 + 24, + } + } + #[doc = "Bit 24 - Enable write to ch1_susp bit"] + #[inline(always)] + pub fn ch1_susp_we(&mut self) -> CH_SUSP_WE_W { + CH_SUSP_WE_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25 - Enable write to ch2_susp bit"] + #[inline(always)] + pub fn ch2_susp_we(&mut self) -> CH_SUSP_WE_W { + CH_SUSP_WE_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26 - Enable write to ch3_susp bit"] + #[inline(always)] + pub fn ch3_susp_we(&mut self) -> CH_SUSP_WE_W { + CH_SUSP_WE_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27 - Enable write to ch4_susp bit"] + #[inline(always)] + pub fn ch4_susp_we(&mut self) -> CH_SUSP_WE_W { + CH_SUSP_WE_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28 - Enable write to ch5_susp bit"] + #[inline(always)] + pub fn ch5_susp_we(&mut self) -> CH_SUSP_WE_W { + CH_SUSP_WE_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29 - Enable write to ch6_susp bit"] + #[inline(always)] + pub fn ch6_susp_we(&mut self) -> CH_SUSP_WE_W { + CH_SUSP_WE_W { + w: self, + offset: 29, + } + } + #[doc = "Abort request channel (1-6)"] + #[inline(always)] + pub unsafe fn ch_abort(&mut self, n: usize) -> CH_ABORT_W { + CH_ABORT_W { + w: self, + offset: n - 1 + 32, + } + } + #[doc = "Bit 32 - Abort request channel 1"] + #[inline(always)] + pub fn ch1_abort(&mut self) -> CH_ABORT_W { + CH_ABORT_W { + w: self, + offset: 32, + } + } + #[doc = "Bit 33 - Abort request channel 2"] + #[inline(always)] + pub fn ch2_abort(&mut self) -> CH_ABORT_W { + CH_ABORT_W { + w: self, + offset: 33, + } + } + #[doc = "Bit 34 - Abort request channel 3"] + #[inline(always)] + pub fn ch3_abort(&mut self) -> CH_ABORT_W { + CH_ABORT_W { + w: self, + offset: 34, + } + } + #[doc = "Bit 35 - Abort request channel 4"] + #[inline(always)] + pub fn ch4_abort(&mut self) -> CH_ABORT_W { + CH_ABORT_W { + w: self, + offset: 35, + } + } + #[doc = "Bit 36 - Abort request channel 5"] + #[inline(always)] + pub fn ch5_abort(&mut self) -> CH_ABORT_W { + CH_ABORT_W { + w: self, + offset: 36, + } + } + #[doc = "Bit 37 - Abort request channel 6"] + #[inline(always)] + pub fn ch6_abort(&mut self) -> CH_ABORT_W { + CH_ABORT_W { + w: self, + offset: 37, + } + } + #[doc = "Enable write to ch(1-6)_abort bit"] + #[inline(always)] + pub unsafe fn ch_abort_we(&mut self, n: usize) -> CH_ABORT_WE_W { + CH_ABORT_WE_W { + w: self, + offset: n - 1 + 40, + } + } + #[doc = "Bit 40 - Enable write to ch1_abort bit"] + #[inline(always)] + pub fn ch1_abort_we(&mut self) -> CH_ABORT_WE_W { + CH_ABORT_WE_W { + w: self, + offset: 40, + } + } + #[doc = "Bit 41 - Enable write to ch2_abort bit"] + #[inline(always)] + pub fn ch2_abort_we(&mut self) -> CH_ABORT_WE_W { + CH_ABORT_WE_W { + w: self, + offset: 41, + } + } + #[doc = "Bit 42 - Enable write to ch3_abort bit"] + #[inline(always)] + pub fn ch3_abort_we(&mut self) -> CH_ABORT_WE_W { + CH_ABORT_WE_W { + w: self, + offset: 42, + } + } + #[doc = "Bit 43 - Enable write to ch4_abort bit"] + #[inline(always)] + pub fn ch4_abort_we(&mut self) -> CH_ABORT_WE_W { + CH_ABORT_WE_W { + w: self, + offset: 43, + } + } + #[doc = "Bit 44 - Enable write to ch5_abort bit"] + #[inline(always)] + pub fn ch5_abort_we(&mut self) -> CH_ABORT_WE_W { + CH_ABORT_WE_W { + w: self, + offset: 44, + } + } + #[doc = "Bit 45 - Enable write to ch6_abort bit"] + #[inline(always)] + pub fn ch6_abort_we(&mut self) -> CH_ABORT_WE_W { + CH_ABORT_WE_W { + w: self, + offset: 45, + } + } + } + } + #[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstatus](intstatus) module"] + pub type INTSTATUS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTSTATUS; + #[doc = "`read()` method returns [intstatus::R](intstatus::R) reader structure"] + impl crate::Readable for INTSTATUS {} + #[doc = "`write(|w| ..)` method takes [intstatus::W](intstatus::W) writer structure"] + impl crate::Writable for INTSTATUS {} + #[doc = "Interrupt Status Register"] + pub mod intstatus { + #[doc = "Reader of register intstatus"] + pub type R = crate::R; + #[doc = "Writer for register intstatus"] + pub type W = crate::W; + #[doc = "Register intstatus `reset()`'s with value 0"] + impl crate::ResetValue for super::INTSTATUS { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `ch(1-6)_intstat`"] + pub type CH_INTSTAT_R = crate::R; + #[doc = "Write proxy for fields `ch(1-6)_intstat`"] + pub struct CH_INTSTAT_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> CH_INTSTAT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u64) & 0x01) << self.offset); + self.w + } + } + #[doc = "Reader of field `commonreg_intstat`"] + pub type COMMONREG_INTSTAT_R = crate::R; + #[doc = "Write proxy for field `commonreg_intstat`"] + pub struct COMMONREG_INTSTAT_W<'a> { + w: &'a mut W, + } + impl<'a> COMMONREG_INTSTAT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u64) & 0x01) << 16); + self.w + } + } + impl R { + #[doc = "Channel (1-6) interrupt bit"] + #[inline(always)] + pub unsafe fn ch_intstat(&self, n: usize) -> CH_INTSTAT_R { + CH_INTSTAT_R::new(((self.bits >> n - 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Channel 1 interrupt bit"] + #[inline(always)] + pub fn ch1_intstat(&self) -> CH_INTSTAT_R { + CH_INTSTAT_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 2 interrupt bit"] + #[inline(always)] + pub fn ch2_intstat(&self) -> CH_INTSTAT_R { + CH_INTSTAT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 3 interrupt bit"] + #[inline(always)] + pub fn ch3_intstat(&self) -> CH_INTSTAT_R { + CH_INTSTAT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 4 interrupt bit"] + #[inline(always)] + pub fn ch4_intstat(&self) -> CH_INTSTAT_R { + CH_INTSTAT_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 5 interrupt bit"] + #[inline(always)] + pub fn ch5_intstat(&self) -> CH_INTSTAT_R { + CH_INTSTAT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 6 interrupt bit"] + #[inline(always)] + pub fn ch6_intstat(&self) -> CH_INTSTAT_R { + CH_INTSTAT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 16 - Common register status bit"] + #[inline(always)] + pub fn commonreg_intstat(&self) -> COMMONREG_INTSTAT_R { + COMMONREG_INTSTAT_R::new(((self.bits >> 16) & 0x01) != 0) + } + } + impl W { + #[doc = "Channel (1-6) interrupt bit"] + #[inline(always)] + pub unsafe fn ch_intstat(&mut self, n: usize) -> CH_INTSTAT_W { + CH_INTSTAT_W { + w: self, + offset: n - 1, + } + } + #[doc = "Bit 0 - Channel 1 interrupt bit"] + #[inline(always)] + pub fn ch1_intstat(&mut self) -> CH_INTSTAT_W { + CH_INTSTAT_W { w: self, offset: 0 } + } + #[doc = "Bit 1 - Channel 2 interrupt bit"] + #[inline(always)] + pub fn ch2_intstat(&mut self) -> CH_INTSTAT_W { + CH_INTSTAT_W { w: self, offset: 1 } + } + #[doc = "Bit 2 - Channel 3 interrupt bit"] + #[inline(always)] + pub fn ch3_intstat(&mut self) -> CH_INTSTAT_W { + CH_INTSTAT_W { w: self, offset: 2 } + } + #[doc = "Bit 3 - Channel 4 interrupt bit"] + #[inline(always)] + pub fn ch4_intstat(&mut self) -> CH_INTSTAT_W { + CH_INTSTAT_W { w: self, offset: 3 } + } + #[doc = "Bit 4 - Channel 5 interrupt bit"] + #[inline(always)] + pub fn ch5_intstat(&mut self) -> CH_INTSTAT_W { + CH_INTSTAT_W { w: self, offset: 4 } + } + #[doc = "Bit 5 - Channel 6 interrupt bit"] + #[inline(always)] + pub fn ch6_intstat(&mut self) -> CH_INTSTAT_W { + CH_INTSTAT_W { w: self, offset: 5 } + } + #[doc = "Bit 16 - Common register status bit"] + #[inline(always)] + pub fn commonreg_intstat(&mut self) -> COMMONREG_INTSTAT_W { + COMMONREG_INTSTAT_W { w: self } + } + } + } + #[doc = "Common Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [com_intclear](com_intclear) module"] + pub type COM_INTCLEAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COM_INTCLEAR; + #[doc = "`read()` method returns [com_intclear::R](com_intclear::R) reader structure"] + impl crate::Readable for COM_INTCLEAR {} + #[doc = "`write(|w| ..)` method takes [com_intclear::W](com_intclear::W) writer structure"] + impl crate::Writable for COM_INTCLEAR {} + #[doc = "Common Interrupt Clear Register"] + pub mod com_intclear { + #[doc = "Reader of register com_intclear"] + pub type R = crate::R; + #[doc = "Writer for register com_intclear"] + pub type W = crate::W; + #[doc = "Register com_intclear `reset()`'s with value 0"] + impl crate::ResetValue for super::COM_INTCLEAR { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `slvif_dec_err`"] + pub type SLVIF_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_dec_err`"] + pub struct SLVIF_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `slvif_wr2ro_err`"] + pub type SLVIF_WR2RO_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_wr2ro_err`"] + pub struct SLVIF_WR2RO_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_WR2RO_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `slvif_rd2wo_err`"] + pub type SLVIF_RD2WO_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_rd2wo_err`"] + pub struct SLVIF_RD2WO_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_RD2WO_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `slvif_wronhold_err`"] + pub type SLVIF_WRONHOLD_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_wronhold_err`"] + pub struct SLVIF_WRONHOLD_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_WRONHOLD_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `slvif_undefinedreg_dec_err`"] + pub type SLVIF_UNDEFINEDREG_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_undefinedreg_dec_err`"] + pub struct SLVIF_UNDEFINEDREG_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_UNDEFINEDREG_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u64) & 0x01) << 8); + self.w + } + } + impl R { + #[doc = "Bit 0 - Clear slvif_dec_err interrupt in com_intstatus"] + #[inline(always)] + pub fn slvif_dec_err(&self) -> SLVIF_DEC_ERR_R { + SLVIF_DEC_ERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Clear slvif_wr2ro_err interrupt in com_intstatus"] + #[inline(always)] + pub fn slvif_wr2ro_err(&self) -> SLVIF_WR2RO_ERR_R { + SLVIF_WR2RO_ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clear slvif_rd2wo_err interrupt in com_intstatus"] + #[inline(always)] + pub fn slvif_rd2wo_err(&self) -> SLVIF_RD2WO_ERR_R { + SLVIF_RD2WO_ERR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear slvif_wronhold_err interrupt in com_intstatus"] + #[inline(always)] + pub fn slvif_wronhold_err(&self) -> SLVIF_WRONHOLD_ERR_R { + SLVIF_WRONHOLD_ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 8 - Clear slvif_undefinedreg_dec_err in com_intstatus"] + #[inline(always)] + pub fn slvif_undefinedreg_dec_err(&self) -> SLVIF_UNDEFINEDREG_DEC_ERR_R { + SLVIF_UNDEFINEDREG_DEC_ERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Clear slvif_dec_err interrupt in com_intstatus"] + #[inline(always)] + pub fn slvif_dec_err(&mut self) -> SLVIF_DEC_ERR_W { + SLVIF_DEC_ERR_W { w: self } + } + #[doc = "Bit 1 - Clear slvif_wr2ro_err interrupt in com_intstatus"] + #[inline(always)] + pub fn slvif_wr2ro_err(&mut self) -> SLVIF_WR2RO_ERR_W { + SLVIF_WR2RO_ERR_W { w: self } + } + #[doc = "Bit 2 - Clear slvif_rd2wo_err interrupt in com_intstatus"] + #[inline(always)] + pub fn slvif_rd2wo_err(&mut self) -> SLVIF_RD2WO_ERR_W { + SLVIF_RD2WO_ERR_W { w: self } + } + #[doc = "Bit 3 - Clear slvif_wronhold_err interrupt in com_intstatus"] + #[inline(always)] + pub fn slvif_wronhold_err(&mut self) -> SLVIF_WRONHOLD_ERR_W { + SLVIF_WRONHOLD_ERR_W { w: self } + } + #[doc = "Bit 8 - Clear slvif_undefinedreg_dec_err in com_intstatus"] + #[inline(always)] + pub fn slvif_undefinedreg_dec_err(&mut self) -> SLVIF_UNDEFINEDREG_DEC_ERR_W { + SLVIF_UNDEFINEDREG_DEC_ERR_W { w: self } + } + } + } + #[doc = "Common Interrupt Status Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [com_intstatus_en](com_intstatus_en) module"] + pub type COM_INTSTATUS_EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COM_INTSTATUS_EN; + #[doc = "`read()` method returns [com_intstatus_en::R](com_intstatus_en::R) reader structure"] + impl crate::Readable for COM_INTSTATUS_EN {} + #[doc = "`write(|w| ..)` method takes [com_intstatus_en::W](com_intstatus_en::W) writer structure"] + impl crate::Writable for COM_INTSTATUS_EN {} + #[doc = "Common Interrupt Status Enable Register"] + pub mod com_intstatus_en { + #[doc = "Reader of register com_intstatus_en"] + pub type R = crate::R; + #[doc = "Writer for register com_intstatus_en"] + pub type W = crate::W; + #[doc = "Register com_intstatus_en `reset()`'s with value 0"] + impl crate::ResetValue for super::COM_INTSTATUS_EN { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `slvif_dec_err`"] + pub type SLVIF_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_dec_err`"] + pub struct SLVIF_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `slvif_wr2ro_err`"] + pub type SLVIF_WR2RO_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_wr2ro_err`"] + pub struct SLVIF_WR2RO_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_WR2RO_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `slvif_rd2wo_err`"] + pub type SLVIF_RD2WO_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_rd2wo_err`"] + pub struct SLVIF_RD2WO_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_RD2WO_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `slvif_wronhold_err`"] + pub type SLVIF_WRONHOLD_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_wronhold_err`"] + pub struct SLVIF_WRONHOLD_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_WRONHOLD_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `slvif_undefinedreg_dec_err`"] + pub type SLVIF_UNDEFINEDREG_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_undefinedreg_dec_err`"] + pub struct SLVIF_UNDEFINEDREG_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_UNDEFINEDREG_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u64) & 0x01) << 8); + self.w + } + } + impl R { + #[doc = "Bit 0 - Slave Interface Common Register Decode Error"] + #[inline(always)] + pub fn slvif_dec_err(&self) -> SLVIF_DEC_ERR_R { + SLVIF_DEC_ERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Interface Common Register Write to Read only Error"] + #[inline(always)] + pub fn slvif_wr2ro_err(&self) -> SLVIF_WR2RO_ERR_R { + SLVIF_WR2RO_ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Slave Interface Common Register Read to Write-only Error"] + #[inline(always)] + pub fn slvif_rd2wo_err(&self) -> SLVIF_RD2WO_ERR_R { + SLVIF_RD2WO_ERR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Interface Common Register Write On Hold Error"] + #[inline(always)] + pub fn slvif_wronhold_err(&self) -> SLVIF_WRONHOLD_ERR_R { + SLVIF_WRONHOLD_ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 8 - Slave Interface Undefined Register Decode Error"] + #[inline(always)] + pub fn slvif_undefinedreg_dec_err(&self) -> SLVIF_UNDEFINEDREG_DEC_ERR_R { + SLVIF_UNDEFINEDREG_DEC_ERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Slave Interface Common Register Decode Error"] + #[inline(always)] + pub fn slvif_dec_err(&mut self) -> SLVIF_DEC_ERR_W { + SLVIF_DEC_ERR_W { w: self } + } + #[doc = "Bit 1 - Slave Interface Common Register Write to Read only Error"] + #[inline(always)] + pub fn slvif_wr2ro_err(&mut self) -> SLVIF_WR2RO_ERR_W { + SLVIF_WR2RO_ERR_W { w: self } + } + #[doc = "Bit 2 - Slave Interface Common Register Read to Write-only Error"] + #[inline(always)] + pub fn slvif_rd2wo_err(&mut self) -> SLVIF_RD2WO_ERR_W { + SLVIF_RD2WO_ERR_W { w: self } + } + #[doc = "Bit 3 - Slave Interface Common Register Write On Hold Error"] + #[inline(always)] + pub fn slvif_wronhold_err(&mut self) -> SLVIF_WRONHOLD_ERR_W { + SLVIF_WRONHOLD_ERR_W { w: self } + } + #[doc = "Bit 8 - Slave Interface Undefined Register Decode Error"] + #[inline(always)] + pub fn slvif_undefinedreg_dec_err(&mut self) -> SLVIF_UNDEFINEDREG_DEC_ERR_W { + SLVIF_UNDEFINEDREG_DEC_ERR_W { w: self } + } + } + } + #[doc = "Common Interrupt Signal Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [com_intsignal_en](com_intsignal_en) module"] + pub type COM_INTSIGNAL_EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COM_INTSIGNAL_EN; + #[doc = "`read()` method returns [com_intsignal_en::R](com_intsignal_en::R) reader structure"] + impl crate::Readable for COM_INTSIGNAL_EN {} + #[doc = "`write(|w| ..)` method takes [com_intsignal_en::W](com_intsignal_en::W) writer structure"] + impl crate::Writable for COM_INTSIGNAL_EN {} + #[doc = "Common Interrupt Signal Enable Register"] + pub mod com_intsignal_en { + #[doc = "Reader of register com_intsignal_en"] + pub type R = crate::R; + #[doc = "Writer for register com_intsignal_en"] + pub type W = crate::W; + #[doc = "Register com_intsignal_en `reset()`'s with value 0"] + impl crate::ResetValue for super::COM_INTSIGNAL_EN { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `slvif_dec_err`"] + pub type SLVIF_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_dec_err`"] + pub struct SLVIF_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `slvif_wr2ro_err`"] + pub type SLVIF_WR2RO_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_wr2ro_err`"] + pub struct SLVIF_WR2RO_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_WR2RO_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `slvif_rd2wo_err`"] + pub type SLVIF_RD2WO_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_rd2wo_err`"] + pub struct SLVIF_RD2WO_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_RD2WO_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `slvif_wronhold_err`"] + pub type SLVIF_WRONHOLD_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_wronhold_err`"] + pub struct SLVIF_WRONHOLD_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_WRONHOLD_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `slvif_undefinedreg_dec_err`"] + pub type SLVIF_UNDEFINEDREG_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_undefinedreg_dec_err`"] + pub struct SLVIF_UNDEFINEDREG_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_UNDEFINEDREG_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u64) & 0x01) << 8); + self.w + } + } + impl R { + #[doc = "Bit 0 - Slave Interface Common Register Decode Error"] + #[inline(always)] + pub fn slvif_dec_err(&self) -> SLVIF_DEC_ERR_R { + SLVIF_DEC_ERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Interface Common Register Write to Read only Error"] + #[inline(always)] + pub fn slvif_wr2ro_err(&self) -> SLVIF_WR2RO_ERR_R { + SLVIF_WR2RO_ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Slave Interface Common Register Read to Write-only Error"] + #[inline(always)] + pub fn slvif_rd2wo_err(&self) -> SLVIF_RD2WO_ERR_R { + SLVIF_RD2WO_ERR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Interface Common Register Write On Hold Error"] + #[inline(always)] + pub fn slvif_wronhold_err(&self) -> SLVIF_WRONHOLD_ERR_R { + SLVIF_WRONHOLD_ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 8 - Slave Interface Undefined Register Decode Error"] + #[inline(always)] + pub fn slvif_undefinedreg_dec_err(&self) -> SLVIF_UNDEFINEDREG_DEC_ERR_R { + SLVIF_UNDEFINEDREG_DEC_ERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Slave Interface Common Register Decode Error"] + #[inline(always)] + pub fn slvif_dec_err(&mut self) -> SLVIF_DEC_ERR_W { + SLVIF_DEC_ERR_W { w: self } + } + #[doc = "Bit 1 - Slave Interface Common Register Write to Read only Error"] + #[inline(always)] + pub fn slvif_wr2ro_err(&mut self) -> SLVIF_WR2RO_ERR_W { + SLVIF_WR2RO_ERR_W { w: self } + } + #[doc = "Bit 2 - Slave Interface Common Register Read to Write-only Error"] + #[inline(always)] + pub fn slvif_rd2wo_err(&mut self) -> SLVIF_RD2WO_ERR_W { + SLVIF_RD2WO_ERR_W { w: self } + } + #[doc = "Bit 3 - Slave Interface Common Register Write On Hold Error"] + #[inline(always)] + pub fn slvif_wronhold_err(&mut self) -> SLVIF_WRONHOLD_ERR_W { + SLVIF_WRONHOLD_ERR_W { w: self } + } + #[doc = "Bit 8 - Slave Interface Undefined Register Decode Error"] + #[inline(always)] + pub fn slvif_undefinedreg_dec_err(&mut self) -> SLVIF_UNDEFINEDREG_DEC_ERR_W { + SLVIF_UNDEFINEDREG_DEC_ERR_W { w: self } + } + } + } + #[doc = "Common Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [com_intstatus](com_intstatus) module"] + pub type COM_INTSTATUS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COM_INTSTATUS; + #[doc = "`read()` method returns [com_intstatus::R](com_intstatus::R) reader structure"] + impl crate::Readable for COM_INTSTATUS {} + #[doc = "`write(|w| ..)` method takes [com_intstatus::W](com_intstatus::W) writer structure"] + impl crate::Writable for COM_INTSTATUS {} + #[doc = "Common Interrupt Status"] + pub mod com_intstatus { + #[doc = "Reader of register com_intstatus"] + pub type R = crate::R; + #[doc = "Writer for register com_intstatus"] + pub type W = crate::W; + #[doc = "Register com_intstatus `reset()`'s with value 0"] + impl crate::ResetValue for super::COM_INTSTATUS { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `slvif_dec_err`"] + pub type SLVIF_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_dec_err`"] + pub struct SLVIF_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `slvif_wr2ro_err`"] + pub type SLVIF_WR2RO_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_wr2ro_err`"] + pub struct SLVIF_WR2RO_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_WR2RO_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `slvif_rd2wo_err`"] + pub type SLVIF_RD2WO_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_rd2wo_err`"] + pub struct SLVIF_RD2WO_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_RD2WO_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `slvif_wronhold_err`"] + pub type SLVIF_WRONHOLD_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_wronhold_err`"] + pub struct SLVIF_WRONHOLD_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_WRONHOLD_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `slvif_undefinedreg_dec_err`"] + pub type SLVIF_UNDEFINEDREG_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_undefinedreg_dec_err`"] + pub struct SLVIF_UNDEFINEDREG_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_UNDEFINEDREG_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u64) & 0x01) << 8); + self.w + } + } + impl R { + #[doc = "Bit 0 - Slave Interface Common Register Decode Error"] + #[inline(always)] + pub fn slvif_dec_err(&self) -> SLVIF_DEC_ERR_R { + SLVIF_DEC_ERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Interface Common Register Write to Read only Error"] + #[inline(always)] + pub fn slvif_wr2ro_err(&self) -> SLVIF_WR2RO_ERR_R { + SLVIF_WR2RO_ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Slave Interface Common Register Read to Write-only Error"] + #[inline(always)] + pub fn slvif_rd2wo_err(&self) -> SLVIF_RD2WO_ERR_R { + SLVIF_RD2WO_ERR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Interface Common Register Write On Hold Error"] + #[inline(always)] + pub fn slvif_wronhold_err(&self) -> SLVIF_WRONHOLD_ERR_R { + SLVIF_WRONHOLD_ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 8 - Slave Interface Undefined Register Decode Error"] + #[inline(always)] + pub fn slvif_undefinedreg_dec_err(&self) -> SLVIF_UNDEFINEDREG_DEC_ERR_R { + SLVIF_UNDEFINEDREG_DEC_ERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Slave Interface Common Register Decode Error"] + #[inline(always)] + pub fn slvif_dec_err(&mut self) -> SLVIF_DEC_ERR_W { + SLVIF_DEC_ERR_W { w: self } + } + #[doc = "Bit 1 - Slave Interface Common Register Write to Read only Error"] + #[inline(always)] + pub fn slvif_wr2ro_err(&mut self) -> SLVIF_WR2RO_ERR_W { + SLVIF_WR2RO_ERR_W { w: self } + } + #[doc = "Bit 2 - Slave Interface Common Register Read to Write-only Error"] + #[inline(always)] + pub fn slvif_rd2wo_err(&mut self) -> SLVIF_RD2WO_ERR_W { + SLVIF_RD2WO_ERR_W { w: self } + } + #[doc = "Bit 3 - Slave Interface Common Register Write On Hold Error"] + #[inline(always)] + pub fn slvif_wronhold_err(&mut self) -> SLVIF_WRONHOLD_ERR_W { + SLVIF_WRONHOLD_ERR_W { w: self } + } + #[doc = "Bit 8 - Slave Interface Undefined Register Decode Error"] + #[inline(always)] + pub fn slvif_undefinedreg_dec_err(&mut self) -> SLVIF_UNDEFINEDREG_DEC_ERR_W { + SLVIF_UNDEFINEDREG_DEC_ERR_W { w: self } + } + } + } + #[doc = "Reset register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [reset](reset) module"] + pub type RESET = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RESET; + #[doc = "`read()` method returns [reset::R](reset::R) reader structure"] + impl crate::Readable for RESET {} + #[doc = "`write(|w| ..)` method takes [reset::W](reset::W) writer structure"] + impl crate::Writable for RESET {} + #[doc = "Reset register"] + pub mod reset { + #[doc = "Reader of register reset"] + pub type R = crate::R; + #[doc = "Writer for register reset"] + pub type W = crate::W; + #[doc = "Register reset `reset()`'s with value 0"] + impl crate::ResetValue for super::RESET { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `rst`"] + pub type RST_R = crate::R; + #[doc = "Write proxy for field `rst`"] + pub struct RST_W<'a> { + w: &'a mut W, + } + impl<'a> RST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - DMAC reset request bit"] + #[inline(always)] + pub fn rst(&self) -> RST_R { + RST_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - DMAC reset request bit"] + #[inline(always)] + pub fn rst(&mut self) -> RST_W { + RST_W { w: self } + } + } + } +} +#[doc = "General Purpose Input/Output Interface"] +pub struct GPIO { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GPIO {} +impl GPIO { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gpio::RegisterBlock { + 0x5020_0000 as *const _ + } +} +impl Deref for GPIO { + type Target = gpio::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*GPIO::ptr() } + } +} +#[doc = "General Purpose Input/Output Interface"] +pub mod gpio { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Data (output) registers"] + pub data_output: DATA_OUTPUT, + #[doc = "0x04 - Data direction registers"] + pub direction: DIRECTION, + #[doc = "0x08 - Data source registers"] + pub source: SOURCE, + _reserved3: [u8; 36usize], + #[doc = "0x30 - Interrupt enable/disable registers"] + pub interrupt_enable: INTERRUPT_ENABLE, + #[doc = "0x34 - Interrupt mask registers"] + pub interrupt_mask: INTERRUPT_MASK, + #[doc = "0x38 - Interrupt level registers"] + pub interrupt_level: INTERRUPT_LEVEL, + #[doc = "0x3c - Interrupt polarity registers"] + pub interrupt_polarity: INTERRUPT_POLARITY, + #[doc = "0x40 - Interrupt status registers"] + pub interrupt_status: INTERRUPT_STATUS, + #[doc = "0x44 - Raw interrupt status registers"] + pub interrupt_status_raw: INTERRUPT_STATUS_RAW, + #[doc = "0x48 - Interrupt debounce registers"] + pub interrupt_debounce: INTERRUPT_DEBOUNCE, + #[doc = "0x4c - Registers for clearing interrupts"] + pub interrupt_clear: INTERRUPT_CLEAR, + #[doc = "0x50 - External port (data input) registers"] + pub data_input: DATA_INPUT, + _reserved12: [u8; 12usize], + #[doc = "0x60 - Sync level registers"] + pub sync_level: SYNC_LEVEL, + #[doc = "0x64 - ID code"] + pub id_code: ID_CODE, + #[doc = "0x68 - Interrupt both edge type"] + pub interrupt_bothedge: INTERRUPT_BOTHEDGE, + } + #[doc = "Data (output) registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data_output](data_output) module"] + pub type DATA_OUTPUT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DATA_OUTPUT; + #[doc = "`read()` method returns [data_output::R](data_output::R) reader structure"] + impl crate::Readable for DATA_OUTPUT {} + #[doc = "`write(|w| ..)` method takes [data_output::W](data_output::W) writer structure"] + impl crate::Writable for DATA_OUTPUT {} + #[doc = "Data (output) registers"] + pub mod data_output { + #[doc = "Reader of register data_output"] + pub type R = crate::R; + #[doc = "Writer for register data_output"] + pub type W = crate::W; + #[doc = "Register data_output `reset()`'s with value 0"] + impl crate::ResetValue for super::DATA_OUTPUT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-7)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-7)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + } + } + #[doc = "Data direction registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [direction](direction) module"] + pub type DIRECTION = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DIRECTION; + #[doc = "`read()` method returns [direction::R](direction::R) reader structure"] + impl crate::Readable for DIRECTION {} + #[doc = "`write(|w| ..)` method takes [direction::W](direction::W) writer structure"] + impl crate::Writable for DIRECTION {} + #[doc = "Data direction registers"] + pub mod direction { + #[doc = "Reader of register direction"] + pub type R = crate::R; + #[doc = "Writer for register direction"] + pub type W = crate::W; + #[doc = "Register direction `reset()`'s with value 0"] + impl crate::ResetValue for super::DIRECTION { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum PIN_A { + #[doc = "0: Pin is input"] + INPUT = 0, + #[doc = "1: Pin is output"] + OUTPUT = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: PIN_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of fields `pin(0-7)`"] + pub type PIN_R = crate::R; + impl PIN_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN_A { + match self.bits { + false => PIN_A::INPUT, + true => PIN_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN_A::OUTPUT + } + } + #[doc = "Write proxy for fields `pin(0-7)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PIN_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Pin is input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN_A::INPUT) + } + #[doc = "Pin is output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN_A::OUTPUT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + } + } + #[doc = "Data source registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [source](source) module"] + pub type SOURCE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SOURCE; + #[doc = "`read()` method returns [source::R](source::R) reader structure"] + impl crate::Readable for SOURCE {} + #[doc = "`write(|w| ..)` method takes [source::W](source::W) writer structure"] + impl crate::Writable for SOURCE {} + #[doc = "Data source registers"] + pub mod source { + #[doc = "Reader of register source"] + pub type R = crate::R; + #[doc = "Writer for register source"] + pub type W = crate::W; + #[doc = "Register source `reset()`'s with value 0"] + impl crate::ResetValue for super::SOURCE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt enable/disable registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_enable](interrupt_enable) module"] + pub type INTERRUPT_ENABLE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_ENABLE; + #[doc = "`read()` method returns [interrupt_enable::R](interrupt_enable::R) reader structure"] + impl crate::Readable for INTERRUPT_ENABLE {} + #[doc = "`write(|w| ..)` method takes [interrupt_enable::W](interrupt_enable::W) writer structure"] + impl crate::Writable for INTERRUPT_ENABLE {} + #[doc = "Interrupt enable/disable registers"] + pub mod interrupt_enable { + #[doc = "Reader of register interrupt_enable"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_enable"] + pub type W = crate::W; + #[doc = "Register interrupt_enable `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_ENABLE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt mask registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_mask](interrupt_mask) module"] + pub type INTERRUPT_MASK = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_MASK; + #[doc = "`read()` method returns [interrupt_mask::R](interrupt_mask::R) reader structure"] + impl crate::Readable for INTERRUPT_MASK {} + #[doc = "`write(|w| ..)` method takes [interrupt_mask::W](interrupt_mask::W) writer structure"] + impl crate::Writable for INTERRUPT_MASK {} + #[doc = "Interrupt mask registers"] + pub mod interrupt_mask { + #[doc = "Reader of register interrupt_mask"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_mask"] + pub type W = crate::W; + #[doc = "Register interrupt_mask `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_MASK { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt level registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_level](interrupt_level) module"] + pub type INTERRUPT_LEVEL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_LEVEL; + #[doc = "`read()` method returns [interrupt_level::R](interrupt_level::R) reader structure"] + impl crate::Readable for INTERRUPT_LEVEL {} + #[doc = "`write(|w| ..)` method takes [interrupt_level::W](interrupt_level::W) writer structure"] + impl crate::Writable for INTERRUPT_LEVEL {} + #[doc = "Interrupt level registers"] + pub mod interrupt_level { + #[doc = "Reader of register interrupt_level"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_level"] + pub type W = crate::W; + #[doc = "Register interrupt_level `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_LEVEL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt polarity registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_polarity](interrupt_polarity) module"] + pub type INTERRUPT_POLARITY = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_POLARITY; + #[doc = "`read()` method returns [interrupt_polarity::R](interrupt_polarity::R) reader structure"] + impl crate::Readable for INTERRUPT_POLARITY {} + #[doc = "`write(|w| ..)` method takes [interrupt_polarity::W](interrupt_polarity::W) writer structure"] + impl crate::Writable for INTERRUPT_POLARITY {} + #[doc = "Interrupt polarity registers"] + pub mod interrupt_polarity { + #[doc = "Reader of register interrupt_polarity"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_polarity"] + pub type W = crate::W; + #[doc = "Register interrupt_polarity `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_POLARITY { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt status registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_status](interrupt_status) module"] + pub type INTERRUPT_STATUS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_STATUS; + #[doc = "`read()` method returns [interrupt_status::R](interrupt_status::R) reader structure"] + impl crate::Readable for INTERRUPT_STATUS {} + #[doc = "`write(|w| ..)` method takes [interrupt_status::W](interrupt_status::W) writer structure"] + impl crate::Writable for INTERRUPT_STATUS {} + #[doc = "Interrupt status registers"] + pub mod interrupt_status { + #[doc = "Reader of register interrupt_status"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_status"] + pub type W = crate::W; + #[doc = "Register interrupt_status `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_STATUS { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Raw interrupt status registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_status_raw](interrupt_status_raw) module"] + pub type INTERRUPT_STATUS_RAW = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_STATUS_RAW; + #[doc = "`read()` method returns [interrupt_status_raw::R](interrupt_status_raw::R) reader structure"] + impl crate::Readable for INTERRUPT_STATUS_RAW {} + #[doc = "`write(|w| ..)` method takes [interrupt_status_raw::W](interrupt_status_raw::W) writer structure"] + impl crate::Writable for INTERRUPT_STATUS_RAW {} + #[doc = "Raw interrupt status registers"] + pub mod interrupt_status_raw { + #[doc = "Reader of register interrupt_status_raw"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_status_raw"] + pub type W = crate::W; + #[doc = "Register interrupt_status_raw `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_STATUS_RAW { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt debounce registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_debounce](interrupt_debounce) module"] + pub type INTERRUPT_DEBOUNCE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_DEBOUNCE; + #[doc = "`read()` method returns [interrupt_debounce::R](interrupt_debounce::R) reader structure"] + impl crate::Readable for INTERRUPT_DEBOUNCE {} + #[doc = "`write(|w| ..)` method takes [interrupt_debounce::W](interrupt_debounce::W) writer structure"] + impl crate::Writable for INTERRUPT_DEBOUNCE {} + #[doc = "Interrupt debounce registers"] + pub mod interrupt_debounce { + #[doc = "Reader of register interrupt_debounce"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_debounce"] + pub type W = crate::W; + #[doc = "Register interrupt_debounce `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_DEBOUNCE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Registers for clearing interrupts\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_clear](interrupt_clear) module"] + pub type INTERRUPT_CLEAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_CLEAR; + #[doc = "`read()` method returns [interrupt_clear::R](interrupt_clear::R) reader structure"] + impl crate::Readable for INTERRUPT_CLEAR {} + #[doc = "`write(|w| ..)` method takes [interrupt_clear::W](interrupt_clear::W) writer structure"] + impl crate::Writable for INTERRUPT_CLEAR {} + #[doc = "Registers for clearing interrupts"] + pub mod interrupt_clear { + #[doc = "Reader of register interrupt_clear"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_clear"] + pub type W = crate::W; + #[doc = "Register interrupt_clear `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_CLEAR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "External port (data input) registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data_input](data_input) module"] + pub type DATA_INPUT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DATA_INPUT; + #[doc = "`read()` method returns [data_input::R](data_input::R) reader structure"] + impl crate::Readable for DATA_INPUT {} + #[doc = "`write(|w| ..)` method takes [data_input::W](data_input::W) writer structure"] + impl crate::Writable for DATA_INPUT {} + #[doc = "External port (data input) registers"] + pub mod data_input { + #[doc = "Reader of register data_input"] + pub type R = crate::R; + #[doc = "Writer for register data_input"] + pub type W = crate::W; + #[doc = "Register data_input `reset()`'s with value 0"] + impl crate::ResetValue for super::DATA_INPUT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-7)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-7)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + } + } + #[doc = "Sync level registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sync_level](sync_level) module"] + pub type SYNC_LEVEL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SYNC_LEVEL; + #[doc = "`read()` method returns [sync_level::R](sync_level::R) reader structure"] + impl crate::Readable for SYNC_LEVEL {} + #[doc = "`write(|w| ..)` method takes [sync_level::W](sync_level::W) writer structure"] + impl crate::Writable for SYNC_LEVEL {} + #[doc = "Sync level registers"] + pub mod sync_level { + #[doc = "Reader of register sync_level"] + pub type R = crate::R; + #[doc = "Writer for register sync_level"] + pub type W = crate::W; + #[doc = "Register sync_level `reset()`'s with value 0"] + impl crate::ResetValue for super::SYNC_LEVEL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "ID code\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id_code](id_code) module"] + pub type ID_CODE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ID_CODE; + #[doc = "`read()` method returns [id_code::R](id_code::R) reader structure"] + impl crate::Readable for ID_CODE {} + #[doc = "`write(|w| ..)` method takes [id_code::W](id_code::W) writer structure"] + impl crate::Writable for ID_CODE {} + #[doc = "ID code"] + pub mod id_code { + #[doc = "Reader of register id_code"] + pub type R = crate::R; + #[doc = "Writer for register id_code"] + pub type W = crate::W; + #[doc = "Register id_code `reset()`'s with value 0"] + impl crate::ResetValue for super::ID_CODE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt both edge type\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_bothedge](interrupt_bothedge) module"] + pub type INTERRUPT_BOTHEDGE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_BOTHEDGE; + #[doc = "`read()` method returns [interrupt_bothedge::R](interrupt_bothedge::R) reader structure"] + impl crate::Readable for INTERRUPT_BOTHEDGE {} + #[doc = "`write(|w| ..)` method takes [interrupt_bothedge::W](interrupt_bothedge::W) writer structure"] + impl crate::Writable for INTERRUPT_BOTHEDGE {} + #[doc = "Interrupt both edge type"] + pub mod interrupt_bothedge { + #[doc = "Reader of register interrupt_bothedge"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_bothedge"] + pub type W = crate::W; + #[doc = "Register interrupt_bothedge `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_BOTHEDGE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Universal Asynchronous Receiver-Transmitter 1"] +pub struct UART1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART1 {} +impl UART1 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart1::RegisterBlock { + 0x5021_0000 as *const _ + } +} +impl Deref for UART1 { + type Target = uart1::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*UART1::ptr() } + } +} +#[doc = "Universal Asynchronous Receiver-Transmitter 1"] +pub mod uart1 { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Receive Buffer Register / Divisor Latch (Low) / Transmit Holding Register (depending on context and R/W)"] + pub rbr_dll_thr: RBR_DLL_THR, + #[doc = "0x04 - Divisor Latch (High) / Interrupt Enable Register"] + pub dlh_ier: DLH_IER, + #[doc = "0x08 - FIFO Control Register / Interrupt Identification Register"] + pub fcr_iir: FCR_IIR, + #[doc = "0x0c - Line Control Register"] + pub lcr: LCR, + #[doc = "0x10 - Modem Control Register"] + pub mcr: MCR, + #[doc = "0x14 - Line Status Register"] + pub lsr: LSR, + #[doc = "0x18 - Modem Status Register"] + pub msr: MSR, + #[doc = "0x1c - Scratchpad Register"] + pub scr: SCR, + #[doc = "0x20 - Low Power Divisor Latch (Low) Register"] + pub lpdll: LPDLL, + #[doc = "0x24 - Low Power Divisor Latch (High) Register"] + pub lpdlh: LPDLH, + _reserved10: [u8; 8usize], + #[doc = "0x30 - Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)"] + pub srbr_sthr: [SRBR_STHR; 16], + #[doc = "0x70 - FIFO Access Register"] + pub far: FAR, + #[doc = "0x74 - Transmit FIFO Read Register"] + pub tfr: TFR, + #[doc = "0x78 - Receive FIFO Write Register"] + pub rfw: RFW, + #[doc = "0x7c - UART Status Register"] + pub usr: USR, + #[doc = "0x80 - Transmit FIFO Level"] + pub tfl: TFL, + #[doc = "0x84 - Receive FIFO Level"] + pub rfl: RFL, + #[doc = "0x88 - Software Reset Register"] + pub srr: SRR, + #[doc = "0x8c - Shadow Request to Send Register"] + pub srts: SRTS, + #[doc = "0x90 - Shadow Break Control Register"] + pub sbcr: SBCR, + #[doc = "0x94 - Shadow DMA Mode"] + pub sdmam: SDMAM, + #[doc = "0x98 - Shadow FIFO Enable"] + pub sfe: SFE, + #[doc = "0x9c - Shadow RCVR Trigger Register"] + pub srt: SRT, + #[doc = "0xa0 - Shadow TX Empty Trigger Register"] + pub stet: STET, + #[doc = "0xa4 - Halt TX Regster"] + pub htx: HTX, + #[doc = "0xa8 - DMA Software Acknowledge Register"] + pub dmasa: DMASA, + #[doc = "0xac - Transfer Control Register"] + pub tcr: TCR, + #[doc = "0xb0 - DE Enable Register"] + pub de_en: DE_EN, + #[doc = "0xb4 - RE Enable Register"] + pub re_en: RE_EN, + #[doc = "0xb8 - DE Assertion Time Register"] + pub det: DET, + #[doc = "0xbc - Turn-Around Time Register"] + pub tat: TAT, + #[doc = "0xc0 - Divisor Latch (Fractional) Register"] + pub dlf: DLF, + #[doc = "0xc4 - Receive-Mode Address Register"] + pub rar: RAR, + #[doc = "0xc8 - Transmit-Mode Address Register"] + pub tar: TAR, + #[doc = "0xcc - Line Control Register (Extended)"] + pub lcr_ext: LCR_EXT, + _reserved35: [u8; 36usize], + #[doc = "0xf4 - Component Parameter Register"] + pub cpr: CPR, + #[doc = "0xf8 - UART Component Version"] + pub ucv: UCV, + #[doc = "0xfc - Component Type Register"] + pub ctr: CTR, + } + #[doc = "Receive Buffer Register / Divisor Latch (Low) / Transmit Holding Register (depending on context and R/W)\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rbr_dll_thr](rbr_dll_thr) module"] + pub type RBR_DLL_THR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RBR_DLL_THR; + #[doc = "`read()` method returns [rbr_dll_thr::R](rbr_dll_thr::R) reader structure"] + impl crate::Readable for RBR_DLL_THR {} + #[doc = "`write(|w| ..)` method takes [rbr_dll_thr::W](rbr_dll_thr::W) writer structure"] + impl crate::Writable for RBR_DLL_THR {} + #[doc = "Receive Buffer Register / Divisor Latch (Low) / Transmit Holding Register (depending on context and R/W)"] + pub mod rbr_dll_thr { + #[doc = "Reader of register rbr_dll_thr"] + pub type R = crate::R; + #[doc = "Writer for register rbr_dll_thr"] + pub type W = crate::W; + #[doc = "Register rbr_dll_thr `reset()`'s with value 0"] + impl crate::ResetValue for super::RBR_DLL_THR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Divisor Latch (High) / Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dlh_ier](dlh_ier) module"] + pub type DLH_IER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DLH_IER; + #[doc = "`read()` method returns [dlh_ier::R](dlh_ier::R) reader structure"] + impl crate::Readable for DLH_IER {} + #[doc = "`write(|w| ..)` method takes [dlh_ier::W](dlh_ier::W) writer structure"] + impl crate::Writable for DLH_IER {} + #[doc = "Divisor Latch (High) / Interrupt Enable Register"] + pub mod dlh_ier { + #[doc = "Reader of register dlh_ier"] + pub type R = crate::R; + #[doc = "Writer for register dlh_ier"] + pub type W = crate::W; + #[doc = "Register dlh_ier `reset()`'s with value 0"] + impl crate::ResetValue for super::DLH_IER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "FIFO Control Register / Interrupt Identification Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcr_iir](fcr_iir) module"] + pub type FCR_IIR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FCR_IIR; + #[doc = "`read()` method returns [fcr_iir::R](fcr_iir::R) reader structure"] + impl crate::Readable for FCR_IIR {} + #[doc = "`write(|w| ..)` method takes [fcr_iir::W](fcr_iir::W) writer structure"] + impl crate::Writable for FCR_IIR {} + #[doc = "FIFO Control Register / Interrupt Identification Register"] + pub mod fcr_iir { + #[doc = "Reader of register fcr_iir"] + pub type R = crate::R; + #[doc = "Writer for register fcr_iir"] + pub type W = crate::W; + #[doc = "Register fcr_iir `reset()`'s with value 0"] + impl crate::ResetValue for super::FCR_IIR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Line Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lcr](lcr) module"] + pub type LCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LCR; + #[doc = "`read()` method returns [lcr::R](lcr::R) reader structure"] + impl crate::Readable for LCR {} + #[doc = "`write(|w| ..)` method takes [lcr::W](lcr::W) writer structure"] + impl crate::Writable for LCR {} + #[doc = "Line Control Register"] + pub mod lcr { + #[doc = "Reader of register lcr"] + pub type R = crate::R; + #[doc = "Writer for register lcr"] + pub type W = crate::W; + #[doc = "Register lcr `reset()`'s with value 0"] + impl crate::ResetValue for super::LCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Modem Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcr](mcr) module"] + pub type MCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _MCR; + #[doc = "`read()` method returns [mcr::R](mcr::R) reader structure"] + impl crate::Readable for MCR {} + #[doc = "`write(|w| ..)` method takes [mcr::W](mcr::W) writer structure"] + impl crate::Writable for MCR {} + #[doc = "Modem Control Register"] + pub mod mcr { + #[doc = "Reader of register mcr"] + pub type R = crate::R; + #[doc = "Writer for register mcr"] + pub type W = crate::W; + #[doc = "Register mcr `reset()`'s with value 0"] + impl crate::ResetValue for super::MCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Line Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lsr](lsr) module"] + pub type LSR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LSR; + #[doc = "`read()` method returns [lsr::R](lsr::R) reader structure"] + impl crate::Readable for LSR {} + #[doc = "`write(|w| ..)` method takes [lsr::W](lsr::W) writer structure"] + impl crate::Writable for LSR {} + #[doc = "Line Status Register"] + pub mod lsr { + #[doc = "Reader of register lsr"] + pub type R = crate::R; + #[doc = "Writer for register lsr"] + pub type W = crate::W; + #[doc = "Register lsr `reset()`'s with value 0"] + impl crate::ResetValue for super::LSR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Modem Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msr](msr) module"] + pub type MSR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _MSR; + #[doc = "`read()` method returns [msr::R](msr::R) reader structure"] + impl crate::Readable for MSR {} + #[doc = "`write(|w| ..)` method takes [msr::W](msr::W) writer structure"] + impl crate::Writable for MSR {} + #[doc = "Modem Status Register"] + pub mod msr { + #[doc = "Reader of register msr"] + pub type R = crate::R; + #[doc = "Writer for register msr"] + pub type W = crate::W; + #[doc = "Register msr `reset()`'s with value 0"] + impl crate::ResetValue for super::MSR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Scratchpad Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr](scr) module"] + pub type SCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SCR; + #[doc = "`read()` method returns [scr::R](scr::R) reader structure"] + impl crate::Readable for SCR {} + #[doc = "`write(|w| ..)` method takes [scr::W](scr::W) writer structure"] + impl crate::Writable for SCR {} + #[doc = "Scratchpad Register"] + pub mod scr { + #[doc = "Reader of register scr"] + pub type R = crate::R; + #[doc = "Writer for register scr"] + pub type W = crate::W; + #[doc = "Register scr `reset()`'s with value 0"] + impl crate::ResetValue for super::SCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Low Power Divisor Latch (Low) Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lpdll](lpdll) module"] + pub type LPDLL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LPDLL; + #[doc = "`read()` method returns [lpdll::R](lpdll::R) reader structure"] + impl crate::Readable for LPDLL {} + #[doc = "`write(|w| ..)` method takes [lpdll::W](lpdll::W) writer structure"] + impl crate::Writable for LPDLL {} + #[doc = "Low Power Divisor Latch (Low) Register"] + pub mod lpdll { + #[doc = "Reader of register lpdll"] + pub type R = crate::R; + #[doc = "Writer for register lpdll"] + pub type W = crate::W; + #[doc = "Register lpdll `reset()`'s with value 0"] + impl crate::ResetValue for super::LPDLL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Low Power Divisor Latch (High) Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lpdlh](lpdlh) module"] + pub type LPDLH = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LPDLH; + #[doc = "`read()` method returns [lpdlh::R](lpdlh::R) reader structure"] + impl crate::Readable for LPDLH {} + #[doc = "`write(|w| ..)` method takes [lpdlh::W](lpdlh::W) writer structure"] + impl crate::Writable for LPDLH {} + #[doc = "Low Power Divisor Latch (High) Register"] + pub mod lpdlh { + #[doc = "Reader of register lpdlh"] + pub type R = crate::R; + #[doc = "Writer for register lpdlh"] + pub type W = crate::W; + #[doc = "Register lpdlh `reset()`'s with value 0"] + impl crate::ResetValue for super::LPDLH { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [srbr_sthr](srbr_sthr) module"] + pub type SRBR_STHR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SRBR_STHR; + #[doc = "`read()` method returns [srbr_sthr::R](srbr_sthr::R) reader structure"] + impl crate::Readable for SRBR_STHR {} + #[doc = "`write(|w| ..)` method takes [srbr_sthr::W](srbr_sthr::W) writer structure"] + impl crate::Writable for SRBR_STHR {} + #[doc = "Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)"] + pub mod srbr_sthr { + #[doc = "Reader of register srbr_sthr[%s]"] + pub type R = crate::R; + #[doc = "Writer for register srbr_sthr[%s]"] + pub type W = crate::W; + #[doc = "Register srbr_sthr[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::SRBR_STHR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "FIFO Access Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [far](far) module"] + pub type FAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FAR; + #[doc = "`read()` method returns [far::R](far::R) reader structure"] + impl crate::Readable for FAR {} + #[doc = "`write(|w| ..)` method takes [far::W](far::W) writer structure"] + impl crate::Writable for FAR {} + #[doc = "FIFO Access Register"] + pub mod far { + #[doc = "Reader of register far"] + pub type R = crate::R; + #[doc = "Writer for register far"] + pub type W = crate::W; + #[doc = "Register far `reset()`'s with value 0"] + impl crate::ResetValue for super::FAR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Transmit FIFO Read Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tfr](tfr) module"] + pub type TFR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TFR; + #[doc = "`read()` method returns [tfr::R](tfr::R) reader structure"] + impl crate::Readable for TFR {} + #[doc = "`write(|w| ..)` method takes [tfr::W](tfr::W) writer structure"] + impl crate::Writable for TFR {} + #[doc = "Transmit FIFO Read Register"] + pub mod tfr { + #[doc = "Reader of register tfr"] + pub type R = crate::R; + #[doc = "Writer for register tfr"] + pub type W = crate::W; + #[doc = "Register tfr `reset()`'s with value 0"] + impl crate::ResetValue for super::TFR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive FIFO Write Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rfw](rfw) module"] + pub type RFW = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RFW; + #[doc = "`read()` method returns [rfw::R](rfw::R) reader structure"] + impl crate::Readable for RFW {} + #[doc = "`write(|w| ..)` method takes [rfw::W](rfw::W) writer structure"] + impl crate::Writable for RFW {} + #[doc = "Receive FIFO Write Register"] + pub mod rfw { + #[doc = "Reader of register rfw"] + pub type R = crate::R; + #[doc = "Writer for register rfw"] + pub type W = crate::W; + #[doc = "Register rfw `reset()`'s with value 0"] + impl crate::ResetValue for super::RFW { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "UART Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usr](usr) module"] + pub type USR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _USR; + #[doc = "`read()` method returns [usr::R](usr::R) reader structure"] + impl crate::Readable for USR {} + #[doc = "`write(|w| ..)` method takes [usr::W](usr::W) writer structure"] + impl crate::Writable for USR {} + #[doc = "UART Status Register"] + pub mod usr { + #[doc = "Reader of register usr"] + pub type R = crate::R; + #[doc = "Writer for register usr"] + pub type W = crate::W; + #[doc = "Register usr `reset()`'s with value 0"] + impl crate::ResetValue for super::USR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Transmit FIFO Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tfl](tfl) module"] + pub type TFL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TFL; + #[doc = "`read()` method returns [tfl::R](tfl::R) reader structure"] + impl crate::Readable for TFL {} + #[doc = "`write(|w| ..)` method takes [tfl::W](tfl::W) writer structure"] + impl crate::Writable for TFL {} + #[doc = "Transmit FIFO Level"] + pub mod tfl { + #[doc = "Reader of register tfl"] + pub type R = crate::R; + #[doc = "Writer for register tfl"] + pub type W = crate::W; + #[doc = "Register tfl `reset()`'s with value 0"] + impl crate::ResetValue for super::TFL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive FIFO Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rfl](rfl) module"] + pub type RFL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RFL; + #[doc = "`read()` method returns [rfl::R](rfl::R) reader structure"] + impl crate::Readable for RFL {} + #[doc = "`write(|w| ..)` method takes [rfl::W](rfl::W) writer structure"] + impl crate::Writable for RFL {} + #[doc = "Receive FIFO Level"] + pub mod rfl { + #[doc = "Reader of register rfl"] + pub type R = crate::R; + #[doc = "Writer for register rfl"] + pub type W = crate::W; + #[doc = "Register rfl `reset()`'s with value 0"] + impl crate::ResetValue for super::RFL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Software Reset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [srr](srr) module"] + pub type SRR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SRR; + #[doc = "`read()` method returns [srr::R](srr::R) reader structure"] + impl crate::Readable for SRR {} + #[doc = "`write(|w| ..)` method takes [srr::W](srr::W) writer structure"] + impl crate::Writable for SRR {} + #[doc = "Software Reset Register"] + pub mod srr { + #[doc = "Reader of register srr"] + pub type R = crate::R; + #[doc = "Writer for register srr"] + pub type W = crate::W; + #[doc = "Register srr `reset()`'s with value 0"] + impl crate::ResetValue for super::SRR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Shadow Request to Send Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [srts](srts) module"] + pub type SRTS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SRTS; + #[doc = "`read()` method returns [srts::R](srts::R) reader structure"] + impl crate::Readable for SRTS {} + #[doc = "`write(|w| ..)` method takes [srts::W](srts::W) writer structure"] + impl crate::Writable for SRTS {} + #[doc = "Shadow Request to Send Register"] + pub mod srts { + #[doc = "Reader of register srts"] + pub type R = crate::R; + #[doc = "Writer for register srts"] + pub type W = crate::W; + #[doc = "Register srts `reset()`'s with value 0"] + impl crate::ResetValue for super::SRTS { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Shadow Break Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sbcr](sbcr) module"] + pub type SBCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SBCR; + #[doc = "`read()` method returns [sbcr::R](sbcr::R) reader structure"] + impl crate::Readable for SBCR {} + #[doc = "`write(|w| ..)` method takes [sbcr::W](sbcr::W) writer structure"] + impl crate::Writable for SBCR {} + #[doc = "Shadow Break Control Register"] + pub mod sbcr { + #[doc = "Reader of register sbcr"] + pub type R = crate::R; + #[doc = "Writer for register sbcr"] + pub type W = crate::W; + #[doc = "Register sbcr `reset()`'s with value 0"] + impl crate::ResetValue for super::SBCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Shadow DMA Mode\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdmam](sdmam) module"] + pub type SDMAM = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SDMAM; + #[doc = "`read()` method returns [sdmam::R](sdmam::R) reader structure"] + impl crate::Readable for SDMAM {} + #[doc = "`write(|w| ..)` method takes [sdmam::W](sdmam::W) writer structure"] + impl crate::Writable for SDMAM {} + #[doc = "Shadow DMA Mode"] + pub mod sdmam { + #[doc = "Reader of register sdmam"] + pub type R = crate::R; + #[doc = "Writer for register sdmam"] + pub type W = crate::W; + #[doc = "Register sdmam `reset()`'s with value 0"] + impl crate::ResetValue for super::SDMAM { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Shadow FIFO Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sfe](sfe) module"] + pub type SFE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SFE; + #[doc = "`read()` method returns [sfe::R](sfe::R) reader structure"] + impl crate::Readable for SFE {} + #[doc = "`write(|w| ..)` method takes [sfe::W](sfe::W) writer structure"] + impl crate::Writable for SFE {} + #[doc = "Shadow FIFO Enable"] + pub mod sfe { + #[doc = "Reader of register sfe"] + pub type R = crate::R; + #[doc = "Writer for register sfe"] + pub type W = crate::W; + #[doc = "Register sfe `reset()`'s with value 0"] + impl crate::ResetValue for super::SFE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Shadow RCVR Trigger Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [srt](srt) module"] + pub type SRT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SRT; + #[doc = "`read()` method returns [srt::R](srt::R) reader structure"] + impl crate::Readable for SRT {} + #[doc = "`write(|w| ..)` method takes [srt::W](srt::W) writer structure"] + impl crate::Writable for SRT {} + #[doc = "Shadow RCVR Trigger Register"] + pub mod srt { + #[doc = "Reader of register srt"] + pub type R = crate::R; + #[doc = "Writer for register srt"] + pub type W = crate::W; + #[doc = "Register srt `reset()`'s with value 0"] + impl crate::ResetValue for super::SRT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Shadow TX Empty Trigger Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stet](stet) module"] + pub type STET = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _STET; + #[doc = "`read()` method returns [stet::R](stet::R) reader structure"] + impl crate::Readable for STET {} + #[doc = "`write(|w| ..)` method takes [stet::W](stet::W) writer structure"] + impl crate::Writable for STET {} + #[doc = "Shadow TX Empty Trigger Register"] + pub mod stet { + #[doc = "Reader of register stet"] + pub type R = crate::R; + #[doc = "Writer for register stet"] + pub type W = crate::W; + #[doc = "Register stet `reset()`'s with value 0"] + impl crate::ResetValue for super::STET { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Halt TX Regster\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [htx](htx) module"] + pub type HTX = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _HTX; + #[doc = "`read()` method returns [htx::R](htx::R) reader structure"] + impl crate::Readable for HTX {} + #[doc = "`write(|w| ..)` method takes [htx::W](htx::W) writer structure"] + impl crate::Writable for HTX {} + #[doc = "Halt TX Regster"] + pub mod htx { + #[doc = "Reader of register htx"] + pub type R = crate::R; + #[doc = "Writer for register htx"] + pub type W = crate::W; + #[doc = "Register htx `reset()`'s with value 0"] + impl crate::ResetValue for super::HTX { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DMA Software Acknowledge Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmasa](dmasa) module"] + pub type DMASA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMASA; + #[doc = "`read()` method returns [dmasa::R](dmasa::R) reader structure"] + impl crate::Readable for DMASA {} + #[doc = "`write(|w| ..)` method takes [dmasa::W](dmasa::W) writer structure"] + impl crate::Writable for DMASA {} + #[doc = "DMA Software Acknowledge Register"] + pub mod dmasa { + #[doc = "Reader of register dmasa"] + pub type R = crate::R; + #[doc = "Writer for register dmasa"] + pub type W = crate::W; + #[doc = "Register dmasa `reset()`'s with value 0"] + impl crate::ResetValue for super::DMASA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Transfer Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tcr](tcr) module"] + pub type TCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TCR; + #[doc = "`read()` method returns [tcr::R](tcr::R) reader structure"] + impl crate::Readable for TCR {} + #[doc = "`write(|w| ..)` method takes [tcr::W](tcr::W) writer structure"] + impl crate::Writable for TCR {} + #[doc = "Transfer Control Register"] + pub mod tcr { + #[doc = "Reader of register tcr"] + pub type R = crate::R; + #[doc = "Writer for register tcr"] + pub type W = crate::W; + #[doc = "Register tcr `reset()`'s with value 0"] + impl crate::ResetValue for super::TCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DE Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [de_en](de_en) module"] + pub type DE_EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DE_EN; + #[doc = "`read()` method returns [de_en::R](de_en::R) reader structure"] + impl crate::Readable for DE_EN {} + #[doc = "`write(|w| ..)` method takes [de_en::W](de_en::W) writer structure"] + impl crate::Writable for DE_EN {} + #[doc = "DE Enable Register"] + pub mod de_en { + #[doc = "Reader of register de_en"] + pub type R = crate::R; + #[doc = "Writer for register de_en"] + pub type W = crate::W; + #[doc = "Register de_en `reset()`'s with value 0"] + impl crate::ResetValue for super::DE_EN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "RE Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [re_en](re_en) module"] + pub type RE_EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RE_EN; + #[doc = "`read()` method returns [re_en::R](re_en::R) reader structure"] + impl crate::Readable for RE_EN {} + #[doc = "`write(|w| ..)` method takes [re_en::W](re_en::W) writer structure"] + impl crate::Writable for RE_EN {} + #[doc = "RE Enable Register"] + pub mod re_en { + #[doc = "Reader of register re_en"] + pub type R = crate::R; + #[doc = "Writer for register re_en"] + pub type W = crate::W; + #[doc = "Register re_en `reset()`'s with value 0"] + impl crate::ResetValue for super::RE_EN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DE Assertion Time Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [det](det) module"] + pub type DET = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DET; + #[doc = "`read()` method returns [det::R](det::R) reader structure"] + impl crate::Readable for DET {} + #[doc = "`write(|w| ..)` method takes [det::W](det::W) writer structure"] + impl crate::Writable for DET {} + #[doc = "DE Assertion Time Register"] + pub mod det { + #[doc = "Reader of register det"] + pub type R = crate::R; + #[doc = "Writer for register det"] + pub type W = crate::W; + #[doc = "Register det `reset()`'s with value 0"] + impl crate::ResetValue for super::DET { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Turn-Around Time Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tat](tat) module"] + pub type TAT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TAT; + #[doc = "`read()` method returns [tat::R](tat::R) reader structure"] + impl crate::Readable for TAT {} + #[doc = "`write(|w| ..)` method takes [tat::W](tat::W) writer structure"] + impl crate::Writable for TAT {} + #[doc = "Turn-Around Time Register"] + pub mod tat { + #[doc = "Reader of register tat"] + pub type R = crate::R; + #[doc = "Writer for register tat"] + pub type W = crate::W; + #[doc = "Register tat `reset()`'s with value 0"] + impl crate::ResetValue for super::TAT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Divisor Latch (Fractional) Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dlf](dlf) module"] + pub type DLF = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DLF; + #[doc = "`read()` method returns [dlf::R](dlf::R) reader structure"] + impl crate::Readable for DLF {} + #[doc = "`write(|w| ..)` method takes [dlf::W](dlf::W) writer structure"] + impl crate::Writable for DLF {} + #[doc = "Divisor Latch (Fractional) Register"] + pub mod dlf { + #[doc = "Reader of register dlf"] + pub type R = crate::R; + #[doc = "Writer for register dlf"] + pub type W = crate::W; + #[doc = "Register dlf `reset()`'s with value 0"] + impl crate::ResetValue for super::DLF { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive-Mode Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rar](rar) module"] + pub type RAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RAR; + #[doc = "`read()` method returns [rar::R](rar::R) reader structure"] + impl crate::Readable for RAR {} + #[doc = "`write(|w| ..)` method takes [rar::W](rar::W) writer structure"] + impl crate::Writable for RAR {} + #[doc = "Receive-Mode Address Register"] + pub mod rar { + #[doc = "Reader of register rar"] + pub type R = crate::R; + #[doc = "Writer for register rar"] + pub type W = crate::W; + #[doc = "Register rar `reset()`'s with value 0"] + impl crate::ResetValue for super::RAR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Transmit-Mode Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tar](tar) module"] + pub type TAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TAR; + #[doc = "`read()` method returns [tar::R](tar::R) reader structure"] + impl crate::Readable for TAR {} + #[doc = "`write(|w| ..)` method takes [tar::W](tar::W) writer structure"] + impl crate::Writable for TAR {} + #[doc = "Transmit-Mode Address Register"] + pub mod tar { + #[doc = "Reader of register tar"] + pub type R = crate::R; + #[doc = "Writer for register tar"] + pub type W = crate::W; + #[doc = "Register tar `reset()`'s with value 0"] + impl crate::ResetValue for super::TAR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Line Control Register (Extended)\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lcr_ext](lcr_ext) module"] + pub type LCR_EXT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LCR_EXT; + #[doc = "`read()` method returns [lcr_ext::R](lcr_ext::R) reader structure"] + impl crate::Readable for LCR_EXT {} + #[doc = "`write(|w| ..)` method takes [lcr_ext::W](lcr_ext::W) writer structure"] + impl crate::Writable for LCR_EXT {} + #[doc = "Line Control Register (Extended)"] + pub mod lcr_ext { + #[doc = "Reader of register lcr_ext"] + pub type R = crate::R; + #[doc = "Writer for register lcr_ext"] + pub type W = crate::W; + #[doc = "Register lcr_ext `reset()`'s with value 0"] + impl crate::ResetValue for super::LCR_EXT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Component Parameter Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpr](cpr) module"] + pub type CPR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CPR; + #[doc = "`read()` method returns [cpr::R](cpr::R) reader structure"] + impl crate::Readable for CPR {} + #[doc = "`write(|w| ..)` method takes [cpr::W](cpr::W) writer structure"] + impl crate::Writable for CPR {} + #[doc = "Component Parameter Register"] + pub mod cpr { + #[doc = "Reader of register cpr"] + pub type R = crate::R; + #[doc = "Writer for register cpr"] + pub type W = crate::W; + #[doc = "Register cpr `reset()`'s with value 0"] + impl crate::ResetValue for super::CPR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "UART Component Version\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ucv](ucv) module"] + pub type UCV = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _UCV; + #[doc = "`read()` method returns [ucv::R](ucv::R) reader structure"] + impl crate::Readable for UCV {} + #[doc = "`write(|w| ..)` method takes [ucv::W](ucv::W) writer structure"] + impl crate::Writable for UCV {} + #[doc = "UART Component Version"] + pub mod ucv { + #[doc = "Reader of register ucv"] + pub type R = crate::R; + #[doc = "Writer for register ucv"] + pub type W = crate::W; + #[doc = "Register ucv `reset()`'s with value 0"] + impl crate::ResetValue for super::UCV { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Component Type Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctr](ctr) module"] + pub type CTR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CTR; + #[doc = "`read()` method returns [ctr::R](ctr::R) reader structure"] + impl crate::Readable for CTR {} + #[doc = "`write(|w| ..)` method takes [ctr::W](ctr::W) writer structure"] + impl crate::Writable for CTR {} + #[doc = "Component Type Register"] + pub mod ctr { + #[doc = "Reader of register ctr"] + pub type R = crate::R; + #[doc = "Writer for register ctr"] + pub type W = crate::W; + #[doc = "Register ctr `reset()`'s with value 0"] + impl crate::ResetValue for super::CTR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Universal Asynchronous Receiver-Transmitter 2"] +pub struct UART2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART2 {} +impl UART2 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart1::RegisterBlock { + 0x5022_0000 as *const _ + } +} +impl Deref for UART2 { + type Target = uart1::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*UART2::ptr() } + } +} +#[doc = "Universal Asynchronous Receiver-Transmitter 3"] +pub struct UART3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART3 {} +impl UART3 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart1::RegisterBlock { + 0x5023_0000 as *const _ + } +} +impl Deref for UART3 { + type Target = uart1::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*UART3::ptr() } + } +} +#[doc = "Serial Peripheral Interface 0 (master)"] +pub struct SPI0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI0 {} +impl SPI0 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + 0x5200_0000 as *const _ + } +} +impl Deref for SPI0 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*SPI0::ptr() } + } +} +#[doc = "Serial Peripheral Interface 0 (master)"] +pub mod spi0 { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Control Register 0"] + pub ctrlr0: CTRLR0, + #[doc = "0x04 - Control Register 1"] + pub ctrlr1: CTRLR1, + #[doc = "0x08 - Enable Register"] + pub ssienr: SSIENR, + #[doc = "0x0c - Microwire Control Register"] + pub mwcr: MWCR, + #[doc = "0x10 - Slave Enable Register"] + pub ser: SER, + #[doc = "0x14 - Baud Rate Select"] + pub baudr: BAUDR, + #[doc = "0x18 - Transmit FIFO Threshold Level"] + pub txftlr: TXFTLR, + #[doc = "0x1c - Receive FIFO Threshold Level"] + pub rxftlr: RXFTLR, + #[doc = "0x20 - Transmit FIFO Level Register"] + pub txflr: TXFLR, + #[doc = "0x24 - Receive FIFO Level Register"] + pub rxflr: RXFLR, + #[doc = "0x28 - Status Register"] + pub sr: SR, + #[doc = "0x2c - Interrupt Mask Register"] + pub imr: IMR, + #[doc = "0x30 - Interrupt Status Register"] + pub isr: ISR, + #[doc = "0x34 - Raw Interrupt Status Register"] + pub risr: RISR, + #[doc = "0x38 - Transmit FIFO Overflow Interrupt Clear Register"] + pub txoicr: TXOICR, + #[doc = "0x3c - Receive FIFO Overflow Interrupt Clear Register"] + pub rxoicr: RXOICR, + #[doc = "0x40 - Receive FIFO Underflow Interrupt Clear Register"] + pub rxuicr: RXUICR, + #[doc = "0x44 - Multi-Master Interrupt Clear Register"] + pub msticr: MSTICR, + #[doc = "0x48 - Interrupt Clear Register"] + pub icr: ICR, + #[doc = "0x4c - DMA Control Register"] + pub dmacr: DMACR, + #[doc = "0x50 - DMA Transmit Data Level"] + pub dmatdlr: DMATDLR, + #[doc = "0x54 - DMA Receive Data Level"] + pub dmardlr: DMARDLR, + #[doc = "0x58 - Identification Register"] + pub idr: IDR, + #[doc = "0x5c - DWC_ssi component version"] + pub ssic_version_id: SSIC_VERSION_ID, + #[doc = "0x60 - Data Register"] + pub dr: [DR; 36], + #[doc = "0xf0 - RX Sample Delay Register"] + pub rx_sample_delay: RX_SAMPLE_DELAY, + #[doc = "0xf4 - SPI Control Register"] + pub spi_ctrlr0: SPI_CTRLR0, + _reserved27: [u8; 4usize], + #[doc = "0xfc - XIP Mode bits"] + pub xip_mode_bits: XIP_MODE_BITS, + #[doc = "0x100 - XIP INCR transfer opcode"] + pub xip_incr_inst: XIP_INCR_INST, + #[doc = "0x104 - XIP WRAP transfer opcode"] + pub xip_wrap_inst: XIP_WRAP_INST, + #[doc = "0x108 - XIP Control Register"] + pub xip_ctrl: XIP_CTRL, + #[doc = "0x10c - XIP Slave Enable Register"] + pub xip_ser: XIP_SER, + #[doc = "0x110 - XIP Receive FIFO Overflow Interrupt Clear Register"] + pub xrxoicr: XRXOICR, + #[doc = "0x114 - XIP time out register for continuous transfers"] + pub xip_cnt_time_out: XIP_CNT_TIME_OUT, + #[doc = "0x118 - ENDIAN"] + pub endian: ENDIAN, + } + #[doc = "Control Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlr0](ctrlr0) module"] + pub type CTRLR0 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CTRLR0; + #[doc = "`read()` method returns [ctrlr0::R](ctrlr0::R) reader structure"] + impl crate::Readable for CTRLR0 {} + #[doc = "`write(|w| ..)` method takes [ctrlr0::W](ctrlr0::W) writer structure"] + impl crate::Writable for CTRLR0 {} + #[doc = "Control Register 0"] + pub mod ctrlr0 { + #[doc = "Reader of register ctrlr0"] + pub type R = crate::R; + #[doc = "Writer for register ctrlr0"] + pub type W = crate::W; + #[doc = "Register ctrlr0 `reset()`'s with value 0"] + impl crate::ResetValue for super::CTRLR0 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "WORK_MODE\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum WORK_MODE_A { + #[doc = "0: MODE_0"] + MODE0 = 0, + #[doc = "1: MODE_1"] + MODE1 = 1, + #[doc = "2: MODE_2"] + MODE2 = 2, + #[doc = "3: MODE_3"] + MODE3 = 3, + } + impl From for u8 { + #[inline(always)] + fn from(variant: WORK_MODE_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `work_mode`"] + pub type WORK_MODE_R = crate::R; + impl WORK_MODE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WORK_MODE_A { + match self.bits { + 0 => WORK_MODE_A::MODE0, + 1 => WORK_MODE_A::MODE1, + 2 => WORK_MODE_A::MODE2, + 3 => WORK_MODE_A::MODE3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `MODE0`"] + #[inline(always)] + pub fn is_mode0(&self) -> bool { + *self == WORK_MODE_A::MODE0 + } + #[doc = "Checks if the value of the field is `MODE1`"] + #[inline(always)] + pub fn is_mode1(&self) -> bool { + *self == WORK_MODE_A::MODE1 + } + #[doc = "Checks if the value of the field is `MODE2`"] + #[inline(always)] + pub fn is_mode2(&self) -> bool { + *self == WORK_MODE_A::MODE2 + } + #[doc = "Checks if the value of the field is `MODE3`"] + #[inline(always)] + pub fn is_mode3(&self) -> bool { + *self == WORK_MODE_A::MODE3 + } + } + #[doc = "Write proxy for field `work_mode`"] + pub struct WORK_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> WORK_MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WORK_MODE_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "MODE_0"] + #[inline(always)] + pub fn mode0(self) -> &'a mut W { + self.variant(WORK_MODE_A::MODE0) + } + #[doc = "MODE_1"] + #[inline(always)] + pub fn mode1(self) -> &'a mut W { + self.variant(WORK_MODE_A::MODE1) + } + #[doc = "MODE_2"] + #[inline(always)] + pub fn mode2(self) -> &'a mut W { + self.variant(WORK_MODE_A::MODE2) + } + #[doc = "MODE_3"] + #[inline(always)] + pub fn mode3(self) -> &'a mut W { + self.variant(WORK_MODE_A::MODE3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6); + self.w + } + } + #[doc = "TRANSFER_MODE\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum TMOD_A { + #[doc = "0: TRANS_RECV"] + TRANS_RECV = 0, + #[doc = "1: TRANS"] + TRANS = 1, + #[doc = "2: RECV"] + RECV = 2, + #[doc = "3: EEROM"] + EEROM = 3, + } + impl From for u8 { + #[inline(always)] + fn from(variant: TMOD_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `tmod`"] + pub type TMOD_R = crate::R; + impl TMOD_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TMOD_A { + match self.bits { + 0 => TMOD_A::TRANS_RECV, + 1 => TMOD_A::TRANS, + 2 => TMOD_A::RECV, + 3 => TMOD_A::EEROM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `TRANS_RECV`"] + #[inline(always)] + pub fn is_trans_recv(&self) -> bool { + *self == TMOD_A::TRANS_RECV + } + #[doc = "Checks if the value of the field is `TRANS`"] + #[inline(always)] + pub fn is_trans(&self) -> bool { + *self == TMOD_A::TRANS + } + #[doc = "Checks if the value of the field is `RECV`"] + #[inline(always)] + pub fn is_recv(&self) -> bool { + *self == TMOD_A::RECV + } + #[doc = "Checks if the value of the field is `EEROM`"] + #[inline(always)] + pub fn is_eerom(&self) -> bool { + *self == TMOD_A::EEROM + } + } + #[doc = "Write proxy for field `tmod`"] + pub struct TMOD_W<'a> { + w: &'a mut W, + } + impl<'a> TMOD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TMOD_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "TRANS_RECV"] + #[inline(always)] + pub fn trans_recv(self) -> &'a mut W { + self.variant(TMOD_A::TRANS_RECV) + } + #[doc = "TRANS"] + #[inline(always)] + pub fn trans(self) -> &'a mut W { + self.variant(TMOD_A::TRANS) + } + #[doc = "RECV"] + #[inline(always)] + pub fn recv(self) -> &'a mut W { + self.variant(TMOD_A::RECV) + } + #[doc = "EEROM"] + #[inline(always)] + pub fn eerom(self) -> &'a mut W { + self.variant(TMOD_A::EEROM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8); + self.w + } + } + #[doc = "FRAME_FORMAT\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum FRAME_FORMAT_A { + #[doc = "0: STANDARD"] + STANDARD = 0, + #[doc = "1: DUAL"] + DUAL = 1, + #[doc = "2: QUAD"] + QUAD = 2, + #[doc = "3: OCTAL"] + OCTAL = 3, + } + impl From for u8 { + #[inline(always)] + fn from(variant: FRAME_FORMAT_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `frame_format`"] + pub type FRAME_FORMAT_R = crate::R; + impl FRAME_FORMAT_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FRAME_FORMAT_A { + match self.bits { + 0 => FRAME_FORMAT_A::STANDARD, + 1 => FRAME_FORMAT_A::DUAL, + 2 => FRAME_FORMAT_A::QUAD, + 3 => FRAME_FORMAT_A::OCTAL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `STANDARD`"] + #[inline(always)] + pub fn is_standard(&self) -> bool { + *self == FRAME_FORMAT_A::STANDARD + } + #[doc = "Checks if the value of the field is `DUAL`"] + #[inline(always)] + pub fn is_dual(&self) -> bool { + *self == FRAME_FORMAT_A::DUAL + } + #[doc = "Checks if the value of the field is `QUAD`"] + #[inline(always)] + pub fn is_quad(&self) -> bool { + *self == FRAME_FORMAT_A::QUAD + } + #[doc = "Checks if the value of the field is `OCTAL`"] + #[inline(always)] + pub fn is_octal(&self) -> bool { + *self == FRAME_FORMAT_A::OCTAL + } + } + #[doc = "Write proxy for field `frame_format`"] + pub struct FRAME_FORMAT_W<'a> { + w: &'a mut W, + } + impl<'a> FRAME_FORMAT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FRAME_FORMAT_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "STANDARD"] + #[inline(always)] + pub fn standard(self) -> &'a mut W { + self.variant(FRAME_FORMAT_A::STANDARD) + } + #[doc = "DUAL"] + #[inline(always)] + pub fn dual(self) -> &'a mut W { + self.variant(FRAME_FORMAT_A::DUAL) + } + #[doc = "QUAD"] + #[inline(always)] + pub fn quad(self) -> &'a mut W { + self.variant(FRAME_FORMAT_A::QUAD) + } + #[doc = "OCTAL"] + #[inline(always)] + pub fn octal(self) -> &'a mut W { + self.variant(FRAME_FORMAT_A::OCTAL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 21)) | (((value as u32) & 0x03) << 21); + self.w + } + } + #[doc = "Reader of field `data_length`"] + pub type DATA_LENGTH_R = crate::R; + #[doc = "Write proxy for field `data_length`"] + pub struct DATA_LENGTH_W<'a> { + w: &'a mut W, + } + impl<'a> DATA_LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 16)) | (((value as u32) & 0x1f) << 16); + self.w + } + } + impl R { + #[doc = "Bits 6:7 - WORK_MODE"] + #[inline(always)] + pub fn work_mode(&self) -> WORK_MODE_R { + WORK_MODE_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bits 8:9 - TRANSFER_MODE"] + #[inline(always)] + pub fn tmod(&self) -> TMOD_R { + TMOD_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 21:22 - FRAME_FORMAT"] + #[inline(always)] + pub fn frame_format(&self) -> FRAME_FORMAT_R { + FRAME_FORMAT_R::new(((self.bits >> 21) & 0x03) as u8) + } + #[doc = "Bits 16:20 - DATA_BIT_LENGTH"] + #[inline(always)] + pub fn data_length(&self) -> DATA_LENGTH_R { + DATA_LENGTH_R::new(((self.bits >> 16) & 0x1f) as u8) + } + } + impl W { + #[doc = "Bits 6:7 - WORK_MODE"] + #[inline(always)] + pub fn work_mode(&mut self) -> WORK_MODE_W { + WORK_MODE_W { w: self } + } + #[doc = "Bits 8:9 - TRANSFER_MODE"] + #[inline(always)] + pub fn tmod(&mut self) -> TMOD_W { + TMOD_W { w: self } + } + #[doc = "Bits 21:22 - FRAME_FORMAT"] + #[inline(always)] + pub fn frame_format(&mut self) -> FRAME_FORMAT_W { + FRAME_FORMAT_W { w: self } + } + #[doc = "Bits 16:20 - DATA_BIT_LENGTH"] + #[inline(always)] + pub fn data_length(&mut self) -> DATA_LENGTH_W { + DATA_LENGTH_W { w: self } + } + } + } + #[doc = "Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlr1](ctrlr1) module"] + pub type CTRLR1 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CTRLR1; + #[doc = "`read()` method returns [ctrlr1::R](ctrlr1::R) reader structure"] + impl crate::Readable for CTRLR1 {} + #[doc = "`write(|w| ..)` method takes [ctrlr1::W](ctrlr1::W) writer structure"] + impl crate::Writable for CTRLR1 {} + #[doc = "Control Register 1"] + pub mod ctrlr1 { + #[doc = "Reader of register ctrlr1"] + pub type R = crate::R; + #[doc = "Writer for register ctrlr1"] + pub type W = crate::W; + #[doc = "Register ctrlr1 `reset()`'s with value 0"] + impl crate::ResetValue for super::CTRLR1 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ssienr](ssienr) module"] + pub type SSIENR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SSIENR; + #[doc = "`read()` method returns [ssienr::R](ssienr::R) reader structure"] + impl crate::Readable for SSIENR {} + #[doc = "`write(|w| ..)` method takes [ssienr::W](ssienr::W) writer structure"] + impl crate::Writable for SSIENR {} + #[doc = "Enable Register"] + pub mod ssienr { + #[doc = "Reader of register ssienr"] + pub type R = crate::R; + #[doc = "Writer for register ssienr"] + pub type W = crate::W; + #[doc = "Register ssienr `reset()`'s with value 0"] + impl crate::ResetValue for super::SSIENR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Microwire Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mwcr](mwcr) module"] + pub type MWCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _MWCR; + #[doc = "`read()` method returns [mwcr::R](mwcr::R) reader structure"] + impl crate::Readable for MWCR {} + #[doc = "`write(|w| ..)` method takes [mwcr::W](mwcr::W) writer structure"] + impl crate::Writable for MWCR {} + #[doc = "Microwire Control Register"] + pub mod mwcr { + #[doc = "Reader of register mwcr"] + pub type R = crate::R; + #[doc = "Writer for register mwcr"] + pub type W = crate::W; + #[doc = "Register mwcr `reset()`'s with value 0"] + impl crate::ResetValue for super::MWCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Slave Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ser](ser) module"] + pub type SER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SER; + #[doc = "`read()` method returns [ser::R](ser::R) reader structure"] + impl crate::Readable for SER {} + #[doc = "`write(|w| ..)` method takes [ser::W](ser::W) writer structure"] + impl crate::Writable for SER {} + #[doc = "Slave Enable Register"] + pub mod ser { + #[doc = "Reader of register ser"] + pub type R = crate::R; + #[doc = "Writer for register ser"] + pub type W = crate::W; + #[doc = "Register ser `reset()`'s with value 0"] + impl crate::ResetValue for super::SER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Baud Rate Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baudr](baudr) module"] + pub type BAUDR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _BAUDR; + #[doc = "`read()` method returns [baudr::R](baudr::R) reader structure"] + impl crate::Readable for BAUDR {} + #[doc = "`write(|w| ..)` method takes [baudr::W](baudr::W) writer structure"] + impl crate::Writable for BAUDR {} + #[doc = "Baud Rate Select"] + pub mod baudr { + #[doc = "Reader of register baudr"] + pub type R = crate::R; + #[doc = "Writer for register baudr"] + pub type W = crate::W; + #[doc = "Register baudr `reset()`'s with value 0"] + impl crate::ResetValue for super::BAUDR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Transmit FIFO Threshold Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txftlr](txftlr) module"] + pub type TXFTLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TXFTLR; + #[doc = "`read()` method returns [txftlr::R](txftlr::R) reader structure"] + impl crate::Readable for TXFTLR {} + #[doc = "`write(|w| ..)` method takes [txftlr::W](txftlr::W) writer structure"] + impl crate::Writable for TXFTLR {} + #[doc = "Transmit FIFO Threshold Level"] + pub mod txftlr { + #[doc = "Reader of register txftlr"] + pub type R = crate::R; + #[doc = "Writer for register txftlr"] + pub type W = crate::W; + #[doc = "Register txftlr `reset()`'s with value 0"] + impl crate::ResetValue for super::TXFTLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive FIFO Threshold Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxftlr](rxftlr) module"] + pub type RXFTLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXFTLR; + #[doc = "`read()` method returns [rxftlr::R](rxftlr::R) reader structure"] + impl crate::Readable for RXFTLR {} + #[doc = "`write(|w| ..)` method takes [rxftlr::W](rxftlr::W) writer structure"] + impl crate::Writable for RXFTLR {} + #[doc = "Receive FIFO Threshold Level"] + pub mod rxftlr { + #[doc = "Reader of register rxftlr"] + pub type R = crate::R; + #[doc = "Writer for register rxftlr"] + pub type W = crate::W; + #[doc = "Register rxftlr `reset()`'s with value 0"] + impl crate::ResetValue for super::RXFTLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Transmit FIFO Level Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txflr](txflr) module"] + pub type TXFLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TXFLR; + #[doc = "`read()` method returns [txflr::R](txflr::R) reader structure"] + impl crate::Readable for TXFLR {} + #[doc = "`write(|w| ..)` method takes [txflr::W](txflr::W) writer structure"] + impl crate::Writable for TXFLR {} + #[doc = "Transmit FIFO Level Register"] + pub mod txflr { + #[doc = "Reader of register txflr"] + pub type R = crate::R; + #[doc = "Writer for register txflr"] + pub type W = crate::W; + #[doc = "Register txflr `reset()`'s with value 0"] + impl crate::ResetValue for super::TXFLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive FIFO Level Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxflr](rxflr) module"] + pub type RXFLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXFLR; + #[doc = "`read()` method returns [rxflr::R](rxflr::R) reader structure"] + impl crate::Readable for RXFLR {} + #[doc = "`write(|w| ..)` method takes [rxflr::W](rxflr::W) writer structure"] + impl crate::Writable for RXFLR {} + #[doc = "Receive FIFO Level Register"] + pub mod rxflr { + #[doc = "Reader of register rxflr"] + pub type R = crate::R; + #[doc = "Writer for register rxflr"] + pub type W = crate::W; + #[doc = "Register rxflr `reset()`'s with value 0"] + impl crate::ResetValue for super::RXFLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](sr) module"] + pub type SR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SR; + #[doc = "`read()` method returns [sr::R](sr::R) reader structure"] + impl crate::Readable for SR {} + #[doc = "`write(|w| ..)` method takes [sr::W](sr::W) writer structure"] + impl crate::Writable for SR {} + #[doc = "Status Register"] + pub mod sr { + #[doc = "Reader of register sr"] + pub type R = crate::R; + #[doc = "Writer for register sr"] + pub type W = crate::W; + #[doc = "Register sr `reset()`'s with value 0"] + impl crate::ResetValue for super::SR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](imr) module"] + pub type IMR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IMR; + #[doc = "`read()` method returns [imr::R](imr::R) reader structure"] + impl crate::Readable for IMR {} + #[doc = "`write(|w| ..)` method takes [imr::W](imr::W) writer structure"] + impl crate::Writable for IMR {} + #[doc = "Interrupt Mask Register"] + pub mod imr { + #[doc = "Reader of register imr"] + pub type R = crate::R; + #[doc = "Writer for register imr"] + pub type W = crate::W; + #[doc = "Register imr `reset()`'s with value 0"] + impl crate::ResetValue for super::IMR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr](isr) module"] + pub type ISR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ISR; + #[doc = "`read()` method returns [isr::R](isr::R) reader structure"] + impl crate::Readable for ISR {} + #[doc = "`write(|w| ..)` method takes [isr::W](isr::W) writer structure"] + impl crate::Writable for ISR {} + #[doc = "Interrupt Status Register"] + pub mod isr { + #[doc = "Reader of register isr"] + pub type R = crate::R; + #[doc = "Writer for register isr"] + pub type W = crate::W; + #[doc = "Register isr `reset()`'s with value 0"] + impl crate::ResetValue for super::ISR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Raw Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [risr](risr) module"] + pub type RISR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RISR; + #[doc = "`read()` method returns [risr::R](risr::R) reader structure"] + impl crate::Readable for RISR {} + #[doc = "`write(|w| ..)` method takes [risr::W](risr::W) writer structure"] + impl crate::Writable for RISR {} + #[doc = "Raw Interrupt Status Register"] + pub mod risr { + #[doc = "Reader of register risr"] + pub type R = crate::R; + #[doc = "Writer for register risr"] + pub type W = crate::W; + #[doc = "Register risr `reset()`'s with value 0"] + impl crate::ResetValue for super::RISR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Transmit FIFO Overflow Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txoicr](txoicr) module"] + pub type TXOICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TXOICR; + #[doc = "`read()` method returns [txoicr::R](txoicr::R) reader structure"] + impl crate::Readable for TXOICR {} + #[doc = "`write(|w| ..)` method takes [txoicr::W](txoicr::W) writer structure"] + impl crate::Writable for TXOICR {} + #[doc = "Transmit FIFO Overflow Interrupt Clear Register"] + pub mod txoicr { + #[doc = "Reader of register txoicr"] + pub type R = crate::R; + #[doc = "Writer for register txoicr"] + pub type W = crate::W; + #[doc = "Register txoicr `reset()`'s with value 0"] + impl crate::ResetValue for super::TXOICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive FIFO Overflow Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxoicr](rxoicr) module"] + pub type RXOICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXOICR; + #[doc = "`read()` method returns [rxoicr::R](rxoicr::R) reader structure"] + impl crate::Readable for RXOICR {} + #[doc = "`write(|w| ..)` method takes [rxoicr::W](rxoicr::W) writer structure"] + impl crate::Writable for RXOICR {} + #[doc = "Receive FIFO Overflow Interrupt Clear Register"] + pub mod rxoicr { + #[doc = "Reader of register rxoicr"] + pub type R = crate::R; + #[doc = "Writer for register rxoicr"] + pub type W = crate::W; + #[doc = "Register rxoicr `reset()`'s with value 0"] + impl crate::ResetValue for super::RXOICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive FIFO Underflow Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxuicr](rxuicr) module"] + pub type RXUICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXUICR; + #[doc = "`read()` method returns [rxuicr::R](rxuicr::R) reader structure"] + impl crate::Readable for RXUICR {} + #[doc = "`write(|w| ..)` method takes [rxuicr::W](rxuicr::W) writer structure"] + impl crate::Writable for RXUICR {} + #[doc = "Receive FIFO Underflow Interrupt Clear Register"] + pub mod rxuicr { + #[doc = "Reader of register rxuicr"] + pub type R = crate::R; + #[doc = "Writer for register rxuicr"] + pub type W = crate::W; + #[doc = "Register rxuicr `reset()`'s with value 0"] + impl crate::ResetValue for super::RXUICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Multi-Master Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msticr](msticr) module"] + pub type MSTICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _MSTICR; + #[doc = "`read()` method returns [msticr::R](msticr::R) reader structure"] + impl crate::Readable for MSTICR {} + #[doc = "`write(|w| ..)` method takes [msticr::W](msticr::W) writer structure"] + impl crate::Writable for MSTICR {} + #[doc = "Multi-Master Interrupt Clear Register"] + pub mod msticr { + #[doc = "Reader of register msticr"] + pub type R = crate::R; + #[doc = "Writer for register msticr"] + pub type W = crate::W; + #[doc = "Register msticr `reset()`'s with value 0"] + impl crate::ResetValue for super::MSTICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icr](icr) module"] + pub type ICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ICR; + #[doc = "`read()` method returns [icr::R](icr::R) reader structure"] + impl crate::Readable for ICR {} + #[doc = "`write(|w| ..)` method takes [icr::W](icr::W) writer structure"] + impl crate::Writable for ICR {} + #[doc = "Interrupt Clear Register"] + pub mod icr { + #[doc = "Reader of register icr"] + pub type R = crate::R; + #[doc = "Writer for register icr"] + pub type W = crate::W; + #[doc = "Register icr `reset()`'s with value 0"] + impl crate::ResetValue for super::ICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DMA Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmacr](dmacr) module"] + pub type DMACR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMACR; + #[doc = "`read()` method returns [dmacr::R](dmacr::R) reader structure"] + impl crate::Readable for DMACR {} + #[doc = "`write(|w| ..)` method takes [dmacr::W](dmacr::W) writer structure"] + impl crate::Writable for DMACR {} + #[doc = "DMA Control Register"] + pub mod dmacr { + #[doc = "Reader of register dmacr"] + pub type R = crate::R; + #[doc = "Writer for register dmacr"] + pub type W = crate::W; + #[doc = "Register dmacr `reset()`'s with value 0"] + impl crate::ResetValue for super::DMACR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DMA Transmit Data Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmatdlr](dmatdlr) module"] + pub type DMATDLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMATDLR; + #[doc = "`read()` method returns [dmatdlr::R](dmatdlr::R) reader structure"] + impl crate::Readable for DMATDLR {} + #[doc = "`write(|w| ..)` method takes [dmatdlr::W](dmatdlr::W) writer structure"] + impl crate::Writable for DMATDLR {} + #[doc = "DMA Transmit Data Level"] + pub mod dmatdlr { + #[doc = "Reader of register dmatdlr"] + pub type R = crate::R; + #[doc = "Writer for register dmatdlr"] + pub type W = crate::W; + #[doc = "Register dmatdlr `reset()`'s with value 0"] + impl crate::ResetValue for super::DMATDLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DMA Receive Data Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmardlr](dmardlr) module"] + pub type DMARDLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMARDLR; + #[doc = "`read()` method returns [dmardlr::R](dmardlr::R) reader structure"] + impl crate::Readable for DMARDLR {} + #[doc = "`write(|w| ..)` method takes [dmardlr::W](dmardlr::W) writer structure"] + impl crate::Writable for DMARDLR {} + #[doc = "DMA Receive Data Level"] + pub mod dmardlr { + #[doc = "Reader of register dmardlr"] + pub type R = crate::R; + #[doc = "Writer for register dmardlr"] + pub type W = crate::W; + #[doc = "Register dmardlr `reset()`'s with value 0"] + impl crate::ResetValue for super::DMARDLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Identification Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](idr) module"] + pub type IDR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IDR; + #[doc = "`read()` method returns [idr::R](idr::R) reader structure"] + impl crate::Readable for IDR {} + #[doc = "`write(|w| ..)` method takes [idr::W](idr::W) writer structure"] + impl crate::Writable for IDR {} + #[doc = "Identification Register"] + pub mod idr { + #[doc = "Reader of register idr"] + pub type R = crate::R; + #[doc = "Writer for register idr"] + pub type W = crate::W; + #[doc = "Register idr `reset()`'s with value 0"] + impl crate::ResetValue for super::IDR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DWC_ssi component version\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ssic_version_id](ssic_version_id) module"] + pub type SSIC_VERSION_ID = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SSIC_VERSION_ID; + #[doc = "`read()` method returns [ssic_version_id::R](ssic_version_id::R) reader structure"] + impl crate::Readable for SSIC_VERSION_ID {} + #[doc = "`write(|w| ..)` method takes [ssic_version_id::W](ssic_version_id::W) writer structure"] + impl crate::Writable for SSIC_VERSION_ID {} + #[doc = "DWC_ssi component version"] + pub mod ssic_version_id { + #[doc = "Reader of register ssic_version_id"] + pub type R = crate::R; + #[doc = "Writer for register ssic_version_id"] + pub type W = crate::W; + #[doc = "Register ssic_version_id `reset()`'s with value 0"] + impl crate::ResetValue for super::SSIC_VERSION_ID { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Data Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr](dr) module"] + pub type DR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DR; + #[doc = "`read()` method returns [dr::R](dr::R) reader structure"] + impl crate::Readable for DR {} + #[doc = "`write(|w| ..)` method takes [dr::W](dr::W) writer structure"] + impl crate::Writable for DR {} + #[doc = "Data Register"] + pub mod dr { + #[doc = "Reader of register dr%s"] + pub type R = crate::R; + #[doc = "Writer for register dr%s"] + pub type W = crate::W; + #[doc = "Register dr%s `reset()`'s with value 0"] + impl crate::ResetValue for super::DR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "RX Sample Delay Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rx_sample_delay](rx_sample_delay) module"] + pub type RX_SAMPLE_DELAY = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RX_SAMPLE_DELAY; + #[doc = "`read()` method returns [rx_sample_delay::R](rx_sample_delay::R) reader structure"] + impl crate::Readable for RX_SAMPLE_DELAY {} + #[doc = "`write(|w| ..)` method takes [rx_sample_delay::W](rx_sample_delay::W) writer structure"] + impl crate::Writable for RX_SAMPLE_DELAY {} + #[doc = "RX Sample Delay Register"] + pub mod rx_sample_delay { + #[doc = "Reader of register rx_sample_delay"] + pub type R = crate::R; + #[doc = "Writer for register rx_sample_delay"] + pub type W = crate::W; + #[doc = "Register rx_sample_delay `reset()`'s with value 0"] + impl crate::ResetValue for super::RX_SAMPLE_DELAY { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "SPI Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spi_ctrlr0](spi_ctrlr0) module"] + pub type SPI_CTRLR0 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SPI_CTRLR0; + #[doc = "`read()` method returns [spi_ctrlr0::R](spi_ctrlr0::R) reader structure"] + impl crate::Readable for SPI_CTRLR0 {} + #[doc = "`write(|w| ..)` method takes [spi_ctrlr0::W](spi_ctrlr0::W) writer structure"] + impl crate::Writable for SPI_CTRLR0 {} + #[doc = "SPI Control Register"] + pub mod spi_ctrlr0 { + #[doc = "Reader of register spi_ctrlr0"] + pub type R = crate::R; + #[doc = "Writer for register spi_ctrlr0"] + pub type W = crate::W; + #[doc = "Register spi_ctrlr0 `reset()`'s with value 0"] + impl crate::ResetValue for super::SPI_CTRLR0 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "instruction_address_trans_mode\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum AITM_A { + #[doc = "0: STANDARD"] + STANDARD = 0, + #[doc = "1: ADDR_STANDARD"] + ADDR_STANDARD = 1, + #[doc = "2: AS_FRAME_FORMAT"] + AS_FRAME_FORMAT = 2, + } + impl From for u8 { + #[inline(always)] + fn from(variant: AITM_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `aitm`"] + pub type AITM_R = crate::R; + impl AITM_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(AITM_A::STANDARD), + 1 => Val(AITM_A::ADDR_STANDARD), + 2 => Val(AITM_A::AS_FRAME_FORMAT), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `STANDARD`"] + #[inline(always)] + pub fn is_standard(&self) -> bool { + *self == AITM_A::STANDARD + } + #[doc = "Checks if the value of the field is `ADDR_STANDARD`"] + #[inline(always)] + pub fn is_addr_standard(&self) -> bool { + *self == AITM_A::ADDR_STANDARD + } + #[doc = "Checks if the value of the field is `AS_FRAME_FORMAT`"] + #[inline(always)] + pub fn is_as_frame_format(&self) -> bool { + *self == AITM_A::AS_FRAME_FORMAT + } + } + #[doc = "Write proxy for field `aitm`"] + pub struct AITM_W<'a> { + w: &'a mut W, + } + impl<'a> AITM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AITM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "STANDARD"] + #[inline(always)] + pub fn standard(self) -> &'a mut W { + self.variant(AITM_A::STANDARD) + } + #[doc = "ADDR_STANDARD"] + #[inline(always)] + pub fn addr_standard(self) -> &'a mut W { + self.variant(AITM_A::ADDR_STANDARD) + } + #[doc = "AS_FRAME_FORMAT"] + #[inline(always)] + pub fn as_frame_format(self) -> &'a mut W { + self.variant(AITM_A::AS_FRAME_FORMAT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03); + self.w + } + } + #[doc = "Reader of field `addr_length`"] + pub type ADDR_LENGTH_R = crate::R; + #[doc = "Write proxy for field `addr_length`"] + pub struct ADDR_LENGTH_W<'a> { + w: &'a mut W, + } + impl<'a> ADDR_LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 2)) | (((value as u32) & 0x0f) << 2); + self.w + } + } + #[doc = "Reader of field `inst_length`"] + pub type INST_LENGTH_R = crate::R; + #[doc = "Write proxy for field `inst_length`"] + pub struct INST_LENGTH_W<'a> { + w: &'a mut W, + } + impl<'a> INST_LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8); + self.w + } + } + #[doc = "Reader of field `wait_cycles`"] + pub type WAIT_CYCLES_R = crate::R; + #[doc = "Write proxy for field `wait_cycles`"] + pub struct WAIT_CYCLES_W<'a> { + w: &'a mut W, + } + impl<'a> WAIT_CYCLES_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 11)) | (((value as u32) & 0x1f) << 11); + self.w + } + } + impl R { + #[doc = "Bits 0:1 - instruction_address_trans_mode"] + #[inline(always)] + pub fn aitm(&self) -> AITM_R { + AITM_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:5 - ADDR_LENGTH"] + #[inline(always)] + pub fn addr_length(&self) -> ADDR_LENGTH_R { + ADDR_LENGTH_R::new(((self.bits >> 2) & 0x0f) as u8) + } + #[doc = "Bits 8:9 - INSTRUCTION_LENGTH"] + #[inline(always)] + pub fn inst_length(&self) -> INST_LENGTH_R { + INST_LENGTH_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 11:15 - WAIT_CYCLES"] + #[inline(always)] + pub fn wait_cycles(&self) -> WAIT_CYCLES_R { + WAIT_CYCLES_R::new(((self.bits >> 11) & 0x1f) as u8) + } + } + impl W { + #[doc = "Bits 0:1 - instruction_address_trans_mode"] + #[inline(always)] + pub fn aitm(&mut self) -> AITM_W { + AITM_W { w: self } + } + #[doc = "Bits 2:5 - ADDR_LENGTH"] + #[inline(always)] + pub fn addr_length(&mut self) -> ADDR_LENGTH_W { + ADDR_LENGTH_W { w: self } + } + #[doc = "Bits 8:9 - INSTRUCTION_LENGTH"] + #[inline(always)] + pub fn inst_length(&mut self) -> INST_LENGTH_W { + INST_LENGTH_W { w: self } + } + #[doc = "Bits 11:15 - WAIT_CYCLES"] + #[inline(always)] + pub fn wait_cycles(&mut self) -> WAIT_CYCLES_W { + WAIT_CYCLES_W { w: self } + } + } + } + #[doc = "XIP Mode bits\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_mode_bits](xip_mode_bits) module"] + pub type XIP_MODE_BITS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_MODE_BITS; + #[doc = "`read()` method returns [xip_mode_bits::R](xip_mode_bits::R) reader structure"] + impl crate::Readable for XIP_MODE_BITS {} + #[doc = "`write(|w| ..)` method takes [xip_mode_bits::W](xip_mode_bits::W) writer structure"] + impl crate::Writable for XIP_MODE_BITS {} + #[doc = "XIP Mode bits"] + pub mod xip_mode_bits { + #[doc = "Reader of register xip_mode_bits"] + pub type R = crate::R; + #[doc = "Writer for register xip_mode_bits"] + pub type W = crate::W; + #[doc = "Register xip_mode_bits `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_MODE_BITS { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP INCR transfer opcode\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_incr_inst](xip_incr_inst) module"] + pub type XIP_INCR_INST = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_INCR_INST; + #[doc = "`read()` method returns [xip_incr_inst::R](xip_incr_inst::R) reader structure"] + impl crate::Readable for XIP_INCR_INST {} + #[doc = "`write(|w| ..)` method takes [xip_incr_inst::W](xip_incr_inst::W) writer structure"] + impl crate::Writable for XIP_INCR_INST {} + #[doc = "XIP INCR transfer opcode"] + pub mod xip_incr_inst { + #[doc = "Reader of register xip_incr_inst"] + pub type R = crate::R; + #[doc = "Writer for register xip_incr_inst"] + pub type W = crate::W; + #[doc = "Register xip_incr_inst `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_INCR_INST { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP WRAP transfer opcode\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_wrap_inst](xip_wrap_inst) module"] + pub type XIP_WRAP_INST = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_WRAP_INST; + #[doc = "`read()` method returns [xip_wrap_inst::R](xip_wrap_inst::R) reader structure"] + impl crate::Readable for XIP_WRAP_INST {} + #[doc = "`write(|w| ..)` method takes [xip_wrap_inst::W](xip_wrap_inst::W) writer structure"] + impl crate::Writable for XIP_WRAP_INST {} + #[doc = "XIP WRAP transfer opcode"] + pub mod xip_wrap_inst { + #[doc = "Reader of register xip_wrap_inst"] + pub type R = crate::R; + #[doc = "Writer for register xip_wrap_inst"] + pub type W = crate::W; + #[doc = "Register xip_wrap_inst `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_WRAP_INST { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_ctrl](xip_ctrl) module"] + pub type XIP_CTRL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_CTRL; + #[doc = "`read()` method returns [xip_ctrl::R](xip_ctrl::R) reader structure"] + impl crate::Readable for XIP_CTRL {} + #[doc = "`write(|w| ..)` method takes [xip_ctrl::W](xip_ctrl::W) writer structure"] + impl crate::Writable for XIP_CTRL {} + #[doc = "XIP Control Register"] + pub mod xip_ctrl { + #[doc = "Reader of register xip_ctrl"] + pub type R = crate::R; + #[doc = "Writer for register xip_ctrl"] + pub type W = crate::W; + #[doc = "Register xip_ctrl `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_CTRL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP Slave Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_ser](xip_ser) module"] + pub type XIP_SER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_SER; + #[doc = "`read()` method returns [xip_ser::R](xip_ser::R) reader structure"] + impl crate::Readable for XIP_SER {} + #[doc = "`write(|w| ..)` method takes [xip_ser::W](xip_ser::W) writer structure"] + impl crate::Writable for XIP_SER {} + #[doc = "XIP Slave Enable Register"] + pub mod xip_ser { + #[doc = "Reader of register xip_ser"] + pub type R = crate::R; + #[doc = "Writer for register xip_ser"] + pub type W = crate::W; + #[doc = "Register xip_ser `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_SER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP Receive FIFO Overflow Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xrxoicr](xrxoicr) module"] + pub type XRXOICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XRXOICR; + #[doc = "`read()` method returns [xrxoicr::R](xrxoicr::R) reader structure"] + impl crate::Readable for XRXOICR {} + #[doc = "`write(|w| ..)` method takes [xrxoicr::W](xrxoicr::W) writer structure"] + impl crate::Writable for XRXOICR {} + #[doc = "XIP Receive FIFO Overflow Interrupt Clear Register"] + pub mod xrxoicr { + #[doc = "Reader of register xrxoicr"] + pub type R = crate::R; + #[doc = "Writer for register xrxoicr"] + pub type W = crate::W; + #[doc = "Register xrxoicr `reset()`'s with value 0"] + impl crate::ResetValue for super::XRXOICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP time out register for continuous transfers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_cnt_time_out](xip_cnt_time_out) module"] + pub type XIP_CNT_TIME_OUT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_CNT_TIME_OUT; + #[doc = "`read()` method returns [xip_cnt_time_out::R](xip_cnt_time_out::R) reader structure"] + impl crate::Readable for XIP_CNT_TIME_OUT {} + #[doc = "`write(|w| ..)` method takes [xip_cnt_time_out::W](xip_cnt_time_out::W) writer structure"] + impl crate::Writable for XIP_CNT_TIME_OUT {} + #[doc = "XIP time out register for continuous transfers"] + pub mod xip_cnt_time_out { + #[doc = "Reader of register xip_cnt_time_out"] + pub type R = crate::R; + #[doc = "Writer for register xip_cnt_time_out"] + pub type W = crate::W; + #[doc = "Register xip_cnt_time_out `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_CNT_TIME_OUT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "ENDIAN\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [endian](endian) module"] + pub type ENDIAN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ENDIAN; + #[doc = "`read()` method returns [endian::R](endian::R) reader structure"] + impl crate::Readable for ENDIAN {} + #[doc = "`write(|w| ..)` method takes [endian::W](endian::W) writer structure"] + impl crate::Writable for ENDIAN {} + #[doc = "ENDIAN"] + pub mod endian { + #[doc = "Reader of register endian"] + pub type R = crate::R; + #[doc = "Writer for register endian"] + pub type W = crate::W; + #[doc = "Register endian `reset()`'s with value 0"] + impl crate::ResetValue for super::ENDIAN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Serial Peripheral Interface 1 (master)"] +pub struct SPI1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI1 {} +impl SPI1 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + 0x5300_0000 as *const _ + } +} +impl Deref for SPI1 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*SPI1::ptr() } + } +} +#[doc = "Serial Peripheral Interface 2 (slave)"] +pub struct SPI2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI2 {} +impl SPI2 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi2::RegisterBlock { + 0x5024_0000 as *const _ + } +} +impl Deref for SPI2 { + type Target = spi2::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*SPI2::ptr() } + } +} +#[doc = "Serial Peripheral Interface 2 (slave)"] +pub mod spi2 { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Dummy register: this peripheral is not implemented yet"] + pub dummy: DUMMY, + } + #[doc = "Dummy register: this peripheral is not implemented yet\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dummy](dummy) module"] + pub type DUMMY = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DUMMY; + #[doc = "`read()` method returns [dummy::R](dummy::R) reader structure"] + impl crate::Readable for DUMMY {} + #[doc = "`write(|w| ..)` method takes [dummy::W](dummy::W) writer structure"] + impl crate::Writable for DUMMY {} + #[doc = "Dummy register: this peripheral is not implemented yet"] + pub mod dummy { + #[doc = "Reader of register dummy"] + pub type R = crate::R; + #[doc = "Writer for register dummy"] + pub type W = crate::W; + #[doc = "Register dummy `reset()`'s with value 0"] + impl crate::ResetValue for super::DUMMY { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Serial Peripheral Interface 3 (master)"] +pub struct SPI3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI3 {} +impl SPI3 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi3::RegisterBlock { + 0x5400_0000 as *const _ + } +} +impl Deref for SPI3 { + type Target = spi3::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*SPI3::ptr() } + } +} +#[doc = "Serial Peripheral Interface 3 (master)"] +pub mod spi3 { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Control Register 0"] + pub ctrlr0: CTRLR0, + #[doc = "0x04 - Control Register 1"] + pub ctrlr1: CTRLR1, + #[doc = "0x08 - Enable Register"] + pub ssienr: SSIENR, + #[doc = "0x0c - Microwire Control Register"] + pub mwcr: MWCR, + #[doc = "0x10 - Slave Enable Register"] + pub ser: SER, + #[doc = "0x14 - Baud Rate Select"] + pub baudr: BAUDR, + #[doc = "0x18 - Transmit FIFO Threshold Level"] + pub txftlr: TXFTLR, + #[doc = "0x1c - Receive FIFO Threshold Level"] + pub rxftlr: RXFTLR, + #[doc = "0x20 - Transmit FIFO Level Register"] + pub txflr: TXFLR, + #[doc = "0x24 - Receive FIFO Level Register"] + pub rxflr: RXFLR, + #[doc = "0x28 - Status Register"] + pub sr: SR, + #[doc = "0x2c - Interrupt Mask Register"] + pub imr: IMR, + #[doc = "0x30 - Interrupt Status Register"] + pub isr: ISR, + #[doc = "0x34 - Raw Interrupt Status Register"] + pub risr: RISR, + #[doc = "0x38 - Transmit FIFO Overflow Interrupt Clear Register"] + pub txoicr: TXOICR, + #[doc = "0x3c - Receive FIFO Overflow Interrupt Clear Register"] + pub rxoicr: RXOICR, + #[doc = "0x40 - Receive FIFO Underflow Interrupt Clear Register"] + pub rxuicr: RXUICR, + #[doc = "0x44 - Multi-Master Interrupt Clear Register"] + pub msticr: MSTICR, + #[doc = "0x48 - Interrupt Clear Register"] + pub icr: ICR, + #[doc = "0x4c - DMA Control Register"] + pub dmacr: DMACR, + #[doc = "0x50 - DMA Transmit Data Level"] + pub dmatdlr: DMATDLR, + #[doc = "0x54 - DMA Receive Data Level"] + pub dmardlr: DMARDLR, + #[doc = "0x58 - Identification Register"] + pub idr: IDR, + #[doc = "0x5c - DWC_ssi component version"] + pub ssic_version_id: SSIC_VERSION_ID, + #[doc = "0x60 - Data Register"] + pub dr: [DR; 36], + #[doc = "0xf0 - RX Sample Delay Register"] + pub rx_sample_delay: RX_SAMPLE_DELAY, + #[doc = "0xf4 - SPI Control Register"] + pub spi_ctrlr0: SPI_CTRLR0, + _reserved27: [u8; 4usize], + #[doc = "0xfc - XIP Mode bits"] + pub xip_mode_bits: XIP_MODE_BITS, + #[doc = "0x100 - XIP INCR transfer opcode"] + pub xip_incr_inst: XIP_INCR_INST, + #[doc = "0x104 - XIP WRAP transfer opcode"] + pub xip_wrap_inst: XIP_WRAP_INST, + #[doc = "0x108 - XIP Control Register"] + pub xip_ctrl: XIP_CTRL, + #[doc = "0x10c - XIP Slave Enable Register"] + pub xip_ser: XIP_SER, + #[doc = "0x110 - XIP Receive FIFO Overflow Interrupt Clear Register"] + pub xrxoicr: XRXOICR, + #[doc = "0x114 - XIP time out register for continuous transfers"] + pub xip_cnt_time_out: XIP_CNT_TIME_OUT, + #[doc = "0x118 - ENDIAN"] + pub endian: ENDIAN, + } + #[doc = "Control Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlr0](ctrlr0) module"] + pub type CTRLR0 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CTRLR0; + #[doc = "`read()` method returns [ctrlr0::R](ctrlr0::R) reader structure"] + impl crate::Readable for CTRLR0 {} + #[doc = "`write(|w| ..)` method takes [ctrlr0::W](ctrlr0::W) writer structure"] + impl crate::Writable for CTRLR0 {} + #[doc = "Control Register 0"] + pub mod ctrlr0 { + #[doc = "Reader of register ctrlr0"] + pub type R = crate::R; + #[doc = "Writer for register ctrlr0"] + pub type W = crate::W; + #[doc = "Register ctrlr0 `reset()`'s with value 0"] + impl crate::ResetValue for super::CTRLR0 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `data_length`"] + pub type DATA_LENGTH_R = crate::R; + #[doc = "Write proxy for field `data_length`"] + pub struct DATA_LENGTH_W<'a> { + w: &'a mut W, + } + impl<'a> DATA_LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f); + self.w + } + } + #[doc = "WORK_MODE\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum WORK_MODE_A { + #[doc = "0: MODE_0"] + MODE0 = 0, + #[doc = "1: MODE_1"] + MODE1 = 1, + #[doc = "2: MODE_2"] + MODE2 = 2, + #[doc = "3: MODE_3"] + MODE3 = 3, + } + impl From for u8 { + #[inline(always)] + fn from(variant: WORK_MODE_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `work_mode`"] + pub type WORK_MODE_R = crate::R; + impl WORK_MODE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WORK_MODE_A { + match self.bits { + 0 => WORK_MODE_A::MODE0, + 1 => WORK_MODE_A::MODE1, + 2 => WORK_MODE_A::MODE2, + 3 => WORK_MODE_A::MODE3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `MODE0`"] + #[inline(always)] + pub fn is_mode0(&self) -> bool { + *self == WORK_MODE_A::MODE0 + } + #[doc = "Checks if the value of the field is `MODE1`"] + #[inline(always)] + pub fn is_mode1(&self) -> bool { + *self == WORK_MODE_A::MODE1 + } + #[doc = "Checks if the value of the field is `MODE2`"] + #[inline(always)] + pub fn is_mode2(&self) -> bool { + *self == WORK_MODE_A::MODE2 + } + #[doc = "Checks if the value of the field is `MODE3`"] + #[inline(always)] + pub fn is_mode3(&self) -> bool { + *self == WORK_MODE_A::MODE3 + } + } + #[doc = "Write proxy for field `work_mode`"] + pub struct WORK_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> WORK_MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WORK_MODE_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "MODE_0"] + #[inline(always)] + pub fn mode0(self) -> &'a mut W { + self.variant(WORK_MODE_A::MODE0) + } + #[doc = "MODE_1"] + #[inline(always)] + pub fn mode1(self) -> &'a mut W { + self.variant(WORK_MODE_A::MODE1) + } + #[doc = "MODE_2"] + #[inline(always)] + pub fn mode2(self) -> &'a mut W { + self.variant(WORK_MODE_A::MODE2) + } + #[doc = "MODE_3"] + #[inline(always)] + pub fn mode3(self) -> &'a mut W { + self.variant(WORK_MODE_A::MODE3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8); + self.w + } + } + #[doc = "TRANSFER_MODE\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum TMOD_A { + #[doc = "0: TRANS_RECV"] + TRANS_RECV = 0, + #[doc = "1: TRANS"] + TRANS = 1, + #[doc = "2: RECV"] + RECV = 2, + #[doc = "3: EEROM"] + EEROM = 3, + } + impl From for u8 { + #[inline(always)] + fn from(variant: TMOD_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `tmod`"] + pub type TMOD_R = crate::R; + impl TMOD_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TMOD_A { + match self.bits { + 0 => TMOD_A::TRANS_RECV, + 1 => TMOD_A::TRANS, + 2 => TMOD_A::RECV, + 3 => TMOD_A::EEROM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `TRANS_RECV`"] + #[inline(always)] + pub fn is_trans_recv(&self) -> bool { + *self == TMOD_A::TRANS_RECV + } + #[doc = "Checks if the value of the field is `TRANS`"] + #[inline(always)] + pub fn is_trans(&self) -> bool { + *self == TMOD_A::TRANS + } + #[doc = "Checks if the value of the field is `RECV`"] + #[inline(always)] + pub fn is_recv(&self) -> bool { + *self == TMOD_A::RECV + } + #[doc = "Checks if the value of the field is `EEROM`"] + #[inline(always)] + pub fn is_eerom(&self) -> bool { + *self == TMOD_A::EEROM + } + } + #[doc = "Write proxy for field `tmod`"] + pub struct TMOD_W<'a> { + w: &'a mut W, + } + impl<'a> TMOD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TMOD_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "TRANS_RECV"] + #[inline(always)] + pub fn trans_recv(self) -> &'a mut W { + self.variant(TMOD_A::TRANS_RECV) + } + #[doc = "TRANS"] + #[inline(always)] + pub fn trans(self) -> &'a mut W { + self.variant(TMOD_A::TRANS) + } + #[doc = "RECV"] + #[inline(always)] + pub fn recv(self) -> &'a mut W { + self.variant(TMOD_A::RECV) + } + #[doc = "EEROM"] + #[inline(always)] + pub fn eerom(self) -> &'a mut W { + self.variant(TMOD_A::EEROM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10); + self.w + } + } + #[doc = "FRAME_FORMAT\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum FRAME_FORMAT_A { + #[doc = "0: STANDARD"] + STANDARD = 0, + #[doc = "1: DUAL"] + DUAL = 1, + #[doc = "2: QUAD"] + QUAD = 2, + #[doc = "3: OCTAL"] + OCTAL = 3, + } + impl From for u8 { + #[inline(always)] + fn from(variant: FRAME_FORMAT_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `frame_format`"] + pub type FRAME_FORMAT_R = crate::R; + impl FRAME_FORMAT_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FRAME_FORMAT_A { + match self.bits { + 0 => FRAME_FORMAT_A::STANDARD, + 1 => FRAME_FORMAT_A::DUAL, + 2 => FRAME_FORMAT_A::QUAD, + 3 => FRAME_FORMAT_A::OCTAL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `STANDARD`"] + #[inline(always)] + pub fn is_standard(&self) -> bool { + *self == FRAME_FORMAT_A::STANDARD + } + #[doc = "Checks if the value of the field is `DUAL`"] + #[inline(always)] + pub fn is_dual(&self) -> bool { + *self == FRAME_FORMAT_A::DUAL + } + #[doc = "Checks if the value of the field is `QUAD`"] + #[inline(always)] + pub fn is_quad(&self) -> bool { + *self == FRAME_FORMAT_A::QUAD + } + #[doc = "Checks if the value of the field is `OCTAL`"] + #[inline(always)] + pub fn is_octal(&self) -> bool { + *self == FRAME_FORMAT_A::OCTAL + } + } + #[doc = "Write proxy for field `frame_format`"] + pub struct FRAME_FORMAT_W<'a> { + w: &'a mut W, + } + impl<'a> FRAME_FORMAT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FRAME_FORMAT_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "STANDARD"] + #[inline(always)] + pub fn standard(self) -> &'a mut W { + self.variant(FRAME_FORMAT_A::STANDARD) + } + #[doc = "DUAL"] + #[inline(always)] + pub fn dual(self) -> &'a mut W { + self.variant(FRAME_FORMAT_A::DUAL) + } + #[doc = "QUAD"] + #[inline(always)] + pub fn quad(self) -> &'a mut W { + self.variant(FRAME_FORMAT_A::QUAD) + } + #[doc = "OCTAL"] + #[inline(always)] + pub fn octal(self) -> &'a mut W { + self.variant(FRAME_FORMAT_A::OCTAL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | (((value as u32) & 0x03) << 22); + self.w + } + } + impl R { + #[doc = "Bits 0:4 - DATA_BIT_LENGTH"] + #[inline(always)] + pub fn data_length(&self) -> DATA_LENGTH_R { + DATA_LENGTH_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:9 - WORK_MODE"] + #[inline(always)] + pub fn work_mode(&self) -> WORK_MODE_R { + WORK_MODE_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - TRANSFER_MODE"] + #[inline(always)] + pub fn tmod(&self) -> TMOD_R { + TMOD_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 22:23 - FRAME_FORMAT"] + #[inline(always)] + pub fn frame_format(&self) -> FRAME_FORMAT_R { + FRAME_FORMAT_R::new(((self.bits >> 22) & 0x03) as u8) + } + } + impl W { + #[doc = "Bits 0:4 - DATA_BIT_LENGTH"] + #[inline(always)] + pub fn data_length(&mut self) -> DATA_LENGTH_W { + DATA_LENGTH_W { w: self } + } + #[doc = "Bits 8:9 - WORK_MODE"] + #[inline(always)] + pub fn work_mode(&mut self) -> WORK_MODE_W { + WORK_MODE_W { w: self } + } + #[doc = "Bits 10:11 - TRANSFER_MODE"] + #[inline(always)] + pub fn tmod(&mut self) -> TMOD_W { + TMOD_W { w: self } + } + #[doc = "Bits 22:23 - FRAME_FORMAT"] + #[inline(always)] + pub fn frame_format(&mut self) -> FRAME_FORMAT_W { + FRAME_FORMAT_W { w: self } + } + } + } + #[doc = "Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlr1](ctrlr1) module"] + pub type CTRLR1 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CTRLR1; + #[doc = "`read()` method returns [ctrlr1::R](ctrlr1::R) reader structure"] + impl crate::Readable for CTRLR1 {} + #[doc = "`write(|w| ..)` method takes [ctrlr1::W](ctrlr1::W) writer structure"] + impl crate::Writable for CTRLR1 {} + #[doc = "Control Register 1"] + pub mod ctrlr1 { + #[doc = "Reader of register ctrlr1"] + pub type R = crate::R; + #[doc = "Writer for register ctrlr1"] + pub type W = crate::W; + #[doc = "Register ctrlr1 `reset()`'s with value 0"] + impl crate::ResetValue for super::CTRLR1 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ssienr](ssienr) module"] + pub type SSIENR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SSIENR; + #[doc = "`read()` method returns [ssienr::R](ssienr::R) reader structure"] + impl crate::Readable for SSIENR {} + #[doc = "`write(|w| ..)` method takes [ssienr::W](ssienr::W) writer structure"] + impl crate::Writable for SSIENR {} + #[doc = "Enable Register"] + pub mod ssienr { + #[doc = "Reader of register ssienr"] + pub type R = crate::R; + #[doc = "Writer for register ssienr"] + pub type W = crate::W; + #[doc = "Register ssienr `reset()`'s with value 0"] + impl crate::ResetValue for super::SSIENR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Microwire Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mwcr](mwcr) module"] + pub type MWCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _MWCR; + #[doc = "`read()` method returns [mwcr::R](mwcr::R) reader structure"] + impl crate::Readable for MWCR {} + #[doc = "`write(|w| ..)` method takes [mwcr::W](mwcr::W) writer structure"] + impl crate::Writable for MWCR {} + #[doc = "Microwire Control Register"] + pub mod mwcr { + #[doc = "Reader of register mwcr"] + pub type R = crate::R; + #[doc = "Writer for register mwcr"] + pub type W = crate::W; + #[doc = "Register mwcr `reset()`'s with value 0"] + impl crate::ResetValue for super::MWCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Slave Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ser](ser) module"] + pub type SER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SER; + #[doc = "`read()` method returns [ser::R](ser::R) reader structure"] + impl crate::Readable for SER {} + #[doc = "`write(|w| ..)` method takes [ser::W](ser::W) writer structure"] + impl crate::Writable for SER {} + #[doc = "Slave Enable Register"] + pub mod ser { + #[doc = "Reader of register ser"] + pub type R = crate::R; + #[doc = "Writer for register ser"] + pub type W = crate::W; + #[doc = "Register ser `reset()`'s with value 0"] + impl crate::ResetValue for super::SER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Baud Rate Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baudr](baudr) module"] + pub type BAUDR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _BAUDR; + #[doc = "`read()` method returns [baudr::R](baudr::R) reader structure"] + impl crate::Readable for BAUDR {} + #[doc = "`write(|w| ..)` method takes [baudr::W](baudr::W) writer structure"] + impl crate::Writable for BAUDR {} + #[doc = "Baud Rate Select"] + pub mod baudr { + #[doc = "Reader of register baudr"] + pub type R = crate::R; + #[doc = "Writer for register baudr"] + pub type W = crate::W; + #[doc = "Register baudr `reset()`'s with value 0"] + impl crate::ResetValue for super::BAUDR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Transmit FIFO Threshold Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txftlr](txftlr) module"] + pub type TXFTLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TXFTLR; + #[doc = "`read()` method returns [txftlr::R](txftlr::R) reader structure"] + impl crate::Readable for TXFTLR {} + #[doc = "`write(|w| ..)` method takes [txftlr::W](txftlr::W) writer structure"] + impl crate::Writable for TXFTLR {} + #[doc = "Transmit FIFO Threshold Level"] + pub mod txftlr { + #[doc = "Reader of register txftlr"] + pub type R = crate::R; + #[doc = "Writer for register txftlr"] + pub type W = crate::W; + #[doc = "Register txftlr `reset()`'s with value 0"] + impl crate::ResetValue for super::TXFTLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive FIFO Threshold Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxftlr](rxftlr) module"] + pub type RXFTLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXFTLR; + #[doc = "`read()` method returns [rxftlr::R](rxftlr::R) reader structure"] + impl crate::Readable for RXFTLR {} + #[doc = "`write(|w| ..)` method takes [rxftlr::W](rxftlr::W) writer structure"] + impl crate::Writable for RXFTLR {} + #[doc = "Receive FIFO Threshold Level"] + pub mod rxftlr { + #[doc = "Reader of register rxftlr"] + pub type R = crate::R; + #[doc = "Writer for register rxftlr"] + pub type W = crate::W; + #[doc = "Register rxftlr `reset()`'s with value 0"] + impl crate::ResetValue for super::RXFTLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Transmit FIFO Level Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txflr](txflr) module"] + pub type TXFLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TXFLR; + #[doc = "`read()` method returns [txflr::R](txflr::R) reader structure"] + impl crate::Readable for TXFLR {} + #[doc = "`write(|w| ..)` method takes [txflr::W](txflr::W) writer structure"] + impl crate::Writable for TXFLR {} + #[doc = "Transmit FIFO Level Register"] + pub mod txflr { + #[doc = "Reader of register txflr"] + pub type R = crate::R; + #[doc = "Writer for register txflr"] + pub type W = crate::W; + #[doc = "Register txflr `reset()`'s with value 0"] + impl crate::ResetValue for super::TXFLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive FIFO Level Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxflr](rxflr) module"] + pub type RXFLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXFLR; + #[doc = "`read()` method returns [rxflr::R](rxflr::R) reader structure"] + impl crate::Readable for RXFLR {} + #[doc = "`write(|w| ..)` method takes [rxflr::W](rxflr::W) writer structure"] + impl crate::Writable for RXFLR {} + #[doc = "Receive FIFO Level Register"] + pub mod rxflr { + #[doc = "Reader of register rxflr"] + pub type R = crate::R; + #[doc = "Writer for register rxflr"] + pub type W = crate::W; + #[doc = "Register rxflr `reset()`'s with value 0"] + impl crate::ResetValue for super::RXFLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](sr) module"] + pub type SR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SR; + #[doc = "`read()` method returns [sr::R](sr::R) reader structure"] + impl crate::Readable for SR {} + #[doc = "`write(|w| ..)` method takes [sr::W](sr::W) writer structure"] + impl crate::Writable for SR {} + #[doc = "Status Register"] + pub mod sr { + #[doc = "Reader of register sr"] + pub type R = crate::R; + #[doc = "Writer for register sr"] + pub type W = crate::W; + #[doc = "Register sr `reset()`'s with value 0"] + impl crate::ResetValue for super::SR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](imr) module"] + pub type IMR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IMR; + #[doc = "`read()` method returns [imr::R](imr::R) reader structure"] + impl crate::Readable for IMR {} + #[doc = "`write(|w| ..)` method takes [imr::W](imr::W) writer structure"] + impl crate::Writable for IMR {} + #[doc = "Interrupt Mask Register"] + pub mod imr { + #[doc = "Reader of register imr"] + pub type R = crate::R; + #[doc = "Writer for register imr"] + pub type W = crate::W; + #[doc = "Register imr `reset()`'s with value 0"] + impl crate::ResetValue for super::IMR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr](isr) module"] + pub type ISR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ISR; + #[doc = "`read()` method returns [isr::R](isr::R) reader structure"] + impl crate::Readable for ISR {} + #[doc = "`write(|w| ..)` method takes [isr::W](isr::W) writer structure"] + impl crate::Writable for ISR {} + #[doc = "Interrupt Status Register"] + pub mod isr { + #[doc = "Reader of register isr"] + pub type R = crate::R; + #[doc = "Writer for register isr"] + pub type W = crate::W; + #[doc = "Register isr `reset()`'s with value 0"] + impl crate::ResetValue for super::ISR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Raw Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [risr](risr) module"] + pub type RISR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RISR; + #[doc = "`read()` method returns [risr::R](risr::R) reader structure"] + impl crate::Readable for RISR {} + #[doc = "`write(|w| ..)` method takes [risr::W](risr::W) writer structure"] + impl crate::Writable for RISR {} + #[doc = "Raw Interrupt Status Register"] + pub mod risr { + #[doc = "Reader of register risr"] + pub type R = crate::R; + #[doc = "Writer for register risr"] + pub type W = crate::W; + #[doc = "Register risr `reset()`'s with value 0"] + impl crate::ResetValue for super::RISR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Transmit FIFO Overflow Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txoicr](txoicr) module"] + pub type TXOICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TXOICR; + #[doc = "`read()` method returns [txoicr::R](txoicr::R) reader structure"] + impl crate::Readable for TXOICR {} + #[doc = "`write(|w| ..)` method takes [txoicr::W](txoicr::W) writer structure"] + impl crate::Writable for TXOICR {} + #[doc = "Transmit FIFO Overflow Interrupt Clear Register"] + pub mod txoicr { + #[doc = "Reader of register txoicr"] + pub type R = crate::R; + #[doc = "Writer for register txoicr"] + pub type W = crate::W; + #[doc = "Register txoicr `reset()`'s with value 0"] + impl crate::ResetValue for super::TXOICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive FIFO Overflow Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxoicr](rxoicr) module"] + pub type RXOICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXOICR; + #[doc = "`read()` method returns [rxoicr::R](rxoicr::R) reader structure"] + impl crate::Readable for RXOICR {} + #[doc = "`write(|w| ..)` method takes [rxoicr::W](rxoicr::W) writer structure"] + impl crate::Writable for RXOICR {} + #[doc = "Receive FIFO Overflow Interrupt Clear Register"] + pub mod rxoicr { + #[doc = "Reader of register rxoicr"] + pub type R = crate::R; + #[doc = "Writer for register rxoicr"] + pub type W = crate::W; + #[doc = "Register rxoicr `reset()`'s with value 0"] + impl crate::ResetValue for super::RXOICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive FIFO Underflow Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxuicr](rxuicr) module"] + pub type RXUICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXUICR; + #[doc = "`read()` method returns [rxuicr::R](rxuicr::R) reader structure"] + impl crate::Readable for RXUICR {} + #[doc = "`write(|w| ..)` method takes [rxuicr::W](rxuicr::W) writer structure"] + impl crate::Writable for RXUICR {} + #[doc = "Receive FIFO Underflow Interrupt Clear Register"] + pub mod rxuicr { + #[doc = "Reader of register rxuicr"] + pub type R = crate::R; + #[doc = "Writer for register rxuicr"] + pub type W = crate::W; + #[doc = "Register rxuicr `reset()`'s with value 0"] + impl crate::ResetValue for super::RXUICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Multi-Master Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msticr](msticr) module"] + pub type MSTICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _MSTICR; + #[doc = "`read()` method returns [msticr::R](msticr::R) reader structure"] + impl crate::Readable for MSTICR {} + #[doc = "`write(|w| ..)` method takes [msticr::W](msticr::W) writer structure"] + impl crate::Writable for MSTICR {} + #[doc = "Multi-Master Interrupt Clear Register"] + pub mod msticr { + #[doc = "Reader of register msticr"] + pub type R = crate::R; + #[doc = "Writer for register msticr"] + pub type W = crate::W; + #[doc = "Register msticr `reset()`'s with value 0"] + impl crate::ResetValue for super::MSTICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icr](icr) module"] + pub type ICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ICR; + #[doc = "`read()` method returns [icr::R](icr::R) reader structure"] + impl crate::Readable for ICR {} + #[doc = "`write(|w| ..)` method takes [icr::W](icr::W) writer structure"] + impl crate::Writable for ICR {} + #[doc = "Interrupt Clear Register"] + pub mod icr { + #[doc = "Reader of register icr"] + pub type R = crate::R; + #[doc = "Writer for register icr"] + pub type W = crate::W; + #[doc = "Register icr `reset()`'s with value 0"] + impl crate::ResetValue for super::ICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DMA Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmacr](dmacr) module"] + pub type DMACR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMACR; + #[doc = "`read()` method returns [dmacr::R](dmacr::R) reader structure"] + impl crate::Readable for DMACR {} + #[doc = "`write(|w| ..)` method takes [dmacr::W](dmacr::W) writer structure"] + impl crate::Writable for DMACR {} + #[doc = "DMA Control Register"] + pub mod dmacr { + #[doc = "Reader of register dmacr"] + pub type R = crate::R; + #[doc = "Writer for register dmacr"] + pub type W = crate::W; + #[doc = "Register dmacr `reset()`'s with value 0"] + impl crate::ResetValue for super::DMACR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DMA Transmit Data Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmatdlr](dmatdlr) module"] + pub type DMATDLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMATDLR; + #[doc = "`read()` method returns [dmatdlr::R](dmatdlr::R) reader structure"] + impl crate::Readable for DMATDLR {} + #[doc = "`write(|w| ..)` method takes [dmatdlr::W](dmatdlr::W) writer structure"] + impl crate::Writable for DMATDLR {} + #[doc = "DMA Transmit Data Level"] + pub mod dmatdlr { + #[doc = "Reader of register dmatdlr"] + pub type R = crate::R; + #[doc = "Writer for register dmatdlr"] + pub type W = crate::W; + #[doc = "Register dmatdlr `reset()`'s with value 0"] + impl crate::ResetValue for super::DMATDLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DMA Receive Data Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmardlr](dmardlr) module"] + pub type DMARDLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMARDLR; + #[doc = "`read()` method returns [dmardlr::R](dmardlr::R) reader structure"] + impl crate::Readable for DMARDLR {} + #[doc = "`write(|w| ..)` method takes [dmardlr::W](dmardlr::W) writer structure"] + impl crate::Writable for DMARDLR {} + #[doc = "DMA Receive Data Level"] + pub mod dmardlr { + #[doc = "Reader of register dmardlr"] + pub type R = crate::R; + #[doc = "Writer for register dmardlr"] + pub type W = crate::W; + #[doc = "Register dmardlr `reset()`'s with value 0"] + impl crate::ResetValue for super::DMARDLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Identification Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](idr) module"] + pub type IDR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IDR; + #[doc = "`read()` method returns [idr::R](idr::R) reader structure"] + impl crate::Readable for IDR {} + #[doc = "`write(|w| ..)` method takes [idr::W](idr::W) writer structure"] + impl crate::Writable for IDR {} + #[doc = "Identification Register"] + pub mod idr { + #[doc = "Reader of register idr"] + pub type R = crate::R; + #[doc = "Writer for register idr"] + pub type W = crate::W; + #[doc = "Register idr `reset()`'s with value 0"] + impl crate::ResetValue for super::IDR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DWC_ssi component version\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ssic_version_id](ssic_version_id) module"] + pub type SSIC_VERSION_ID = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SSIC_VERSION_ID; + #[doc = "`read()` method returns [ssic_version_id::R](ssic_version_id::R) reader structure"] + impl crate::Readable for SSIC_VERSION_ID {} + #[doc = "`write(|w| ..)` method takes [ssic_version_id::W](ssic_version_id::W) writer structure"] + impl crate::Writable for SSIC_VERSION_ID {} + #[doc = "DWC_ssi component version"] + pub mod ssic_version_id { + #[doc = "Reader of register ssic_version_id"] + pub type R = crate::R; + #[doc = "Writer for register ssic_version_id"] + pub type W = crate::W; + #[doc = "Register ssic_version_id `reset()`'s with value 0"] + impl crate::ResetValue for super::SSIC_VERSION_ID { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Data Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr](dr) module"] + pub type DR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DR; + #[doc = "`read()` method returns [dr::R](dr::R) reader structure"] + impl crate::Readable for DR {} + #[doc = "`write(|w| ..)` method takes [dr::W](dr::W) writer structure"] + impl crate::Writable for DR {} + #[doc = "Data Register"] + pub mod dr { + #[doc = "Reader of register dr%s"] + pub type R = crate::R; + #[doc = "Writer for register dr%s"] + pub type W = crate::W; + #[doc = "Register dr%s `reset()`'s with value 0"] + impl crate::ResetValue for super::DR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "RX Sample Delay Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rx_sample_delay](rx_sample_delay) module"] + pub type RX_SAMPLE_DELAY = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RX_SAMPLE_DELAY; + #[doc = "`read()` method returns [rx_sample_delay::R](rx_sample_delay::R) reader structure"] + impl crate::Readable for RX_SAMPLE_DELAY {} + #[doc = "`write(|w| ..)` method takes [rx_sample_delay::W](rx_sample_delay::W) writer structure"] + impl crate::Writable for RX_SAMPLE_DELAY {} + #[doc = "RX Sample Delay Register"] + pub mod rx_sample_delay { + #[doc = "Reader of register rx_sample_delay"] + pub type R = crate::R; + #[doc = "Writer for register rx_sample_delay"] + pub type W = crate::W; + #[doc = "Register rx_sample_delay `reset()`'s with value 0"] + impl crate::ResetValue for super::RX_SAMPLE_DELAY { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "SPI Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spi_ctrlr0](spi_ctrlr0) module"] + pub type SPI_CTRLR0 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SPI_CTRLR0; + #[doc = "`read()` method returns [spi_ctrlr0::R](spi_ctrlr0::R) reader structure"] + impl crate::Readable for SPI_CTRLR0 {} + #[doc = "`write(|w| ..)` method takes [spi_ctrlr0::W](spi_ctrlr0::W) writer structure"] + impl crate::Writable for SPI_CTRLR0 {} + #[doc = "SPI Control Register"] + pub mod spi_ctrlr0 { + #[doc = "Reader of register spi_ctrlr0"] + pub type R = crate::R; + #[doc = "Writer for register spi_ctrlr0"] + pub type W = crate::W; + #[doc = "Register spi_ctrlr0 `reset()`'s with value 0"] + impl crate::ResetValue for super::SPI_CTRLR0 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "instruction_address_trans_mode\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum AITM_A { + #[doc = "0: STANDARD"] + STANDARD = 0, + #[doc = "1: ADDR_STANDARD"] + ADDR_STANDARD = 1, + #[doc = "2: AS_FRAME_FORMAT"] + AS_FRAME_FORMAT = 2, + } + impl From for u8 { + #[inline(always)] + fn from(variant: AITM_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `aitm`"] + pub type AITM_R = crate::R; + impl AITM_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(AITM_A::STANDARD), + 1 => Val(AITM_A::ADDR_STANDARD), + 2 => Val(AITM_A::AS_FRAME_FORMAT), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `STANDARD`"] + #[inline(always)] + pub fn is_standard(&self) -> bool { + *self == AITM_A::STANDARD + } + #[doc = "Checks if the value of the field is `ADDR_STANDARD`"] + #[inline(always)] + pub fn is_addr_standard(&self) -> bool { + *self == AITM_A::ADDR_STANDARD + } + #[doc = "Checks if the value of the field is `AS_FRAME_FORMAT`"] + #[inline(always)] + pub fn is_as_frame_format(&self) -> bool { + *self == AITM_A::AS_FRAME_FORMAT + } + } + #[doc = "Write proxy for field `aitm`"] + pub struct AITM_W<'a> { + w: &'a mut W, + } + impl<'a> AITM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AITM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "STANDARD"] + #[inline(always)] + pub fn standard(self) -> &'a mut W { + self.variant(AITM_A::STANDARD) + } + #[doc = "ADDR_STANDARD"] + #[inline(always)] + pub fn addr_standard(self) -> &'a mut W { + self.variant(AITM_A::ADDR_STANDARD) + } + #[doc = "AS_FRAME_FORMAT"] + #[inline(always)] + pub fn as_frame_format(self) -> &'a mut W { + self.variant(AITM_A::AS_FRAME_FORMAT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03); + self.w + } + } + #[doc = "Reader of field `addr_length`"] + pub type ADDR_LENGTH_R = crate::R; + #[doc = "Write proxy for field `addr_length`"] + pub struct ADDR_LENGTH_W<'a> { + w: &'a mut W, + } + impl<'a> ADDR_LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 2)) | (((value as u32) & 0x0f) << 2); + self.w + } + } + #[doc = "Reader of field `inst_length`"] + pub type INST_LENGTH_R = crate::R; + #[doc = "Write proxy for field `inst_length`"] + pub struct INST_LENGTH_W<'a> { + w: &'a mut W, + } + impl<'a> INST_LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8); + self.w + } + } + #[doc = "Reader of field `wait_cycles`"] + pub type WAIT_CYCLES_R = crate::R; + #[doc = "Write proxy for field `wait_cycles`"] + pub struct WAIT_CYCLES_W<'a> { + w: &'a mut W, + } + impl<'a> WAIT_CYCLES_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 11)) | (((value as u32) & 0x1f) << 11); + self.w + } + } + impl R { + #[doc = "Bits 0:1 - instruction_address_trans_mode"] + #[inline(always)] + pub fn aitm(&self) -> AITM_R { + AITM_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:5 - ADDR_LENGTH"] + #[inline(always)] + pub fn addr_length(&self) -> ADDR_LENGTH_R { + ADDR_LENGTH_R::new(((self.bits >> 2) & 0x0f) as u8) + } + #[doc = "Bits 8:9 - INSTRUCTION_LENGTH"] + #[inline(always)] + pub fn inst_length(&self) -> INST_LENGTH_R { + INST_LENGTH_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 11:15 - WAIT_CYCLES"] + #[inline(always)] + pub fn wait_cycles(&self) -> WAIT_CYCLES_R { + WAIT_CYCLES_R::new(((self.bits >> 11) & 0x1f) as u8) + } + } + impl W { + #[doc = "Bits 0:1 - instruction_address_trans_mode"] + #[inline(always)] + pub fn aitm(&mut self) -> AITM_W { + AITM_W { w: self } + } + #[doc = "Bits 2:5 - ADDR_LENGTH"] + #[inline(always)] + pub fn addr_length(&mut self) -> ADDR_LENGTH_W { + ADDR_LENGTH_W { w: self } + } + #[doc = "Bits 8:9 - INSTRUCTION_LENGTH"] + #[inline(always)] + pub fn inst_length(&mut self) -> INST_LENGTH_W { + INST_LENGTH_W { w: self } + } + #[doc = "Bits 11:15 - WAIT_CYCLES"] + #[inline(always)] + pub fn wait_cycles(&mut self) -> WAIT_CYCLES_W { + WAIT_CYCLES_W { w: self } + } + } + } + #[doc = "XIP Mode bits\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_mode_bits](xip_mode_bits) module"] + pub type XIP_MODE_BITS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_MODE_BITS; + #[doc = "`read()` method returns [xip_mode_bits::R](xip_mode_bits::R) reader structure"] + impl crate::Readable for XIP_MODE_BITS {} + #[doc = "`write(|w| ..)` method takes [xip_mode_bits::W](xip_mode_bits::W) writer structure"] + impl crate::Writable for XIP_MODE_BITS {} + #[doc = "XIP Mode bits"] + pub mod xip_mode_bits { + #[doc = "Reader of register xip_mode_bits"] + pub type R = crate::R; + #[doc = "Writer for register xip_mode_bits"] + pub type W = crate::W; + #[doc = "Register xip_mode_bits `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_MODE_BITS { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP INCR transfer opcode\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_incr_inst](xip_incr_inst) module"] + pub type XIP_INCR_INST = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_INCR_INST; + #[doc = "`read()` method returns [xip_incr_inst::R](xip_incr_inst::R) reader structure"] + impl crate::Readable for XIP_INCR_INST {} + #[doc = "`write(|w| ..)` method takes [xip_incr_inst::W](xip_incr_inst::W) writer structure"] + impl crate::Writable for XIP_INCR_INST {} + #[doc = "XIP INCR transfer opcode"] + pub mod xip_incr_inst { + #[doc = "Reader of register xip_incr_inst"] + pub type R = crate::R; + #[doc = "Writer for register xip_incr_inst"] + pub type W = crate::W; + #[doc = "Register xip_incr_inst `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_INCR_INST { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP WRAP transfer opcode\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_wrap_inst](xip_wrap_inst) module"] + pub type XIP_WRAP_INST = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_WRAP_INST; + #[doc = "`read()` method returns [xip_wrap_inst::R](xip_wrap_inst::R) reader structure"] + impl crate::Readable for XIP_WRAP_INST {} + #[doc = "`write(|w| ..)` method takes [xip_wrap_inst::W](xip_wrap_inst::W) writer structure"] + impl crate::Writable for XIP_WRAP_INST {} + #[doc = "XIP WRAP transfer opcode"] + pub mod xip_wrap_inst { + #[doc = "Reader of register xip_wrap_inst"] + pub type R = crate::R; + #[doc = "Writer for register xip_wrap_inst"] + pub type W = crate::W; + #[doc = "Register xip_wrap_inst `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_WRAP_INST { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_ctrl](xip_ctrl) module"] + pub type XIP_CTRL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_CTRL; + #[doc = "`read()` method returns [xip_ctrl::R](xip_ctrl::R) reader structure"] + impl crate::Readable for XIP_CTRL {} + #[doc = "`write(|w| ..)` method takes [xip_ctrl::W](xip_ctrl::W) writer structure"] + impl crate::Writable for XIP_CTRL {} + #[doc = "XIP Control Register"] + pub mod xip_ctrl { + #[doc = "Reader of register xip_ctrl"] + pub type R = crate::R; + #[doc = "Writer for register xip_ctrl"] + pub type W = crate::W; + #[doc = "Register xip_ctrl `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_CTRL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP Slave Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_ser](xip_ser) module"] + pub type XIP_SER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_SER; + #[doc = "`read()` method returns [xip_ser::R](xip_ser::R) reader structure"] + impl crate::Readable for XIP_SER {} + #[doc = "`write(|w| ..)` method takes [xip_ser::W](xip_ser::W) writer structure"] + impl crate::Writable for XIP_SER {} + #[doc = "XIP Slave Enable Register"] + pub mod xip_ser { + #[doc = "Reader of register xip_ser"] + pub type R = crate::R; + #[doc = "Writer for register xip_ser"] + pub type W = crate::W; + #[doc = "Register xip_ser `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_SER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP Receive FIFO Overflow Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xrxoicr](xrxoicr) module"] + pub type XRXOICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XRXOICR; + #[doc = "`read()` method returns [xrxoicr::R](xrxoicr::R) reader structure"] + impl crate::Readable for XRXOICR {} + #[doc = "`write(|w| ..)` method takes [xrxoicr::W](xrxoicr::W) writer structure"] + impl crate::Writable for XRXOICR {} + #[doc = "XIP Receive FIFO Overflow Interrupt Clear Register"] + pub mod xrxoicr { + #[doc = "Reader of register xrxoicr"] + pub type R = crate::R; + #[doc = "Writer for register xrxoicr"] + pub type W = crate::W; + #[doc = "Register xrxoicr `reset()`'s with value 0"] + impl crate::ResetValue for super::XRXOICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP time out register for continuous transfers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_cnt_time_out](xip_cnt_time_out) module"] + pub type XIP_CNT_TIME_OUT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_CNT_TIME_OUT; + #[doc = "`read()` method returns [xip_cnt_time_out::R](xip_cnt_time_out::R) reader structure"] + impl crate::Readable for XIP_CNT_TIME_OUT {} + #[doc = "`write(|w| ..)` method takes [xip_cnt_time_out::W](xip_cnt_time_out::W) writer structure"] + impl crate::Writable for XIP_CNT_TIME_OUT {} + #[doc = "XIP time out register for continuous transfers"] + pub mod xip_cnt_time_out { + #[doc = "Reader of register xip_cnt_time_out"] + pub type R = crate::R; + #[doc = "Writer for register xip_cnt_time_out"] + pub type W = crate::W; + #[doc = "Register xip_cnt_time_out `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_CNT_TIME_OUT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "ENDIAN\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [endian](endian) module"] + pub type ENDIAN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ENDIAN; + #[doc = "`read()` method returns [endian::R](endian::R) reader structure"] + impl crate::Readable for ENDIAN {} + #[doc = "`write(|w| ..)` method takes [endian::W](endian::W) writer structure"] + impl crate::Writable for ENDIAN {} + #[doc = "ENDIAN"] + pub mod endian { + #[doc = "Reader of register endian"] + pub type R = crate::R; + #[doc = "Writer for register endian"] + pub type W = crate::W; + #[doc = "Register endian `reset()`'s with value 0"] + impl crate::ResetValue for super::ENDIAN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Inter-Integrated Sound Interface 0"] +pub struct I2S0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2S0 {} +impl I2S0 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2s0::RegisterBlock { + 0x5025_0000 as *const _ + } +} +impl Deref for I2S0 { + type Target = i2s0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*I2S0::ptr() } + } +} +#[doc = "Inter-Integrated Sound Interface 0"] +pub mod i2s0 { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Enable Register"] + pub ier: IER, + #[doc = "0x04 - Receiver Block Enable Register"] + pub irer: IRER, + #[doc = "0x08 - Transmitter Block Enable Register"] + pub iter: ITER, + #[doc = "0x0c - Clock Generation enable"] + pub cer: CER, + #[doc = "0x10 - Clock Configuration Register"] + pub ccr: CCR, + #[doc = "0x14 - Receiver Block FIFO Reset Register"] + pub rxffr: RXFFR, + #[doc = "0x18 - Transmitter Block FIFO Reset Register"] + pub txffr: TXFFR, + _reserved7: [u8; 4usize], + #[doc = "0x20 - Channel cluster"] + pub channel: [CHANNEL; 4], + _reserved8: [u8; 160usize], + #[doc = "0x1c0 - Receiver Block DMA Register"] + pub rxdma: RXDMA, + #[doc = "0x1c4 - Reset Receiver Block DMA Register"] + pub rrxdma: RRXDMA, + #[doc = "0x1c8 - Transmitter Block DMA Register"] + pub txdma: TXDMA, + #[doc = "0x1cc - Reset Transmitter Block DMA Register"] + pub rtxdma: RTXDMA, + _reserved12: [u8; 32usize], + #[doc = "0x1f0 - Component Parameter Register 2"] + pub i2s_comp_param_2: I2S_COMP_PARAM_2, + #[doc = "0x1f4 - Component Parameter Register 1"] + pub i2s_comp_param_1: I2S_COMP_PARAM_1, + #[doc = "0x1f8 - Component Version Register"] + pub i2s_comp_version_1: I2S_COMP_VERSION_1, + #[doc = "0x1fc - Component Type Register"] + pub i2s_comp_type: I2S_COMP_TYPE, + } + #[doc = r"Register block"] + #[repr(C)] + pub struct CHANNEL { + #[doc = "0x00 - Left Receive or Left Transmit Register"] + pub left_rxtx: self::channel::LEFT_RXTX, + #[doc = "0x04 - Right Receive or Right Transmit Register"] + pub right_rxtx: self::channel::RIGHT_RXTX, + #[doc = "0x08 - Receive Enable Register"] + pub rer: self::channel::RER, + #[doc = "0x0c - Transmit Enable Register"] + pub ter: self::channel::TER, + #[doc = "0x10 - Receive Configuration Register"] + pub rcr: self::channel::RCR, + #[doc = "0x14 - Transmit Configuration Register"] + pub tcr: self::channel::TCR, + #[doc = "0x18 - Interrupt Status Register"] + pub isr: self::channel::ISR, + #[doc = "0x1c - Interrupt Mask Register"] + pub imr: self::channel::IMR, + #[doc = "0x20 - Receive Overrun Register"] + pub ror: self::channel::ROR, + #[doc = "0x24 - Transmit Overrun Register"] + pub tor: self::channel::TOR, + #[doc = "0x28 - Receive FIFO Configuration Register"] + pub rfcr: self::channel::RFCR, + #[doc = "0x2c - Transmit FIFO Configuration Register"] + pub tfcr: self::channel::TFCR, + #[doc = "0x30 - Receive FIFO Flush Register"] + pub rff: self::channel::RFF, + #[doc = "0x34 - Transmit FIFO Flush Register"] + pub tff: self::channel::TFF, + #[doc = "0x38 - _RESERVED0"] + pub _reserved: [self::channel::_RESERVED; 2], + } + #[doc = r"Register block"] + #[doc = "Channel cluster"] + pub mod channel { + #[doc = "Left Receive or Left Transmit Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [left_rxtx](left_rxtx) module"] + pub type LEFT_RXTX = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LEFT_RXTX; + #[doc = "`read()` method returns [left_rxtx::R](left_rxtx::R) reader structure"] + impl crate::Readable for LEFT_RXTX {} + #[doc = "`write(|w| ..)` method takes [left_rxtx::W](left_rxtx::W) writer structure"] + impl crate::Writable for LEFT_RXTX {} + #[doc = "Left Receive or Left Transmit Register"] + pub mod left_rxtx { + #[doc = "Reader of register left_rxtx"] + pub type R = crate::R; + #[doc = "Writer for register left_rxtx"] + pub type W = crate::W; + #[doc = "Register left_rxtx `reset()`'s with value 0"] + impl crate::ResetValue for super::LEFT_RXTX { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Right Receive or Right Transmit Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [right_rxtx](right_rxtx) module"] + pub type RIGHT_RXTX = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RIGHT_RXTX; + #[doc = "`read()` method returns [right_rxtx::R](right_rxtx::R) reader structure"] + impl crate::Readable for RIGHT_RXTX {} + #[doc = "`write(|w| ..)` method takes [right_rxtx::W](right_rxtx::W) writer structure"] + impl crate::Writable for RIGHT_RXTX {} + #[doc = "Right Receive or Right Transmit Register"] + pub mod right_rxtx { + #[doc = "Reader of register right_rxtx"] + pub type R = crate::R; + #[doc = "Writer for register right_rxtx"] + pub type W = crate::W; + #[doc = "Register right_rxtx `reset()`'s with value 0"] + impl crate::ResetValue for super::RIGHT_RXTX { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rer](rer) module"] + pub type RER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RER; + #[doc = "`read()` method returns [rer::R](rer::R) reader structure"] + impl crate::Readable for RER {} + #[doc = "`write(|w| ..)` method takes [rer::W](rer::W) writer structure"] + impl crate::Writable for RER {} + #[doc = "Receive Enable Register"] + pub mod rer { + #[doc = "Reader of register rer"] + pub type R = crate::R; + #[doc = "Writer for register rer"] + pub type W = crate::W; + #[doc = "Register rer `reset()`'s with value 0"] + impl crate::ResetValue for super::RER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `rxchenx`"] + pub type RXCHENX_R = crate::R; + #[doc = "Write proxy for field `rxchenx`"] + pub struct RXCHENX_W<'a> { + w: &'a mut W, + } + impl<'a> RXCHENX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Receive channel enable/disable"] + #[inline(always)] + pub fn rxchenx(&self) -> RXCHENX_R { + RXCHENX_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Receive channel enable/disable"] + #[inline(always)] + pub fn rxchenx(&mut self) -> RXCHENX_W { + RXCHENX_W { w: self } + } + } + } + #[doc = "Transmit Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ter](ter) module"] + pub type TER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TER; + #[doc = "`read()` method returns [ter::R](ter::R) reader structure"] + impl crate::Readable for TER {} + #[doc = "`write(|w| ..)` method takes [ter::W](ter::W) writer structure"] + impl crate::Writable for TER {} + #[doc = "Transmit Enable Register"] + pub mod ter { + #[doc = "Reader of register ter"] + pub type R = crate::R; + #[doc = "Writer for register ter"] + pub type W = crate::W; + #[doc = "Register ter `reset()`'s with value 0"] + impl crate::ResetValue for super::TER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `txchenx`"] + pub type TXCHENX_R = crate::R; + #[doc = "Write proxy for field `txchenx`"] + pub struct TXCHENX_W<'a> { + w: &'a mut W, + } + impl<'a> TXCHENX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Transmit channel enable/disable"] + #[inline(always)] + pub fn txchenx(&self) -> TXCHENX_R { + TXCHENX_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Transmit channel enable/disable"] + #[inline(always)] + pub fn txchenx(&mut self) -> TXCHENX_W { + TXCHENX_W { w: self } + } + } + } + #[doc = "Receive Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rcr](rcr) module"] + pub type RCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RCR; + #[doc = "`read()` method returns [rcr::R](rcr::R) reader structure"] + impl crate::Readable for RCR {} + #[doc = "`write(|w| ..)` method takes [rcr::W](rcr::W) writer structure"] + impl crate::Writable for RCR {} + #[doc = "Receive Configuration Register"] + pub mod rcr { + #[doc = "Reader of register rcr"] + pub type R = crate::R; + #[doc = "Writer for register rcr"] + pub type W = crate::W; + #[doc = "Register rcr `reset()`'s with value 0"] + impl crate::ResetValue for super::RCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Desired data resolution of receiver\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum WLEN_A { + #[doc = "0: Ignore the word length"] + IGNORE = 0, + #[doc = "1: 12-bit data resolution of the receiver"] + RESOLUTION12 = 1, + #[doc = "2: 16-bit data resolution of the receiver"] + RESOLUTION16 = 2, + #[doc = "3: 20-bit data resolution of the receiver"] + RESOLUTION20 = 3, + #[doc = "4: 24-bit data resolution of the receiver"] + RESOLUTION24 = 4, + #[doc = "5: 32-bit data resolution of the receiver"] + RESOLUTION32 = 5, + } + impl From for u8 { + #[inline(always)] + fn from(variant: WLEN_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `wlen`"] + pub type WLEN_R = crate::R; + impl WLEN_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(WLEN_A::IGNORE), + 1 => Val(WLEN_A::RESOLUTION12), + 2 => Val(WLEN_A::RESOLUTION16), + 3 => Val(WLEN_A::RESOLUTION20), + 4 => Val(WLEN_A::RESOLUTION24), + 5 => Val(WLEN_A::RESOLUTION32), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `IGNORE`"] + #[inline(always)] + pub fn is_ignore(&self) -> bool { + *self == WLEN_A::IGNORE + } + #[doc = "Checks if the value of the field is `RESOLUTION12`"] + #[inline(always)] + pub fn is_resolution12(&self) -> bool { + *self == WLEN_A::RESOLUTION12 + } + #[doc = "Checks if the value of the field is `RESOLUTION16`"] + #[inline(always)] + pub fn is_resolution16(&self) -> bool { + *self == WLEN_A::RESOLUTION16 + } + #[doc = "Checks if the value of the field is `RESOLUTION20`"] + #[inline(always)] + pub fn is_resolution20(&self) -> bool { + *self == WLEN_A::RESOLUTION20 + } + #[doc = "Checks if the value of the field is `RESOLUTION24`"] + #[inline(always)] + pub fn is_resolution24(&self) -> bool { + *self == WLEN_A::RESOLUTION24 + } + #[doc = "Checks if the value of the field is `RESOLUTION32`"] + #[inline(always)] + pub fn is_resolution32(&self) -> bool { + *self == WLEN_A::RESOLUTION32 + } + } + #[doc = "Write proxy for field `wlen`"] + pub struct WLEN_W<'a> { + w: &'a mut W, + } + impl<'a> WLEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WLEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Ignore the word length"] + #[inline(always)] + pub fn ignore(self) -> &'a mut W { + self.variant(WLEN_A::IGNORE) + } + #[doc = "12-bit data resolution of the receiver"] + #[inline(always)] + pub fn resolution12(self) -> &'a mut W { + self.variant(WLEN_A::RESOLUTION12) + } + #[doc = "16-bit data resolution of the receiver"] + #[inline(always)] + pub fn resolution16(self) -> &'a mut W { + self.variant(WLEN_A::RESOLUTION16) + } + #[doc = "20-bit data resolution of the receiver"] + #[inline(always)] + pub fn resolution20(self) -> &'a mut W { + self.variant(WLEN_A::RESOLUTION20) + } + #[doc = "24-bit data resolution of the receiver"] + #[inline(always)] + pub fn resolution24(self) -> &'a mut W { + self.variant(WLEN_A::RESOLUTION24) + } + #[doc = "32-bit data resolution of the receiver"] + #[inline(always)] + pub fn resolution32(self) -> &'a mut W { + self.variant(WLEN_A::RESOLUTION32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - Desired data resolution of receiver"] + #[inline(always)] + pub fn wlen(&self) -> WLEN_R { + WLEN_R::new((self.bits & 0x07) as u8) + } + } + impl W { + #[doc = "Bits 0:2 - Desired data resolution of receiver"] + #[inline(always)] + pub fn wlen(&mut self) -> WLEN_W { + WLEN_W { w: self } + } + } + } + #[doc = "Transmit Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tcr](tcr) module"] + pub type TCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TCR; + #[doc = "`read()` method returns [tcr::R](tcr::R) reader structure"] + impl crate::Readable for TCR {} + #[doc = "`write(|w| ..)` method takes [tcr::W](tcr::W) writer structure"] + impl crate::Writable for TCR {} + #[doc = "Transmit Configuration Register"] + pub mod tcr { + #[doc = "Reader of register tcr"] + pub type R = crate::R; + #[doc = "Writer for register tcr"] + pub type W = crate::W; + #[doc = "Register tcr `reset()`'s with value 0"] + impl crate::ResetValue for super::TCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Desired data resolution of transmitter"] + pub type WLEN_A = super::rcr::WLEN_A; + #[doc = "Reader of field `wlen`"] + pub type WLEN_R = crate::R; + #[doc = "Write proxy for field `wlen`"] + pub struct WLEN_W<'a> { + w: &'a mut W, + } + impl<'a> WLEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WLEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Ignore the word length"] + #[inline(always)] + pub fn ignore(self) -> &'a mut W { + self.variant(WLEN_A::IGNORE) + } + #[doc = "12-bit data resolution of the receiver"] + #[inline(always)] + pub fn resolution12(self) -> &'a mut W { + self.variant(WLEN_A::RESOLUTION12) + } + #[doc = "16-bit data resolution of the receiver"] + #[inline(always)] + pub fn resolution16(self) -> &'a mut W { + self.variant(WLEN_A::RESOLUTION16) + } + #[doc = "20-bit data resolution of the receiver"] + #[inline(always)] + pub fn resolution20(self) -> &'a mut W { + self.variant(WLEN_A::RESOLUTION20) + } + #[doc = "24-bit data resolution of the receiver"] + #[inline(always)] + pub fn resolution24(self) -> &'a mut W { + self.variant(WLEN_A::RESOLUTION24) + } + #[doc = "32-bit data resolution of the receiver"] + #[inline(always)] + pub fn resolution32(self) -> &'a mut W { + self.variant(WLEN_A::RESOLUTION32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - Desired data resolution of transmitter"] + #[inline(always)] + pub fn wlen(&self) -> WLEN_R { + WLEN_R::new((self.bits & 0x07) as u8) + } + } + impl W { + #[doc = "Bits 0:2 - Desired data resolution of transmitter"] + #[inline(always)] + pub fn wlen(&mut self) -> WLEN_W { + WLEN_W { w: self } + } + } + } + #[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr](isr) module"] + pub type ISR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ISR; + #[doc = "`read()` method returns [isr::R](isr::R) reader structure"] + impl crate::Readable for ISR {} + #[doc = "Interrupt Status Register"] + pub mod isr { + #[doc = "Reader of register isr"] + pub type R = crate::R; + #[doc = "Reader of field `rxda`"] + pub type RXDA_R = crate::R; + #[doc = "Reader of field `rxfo`"] + pub type RXFO_R = crate::R; + #[doc = "Reader of field `txfe`"] + pub type TXFE_R = crate::R; + #[doc = "Reader of field `txfo`"] + pub type TXFO_R = crate::R; + impl R { + #[doc = "Bit 0 - Status of receiver data avaliable interrupt"] + #[inline(always)] + pub fn rxda(&self) -> RXDA_R { + RXDA_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Status of data overrun interrupt for RX channel"] + #[inline(always)] + pub fn rxfo(&self) -> RXFO_R { + RXFO_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Status of transmit empty triger interrupt"] + #[inline(always)] + pub fn txfe(&self) -> TXFE_R { + TXFE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Status of data overrun interrupt for the TX channel"] + #[inline(always)] + pub fn txfo(&self) -> TXFO_R { + TXFO_R::new(((self.bits >> 5) & 0x01) != 0) + } + } + } + #[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](imr) module"] + pub type IMR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IMR; + #[doc = "`read()` method returns [imr::R](imr::R) reader structure"] + impl crate::Readable for IMR {} + #[doc = "`write(|w| ..)` method takes [imr::W](imr::W) writer structure"] + impl crate::Writable for IMR {} + #[doc = "Interrupt Mask Register"] + pub mod imr { + #[doc = "Reader of register imr"] + pub type R = crate::R; + #[doc = "Writer for register imr"] + pub type W = crate::W; + #[doc = "Register imr `reset()`'s with value 0"] + impl crate::ResetValue for super::IMR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `rxdam`"] + pub type RXDAM_R = crate::R; + #[doc = "Write proxy for field `rxdam`"] + pub struct RXDAM_W<'a> { + w: &'a mut W, + } + impl<'a> RXDAM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `rxfom`"] + pub type RXFOM_R = crate::R; + #[doc = "Write proxy for field `rxfom`"] + pub struct RXFOM_W<'a> { + w: &'a mut W, + } + impl<'a> RXFOM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `txfem`"] + pub type TXFEM_R = crate::R; + #[doc = "Write proxy for field `txfem`"] + pub struct TXFEM_W<'a> { + w: &'a mut W, + } + impl<'a> TXFEM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `txfom`"] + pub type TXFOM_R = crate::R; + #[doc = "Write proxy for field `txfom`"] + pub struct TXFOM_W<'a> { + w: &'a mut W, + } + impl<'a> TXFOM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + impl R { + #[doc = "Bit 0 - Mask RX FIFO data avaliable interrupt"] + #[inline(always)] + pub fn rxdam(&self) -> RXDAM_R { + RXDAM_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Mask RX FIFO overrun interrupt"] + #[inline(always)] + pub fn rxfom(&self) -> RXFOM_R { + RXFOM_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Mask TX FIFO empty interrupt"] + #[inline(always)] + pub fn txfem(&self) -> TXFEM_R { + TXFEM_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Mask TX FIFO overrun interrupt"] + #[inline(always)] + pub fn txfom(&self) -> TXFOM_R { + TXFOM_R::new(((self.bits >> 5) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Mask RX FIFO data avaliable interrupt"] + #[inline(always)] + pub fn rxdam(&mut self) -> RXDAM_W { + RXDAM_W { w: self } + } + #[doc = "Bit 1 - Mask RX FIFO overrun interrupt"] + #[inline(always)] + pub fn rxfom(&mut self) -> RXFOM_W { + RXFOM_W { w: self } + } + #[doc = "Bit 4 - Mask TX FIFO empty interrupt"] + #[inline(always)] + pub fn txfem(&mut self) -> TXFEM_W { + TXFEM_W { w: self } + } + #[doc = "Bit 5 - Mask TX FIFO overrun interrupt"] + #[inline(always)] + pub fn txfom(&mut self) -> TXFOM_W { + TXFOM_W { w: self } + } + } + } + #[doc = "Receive Overrun Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ror](ror) module"] + pub type ROR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ROR; + #[doc = "`read()` method returns [ror::R](ror::R) reader structure"] + impl crate::Readable for ROR {} + #[doc = "Receive Overrun Register"] + pub mod ror { + #[doc = "Reader of register ror"] + pub type R = crate::R; + #[doc = "Reader of field `rxcho`"] + pub type RXCHO_R = crate::R; + impl R { + #[doc = "Bit 0 - Read this bit to clear RX FIFO data overrun interrupt. 0x0 for RX FIFO write valid, 0x1 for RX FIFO write overrun"] + #[inline(always)] + pub fn rxcho(&self) -> RXCHO_R { + RXCHO_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Transmit Overrun Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tor](tor) module"] + pub type TOR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TOR; + #[doc = "`read()` method returns [tor::R](tor::R) reader structure"] + impl crate::Readable for TOR {} + #[doc = "Transmit Overrun Register"] + pub mod tor { + #[doc = "Reader of register tor"] + pub type R = crate::R; + #[doc = "Reader of field `txcho`"] + pub type TXCHO_R = crate::R; + impl R { + #[doc = "Bit 0 - Read this bit to clear TX FIFO data overrun interrupt. 0x0 for TX FIFO write valid, 0x1 for TX FIFO write overrun"] + #[inline(always)] + pub fn txcho(&self) -> TXCHO_R { + TXCHO_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Receive FIFO Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rfcr](rfcr) module"] + pub type RFCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RFCR; + #[doc = "`read()` method returns [rfcr::R](rfcr::R) reader structure"] + impl crate::Readable for RFCR {} + #[doc = "`write(|w| ..)` method takes [rfcr::W](rfcr::W) writer structure"] + impl crate::Writable for RFCR {} + #[doc = "Receive FIFO Configuration Register"] + pub mod rfcr { + #[doc = "Reader of register rfcr"] + pub type R = crate::R; + #[doc = "Writer for register rfcr"] + pub type W = crate::W; + #[doc = "Register rfcr `reset()`'s with value 0"] + impl crate::ResetValue for super::RFCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Trigger level in the RX FIFO at which the receiver data available interrupt generate\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum RXCHDT_A { + #[doc = "0: Interrupt trigger when FIFO level is 1"] + LEVEL1 = 0, + #[doc = "1: Interrupt trigger when FIFO level is 2"] + LEVEL2 = 1, + #[doc = "2: Interrupt trigger when FIFO level is 3"] + LEVEL3 = 2, + #[doc = "3: Interrupt trigger when FIFO level is 4"] + LEVEL4 = 3, + #[doc = "4: Interrupt trigger when FIFO level is 5"] + LEVEL5 = 4, + #[doc = "5: Interrupt trigger when FIFO level is 6"] + LEVEL6 = 5, + #[doc = "6: Interrupt trigger when FIFO level is 7"] + LEVEL7 = 6, + #[doc = "7: Interrupt trigger when FIFO level is 8"] + LEVEL8 = 7, + #[doc = "8: Interrupt trigger when FIFO level is 9"] + LEVEL9 = 8, + #[doc = "9: Interrupt trigger when FIFO level is 10"] + LEVEL10 = 9, + #[doc = "10: Interrupt trigger when FIFO level is 11"] + LEVEL11 = 10, + #[doc = "11: Interrupt trigger when FIFO level is 12"] + LEVEL12 = 11, + #[doc = "12: Interrupt trigger when FIFO level is 13"] + LEVEL13 = 12, + #[doc = "13: Interrupt trigger when FIFO level is 14"] + LEVEL14 = 13, + #[doc = "14: Interrupt trigger when FIFO level is 15"] + LEVEL15 = 14, + #[doc = "15: Interrupt trigger when FIFO level is 16"] + LEVEL16 = 15, + } + impl From for u8 { + #[inline(always)] + fn from(variant: RXCHDT_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `rxchdt`"] + pub type RXCHDT_R = crate::R; + impl RXCHDT_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXCHDT_A { + match self.bits { + 0 => RXCHDT_A::LEVEL1, + 1 => RXCHDT_A::LEVEL2, + 2 => RXCHDT_A::LEVEL3, + 3 => RXCHDT_A::LEVEL4, + 4 => RXCHDT_A::LEVEL5, + 5 => RXCHDT_A::LEVEL6, + 6 => RXCHDT_A::LEVEL7, + 7 => RXCHDT_A::LEVEL8, + 8 => RXCHDT_A::LEVEL9, + 9 => RXCHDT_A::LEVEL10, + 10 => RXCHDT_A::LEVEL11, + 11 => RXCHDT_A::LEVEL12, + 12 => RXCHDT_A::LEVEL13, + 13 => RXCHDT_A::LEVEL14, + 14 => RXCHDT_A::LEVEL15, + 15 => RXCHDT_A::LEVEL16, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `LEVEL1`"] + #[inline(always)] + pub fn is_level1(&self) -> bool { + *self == RXCHDT_A::LEVEL1 + } + #[doc = "Checks if the value of the field is `LEVEL2`"] + #[inline(always)] + pub fn is_level2(&self) -> bool { + *self == RXCHDT_A::LEVEL2 + } + #[doc = "Checks if the value of the field is `LEVEL3`"] + #[inline(always)] + pub fn is_level3(&self) -> bool { + *self == RXCHDT_A::LEVEL3 + } + #[doc = "Checks if the value of the field is `LEVEL4`"] + #[inline(always)] + pub fn is_level4(&self) -> bool { + *self == RXCHDT_A::LEVEL4 + } + #[doc = "Checks if the value of the field is `LEVEL5`"] + #[inline(always)] + pub fn is_level5(&self) -> bool { + *self == RXCHDT_A::LEVEL5 + } + #[doc = "Checks if the value of the field is `LEVEL6`"] + #[inline(always)] + pub fn is_level6(&self) -> bool { + *self == RXCHDT_A::LEVEL6 + } + #[doc = "Checks if the value of the field is `LEVEL7`"] + #[inline(always)] + pub fn is_level7(&self) -> bool { + *self == RXCHDT_A::LEVEL7 + } + #[doc = "Checks if the value of the field is `LEVEL8`"] + #[inline(always)] + pub fn is_level8(&self) -> bool { + *self == RXCHDT_A::LEVEL8 + } + #[doc = "Checks if the value of the field is `LEVEL9`"] + #[inline(always)] + pub fn is_level9(&self) -> bool { + *self == RXCHDT_A::LEVEL9 + } + #[doc = "Checks if the value of the field is `LEVEL10`"] + #[inline(always)] + pub fn is_level10(&self) -> bool { + *self == RXCHDT_A::LEVEL10 + } + #[doc = "Checks if the value of the field is `LEVEL11`"] + #[inline(always)] + pub fn is_level11(&self) -> bool { + *self == RXCHDT_A::LEVEL11 + } + #[doc = "Checks if the value of the field is `LEVEL12`"] + #[inline(always)] + pub fn is_level12(&self) -> bool { + *self == RXCHDT_A::LEVEL12 + } + #[doc = "Checks if the value of the field is `LEVEL13`"] + #[inline(always)] + pub fn is_level13(&self) -> bool { + *self == RXCHDT_A::LEVEL13 + } + #[doc = "Checks if the value of the field is `LEVEL14`"] + #[inline(always)] + pub fn is_level14(&self) -> bool { + *self == RXCHDT_A::LEVEL14 + } + #[doc = "Checks if the value of the field is `LEVEL15`"] + #[inline(always)] + pub fn is_level15(&self) -> bool { + *self == RXCHDT_A::LEVEL15 + } + #[doc = "Checks if the value of the field is `LEVEL16`"] + #[inline(always)] + pub fn is_level16(&self) -> bool { + *self == RXCHDT_A::LEVEL16 + } + } + #[doc = "Write proxy for field `rxchdt`"] + pub struct RXCHDT_W<'a> { + w: &'a mut W, + } + impl<'a> RXCHDT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXCHDT_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "Interrupt trigger when FIFO level is 1"] + #[inline(always)] + pub fn level1(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL1) + } + #[doc = "Interrupt trigger when FIFO level is 2"] + #[inline(always)] + pub fn level2(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL2) + } + #[doc = "Interrupt trigger when FIFO level is 3"] + #[inline(always)] + pub fn level3(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL3) + } + #[doc = "Interrupt trigger when FIFO level is 4"] + #[inline(always)] + pub fn level4(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL4) + } + #[doc = "Interrupt trigger when FIFO level is 5"] + #[inline(always)] + pub fn level5(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL5) + } + #[doc = "Interrupt trigger when FIFO level is 6"] + #[inline(always)] + pub fn level6(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL6) + } + #[doc = "Interrupt trigger when FIFO level is 7"] + #[inline(always)] + pub fn level7(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL7) + } + #[doc = "Interrupt trigger when FIFO level is 8"] + #[inline(always)] + pub fn level8(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL8) + } + #[doc = "Interrupt trigger when FIFO level is 9"] + #[inline(always)] + pub fn level9(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL9) + } + #[doc = "Interrupt trigger when FIFO level is 10"] + #[inline(always)] + pub fn level10(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL10) + } + #[doc = "Interrupt trigger when FIFO level is 11"] + #[inline(always)] + pub fn level11(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL11) + } + #[doc = "Interrupt trigger when FIFO level is 12"] + #[inline(always)] + pub fn level12(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL12) + } + #[doc = "Interrupt trigger when FIFO level is 13"] + #[inline(always)] + pub fn level13(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL13) + } + #[doc = "Interrupt trigger when FIFO level is 14"] + #[inline(always)] + pub fn level14(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL14) + } + #[doc = "Interrupt trigger when FIFO level is 15"] + #[inline(always)] + pub fn level15(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL15) + } + #[doc = "Interrupt trigger when FIFO level is 16"] + #[inline(always)] + pub fn level16(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL16) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f); + self.w + } + } + impl R { + #[doc = "Bits 0:3 - Trigger level in the RX FIFO at which the receiver data available interrupt generate"] + #[inline(always)] + pub fn rxchdt(&self) -> RXCHDT_R { + RXCHDT_R::new((self.bits & 0x0f) as u8) + } + } + impl W { + #[doc = "Bits 0:3 - Trigger level in the RX FIFO at which the receiver data available interrupt generate"] + #[inline(always)] + pub fn rxchdt(&mut self) -> RXCHDT_W { + RXCHDT_W { w: self } + } + } + } + #[doc = "Transmit FIFO Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tfcr](tfcr) module"] + pub type TFCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TFCR; + #[doc = "`read()` method returns [tfcr::R](tfcr::R) reader structure"] + impl crate::Readable for TFCR {} + #[doc = "`write(|w| ..)` method takes [tfcr::W](tfcr::W) writer structure"] + impl crate::Writable for TFCR {} + #[doc = "Transmit FIFO Configuration Register"] + pub mod tfcr { + #[doc = "Reader of register tfcr"] + pub type R = crate::R; + #[doc = "Writer for register tfcr"] + pub type W = crate::W; + #[doc = "Register tfcr `reset()`'s with value 0"] + impl crate::ResetValue for super::TFCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Trigger level in the TX FIFO at which the transmitter data available interrupt generate"] + pub type TXCHET_A = super::rfcr::RXCHDT_A; + #[doc = "Reader of field `txchet`"] + pub type TXCHET_R = crate::R; + #[doc = "Write proxy for field `txchet`"] + pub struct TXCHET_W<'a> { + w: &'a mut W, + } + impl<'a> TXCHET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXCHET_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "Interrupt trigger when FIFO level is 1"] + #[inline(always)] + pub fn level1(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL1) + } + #[doc = "Interrupt trigger when FIFO level is 2"] + #[inline(always)] + pub fn level2(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL2) + } + #[doc = "Interrupt trigger when FIFO level is 3"] + #[inline(always)] + pub fn level3(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL3) + } + #[doc = "Interrupt trigger when FIFO level is 4"] + #[inline(always)] + pub fn level4(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL4) + } + #[doc = "Interrupt trigger when FIFO level is 5"] + #[inline(always)] + pub fn level5(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL5) + } + #[doc = "Interrupt trigger when FIFO level is 6"] + #[inline(always)] + pub fn level6(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL6) + } + #[doc = "Interrupt trigger when FIFO level is 7"] + #[inline(always)] + pub fn level7(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL7) + } + #[doc = "Interrupt trigger when FIFO level is 8"] + #[inline(always)] + pub fn level8(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL8) + } + #[doc = "Interrupt trigger when FIFO level is 9"] + #[inline(always)] + pub fn level9(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL9) + } + #[doc = "Interrupt trigger when FIFO level is 10"] + #[inline(always)] + pub fn level10(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL10) + } + #[doc = "Interrupt trigger when FIFO level is 11"] + #[inline(always)] + pub fn level11(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL11) + } + #[doc = "Interrupt trigger when FIFO level is 12"] + #[inline(always)] + pub fn level12(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL12) + } + #[doc = "Interrupt trigger when FIFO level is 13"] + #[inline(always)] + pub fn level13(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL13) + } + #[doc = "Interrupt trigger when FIFO level is 14"] + #[inline(always)] + pub fn level14(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL14) + } + #[doc = "Interrupt trigger when FIFO level is 15"] + #[inline(always)] + pub fn level15(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL15) + } + #[doc = "Interrupt trigger when FIFO level is 16"] + #[inline(always)] + pub fn level16(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL16) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f); + self.w + } + } + impl R { + #[doc = "Bits 0:3 - Trigger level in the TX FIFO at which the transmitter data available interrupt generate"] + #[inline(always)] + pub fn txchet(&self) -> TXCHET_R { + TXCHET_R::new((self.bits & 0x0f) as u8) + } + } + impl W { + #[doc = "Bits 0:3 - Trigger level in the TX FIFO at which the transmitter data available interrupt generate"] + #[inline(always)] + pub fn txchet(&mut self) -> TXCHET_W { + TXCHET_W { w: self } + } + } + } + #[doc = "Receive FIFO Flush Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rff](rff) module"] + pub type RFF = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RFF; + #[doc = "`read()` method returns [rff::R](rff::R) reader structure"] + impl crate::Readable for RFF {} + #[doc = "`write(|w| ..)` method takes [rff::W](rff::W) writer structure"] + impl crate::Writable for RFF {} + #[doc = "Receive FIFO Flush Register"] + pub mod rff { + #[doc = "Reader of register rff"] + pub type R = crate::R; + #[doc = "Writer for register rff"] + pub type W = crate::W; + #[doc = "Register rff `reset()`'s with value 0"] + impl crate::ResetValue for super::RFF { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Receiver channel FIFO reset\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum RXCHFR_A { + #[doc = "0: Not flush an individual FIFO"] + NOT_FLUSH = 0, + #[doc = "1: Flush an indiviadual FIFO"] + FLUSH = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: RXCHFR_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `rxchfr`"] + pub type RXCHFR_R = crate::R; + impl RXCHFR_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXCHFR_A { + match self.bits { + false => RXCHFR_A::NOT_FLUSH, + true => RXCHFR_A::FLUSH, + } + } + #[doc = "Checks if the value of the field is `NOT_FLUSH`"] + #[inline(always)] + pub fn is_not_flush(&self) -> bool { + *self == RXCHFR_A::NOT_FLUSH + } + #[doc = "Checks if the value of the field is `FLUSH`"] + #[inline(always)] + pub fn is_flush(&self) -> bool { + *self == RXCHFR_A::FLUSH + } + } + #[doc = "Write proxy for field `rxchfr`"] + pub struct RXCHFR_W<'a> { + w: &'a mut W, + } + impl<'a> RXCHFR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXCHFR_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Not flush an individual FIFO"] + #[inline(always)] + pub fn not_flush(self) -> &'a mut W { + self.variant(RXCHFR_A::NOT_FLUSH) + } + #[doc = "Flush an indiviadual FIFO"] + #[inline(always)] + pub fn flush(self) -> &'a mut W { + self.variant(RXCHFR_A::FLUSH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Receiver channel FIFO reset"] + #[inline(always)] + pub fn rxchfr(&self) -> RXCHFR_R { + RXCHFR_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Receiver channel FIFO reset"] + #[inline(always)] + pub fn rxchfr(&mut self) -> RXCHFR_W { + RXCHFR_W { w: self } + } + } + } + #[doc = "Transmit FIFO Flush Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tff](tff) module"] + pub type TFF = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TFF; + #[doc = "`read()` method returns [tff::R](tff::R) reader structure"] + impl crate::Readable for TFF {} + #[doc = "`write(|w| ..)` method takes [tff::W](tff::W) writer structure"] + impl crate::Writable for TFF {} + #[doc = "Transmit FIFO Flush Register"] + pub mod tff { + #[doc = "Reader of register tff"] + pub type R = crate::R; + #[doc = "Writer for register tff"] + pub type W = crate::W; + #[doc = "Register tff `reset()`'s with value 0"] + impl crate::ResetValue for super::TFF { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Transmit channel FIFO reset"] + pub type RTXCHFR_A = super::rff::RXCHFR_A; + #[doc = "Reader of field `rtxchfr`"] + pub type RTXCHFR_R = crate::R; + #[doc = "Write proxy for field `rtxchfr`"] + pub struct RTXCHFR_W<'a> { + w: &'a mut W, + } + impl<'a> RTXCHFR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RTXCHFR_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Not flush an individual FIFO"] + #[inline(always)] + pub fn not_flush(self) -> &'a mut W { + self.variant(RTXCHFR_A::NOT_FLUSH) + } + #[doc = "Flush an indiviadual FIFO"] + #[inline(always)] + pub fn flush(self) -> &'a mut W { + self.variant(RTXCHFR_A::FLUSH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Transmit channel FIFO reset"] + #[inline(always)] + pub fn rtxchfr(&self) -> RTXCHFR_R { + RTXCHFR_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Transmit channel FIFO reset"] + #[inline(always)] + pub fn rtxchfr(&mut self) -> RTXCHFR_W { + RTXCHFR_W { w: self } + } + } + } + #[doc = "_RESERVED0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_reserved](_reserved) module"] + pub type _RESERVED = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct __RESERVED; + #[doc = "`read()` method returns [_reserved::R](_reserved::R) reader structure"] + impl crate::Readable for _RESERVED {} + #[doc = "`write(|w| ..)` method takes [_reserved::W](_reserved::W) writer structure"] + impl crate::Writable for _RESERVED {} + #[doc = "_RESERVED0"] + pub mod _reserved { + #[doc = "Reader of register _reserved%s"] + pub type R = crate::R; + #[doc = "Writer for register _reserved%s"] + pub type W = crate::W; + #[doc = "Register _reserved%s `reset()`'s with value 0"] + impl crate::ResetValue for super::_RESERVED { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + } + #[doc = "Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](ier) module"] + pub type IER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IER; + #[doc = "`read()` method returns [ier::R](ier::R) reader structure"] + impl crate::Readable for IER {} + #[doc = "`write(|w| ..)` method takes [ier::W](ier::W) writer structure"] + impl crate::Writable for IER {} + #[doc = "Enable Register"] + pub mod ier { + #[doc = "Reader of register ier"] + pub type R = crate::R; + #[doc = "Writer for register ier"] + pub type W = crate::W; + #[doc = "Register ier `reset()`'s with value 0"] + impl crate::ResetValue for super::IER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `ien`"] + pub type IEN_R = crate::R; + #[doc = "Write proxy for field `ien`"] + pub struct IEN_W<'a> { + w: &'a mut W, + } + impl<'a> IEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - I2S Enable"] + #[inline(always)] + pub fn ien(&self) -> IEN_R { + IEN_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - I2S Enable"] + #[inline(always)] + pub fn ien(&mut self) -> IEN_W { + IEN_W { w: self } + } + } + } + #[doc = "Receiver Block Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irer](irer) module"] + pub type IRER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IRER; + #[doc = "`read()` method returns [irer::R](irer::R) reader structure"] + impl crate::Readable for IRER {} + #[doc = "`write(|w| ..)` method takes [irer::W](irer::W) writer structure"] + impl crate::Writable for IRER {} + #[doc = "Receiver Block Enable Register"] + pub mod irer { + #[doc = "Reader of register irer"] + pub type R = crate::R; + #[doc = "Writer for register irer"] + pub type W = crate::W; + #[doc = "Register irer `reset()`'s with value 0"] + impl crate::ResetValue for super::IRER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `rxen`"] + pub type RXEN_R = crate::R; + #[doc = "Write proxy for field `rxen`"] + pub struct RXEN_W<'a> { + w: &'a mut W, + } + impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Receiver block enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Receiver block enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + } + } + #[doc = "Transmitter Block Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iter](iter) module"] + pub type ITER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ITER; + #[doc = "`read()` method returns [iter::R](iter::R) reader structure"] + impl crate::Readable for ITER {} + #[doc = "`write(|w| ..)` method takes [iter::W](iter::W) writer structure"] + impl crate::Writable for ITER {} + #[doc = "Transmitter Block Enable Register"] + pub mod iter { + #[doc = "Reader of register iter"] + pub type R = crate::R; + #[doc = "Writer for register iter"] + pub type W = crate::W; + #[doc = "Register iter `reset()`'s with value 0"] + impl crate::ResetValue for super::ITER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `txen`"] + pub type TXEN_R = crate::R; + #[doc = "Write proxy for field `txen`"] + pub struct TXEN_W<'a> { + w: &'a mut W, + } + impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Transmitter block enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Transmitter block enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + } + } + #[doc = "Clock Generation enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cer](cer) module"] + pub type CER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CER; + #[doc = "`read()` method returns [cer::R](cer::R) reader structure"] + impl crate::Readable for CER {} + #[doc = "`write(|w| ..)` method takes [cer::W](cer::W) writer structure"] + impl crate::Writable for CER {} + #[doc = "Clock Generation enable"] + pub mod cer { + #[doc = "Reader of register cer"] + pub type R = crate::R; + #[doc = "Writer for register cer"] + pub type W = crate::W; + #[doc = "Register cer `reset()`'s with value 0"] + impl crate::ResetValue for super::CER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `clken`"] + pub type CLKEN_R = crate::R; + #[doc = "Write proxy for field `clken`"] + pub struct CLKEN_W<'a> { + w: &'a mut W, + } + impl<'a> CLKEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Transmitter block enable"] + #[inline(always)] + pub fn clken(&self) -> CLKEN_R { + CLKEN_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Transmitter block enable"] + #[inline(always)] + pub fn clken(&mut self) -> CLKEN_W { + CLKEN_W { w: self } + } + } + } + #[doc = "Clock Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr](ccr) module"] + pub type CCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CCR; + #[doc = "`read()` method returns [ccr::R](ccr::R) reader structure"] + impl crate::Readable for CCR {} + #[doc = "`write(|w| ..)` method takes [ccr::W](ccr::W) writer structure"] + impl crate::Writable for CCR {} + #[doc = "Clock Configuration Register"] + pub mod ccr { + #[doc = "Reader of register ccr"] + pub type R = crate::R; + #[doc = "Writer for register ccr"] + pub type W = crate::W; + #[doc = "Register ccr `reset()`'s with value 0"] + impl crate::ResetValue for super::CCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Gating of sclk\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum CLK_GATE_A { + #[doc = "0: Clock gating is disabled"] + NO = 0, + #[doc = "1: Gating after 12 sclk cycles"] + CYCLES12 = 1, + #[doc = "2: Gating after 16 sclk cycles"] + CYCLES16 = 2, + #[doc = "3: Gating after 20 sclk cycles"] + CYCLES20 = 3, + #[doc = "4: Gating after 24 sclk cycles"] + CYCLES24 = 4, + } + impl From for u8 { + #[inline(always)] + fn from(variant: CLK_GATE_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `clk_gate`"] + pub type CLK_GATE_R = crate::R; + impl CLK_GATE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(CLK_GATE_A::NO), + 1 => Val(CLK_GATE_A::CYCLES12), + 2 => Val(CLK_GATE_A::CYCLES16), + 3 => Val(CLK_GATE_A::CYCLES20), + 4 => Val(CLK_GATE_A::CYCLES24), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `NO`"] + #[inline(always)] + pub fn is_no(&self) -> bool { + *self == CLK_GATE_A::NO + } + #[doc = "Checks if the value of the field is `CYCLES12`"] + #[inline(always)] + pub fn is_cycles12(&self) -> bool { + *self == CLK_GATE_A::CYCLES12 + } + #[doc = "Checks if the value of the field is `CYCLES16`"] + #[inline(always)] + pub fn is_cycles16(&self) -> bool { + *self == CLK_GATE_A::CYCLES16 + } + #[doc = "Checks if the value of the field is `CYCLES20`"] + #[inline(always)] + pub fn is_cycles20(&self) -> bool { + *self == CLK_GATE_A::CYCLES20 + } + #[doc = "Checks if the value of the field is `CYCLES24`"] + #[inline(always)] + pub fn is_cycles24(&self) -> bool { + *self == CLK_GATE_A::CYCLES24 + } + } + #[doc = "Write proxy for field `clk_gate`"] + pub struct CLK_GATE_W<'a> { + w: &'a mut W, + } + impl<'a> CLK_GATE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLK_GATE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Clock gating is disabled"] + #[inline(always)] + pub fn no(self) -> &'a mut W { + self.variant(CLK_GATE_A::NO) + } + #[doc = "Gating after 12 sclk cycles"] + #[inline(always)] + pub fn cycles12(self) -> &'a mut W { + self.variant(CLK_GATE_A::CYCLES12) + } + #[doc = "Gating after 16 sclk cycles"] + #[inline(always)] + pub fn cycles16(self) -> &'a mut W { + self.variant(CLK_GATE_A::CYCLES16) + } + #[doc = "Gating after 20 sclk cycles"] + #[inline(always)] + pub fn cycles20(self) -> &'a mut W { + self.variant(CLK_GATE_A::CYCLES20) + } + #[doc = "Gating after 24 sclk cycles"] + #[inline(always)] + pub fn cycles24(self) -> &'a mut W { + self.variant(CLK_GATE_A::CYCLES24) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + #[doc = "The number of sclk cycles for which the word select line stayd in the left aligned or right aligned mode\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum CLK_WORD_SIZE_A { + #[doc = "0: 16 sclk cycles"] + CYCLES16 = 0, + #[doc = "1: 24 sclk cycles"] + CYCLES24 = 1, + #[doc = "2: 32 sclk cycles"] + CYCLES32 = 2, + } + impl From for u8 { + #[inline(always)] + fn from(variant: CLK_WORD_SIZE_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `clk_word_size`"] + pub type CLK_WORD_SIZE_R = crate::R; + impl CLK_WORD_SIZE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(CLK_WORD_SIZE_A::CYCLES16), + 1 => Val(CLK_WORD_SIZE_A::CYCLES24), + 2 => Val(CLK_WORD_SIZE_A::CYCLES32), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `CYCLES16`"] + #[inline(always)] + pub fn is_cycles16(&self) -> bool { + *self == CLK_WORD_SIZE_A::CYCLES16 + } + #[doc = "Checks if the value of the field is `CYCLES24`"] + #[inline(always)] + pub fn is_cycles24(&self) -> bool { + *self == CLK_WORD_SIZE_A::CYCLES24 + } + #[doc = "Checks if the value of the field is `CYCLES32`"] + #[inline(always)] + pub fn is_cycles32(&self) -> bool { + *self == CLK_WORD_SIZE_A::CYCLES32 + } + } + #[doc = "Write proxy for field `clk_word_size`"] + pub struct CLK_WORD_SIZE_W<'a> { + w: &'a mut W, + } + impl<'a> CLK_WORD_SIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLK_WORD_SIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16 sclk cycles"] + #[inline(always)] + pub fn cycles16(self) -> &'a mut W { + self.variant(CLK_WORD_SIZE_A::CYCLES16) + } + #[doc = "24 sclk cycles"] + #[inline(always)] + pub fn cycles24(self) -> &'a mut W { + self.variant(CLK_WORD_SIZE_A::CYCLES24) + } + #[doc = "32 sclk cycles"] + #[inline(always)] + pub fn cycles32(self) -> &'a mut W { + self.variant(CLK_WORD_SIZE_A::CYCLES32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | (((value as u32) & 0x03) << 3); + self.w + } + } + #[doc = "Alignment mode setting\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum ALIGN_MODE_A { + #[doc = "1: Standard I2S format"] + STANDARD = 1, + #[doc = "2: Right aligned format"] + RIGHT = 2, + #[doc = "4: Left aligned format"] + LEFT = 4, + } + impl From for u8 { + #[inline(always)] + fn from(variant: ALIGN_MODE_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `align_mode`"] + pub type ALIGN_MODE_R = crate::R; + impl ALIGN_MODE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 1 => Val(ALIGN_MODE_A::STANDARD), + 2 => Val(ALIGN_MODE_A::RIGHT), + 4 => Val(ALIGN_MODE_A::LEFT), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `STANDARD`"] + #[inline(always)] + pub fn is_standard(&self) -> bool { + *self == ALIGN_MODE_A::STANDARD + } + #[doc = "Checks if the value of the field is `RIGHT`"] + #[inline(always)] + pub fn is_right(&self) -> bool { + *self == ALIGN_MODE_A::RIGHT + } + #[doc = "Checks if the value of the field is `LEFT`"] + #[inline(always)] + pub fn is_left(&self) -> bool { + *self == ALIGN_MODE_A::LEFT + } + } + #[doc = "Write proxy for field `align_mode`"] + pub struct ALIGN_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> ALIGN_MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ALIGN_MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard I2S format"] + #[inline(always)] + pub fn standard(self) -> &'a mut W { + self.variant(ALIGN_MODE_A::STANDARD) + } + #[doc = "Right aligned format"] + #[inline(always)] + pub fn right(self) -> &'a mut W { + self.variant(ALIGN_MODE_A::RIGHT) + } + #[doc = "Left aligned format"] + #[inline(always)] + pub fn left(self) -> &'a mut W { + self.variant(ALIGN_MODE_A::LEFT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | (((value as u32) & 0x07) << 5); + self.w + } + } + #[doc = "Reader of field `dma_tx_en`"] + pub type DMA_TX_EN_R = crate::R; + #[doc = "Write proxy for field `dma_tx_en`"] + pub struct DMA_TX_EN_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_TX_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `dma_rx_en`"] + pub type DMA_RX_EN_R = crate::R; + #[doc = "Write proxy for field `dma_rx_en`"] + pub struct DMA_RX_EN_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_RX_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `dma_divide_16`"] + pub type DMA_DIVIDE_16_R = crate::R; + #[doc = "Write proxy for field `dma_divide_16`"] + pub struct DMA_DIVIDE_16_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_DIVIDE_16_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `sign_expand_en`"] + pub type SIGN_EXPAND_EN_R = crate::R; + #[doc = "Write proxy for field `sign_expand_en`"] + pub struct SIGN_EXPAND_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SIGN_EXPAND_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - Gating of sclk"] + #[inline(always)] + pub fn clk_gate(&self) -> CLK_GATE_R { + CLK_GATE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:4 - The number of sclk cycles for which the word select line stayd in the left aligned or right aligned mode"] + #[inline(always)] + pub fn clk_word_size(&self) -> CLK_WORD_SIZE_R { + CLK_WORD_SIZE_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - Alignment mode setting"] + #[inline(always)] + pub fn align_mode(&self) -> ALIGN_MODE_R { + ALIGN_MODE_R::new(((self.bits >> 5) & 0x07) as u8) + } + #[doc = "Bit 8 - DMA transmit enable control"] + #[inline(always)] + pub fn dma_tx_en(&self) -> DMA_TX_EN_R { + DMA_TX_EN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DMA receive enable control"] + #[inline(always)] + pub fn dma_rx_en(&self) -> DMA_RX_EN_R { + DMA_RX_EN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Split 32bit data to two 16 bit data and filled in left and right channel. Used with dma_tx_en or dma_rx_en"] + #[inline(always)] + pub fn dma_divide_16(&self) -> DMA_DIVIDE_16_R { + DMA_DIVIDE_16_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - SIGN_EXPAND_EN"] + #[inline(always)] + pub fn sign_expand_en(&self) -> SIGN_EXPAND_EN_R { + SIGN_EXPAND_EN_R::new(((self.bits >> 11) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:2 - Gating of sclk"] + #[inline(always)] + pub fn clk_gate(&mut self) -> CLK_GATE_W { + CLK_GATE_W { w: self } + } + #[doc = "Bits 3:4 - The number of sclk cycles for which the word select line stayd in the left aligned or right aligned mode"] + #[inline(always)] + pub fn clk_word_size(&mut self) -> CLK_WORD_SIZE_W { + CLK_WORD_SIZE_W { w: self } + } + #[doc = "Bits 5:7 - Alignment mode setting"] + #[inline(always)] + pub fn align_mode(&mut self) -> ALIGN_MODE_W { + ALIGN_MODE_W { w: self } + } + #[doc = "Bit 8 - DMA transmit enable control"] + #[inline(always)] + pub fn dma_tx_en(&mut self) -> DMA_TX_EN_W { + DMA_TX_EN_W { w: self } + } + #[doc = "Bit 9 - DMA receive enable control"] + #[inline(always)] + pub fn dma_rx_en(&mut self) -> DMA_RX_EN_W { + DMA_RX_EN_W { w: self } + } + #[doc = "Bit 10 - Split 32bit data to two 16 bit data and filled in left and right channel. Used with dma_tx_en or dma_rx_en"] + #[inline(always)] + pub fn dma_divide_16(&mut self) -> DMA_DIVIDE_16_W { + DMA_DIVIDE_16_W { w: self } + } + #[doc = "Bit 11 - SIGN_EXPAND_EN"] + #[inline(always)] + pub fn sign_expand_en(&mut self) -> SIGN_EXPAND_EN_W { + SIGN_EXPAND_EN_W { w: self } + } + } + } + #[doc = "Receiver Block FIFO Reset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxffr](rxffr) module"] + pub type RXFFR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXFFR; + #[doc = "`read()` method returns [rxffr::R](rxffr::R) reader structure"] + impl crate::Readable for RXFFR {} + #[doc = "`write(|w| ..)` method takes [rxffr::W](rxffr::W) writer structure"] + impl crate::Writable for RXFFR {} + #[doc = "Receiver Block FIFO Reset Register"] + pub mod rxffr { + #[doc = "Reader of register rxffr"] + pub type R = crate::R; + #[doc = "Writer for register rxffr"] + pub type W = crate::W; + #[doc = "Register rxffr `reset()`'s with value 0"] + impl crate::ResetValue for super::RXFFR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Receiver FIFO reset\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum RXFFR_A { + #[doc = "0: Not flush FIFO"] + NOT_FLUSH = 0, + #[doc = "1: Flush FIFO"] + FLUSH = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: RXFFR_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `rxffr`"] + pub type RXFFR_R = crate::R; + impl RXFFR_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXFFR_A { + match self.bits { + false => RXFFR_A::NOT_FLUSH, + true => RXFFR_A::FLUSH, + } + } + #[doc = "Checks if the value of the field is `NOT_FLUSH`"] + #[inline(always)] + pub fn is_not_flush(&self) -> bool { + *self == RXFFR_A::NOT_FLUSH + } + #[doc = "Checks if the value of the field is `FLUSH`"] + #[inline(always)] + pub fn is_flush(&self) -> bool { + *self == RXFFR_A::FLUSH + } + } + #[doc = "Write proxy for field `rxffr`"] + pub struct RXFFR_W<'a> { + w: &'a mut W, + } + impl<'a> RXFFR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXFFR_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Not flush FIFO"] + #[inline(always)] + pub fn not_flush(self) -> &'a mut W { + self.variant(RXFFR_A::NOT_FLUSH) + } + #[doc = "Flush FIFO"] + #[inline(always)] + pub fn flush(self) -> &'a mut W { + self.variant(RXFFR_A::FLUSH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Receiver FIFO reset"] + #[inline(always)] + pub fn rxffr(&self) -> RXFFR_R { + RXFFR_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Receiver FIFO reset"] + #[inline(always)] + pub fn rxffr(&mut self) -> RXFFR_W { + RXFFR_W { w: self } + } + } + } + #[doc = "Transmitter Block FIFO Reset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txffr](txffr) module"] + pub type TXFFR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TXFFR; + #[doc = "`read()` method returns [txffr::R](txffr::R) reader structure"] + impl crate::Readable for TXFFR {} + #[doc = "`write(|w| ..)` method takes [txffr::W](txffr::W) writer structure"] + impl crate::Writable for TXFFR {} + #[doc = "Transmitter Block FIFO Reset Register"] + pub mod txffr { + #[doc = "Reader of register txffr"] + pub type R = crate::R; + #[doc = "Writer for register txffr"] + pub type W = crate::W; + #[doc = "Register txffr `reset()`'s with value 0"] + impl crate::ResetValue for super::TXFFR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Transmitter FIFO reset"] + pub type RXFFR_A = super::rxffr::RXFFR_A; + #[doc = "Reader of field `rxffr`"] + pub type RXFFR_R = crate::R; + #[doc = "Write proxy for field `rxffr`"] + pub struct RXFFR_W<'a> { + w: &'a mut W, + } + impl<'a> RXFFR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXFFR_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Not flush FIFO"] + #[inline(always)] + pub fn not_flush(self) -> &'a mut W { + self.variant(RXFFR_A::NOT_FLUSH) + } + #[doc = "Flush FIFO"] + #[inline(always)] + pub fn flush(self) -> &'a mut W { + self.variant(RXFFR_A::FLUSH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Transmitter FIFO reset"] + #[inline(always)] + pub fn rxffr(&self) -> RXFFR_R { + RXFFR_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Transmitter FIFO reset"] + #[inline(always)] + pub fn rxffr(&mut self) -> RXFFR_W { + RXFFR_W { w: self } + } + } + } + #[doc = "Receiver Block DMA Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxdma](rxdma) module"] + pub type RXDMA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXDMA; + #[doc = "`read()` method returns [rxdma::R](rxdma::R) reader structure"] + impl crate::Readable for RXDMA {} + #[doc = "`write(|w| ..)` method takes [rxdma::W](rxdma::W) writer structure"] + impl crate::Writable for RXDMA {} + #[doc = "Receiver Block DMA Register"] + pub mod rxdma { + #[doc = "Reader of register rxdma"] + pub type R = crate::R; + #[doc = "Writer for register rxdma"] + pub type W = crate::W; + #[doc = "Register rxdma `reset()`'s with value 0"] + impl crate::ResetValue for super::RXDMA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Reset Receiver Block DMA Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rrxdma](rrxdma) module"] + pub type RRXDMA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RRXDMA; + #[doc = "`read()` method returns [rrxdma::R](rrxdma::R) reader structure"] + impl crate::Readable for RRXDMA {} + #[doc = "`write(|w| ..)` method takes [rrxdma::W](rrxdma::W) writer structure"] + impl crate::Writable for RRXDMA {} + #[doc = "Reset Receiver Block DMA Register"] + pub mod rrxdma { + #[doc = "Reader of register rrxdma"] + pub type R = crate::R; + #[doc = "Writer for register rrxdma"] + pub type W = crate::W; + #[doc = "Register rrxdma `reset()`'s with value 0"] + impl crate::ResetValue for super::RRXDMA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Transmitter Block DMA Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txdma](txdma) module"] + pub type TXDMA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TXDMA; + #[doc = "`read()` method returns [txdma::R](txdma::R) reader structure"] + impl crate::Readable for TXDMA {} + #[doc = "`write(|w| ..)` method takes [txdma::W](txdma::W) writer structure"] + impl crate::Writable for TXDMA {} + #[doc = "Transmitter Block DMA Register"] + pub mod txdma { + #[doc = "Reader of register txdma"] + pub type R = crate::R; + #[doc = "Writer for register txdma"] + pub type W = crate::W; + #[doc = "Register txdma `reset()`'s with value 0"] + impl crate::ResetValue for super::TXDMA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Reset Transmitter Block DMA Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtxdma](rtxdma) module"] + pub type RTXDMA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RTXDMA; + #[doc = "`read()` method returns [rtxdma::R](rtxdma::R) reader structure"] + impl crate::Readable for RTXDMA {} + #[doc = "`write(|w| ..)` method takes [rtxdma::W](rtxdma::W) writer structure"] + impl crate::Writable for RTXDMA {} + #[doc = "Reset Transmitter Block DMA Register"] + pub mod rtxdma { + #[doc = "Reader of register rtxdma"] + pub type R = crate::R; + #[doc = "Writer for register rtxdma"] + pub type W = crate::W; + #[doc = "Register rtxdma `reset()`'s with value 0"] + impl crate::ResetValue for super::RTXDMA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Component Parameter Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2s_comp_param_2](i2s_comp_param_2) module"] + pub type I2S_COMP_PARAM_2 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _I2S_COMP_PARAM_2; + #[doc = "`read()` method returns [i2s_comp_param_2::R](i2s_comp_param_2::R) reader structure"] + impl crate::Readable for I2S_COMP_PARAM_2 {} + #[doc = "`write(|w| ..)` method takes [i2s_comp_param_2::W](i2s_comp_param_2::W) writer structure"] + impl crate::Writable for I2S_COMP_PARAM_2 {} + #[doc = "Component Parameter Register 2"] + pub mod i2s_comp_param_2 { + #[doc = "Reader of register i2s_comp_param_2"] + pub type R = crate::R; + #[doc = "Writer for register i2s_comp_param_2"] + pub type W = crate::W; + #[doc = "Register i2s_comp_param_2 `reset()`'s with value 0"] + impl crate::ResetValue for super::I2S_COMP_PARAM_2 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Component Parameter Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2s_comp_param_1](i2s_comp_param_1) module"] + pub type I2S_COMP_PARAM_1 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _I2S_COMP_PARAM_1; + #[doc = "`read()` method returns [i2s_comp_param_1::R](i2s_comp_param_1::R) reader structure"] + impl crate::Readable for I2S_COMP_PARAM_1 {} + #[doc = "`write(|w| ..)` method takes [i2s_comp_param_1::W](i2s_comp_param_1::W) writer structure"] + impl crate::Writable for I2S_COMP_PARAM_1 {} + #[doc = "Component Parameter Register 1"] + pub mod i2s_comp_param_1 { + #[doc = "Reader of register i2s_comp_param_1"] + pub type R = crate::R; + #[doc = "Writer for register i2s_comp_param_1"] + pub type W = crate::W; + #[doc = "Register i2s_comp_param_1 `reset()`'s with value 0"] + impl crate::ResetValue for super::I2S_COMP_PARAM_1 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Component Version Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2s_comp_version_1](i2s_comp_version_1) module"] + pub type I2S_COMP_VERSION_1 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _I2S_COMP_VERSION_1; + #[doc = "`read()` method returns [i2s_comp_version_1::R](i2s_comp_version_1::R) reader structure"] + impl crate::Readable for I2S_COMP_VERSION_1 {} + #[doc = "`write(|w| ..)` method takes [i2s_comp_version_1::W](i2s_comp_version_1::W) writer structure"] + impl crate::Writable for I2S_COMP_VERSION_1 {} + #[doc = "Component Version Register"] + pub mod i2s_comp_version_1 { + #[doc = "Reader of register i2s_comp_version_1"] + pub type R = crate::R; + #[doc = "Writer for register i2s_comp_version_1"] + pub type W = crate::W; + #[doc = "Register i2s_comp_version_1 `reset()`'s with value 0"] + impl crate::ResetValue for super::I2S_COMP_VERSION_1 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Component Type Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2s_comp_type](i2s_comp_type) module"] + pub type I2S_COMP_TYPE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _I2S_COMP_TYPE; + #[doc = "`read()` method returns [i2s_comp_type::R](i2s_comp_type::R) reader structure"] + impl crate::Readable for I2S_COMP_TYPE {} + #[doc = "`write(|w| ..)` method takes [i2s_comp_type::W](i2s_comp_type::W) writer structure"] + impl crate::Writable for I2S_COMP_TYPE {} + #[doc = "Component Type Register"] + pub mod i2s_comp_type { + #[doc = "Reader of register i2s_comp_type"] + pub type R = crate::R; + #[doc = "Writer for register i2s_comp_type"] + pub type W = crate::W; + #[doc = "Register i2s_comp_type `reset()`'s with value 0"] + impl crate::ResetValue for super::I2S_COMP_TYPE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Audio Processor"] +pub struct APU { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for APU {} +impl APU { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const apu::RegisterBlock { + 0x5025_0200 as *const _ + } +} +impl Deref for APU { + type Target = apu::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*APU::ptr() } + } +} +#[doc = "Audio Processor"] +pub mod apu { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Channel Config Register"] + pub ch_cfg: CH_CFG, + #[doc = "0x04 - Control Register"] + pub ctl: CTL, + #[doc = "0x08 - Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)"] + pub dir_bidx: [DIR_BIDX; 32], + #[doc = "0x88 - FIR0 pre-filter coefficients"] + pub pre_fir0_coef: [PRE_FIR0_COEF; 9], + #[doc = "0xac - FIR0 post-filter coefficients"] + pub post_fir0_coef: [POST_FIR0_COEF; 9], + #[doc = "0xd0 - FIR1 pre-filter coeffecients"] + pub pre_fir1_coef: [PRE_FIR1_COEF; 9], + #[doc = "0xf4 - FIR1 post-filter coefficients"] + pub post_fir1_coef: [POST_FIR1_COEF; 9], + #[doc = "0x118 - Downsize Config Register"] + pub dwsz_cfg: DWSZ_CFG, + #[doc = "0x11c - FFT Config Register"] + pub fft_cfg: FFT_CFG, + #[doc = "0x120 - Read register for DMA to sample-out buffers"] + pub sobuf_dma_rdata: SOBUF_DMA_RDATA, + #[doc = "0x124 - Read register for DMA to voice-out buffers"] + pub vobuf_dma_rdata: VOBUF_DMA_RDATA, + #[doc = "0x128 - Interrupt Status Register"] + pub int_stat: INT_STAT, + #[doc = "0x12c - Interrupt Mask Register"] + pub int_mask: INT_MASK, + #[doc = "0x130 - Saturation Counter"] + pub sat_counter: SAT_COUNTER, + #[doc = "0x134 - Saturation Limits"] + pub sat_limits: SAT_LIMITS, + } + #[doc = "Channel Config Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch_cfg](ch_cfg) module"] + pub type CH_CFG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CH_CFG; + #[doc = "`read()` method returns [ch_cfg::R](ch_cfg::R) reader structure"] + impl crate::Readable for CH_CFG {} + #[doc = "`write(|w| ..)` method takes [ch_cfg::W](ch_cfg::W) writer structure"] + impl crate::Writable for CH_CFG {} + #[doc = "Channel Config Register"] + pub mod ch_cfg { + #[doc = "Reader of register ch_cfg"] + pub type R = crate::R; + #[doc = "Writer for register ch_cfg"] + pub type W = crate::W; + #[doc = "Register ch_cfg `reset()`'s with value 0"] + impl crate::ResetValue for super::CH_CFG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `sound_ch_en`"] + pub type SOUND_CH_EN_R = crate::R; + #[doc = "Write proxy for field `sound_ch_en`"] + pub struct SOUND_CH_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SOUND_CH_EN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + #[doc = "Reader of field `target_dir`"] + pub type TARGET_DIR_R = crate::R; + #[doc = "Write proxy for field `target_dir`"] + pub struct TARGET_DIR_W<'a> { + w: &'a mut W, + } + impl<'a> TARGET_DIR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8); + self.w + } + } + #[doc = "Reader of field `audio_gain`"] + pub type AUDIO_GAIN_R = crate::R; + #[doc = "Write proxy for field `audio_gain`"] + pub struct AUDIO_GAIN_W<'a> { + w: &'a mut W, + } + impl<'a> AUDIO_GAIN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 12)) | (((value as u32) & 0x07ff) << 12); + self.w + } + } + #[doc = "Reader of field `data_src_mode`"] + pub type DATA_SRC_MODE_R = crate::R; + #[doc = "Write proxy for field `data_src_mode`"] + pub struct DATA_SRC_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> DATA_SRC_MODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); + self.w + } + } + #[doc = "Write proxy for field `we_sound_ch_en`"] + pub struct WE_SOUND_CH_EN_W<'a> { + w: &'a mut W, + } + impl<'a> WE_SOUND_CH_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28); + self.w + } + } + #[doc = "Write proxy for field `we_target_dir`"] + pub struct WE_TARGET_DIR_W<'a> { + w: &'a mut W, + } + impl<'a> WE_TARGET_DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29); + self.w + } + } + #[doc = "Write proxy for field `we_audio_gain`"] + pub struct WE_AUDIO_GAIN_W<'a> { + w: &'a mut W, + } + impl<'a> WE_AUDIO_GAIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30); + self.w + } + } + #[doc = "Write proxy for field `we_data_src_mode`"] + pub struct WE_DATA_SRC_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> WE_DATA_SRC_MODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31); + self.w + } + } + impl R { + #[doc = "Bits 0:7 - BF unit sound channel enable control bits"] + #[inline(always)] + pub fn sound_ch_en(&self) -> SOUND_CH_EN_R { + SOUND_CH_EN_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:11 - Target direction select for valid voice output"] + #[inline(always)] + pub fn target_dir(&self) -> TARGET_DIR_R { + TARGET_DIR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:22 - Audio sample gain factor"] + #[inline(always)] + pub fn audio_gain(&self) -> AUDIO_GAIN_R { + AUDIO_GAIN_R::new(((self.bits >> 12) & 0x07ff) as u16) + } + #[doc = "Bit 24 - Audio data source configure parameter"] + #[inline(always)] + pub fn data_src_mode(&self) -> DATA_SRC_MODE_R { + DATA_SRC_MODE_R::new(((self.bits >> 24) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:7 - BF unit sound channel enable control bits"] + #[inline(always)] + pub fn sound_ch_en(&mut self) -> SOUND_CH_EN_W { + SOUND_CH_EN_W { w: self } + } + #[doc = "Bits 8:11 - Target direction select for valid voice output"] + #[inline(always)] + pub fn target_dir(&mut self) -> TARGET_DIR_W { + TARGET_DIR_W { w: self } + } + #[doc = "Bits 12:22 - Audio sample gain factor"] + #[inline(always)] + pub fn audio_gain(&mut self) -> AUDIO_GAIN_W { + AUDIO_GAIN_W { w: self } + } + #[doc = "Bit 24 - Audio data source configure parameter"] + #[inline(always)] + pub fn data_src_mode(&mut self) -> DATA_SRC_MODE_W { + DATA_SRC_MODE_W { w: self } + } + #[doc = "Bit 28 - Write enable for sound_ch_en parameter"] + #[inline(always)] + pub fn we_sound_ch_en(&mut self) -> WE_SOUND_CH_EN_W { + WE_SOUND_CH_EN_W { w: self } + } + #[doc = "Bit 29 - Write enable for target_dir parameter"] + #[inline(always)] + pub fn we_target_dir(&mut self) -> WE_TARGET_DIR_W { + WE_TARGET_DIR_W { w: self } + } + #[doc = "Bit 30 - Write enable for audio_gain parameter"] + #[inline(always)] + pub fn we_audio_gain(&mut self) -> WE_AUDIO_GAIN_W { + WE_AUDIO_GAIN_W { w: self } + } + #[doc = "Bit 31 - Write enable for data_out_mode parameter"] + #[inline(always)] + pub fn we_data_src_mode(&mut self) -> WE_DATA_SRC_MODE_W { + WE_DATA_SRC_MODE_W { w: self } + } + } + } + #[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl](ctl) module"] + pub type CTL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CTL; + #[doc = "`read()` method returns [ctl::R](ctl::R) reader structure"] + impl crate::Readable for CTL {} + #[doc = "`write(|w| ..)` method takes [ctl::W](ctl::W) writer structure"] + impl crate::Writable for CTL {} + #[doc = "Control Register"] + pub mod ctl { + #[doc = "Reader of register ctl"] + pub type R = crate::R; + #[doc = "Writer for register ctl"] + pub type W = crate::W; + #[doc = "Register ctl `reset()`'s with value 0"] + impl crate::ResetValue for super::CTL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `dir_search_en`"] + pub type DIR_SEARCH_EN_R = crate::R; + #[doc = "Write proxy for field `dir_search_en`"] + pub struct DIR_SEARCH_EN_W<'a> { + w: &'a mut W, + } + impl<'a> DIR_SEARCH_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `search_path_reset`"] + pub type SEARCH_PATH_RESET_R = crate::R; + #[doc = "Write proxy for field `search_path_reset`"] + pub struct SEARCH_PATH_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> SEARCH_PATH_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `stream_gen_en`"] + pub type STREAM_GEN_EN_R = crate::R; + #[doc = "Write proxy for field `stream_gen_en`"] + pub struct STREAM_GEN_EN_W<'a> { + w: &'a mut W, + } + impl<'a> STREAM_GEN_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `voice_gen_path_reset`"] + pub type VOICE_GEN_PATH_RESET_R = crate::R; + #[doc = "Write proxy for field `voice_gen_path_reset`"] + pub struct VOICE_GEN_PATH_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> VOICE_GEN_PATH_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `update_voice_dir`"] + pub type UPDATE_VOICE_DIR_R = crate::R; + #[doc = "Write proxy for field `update_voice_dir`"] + pub struct UPDATE_VOICE_DIR_W<'a> { + w: &'a mut W, + } + impl<'a> UPDATE_VOICE_DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); + self.w + } + } + #[doc = "Write proxy for field `we_dir_search_en`"] + pub struct WE_DIR_SEARCH_EN_W<'a> { + w: &'a mut W, + } + impl<'a> WE_DIR_SEARCH_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Write proxy for field `we_search_path_rst`"] + pub struct WE_SEARCH_PATH_RST_W<'a> { + w: &'a mut W, + } + impl<'a> WE_SEARCH_PATH_RST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); + self.w + } + } + #[doc = "Write proxy for field `we_stream_gen`"] + pub struct WE_STREAM_GEN_W<'a> { + w: &'a mut W, + } + impl<'a> WE_STREAM_GEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); + self.w + } + } + #[doc = "Write proxy for field `we_voice_gen_path_rst`"] + pub struct WE_VOICE_GEN_PATH_RST_W<'a> { + w: &'a mut W, + } + impl<'a> WE_VOICE_GEN_PATH_RST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); + self.w + } + } + #[doc = "Write proxy for field `we_update_voice_dir`"] + pub struct WE_UPDATE_VOICE_DIR_W<'a> { + w: &'a mut W, + } + impl<'a> WE_UPDATE_VOICE_DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); + self.w + } + } + impl R { + #[doc = "Bit 0 - Sound direction searching enable bit"] + #[inline(always)] + pub fn dir_search_en(&self) -> DIR_SEARCH_EN_R { + DIR_SEARCH_EN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Reset all control logic on direction search processing path"] + #[inline(always)] + pub fn search_path_reset(&self) -> SEARCH_PATH_RESET_R { + SEARCH_PATH_RESET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Valid voice sample stream generation enable bit"] + #[inline(always)] + pub fn stream_gen_en(&self) -> STREAM_GEN_EN_R { + STREAM_GEN_EN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Reset all control logic on voice stream generating path"] + #[inline(always)] + pub fn voice_gen_path_reset(&self) -> VOICE_GEN_PATH_RESET_R { + VOICE_GEN_PATH_RESET_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Switch to a new voice source direction"] + #[inline(always)] + pub fn update_voice_dir(&self) -> UPDATE_VOICE_DIR_R { + UPDATE_VOICE_DIR_R::new(((self.bits >> 6) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Sound direction searching enable bit"] + #[inline(always)] + pub fn dir_search_en(&mut self) -> DIR_SEARCH_EN_W { + DIR_SEARCH_EN_W { w: self } + } + #[doc = "Bit 1 - Reset all control logic on direction search processing path"] + #[inline(always)] + pub fn search_path_reset(&mut self) -> SEARCH_PATH_RESET_W { + SEARCH_PATH_RESET_W { w: self } + } + #[doc = "Bit 4 - Valid voice sample stream generation enable bit"] + #[inline(always)] + pub fn stream_gen_en(&mut self) -> STREAM_GEN_EN_W { + STREAM_GEN_EN_W { w: self } + } + #[doc = "Bit 5 - Reset all control logic on voice stream generating path"] + #[inline(always)] + pub fn voice_gen_path_reset(&mut self) -> VOICE_GEN_PATH_RESET_W { + VOICE_GEN_PATH_RESET_W { w: self } + } + #[doc = "Bit 6 - Switch to a new voice source direction"] + #[inline(always)] + pub fn update_voice_dir(&mut self) -> UPDATE_VOICE_DIR_W { + UPDATE_VOICE_DIR_W { w: self } + } + #[doc = "Bit 8 - Write enable for we_dir_search_en parameter"] + #[inline(always)] + pub fn we_dir_search_en(&mut self) -> WE_DIR_SEARCH_EN_W { + WE_DIR_SEARCH_EN_W { w: self } + } + #[doc = "Bit 9 - Write enable for we_search_path_rst parameter"] + #[inline(always)] + pub fn we_search_path_rst(&mut self) -> WE_SEARCH_PATH_RST_W { + WE_SEARCH_PATH_RST_W { w: self } + } + #[doc = "Bit 10 - Write enable for we_stream_gen parameter"] + #[inline(always)] + pub fn we_stream_gen(&mut self) -> WE_STREAM_GEN_W { + WE_STREAM_GEN_W { w: self } + } + #[doc = "Bit 11 - Write enable for we_voice_gen_path_rst parameter"] + #[inline(always)] + pub fn we_voice_gen_path_rst(&mut self) -> WE_VOICE_GEN_PATH_RST_W { + WE_VOICE_GEN_PATH_RST_W { w: self } + } + #[doc = "Bit 12 - Write enable for we_update_voice_dir parameter"] + #[inline(always)] + pub fn we_update_voice_dir(&mut self) -> WE_UPDATE_VOICE_DIR_W { + WE_UPDATE_VOICE_DIR_W { w: self } + } + } + } + #[doc = "Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dir_bidx](dir_bidx) module"] + pub type DIR_BIDX = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DIR_BIDX; + #[doc = "`read()` method returns [dir_bidx::R](dir_bidx::R) reader structure"] + impl crate::Readable for DIR_BIDX {} + #[doc = "`write(|w| ..)` method takes [dir_bidx::W](dir_bidx::W) writer structure"] + impl crate::Writable for DIR_BIDX {} + #[doc = "Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)"] + pub mod dir_bidx { + #[doc = "Reader of register dir_bidx[%s]"] + pub type R = crate::R; + #[doc = "Writer for register dir_bidx[%s]"] + pub type W = crate::W; + #[doc = "Register dir_bidx[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::DIR_BIDX { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `rd_idx(0-3)`"] + pub type RD_IDX_R = crate::R; + #[doc = "Write proxy for fields `rd_idx(0-3)`"] + pub struct RD_IDX_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> RD_IDX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << self.offset)) + | (((value as u32) & 0x3f) << self.offset); + self.w + } + } + impl R { + #[doc = "rd_idx(0-3)"] + #[inline(always)] + pub unsafe fn rd_idx(&self, n: usize) -> RD_IDX_R { + RD_IDX_R::new(((self.bits >> n * 8) & 0x3f) as u8) + } + #[doc = "Bits 0:5 - rd_idx0"] + #[inline(always)] + pub fn rd_idx0(&self) -> RD_IDX_R { + RD_IDX_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:13 - rd_idx1"] + #[inline(always)] + pub fn rd_idx1(&self) -> RD_IDX_R { + RD_IDX_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 16:21 - rd_idx2"] + #[inline(always)] + pub fn rd_idx2(&self) -> RD_IDX_R { + RD_IDX_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 24:29 - rd_idx3"] + #[inline(always)] + pub fn rd_idx3(&self) -> RD_IDX_R { + RD_IDX_R::new(((self.bits >> 24) & 0x3f) as u8) + } + } + impl W { + #[doc = "rd_idx(0-3)"] + #[inline(always)] + pub unsafe fn rd_idx(&mut self, n: usize) -> RD_IDX_W { + RD_IDX_W { + w: self, + offset: n * 8, + } + } + #[doc = "Bits 0:5 - rd_idx0"] + #[inline(always)] + pub fn rd_idx0(&mut self) -> RD_IDX_W { + RD_IDX_W { w: self, offset: 0 } + } + #[doc = "Bits 8:13 - rd_idx1"] + #[inline(always)] + pub fn rd_idx1(&mut self) -> RD_IDX_W { + RD_IDX_W { w: self, offset: 8 } + } + #[doc = "Bits 16:21 - rd_idx2"] + #[inline(always)] + pub fn rd_idx2(&mut self) -> RD_IDX_W { + RD_IDX_W { + w: self, + offset: 16, + } + } + #[doc = "Bits 24:29 - rd_idx3"] + #[inline(always)] + pub fn rd_idx3(&mut self) -> RD_IDX_W { + RD_IDX_W { + w: self, + offset: 24, + } + } + } + } + #[doc = "FIR0 pre-filter coefficients\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pre_fir0_coef](pre_fir0_coef) module"] + pub type PRE_FIR0_COEF = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PRE_FIR0_COEF; + #[doc = "`read()` method returns [pre_fir0_coef::R](pre_fir0_coef::R) reader structure"] + impl crate::Readable for PRE_FIR0_COEF {} + #[doc = "`write(|w| ..)` method takes [pre_fir0_coef::W](pre_fir0_coef::W) writer structure"] + impl crate::Writable for PRE_FIR0_COEF {} + #[doc = "FIR0 pre-filter coefficients"] + pub mod pre_fir0_coef { + #[doc = "Reader of register pre_fir0_coef[%s]"] + pub type R = crate::R; + #[doc = "Writer for register pre_fir0_coef[%s]"] + pub type W = crate::W; + #[doc = "Register pre_fir0_coef[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::PRE_FIR0_COEF { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `tap0`"] + pub type TAP0_R = crate::R; + #[doc = "Write proxy for field `tap0`"] + pub struct TAP0_W<'a> { + w: &'a mut W, + } + impl<'a> TAP0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + #[doc = "Reader of field `tap1`"] + pub type TAP1_R = crate::R; + #[doc = "Write proxy for field `tap1`"] + pub struct TAP1_W<'a> { + w: &'a mut W, + } + impl<'a> TAP1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16); + self.w + } + } + impl R { + #[doc = "Bits 0:15 - Tap 0"] + #[inline(always)] + pub fn tap0(&self) -> TAP0_R { + TAP0_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Tap 1"] + #[inline(always)] + pub fn tap1(&self) -> TAP1_R { + TAP1_R::new(((self.bits >> 16) & 0xffff) as u16) + } + } + impl W { + #[doc = "Bits 0:15 - Tap 0"] + #[inline(always)] + pub fn tap0(&mut self) -> TAP0_W { + TAP0_W { w: self } + } + #[doc = "Bits 16:31 - Tap 1"] + #[inline(always)] + pub fn tap1(&mut self) -> TAP1_W { + TAP1_W { w: self } + } + } + } + #[doc = "FIR0 post-filter coefficients\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [post_fir0_coef](post_fir0_coef) module"] + pub type POST_FIR0_COEF = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _POST_FIR0_COEF; + #[doc = "`read()` method returns [post_fir0_coef::R](post_fir0_coef::R) reader structure"] + impl crate::Readable for POST_FIR0_COEF {} + #[doc = "`write(|w| ..)` method takes [post_fir0_coef::W](post_fir0_coef::W) writer structure"] + impl crate::Writable for POST_FIR0_COEF {} + #[doc = "FIR0 post-filter coefficients"] + pub mod post_fir0_coef { + #[doc = "Reader of register post_fir0_coef[%s]"] + pub type R = crate::R; + #[doc = "Writer for register post_fir0_coef[%s]"] + pub type W = crate::W; + #[doc = "Register post_fir0_coef[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::POST_FIR0_COEF { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `tap0`"] + pub type TAP0_R = crate::R; + #[doc = "Write proxy for field `tap0`"] + pub struct TAP0_W<'a> { + w: &'a mut W, + } + impl<'a> TAP0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + #[doc = "Reader of field `tap1`"] + pub type TAP1_R = crate::R; + #[doc = "Write proxy for field `tap1`"] + pub struct TAP1_W<'a> { + w: &'a mut W, + } + impl<'a> TAP1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16); + self.w + } + } + impl R { + #[doc = "Bits 0:15 - Tap 0"] + #[inline(always)] + pub fn tap0(&self) -> TAP0_R { + TAP0_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Tap 1"] + #[inline(always)] + pub fn tap1(&self) -> TAP1_R { + TAP1_R::new(((self.bits >> 16) & 0xffff) as u16) + } + } + impl W { + #[doc = "Bits 0:15 - Tap 0"] + #[inline(always)] + pub fn tap0(&mut self) -> TAP0_W { + TAP0_W { w: self } + } + #[doc = "Bits 16:31 - Tap 1"] + #[inline(always)] + pub fn tap1(&mut self) -> TAP1_W { + TAP1_W { w: self } + } + } + } + #[doc = "FIR1 pre-filter coeffecients\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pre_fir1_coef](pre_fir1_coef) module"] + pub type PRE_FIR1_COEF = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PRE_FIR1_COEF; + #[doc = "`read()` method returns [pre_fir1_coef::R](pre_fir1_coef::R) reader structure"] + impl crate::Readable for PRE_FIR1_COEF {} + #[doc = "`write(|w| ..)` method takes [pre_fir1_coef::W](pre_fir1_coef::W) writer structure"] + impl crate::Writable for PRE_FIR1_COEF {} + #[doc = "FIR1 pre-filter coeffecients"] + pub mod pre_fir1_coef { + #[doc = "Reader of register pre_fir1_coef[%s]"] + pub type R = crate::R; + #[doc = "Writer for register pre_fir1_coef[%s]"] + pub type W = crate::W; + #[doc = "Register pre_fir1_coef[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::PRE_FIR1_COEF { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `tap0`"] + pub type TAP0_R = crate::R; + #[doc = "Write proxy for field `tap0`"] + pub struct TAP0_W<'a> { + w: &'a mut W, + } + impl<'a> TAP0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + #[doc = "Reader of field `tap1`"] + pub type TAP1_R = crate::R; + #[doc = "Write proxy for field `tap1`"] + pub struct TAP1_W<'a> { + w: &'a mut W, + } + impl<'a> TAP1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16); + self.w + } + } + impl R { + #[doc = "Bits 0:15 - Tap 0"] + #[inline(always)] + pub fn tap0(&self) -> TAP0_R { + TAP0_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Tap 1"] + #[inline(always)] + pub fn tap1(&self) -> TAP1_R { + TAP1_R::new(((self.bits >> 16) & 0xffff) as u16) + } + } + impl W { + #[doc = "Bits 0:15 - Tap 0"] + #[inline(always)] + pub fn tap0(&mut self) -> TAP0_W { + TAP0_W { w: self } + } + #[doc = "Bits 16:31 - Tap 1"] + #[inline(always)] + pub fn tap1(&mut self) -> TAP1_W { + TAP1_W { w: self } + } + } + } + #[doc = "FIR1 post-filter coefficients\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [post_fir1_coef](post_fir1_coef) module"] + pub type POST_FIR1_COEF = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _POST_FIR1_COEF; + #[doc = "`read()` method returns [post_fir1_coef::R](post_fir1_coef::R) reader structure"] + impl crate::Readable for POST_FIR1_COEF {} + #[doc = "`write(|w| ..)` method takes [post_fir1_coef::W](post_fir1_coef::W) writer structure"] + impl crate::Writable for POST_FIR1_COEF {} + #[doc = "FIR1 post-filter coefficients"] + pub mod post_fir1_coef { + #[doc = "Reader of register post_fir1_coef[%s]"] + pub type R = crate::R; + #[doc = "Writer for register post_fir1_coef[%s]"] + pub type W = crate::W; + #[doc = "Register post_fir1_coef[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::POST_FIR1_COEF { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `tap0`"] + pub type TAP0_R = crate::R; + #[doc = "Write proxy for field `tap0`"] + pub struct TAP0_W<'a> { + w: &'a mut W, + } + impl<'a> TAP0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + #[doc = "Reader of field `tap1`"] + pub type TAP1_R = crate::R; + #[doc = "Write proxy for field `tap1`"] + pub struct TAP1_W<'a> { + w: &'a mut W, + } + impl<'a> TAP1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16); + self.w + } + } + impl R { + #[doc = "Bits 0:15 - Tap 0"] + #[inline(always)] + pub fn tap0(&self) -> TAP0_R { + TAP0_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Tap 1"] + #[inline(always)] + pub fn tap1(&self) -> TAP1_R { + TAP1_R::new(((self.bits >> 16) & 0xffff) as u16) + } + } + impl W { + #[doc = "Bits 0:15 - Tap 0"] + #[inline(always)] + pub fn tap0(&mut self) -> TAP0_W { + TAP0_W { w: self } + } + #[doc = "Bits 16:31 - Tap 1"] + #[inline(always)] + pub fn tap1(&mut self) -> TAP1_W { + TAP1_W { w: self } + } + } + } + #[doc = "Downsize Config Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dwsz_cfg](dwsz_cfg) module"] + pub type DWSZ_CFG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DWSZ_CFG; + #[doc = "`read()` method returns [dwsz_cfg::R](dwsz_cfg::R) reader structure"] + impl crate::Readable for DWSZ_CFG {} + #[doc = "`write(|w| ..)` method takes [dwsz_cfg::W](dwsz_cfg::W) writer structure"] + impl crate::Writable for DWSZ_CFG {} + #[doc = "Downsize Config Register"] + pub mod dwsz_cfg { + #[doc = "Reader of register dwsz_cfg"] + pub type R = crate::R; + #[doc = "Writer for register dwsz_cfg"] + pub type W = crate::W; + #[doc = "Register dwsz_cfg `reset()`'s with value 0"] + impl crate::ResetValue for super::DWSZ_CFG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `dir_dwn_siz_rate`"] + pub type DIR_DWN_SIZ_RATE_R = crate::R; + #[doc = "Write proxy for field `dir_dwn_siz_rate`"] + pub struct DIR_DWN_SIZ_RATE_W<'a> { + w: &'a mut W, + } + impl<'a> DIR_DWN_SIZ_RATE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f); + self.w + } + } + #[doc = "Reader of field `voc_dwn_siz_rate`"] + pub type VOC_DWN_SIZ_RATE_R = crate::R; + #[doc = "Write proxy for field `voc_dwn_siz_rate`"] + pub struct VOC_DWN_SIZ_RATE_W<'a> { + w: &'a mut W, + } + impl<'a> VOC_DWN_SIZ_RATE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4); + self.w + } + } + #[doc = "Reader of field `smpl_shift_bits`"] + pub type SMPL_SHIFT_BITS_R = crate::R; + #[doc = "Write proxy for field `smpl_shift_bits`"] + pub struct SMPL_SHIFT_BITS_W<'a> { + w: &'a mut W, + } + impl<'a> SMPL_SHIFT_BITS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | (((value as u32) & 0x1f) << 8); + self.w + } + } + impl R { + #[doc = "Bits 0:3 - Down-sizing ratio used for direction searching"] + #[inline(always)] + pub fn dir_dwn_siz_rate(&self) -> DIR_DWN_SIZ_RATE_R { + DIR_DWN_SIZ_RATE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Down-sizing ratio used for voice stream generation"] + #[inline(always)] + pub fn voc_dwn_siz_rate(&self) -> VOC_DWN_SIZ_RATE_R { + VOC_DWN_SIZ_RATE_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:12 - Sample precision reduction when the source sound sample precision is 20/24/32 bits"] + #[inline(always)] + pub fn smpl_shift_bits(&self) -> SMPL_SHIFT_BITS_R { + SMPL_SHIFT_BITS_R::new(((self.bits >> 8) & 0x1f) as u8) + } + } + impl W { + #[doc = "Bits 0:3 - Down-sizing ratio used for direction searching"] + #[inline(always)] + pub fn dir_dwn_siz_rate(&mut self) -> DIR_DWN_SIZ_RATE_W { + DIR_DWN_SIZ_RATE_W { w: self } + } + #[doc = "Bits 4:7 - Down-sizing ratio used for voice stream generation"] + #[inline(always)] + pub fn voc_dwn_siz_rate(&mut self) -> VOC_DWN_SIZ_RATE_W { + VOC_DWN_SIZ_RATE_W { w: self } + } + #[doc = "Bits 8:12 - Sample precision reduction when the source sound sample precision is 20/24/32 bits"] + #[inline(always)] + pub fn smpl_shift_bits(&mut self) -> SMPL_SHIFT_BITS_W { + SMPL_SHIFT_BITS_W { w: self } + } + } + } + #[doc = "FFT Config Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fft_cfg](fft_cfg) module"] + pub type FFT_CFG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FFT_CFG; + #[doc = "`read()` method returns [fft_cfg::R](fft_cfg::R) reader structure"] + impl crate::Readable for FFT_CFG {} + #[doc = "`write(|w| ..)` method takes [fft_cfg::W](fft_cfg::W) writer structure"] + impl crate::Writable for FFT_CFG {} + #[doc = "FFT Config Register"] + pub mod fft_cfg { + #[doc = "Reader of register fft_cfg"] + pub type R = crate::R; + #[doc = "Writer for register fft_cfg"] + pub type W = crate::W; + #[doc = "Register fft_cfg `reset()`'s with value 0"] + impl crate::ResetValue for super::FFT_CFG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Read register for DMA to sample-out buffers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sobuf_dma_rdata](sobuf_dma_rdata) module"] + pub type SOBUF_DMA_RDATA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SOBUF_DMA_RDATA; + #[doc = "`read()` method returns [sobuf_dma_rdata::R](sobuf_dma_rdata::R) reader structure"] + impl crate::Readable for SOBUF_DMA_RDATA {} + #[doc = "`write(|w| ..)` method takes [sobuf_dma_rdata::W](sobuf_dma_rdata::W) writer structure"] + impl crate::Writable for SOBUF_DMA_RDATA {} + #[doc = "Read register for DMA to sample-out buffers"] + pub mod sobuf_dma_rdata { + #[doc = "Reader of register sobuf_dma_rdata"] + pub type R = crate::R; + #[doc = "Writer for register sobuf_dma_rdata"] + pub type W = crate::W; + #[doc = "Register sobuf_dma_rdata `reset()`'s with value 0"] + impl crate::ResetValue for super::SOBUF_DMA_RDATA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Read register for DMA to voice-out buffers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vobuf_dma_rdata](vobuf_dma_rdata) module"] + pub type VOBUF_DMA_RDATA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _VOBUF_DMA_RDATA; + #[doc = "`read()` method returns [vobuf_dma_rdata::R](vobuf_dma_rdata::R) reader structure"] + impl crate::Readable for VOBUF_DMA_RDATA {} + #[doc = "`write(|w| ..)` method takes [vobuf_dma_rdata::W](vobuf_dma_rdata::W) writer structure"] + impl crate::Writable for VOBUF_DMA_RDATA {} + #[doc = "Read register for DMA to voice-out buffers"] + pub mod vobuf_dma_rdata { + #[doc = "Reader of register vobuf_dma_rdata"] + pub type R = crate::R; + #[doc = "Writer for register vobuf_dma_rdata"] + pub type W = crate::W; + #[doc = "Register vobuf_dma_rdata `reset()`'s with value 0"] + impl crate::ResetValue for super::VOBUF_DMA_RDATA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [int_stat](int_stat) module"] + pub type INT_STAT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INT_STAT; + #[doc = "`read()` method returns [int_stat::R](int_stat::R) reader structure"] + impl crate::Readable for INT_STAT {} + #[doc = "`write(|w| ..)` method takes [int_stat::W](int_stat::W) writer structure"] + impl crate::Writable for INT_STAT {} + #[doc = "Interrupt Status Register"] + pub mod int_stat { + #[doc = "Reader of register int_stat"] + pub type R = crate::R; + #[doc = "Writer for register int_stat"] + pub type W = crate::W; + #[doc = "Register int_stat `reset()`'s with value 0"] + impl crate::ResetValue for super::INT_STAT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `dir_search_data_rdy`"] + pub type DIR_SEARCH_DATA_RDY_R = crate::R; + #[doc = "Write proxy for field `dir_search_data_rdy`"] + pub struct DIR_SEARCH_DATA_RDY_W<'a> { + w: &'a mut W, + } + impl<'a> DIR_SEARCH_DATA_RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `voc_buf_data_rdy`"] + pub type VOC_BUF_DATA_RDY_R = crate::R; + #[doc = "Write proxy for field `voc_buf_data_rdy`"] + pub struct VOC_BUF_DATA_RDY_W<'a> { + w: &'a mut W, + } + impl<'a> VOC_BUF_DATA_RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + impl R { + #[doc = "Bit 0 - Sound direction searching data ready interrupt event"] + #[inline(always)] + pub fn dir_search_data_rdy(&self) -> DIR_SEARCH_DATA_RDY_R { + DIR_SEARCH_DATA_RDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Voice output stream buffer data ready interrupt event"] + #[inline(always)] + pub fn voc_buf_data_rdy(&self) -> VOC_BUF_DATA_RDY_R { + VOC_BUF_DATA_RDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Sound direction searching data ready interrupt event"] + #[inline(always)] + pub fn dir_search_data_rdy(&mut self) -> DIR_SEARCH_DATA_RDY_W { + DIR_SEARCH_DATA_RDY_W { w: self } + } + #[doc = "Bit 1 - Voice output stream buffer data ready interrupt event"] + #[inline(always)] + pub fn voc_buf_data_rdy(&mut self) -> VOC_BUF_DATA_RDY_W { + VOC_BUF_DATA_RDY_W { w: self } + } + } + } + #[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [int_mask](int_mask) module"] + pub type INT_MASK = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INT_MASK; + #[doc = "`read()` method returns [int_mask::R](int_mask::R) reader structure"] + impl crate::Readable for INT_MASK {} + #[doc = "`write(|w| ..)` method takes [int_mask::W](int_mask::W) writer structure"] + impl crate::Writable for INT_MASK {} + #[doc = "Interrupt Mask Register"] + pub mod int_mask { + #[doc = "Reader of register int_mask"] + pub type R = crate::R; + #[doc = "Writer for register int_mask"] + pub type W = crate::W; + #[doc = "Register int_mask `reset()`'s with value 0"] + impl crate::ResetValue for super::INT_MASK { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `dir_search_data_rdy`"] + pub type DIR_SEARCH_DATA_RDY_R = crate::R; + #[doc = "Write proxy for field `dir_search_data_rdy`"] + pub struct DIR_SEARCH_DATA_RDY_W<'a> { + w: &'a mut W, + } + impl<'a> DIR_SEARCH_DATA_RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `voc_buf_data_rdy`"] + pub type VOC_BUF_DATA_RDY_R = crate::R; + #[doc = "Write proxy for field `voc_buf_data_rdy`"] + pub struct VOC_BUF_DATA_RDY_W<'a> { + w: &'a mut W, + } + impl<'a> VOC_BUF_DATA_RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + impl R { + #[doc = "Bit 0 - Sound direction searching data ready interrupt event"] + #[inline(always)] + pub fn dir_search_data_rdy(&self) -> DIR_SEARCH_DATA_RDY_R { + DIR_SEARCH_DATA_RDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Voice output stream buffer data ready interrupt event"] + #[inline(always)] + pub fn voc_buf_data_rdy(&self) -> VOC_BUF_DATA_RDY_R { + VOC_BUF_DATA_RDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Sound direction searching data ready interrupt event"] + #[inline(always)] + pub fn dir_search_data_rdy(&mut self) -> DIR_SEARCH_DATA_RDY_W { + DIR_SEARCH_DATA_RDY_W { w: self } + } + #[doc = "Bit 1 - Voice output stream buffer data ready interrupt event"] + #[inline(always)] + pub fn voc_buf_data_rdy(&mut self) -> VOC_BUF_DATA_RDY_W { + VOC_BUF_DATA_RDY_W { w: self } + } + } + } + #[doc = "Saturation Counter\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sat_counter](sat_counter) module"] + pub type SAT_COUNTER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SAT_COUNTER; + #[doc = "`read()` method returns [sat_counter::R](sat_counter::R) reader structure"] + impl crate::Readable for SAT_COUNTER {} + #[doc = "`write(|w| ..)` method takes [sat_counter::W](sat_counter::W) writer structure"] + impl crate::Writable for SAT_COUNTER {} + #[doc = "Saturation Counter"] + pub mod sat_counter { + #[doc = "Reader of register sat_counter"] + pub type R = crate::R; + #[doc = "Writer for register sat_counter"] + pub type W = crate::W; + #[doc = "Register sat_counter `reset()`'s with value 0"] + impl crate::ResetValue for super::SAT_COUNTER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `counter`"] + pub type COUNTER_R = crate::R; + #[doc = "Write proxy for field `counter`"] + pub struct COUNTER_W<'a> { + w: &'a mut W, + } + impl<'a> COUNTER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + #[doc = "Reader of field `total`"] + pub type TOTAL_R = crate::R; + #[doc = "Write proxy for field `total`"] + pub struct TOTAL_W<'a> { + w: &'a mut W, + } + impl<'a> TOTAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16); + self.w + } + } + impl R { + #[doc = "Bits 0:15 - Counter"] + #[inline(always)] + pub fn counter(&self) -> COUNTER_R { + COUNTER_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Total"] + #[inline(always)] + pub fn total(&self) -> TOTAL_R { + TOTAL_R::new(((self.bits >> 16) & 0xffff) as u16) + } + } + impl W { + #[doc = "Bits 0:15 - Counter"] + #[inline(always)] + pub fn counter(&mut self) -> COUNTER_W { + COUNTER_W { w: self } + } + #[doc = "Bits 16:31 - Total"] + #[inline(always)] + pub fn total(&mut self) -> TOTAL_W { + TOTAL_W { w: self } + } + } + } + #[doc = "Saturation Limits\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sat_limits](sat_limits) module"] + pub type SAT_LIMITS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SAT_LIMITS; + #[doc = "`read()` method returns [sat_limits::R](sat_limits::R) reader structure"] + impl crate::Readable for SAT_LIMITS {} + #[doc = "`write(|w| ..)` method takes [sat_limits::W](sat_limits::W) writer structure"] + impl crate::Writable for SAT_LIMITS {} + #[doc = "Saturation Limits"] + pub mod sat_limits { + #[doc = "Reader of register sat_limits"] + pub type R = crate::R; + #[doc = "Writer for register sat_limits"] + pub type W = crate::W; + #[doc = "Register sat_limits `reset()`'s with value 0"] + impl crate::ResetValue for super::SAT_LIMITS { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `upper`"] + pub type UPPER_R = crate::R; + #[doc = "Write proxy for field `upper`"] + pub struct UPPER_W<'a> { + w: &'a mut W, + } + impl<'a> UPPER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + #[doc = "Reader of field `bottom`"] + pub type BOTTOM_R = crate::R; + #[doc = "Write proxy for field `bottom`"] + pub struct BOTTOM_W<'a> { + w: &'a mut W, + } + impl<'a> BOTTOM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16); + self.w + } + } + impl R { + #[doc = "Bits 0:15 - Upper limit"] + #[inline(always)] + pub fn upper(&self) -> UPPER_R { + UPPER_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Bottom limit"] + #[inline(always)] + pub fn bottom(&self) -> BOTTOM_R { + BOTTOM_R::new(((self.bits >> 16) & 0xffff) as u16) + } + } + impl W { + #[doc = "Bits 0:15 - Upper limit"] + #[inline(always)] + pub fn upper(&mut self) -> UPPER_W { + UPPER_W { w: self } + } + #[doc = "Bits 16:31 - Bottom limit"] + #[inline(always)] + pub fn bottom(&mut self) -> BOTTOM_W { + BOTTOM_W { w: self } + } + } + } +} +#[doc = "Inter-Integrated Sound Interface 1"] +pub struct I2S1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2S1 {} +impl I2S1 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2s0::RegisterBlock { + 0x5026_0000 as *const _ + } +} +impl Deref for I2S1 { + type Target = i2s0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*I2S1::ptr() } + } +} +#[doc = "Inter-Integrated Sound Interface 2"] +pub struct I2S2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2S2 {} +impl I2S2 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2s0::RegisterBlock { + 0x5027_0000 as *const _ + } +} +impl Deref for I2S2 { + type Target = i2s0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*I2S2::ptr() } + } +} +#[doc = "Inter-Integrated Circuit Bus 0"] +pub struct I2C0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2C0 {} +impl I2C0 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2c0::RegisterBlock { + 0x5028_0000 as *const _ + } +} +impl Deref for I2C0 { + type Target = i2c0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*I2C0::ptr() } + } +} +#[doc = "Inter-Integrated Circuit Bus 0"] +pub mod i2c0 { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Control Register"] + pub con: CON, + #[doc = "0x04 - Target Address Register"] + pub tar: TAR, + #[doc = "0x08 - Slave Address Register"] + pub sar: SAR, + _reserved3: [u8; 4usize], + #[doc = "0x10 - Data Buffer and Command Register"] + pub data_cmd: DATA_CMD, + #[doc = "0x14 - Standard Speed Clock SCL High Count Register"] + pub ss_scl_hcnt: SS_SCL_HCNT, + #[doc = "0x18 - Standard Speed Clock SCL Low Count Register"] + pub ss_scl_lcnt: SS_SCL_LCNT, + _reserved6: [u8; 16usize], + #[doc = "0x2c - Interrupt Status Register"] + pub intr_stat: INTR_STAT, + #[doc = "0x30 - Interrupt Mask Register"] + pub intr_mask: INTR_MASK, + #[doc = "0x34 - Raw Interrupt Status Register"] + pub raw_intr_stat: RAW_INTR_STAT, + #[doc = "0x38 - Receive FIFO Threshold Register"] + pub rx_tl: RX_TL, + #[doc = "0x3c - Transmit FIFO Threshold Register"] + pub tx_tl: TX_TL, + #[doc = "0x40 - Clear Combined and Individual Interrupt Register"] + pub clr_intr: CLR_INTR, + #[doc = "0x44 - Clear RX_UNDER Interrupt Register"] + pub clr_rx_under: CLR_RX_UNDER, + #[doc = "0x48 - Clear RX_OVER Interrupt Register"] + pub clr_rx_over: CLR_RX_OVER, + #[doc = "0x4c - Clear TX_OVER Interrupt Register"] + pub clr_tx_over: CLR_TX_OVER, + #[doc = "0x50 - Clear RD_REQ Interrupt Register"] + pub clr_rd_req: CLR_RD_REQ, + #[doc = "0x54 - Clear TX_ABRT Interrupt Register"] + pub clr_tx_abrt: CLR_TX_ABRT, + #[doc = "0x58 - Clear RX_DONE Interrupt Register"] + pub clr_rx_done: CLR_RX_DONE, + #[doc = "0x5c - Clear ACTIVITY Interrupt Register"] + pub clr_activity: CLR_ACTIVITY, + #[doc = "0x60 - Clear STOP_DET Interrupt Register"] + pub clr_stop_det: CLR_STOP_DET, + #[doc = "0x64 - Clear START_DET Interrupt Register"] + pub clr_start_det: CLR_START_DET, + #[doc = "0x68 - I2C Clear GEN_CALL Interrupt Register"] + pub clr_gen_call: CLR_GEN_CALL, + #[doc = "0x6c - Enable Register"] + pub enable: ENABLE, + #[doc = "0x70 - Status Register"] + pub status: STATUS, + #[doc = "0x74 - Transmit FIFO Level Register"] + pub txflr: TXFLR, + #[doc = "0x78 - Receive FIFO Level Register"] + pub rxflr: RXFLR, + #[doc = "0x7c - SDA Hold Time Length Register"] + pub sda_hold: SDA_HOLD, + #[doc = "0x80 - Transmit Abort Source Register"] + pub tx_abrt_source: TX_ABRT_SOURCE, + _reserved28: [u8; 4usize], + #[doc = "0x88 - I2C DMA Control Register"] + pub dma_cr: DMA_CR, + #[doc = "0x8c - DMA Transmit Data Level Register"] + pub dma_tdlr: DMA_TDLR, + #[doc = "0x90 - DMA Receive Data Level Register"] + pub dma_rdlr: DMA_RDLR, + #[doc = "0x94 - SDA Setup Register"] + pub sda_setup: SDA_SETUP, + #[doc = "0x98 - ACK General Call Register"] + pub general_call: GENERAL_CALL, + #[doc = "0x9c - Enable Status Register"] + pub enable_status: ENABLE_STATUS, + #[doc = "0xa0 - SS, FS or FM+ spike suppression limit"] + pub fs_spklen: FS_SPKLEN, + _reserved35: [u8; 80usize], + #[doc = "0xf4 - Component Parameter Register 1"] + pub comp_param_1: COMP_PARAM_1, + #[doc = "0xf8 - Component Version Register"] + pub comp_version: COMP_VERSION, + #[doc = "0xfc - Component Type Register"] + pub comp_type: COMP_TYPE, + } + #[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [con](con) module"] + pub type CON = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CON; + #[doc = "`read()` method returns [con::R](con::R) reader structure"] + impl crate::Readable for CON {} + #[doc = "`write(|w| ..)` method takes [con::W](con::W) writer structure"] + impl crate::Writable for CON {} + #[doc = "Control Register"] + pub mod con { + #[doc = "Reader of register con"] + pub type R = crate::R; + #[doc = "Writer for register con"] + pub type W = crate::W; + #[doc = "Register con `reset()`'s with value 0"] + impl crate::ResetValue for super::CON { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `master_mode`"] + pub type MASTER_MODE_R = crate::R; + #[doc = "Write proxy for field `master_mode`"] + pub struct MASTER_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> MASTER_MODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Speed\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum SPEED_A { + #[doc = "0: STANDARD"] + STANDARD = 0, + #[doc = "1: FAST"] + FAST = 1, + #[doc = "2: HIGHSPEED"] + HIGHSPEED = 2, + } + impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `speed`"] + pub type SPEED_R = crate::R; + impl SPEED_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(SPEED_A::STANDARD), + 1 => Val(SPEED_A::FAST), + 2 => Val(SPEED_A::HIGHSPEED), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `STANDARD`"] + #[inline(always)] + pub fn is_standard(&self) -> bool { + *self == SPEED_A::STANDARD + } + #[doc = "Checks if the value of the field is `FAST`"] + #[inline(always)] + pub fn is_fast(&self) -> bool { + *self == SPEED_A::FAST + } + #[doc = "Checks if the value of the field is `HIGHSPEED`"] + #[inline(always)] + pub fn is_highspeed(&self) -> bool { + *self == SPEED_A::HIGHSPEED + } + } + #[doc = "Write proxy for field `speed`"] + pub struct SPEED_W<'a> { + w: &'a mut W, + } + impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "STANDARD"] + #[inline(always)] + pub fn standard(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD) + } + #[doc = "FAST"] + #[inline(always)] + pub fn fast(self) -> &'a mut W { + self.variant(SPEED_A::FAST) + } + #[doc = "HIGHSPEED"] + #[inline(always)] + pub fn highspeed(self) -> &'a mut W { + self.variant(SPEED_A::HIGHSPEED) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 1)) | (((value as u32) & 0x03) << 1); + self.w + } + } + #[doc = "Slave address width\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum ADDR_SLAVE_WIDTH_A { + #[doc = "0: 7-bit address"] + B7 = 0, + #[doc = "1: 10-bit address"] + B10 = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: ADDR_SLAVE_WIDTH_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `addr_slave_width`"] + pub type ADDR_SLAVE_WIDTH_R = crate::R; + impl ADDR_SLAVE_WIDTH_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ADDR_SLAVE_WIDTH_A { + match self.bits { + false => ADDR_SLAVE_WIDTH_A::B7, + true => ADDR_SLAVE_WIDTH_A::B10, + } + } + #[doc = "Checks if the value of the field is `B7`"] + #[inline(always)] + pub fn is_b7(&self) -> bool { + *self == ADDR_SLAVE_WIDTH_A::B7 + } + #[doc = "Checks if the value of the field is `B10`"] + #[inline(always)] + pub fn is_b10(&self) -> bool { + *self == ADDR_SLAVE_WIDTH_A::B10 + } + } + #[doc = "Write proxy for field `addr_slave_width`"] + pub struct ADDR_SLAVE_WIDTH_W<'a> { + w: &'a mut W, + } + impl<'a> ADDR_SLAVE_WIDTH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ADDR_SLAVE_WIDTH_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "7-bit address"] + #[inline(always)] + pub fn b7(self) -> &'a mut W { + self.variant(ADDR_SLAVE_WIDTH_A::B7) + } + #[doc = "10-bit address"] + #[inline(always)] + pub fn b10(self) -> &'a mut W { + self.variant(ADDR_SLAVE_WIDTH_A::B10) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `restart_en`"] + pub type RESTART_EN_R = crate::R; + #[doc = "Write proxy for field `restart_en`"] + pub struct RESTART_EN_W<'a> { + w: &'a mut W, + } + impl<'a> RESTART_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `slave_disable`"] + pub type SLAVE_DISABLE_R = crate::R; + #[doc = "Write proxy for field `slave_disable`"] + pub struct SLAVE_DISABLE_W<'a> { + w: &'a mut W, + } + impl<'a> SLAVE_DISABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `stop_det`"] + pub type STOP_DET_R = crate::R; + #[doc = "Write proxy for field `stop_det`"] + pub struct STOP_DET_W<'a> { + w: &'a mut W, + } + impl<'a> STOP_DET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `tx_empty`"] + pub type TX_EMPTY_R = crate::R; + #[doc = "Write proxy for field `tx_empty`"] + pub struct TX_EMPTY_W<'a> { + w: &'a mut W, + } + impl<'a> TX_EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + impl R { + #[doc = "Bit 0 - Master Mode"] + #[inline(always)] + pub fn master_mode(&self) -> MASTER_MODE_R { + MASTER_MODE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:2 - Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 1) & 0x03) as u8) + } + #[doc = "Bit 3 - Slave address width"] + #[inline(always)] + pub fn addr_slave_width(&self) -> ADDR_SLAVE_WIDTH_R { + ADDR_SLAVE_WIDTH_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 5 - Enable Restart"] + #[inline(always)] + pub fn restart_en(&self) -> RESTART_EN_R { + RESTART_EN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Disable Slave"] + #[inline(always)] + pub fn slave_disable(&self) -> SLAVE_DISABLE_R { + SLAVE_DISABLE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - STOP_DET_IFADDRESSED"] + #[inline(always)] + pub fn stop_det(&self) -> STOP_DET_R { + STOP_DET_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - TX_EMPTY_CTRL"] + #[inline(always)] + pub fn tx_empty(&self) -> TX_EMPTY_R { + TX_EMPTY_R::new(((self.bits >> 8) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Master Mode"] + #[inline(always)] + pub fn master_mode(&mut self) -> MASTER_MODE_W { + MASTER_MODE_W { w: self } + } + #[doc = "Bits 1:2 - Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 3 - Slave address width"] + #[inline(always)] + pub fn addr_slave_width(&mut self) -> ADDR_SLAVE_WIDTH_W { + ADDR_SLAVE_WIDTH_W { w: self } + } + #[doc = "Bit 5 - Enable Restart"] + #[inline(always)] + pub fn restart_en(&mut self) -> RESTART_EN_W { + RESTART_EN_W { w: self } + } + #[doc = "Bit 6 - Disable Slave"] + #[inline(always)] + pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { + SLAVE_DISABLE_W { w: self } + } + #[doc = "Bit 7 - STOP_DET_IFADDRESSED"] + #[inline(always)] + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W { w: self } + } + #[doc = "Bit 8 - TX_EMPTY_CTRL"] + #[inline(always)] + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W { w: self } + } + } + } + #[doc = "Target Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tar](tar) module"] + pub type TAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TAR; + #[doc = "`read()` method returns [tar::R](tar::R) reader structure"] + impl crate::Readable for TAR {} + #[doc = "`write(|w| ..)` method takes [tar::W](tar::W) writer structure"] + impl crate::Writable for TAR {} + #[doc = "Target Address Register"] + pub mod tar { + #[doc = "Reader of register tar"] + pub type R = crate::R; + #[doc = "Writer for register tar"] + pub type W = crate::W; + #[doc = "Register tar `reset()`'s with value 0"] + impl crate::ResetValue for super::TAR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `address`"] + pub type ADDRESS_R = crate::R; + #[doc = "Write proxy for field `address`"] + pub struct ADDRESS_W<'a> { + w: &'a mut W, + } + impl<'a> ADDRESS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03ff) | ((value as u32) & 0x03ff); + self.w + } + } + #[doc = "Reader of field `gc`"] + pub type GC_R = crate::R; + #[doc = "Write proxy for field `gc`"] + pub struct GC_W<'a> { + w: &'a mut W, + } + impl<'a> GC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `special`"] + pub type SPECIAL_R = crate::R; + #[doc = "Write proxy for field `special`"] + pub struct SPECIAL_W<'a> { + w: &'a mut W, + } + impl<'a> SPECIAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); + self.w + } + } + #[doc = "Master Address\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum ADDR_MASTER_WIDTH_A { + #[doc = "0: 7-bit address"] + B7 = 0, + #[doc = "1: 10-bit address"] + B10 = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: ADDR_MASTER_WIDTH_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `addr_master_width`"] + pub type ADDR_MASTER_WIDTH_R = crate::R; + impl ADDR_MASTER_WIDTH_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ADDR_MASTER_WIDTH_A { + match self.bits { + false => ADDR_MASTER_WIDTH_A::B7, + true => ADDR_MASTER_WIDTH_A::B10, + } + } + #[doc = "Checks if the value of the field is `B7`"] + #[inline(always)] + pub fn is_b7(&self) -> bool { + *self == ADDR_MASTER_WIDTH_A::B7 + } + #[doc = "Checks if the value of the field is `B10`"] + #[inline(always)] + pub fn is_b10(&self) -> bool { + *self == ADDR_MASTER_WIDTH_A::B10 + } + } + #[doc = "Write proxy for field `addr_master_width`"] + pub struct ADDR_MASTER_WIDTH_W<'a> { + w: &'a mut W, + } + impl<'a> ADDR_MASTER_WIDTH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ADDR_MASTER_WIDTH_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "7-bit address"] + #[inline(always)] + pub fn b7(self) -> &'a mut W { + self.variant(ADDR_MASTER_WIDTH_A::B7) + } + #[doc = "10-bit address"] + #[inline(always)] + pub fn b10(self) -> &'a mut W { + self.variant(ADDR_MASTER_WIDTH_A::B10) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); + self.w + } + } + impl R { + #[doc = "Bits 0:9 - Target Address"] + #[inline(always)] + pub fn address(&self) -> ADDRESS_R { + ADDRESS_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bit 10 - GC_OR_START"] + #[inline(always)] + pub fn gc(&self) -> GC_R { + GC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - SPECIAL"] + #[inline(always)] + pub fn special(&self) -> SPECIAL_R { + SPECIAL_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Master Address"] + #[inline(always)] + pub fn addr_master_width(&self) -> ADDR_MASTER_WIDTH_R { + ADDR_MASTER_WIDTH_R::new(((self.bits >> 12) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:9 - Target Address"] + #[inline(always)] + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W { w: self } + } + #[doc = "Bit 10 - GC_OR_START"] + #[inline(always)] + pub fn gc(&mut self) -> GC_W { + GC_W { w: self } + } + #[doc = "Bit 11 - SPECIAL"] + #[inline(always)] + pub fn special(&mut self) -> SPECIAL_W { + SPECIAL_W { w: self } + } + #[doc = "Bit 12 - Master Address"] + #[inline(always)] + pub fn addr_master_width(&mut self) -> ADDR_MASTER_WIDTH_W { + ADDR_MASTER_WIDTH_W { w: self } + } + } + } + #[doc = "Slave Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sar](sar) module"] + pub type SAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SAR; + #[doc = "`read()` method returns [sar::R](sar::R) reader structure"] + impl crate::Readable for SAR {} + #[doc = "`write(|w| ..)` method takes [sar::W](sar::W) writer structure"] + impl crate::Writable for SAR {} + #[doc = "Slave Address Register"] + pub mod sar { + #[doc = "Reader of register sar"] + pub type R = crate::R; + #[doc = "Writer for register sar"] + pub type W = crate::W; + #[doc = "Register sar `reset()`'s with value 0"] + impl crate::ResetValue for super::SAR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `address`"] + pub type ADDRESS_R = crate::R; + #[doc = "Write proxy for field `address`"] + pub struct ADDRESS_W<'a> { + w: &'a mut W, + } + impl<'a> ADDRESS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03ff) | ((value as u32) & 0x03ff); + self.w + } + } + impl R { + #[doc = "Bits 0:9 - Slave Address"] + #[inline(always)] + pub fn address(&self) -> ADDRESS_R { + ADDRESS_R::new((self.bits & 0x03ff) as u16) + } + } + impl W { + #[doc = "Bits 0:9 - Slave Address"] + #[inline(always)] + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W { w: self } + } + } + } + #[doc = "Data Buffer and Command Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data_cmd](data_cmd) module"] + pub type DATA_CMD = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DATA_CMD; + #[doc = "`read()` method returns [data_cmd::R](data_cmd::R) reader structure"] + impl crate::Readable for DATA_CMD {} + #[doc = "`write(|w| ..)` method takes [data_cmd::W](data_cmd::W) writer structure"] + impl crate::Writable for DATA_CMD {} + #[doc = "Data Buffer and Command Register"] + pub mod data_cmd { + #[doc = "Reader of register data_cmd"] + pub type R = crate::R; + #[doc = "Writer for register data_cmd"] + pub type W = crate::W; + #[doc = "Register data_cmd `reset()`'s with value 0"] + impl crate::ResetValue for super::DATA_CMD { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `cmd`"] + pub type CMD_R = crate::R; + #[doc = "Write proxy for field `cmd`"] + pub struct CMD_W<'a> { + w: &'a mut W, + } + impl<'a> CMD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `data`"] + pub type DATA_R = crate::R; + #[doc = "Write proxy for field `data`"] + pub struct DATA_W<'a> { + w: &'a mut W, + } + impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + impl R { + #[doc = "Bit 8 - CMD"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 0:7 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xff) as u8) + } + } + impl W { + #[doc = "Bit 8 - CMD"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bits 0:7 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + } + } + #[doc = "Standard Speed Clock SCL High Count Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ss_scl_hcnt](ss_scl_hcnt) module"] + pub type SS_SCL_HCNT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SS_SCL_HCNT; + #[doc = "`read()` method returns [ss_scl_hcnt::R](ss_scl_hcnt::R) reader structure"] + impl crate::Readable for SS_SCL_HCNT {} + #[doc = "`write(|w| ..)` method takes [ss_scl_hcnt::W](ss_scl_hcnt::W) writer structure"] + impl crate::Writable for SS_SCL_HCNT {} + #[doc = "Standard Speed Clock SCL High Count Register"] + pub mod ss_scl_hcnt { + #[doc = "Reader of register ss_scl_hcnt"] + pub type R = crate::R; + #[doc = "Writer for register ss_scl_hcnt"] + pub type W = crate::W; + #[doc = "Register ss_scl_hcnt `reset()`'s with value 0"] + impl crate::ResetValue for super::SS_SCL_HCNT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `count`"] + pub type COUNT_R = crate::R; + #[doc = "Write proxy for field `count`"] + pub struct COUNT_W<'a> { + w: &'a mut W, + } + impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + impl R { + #[doc = "Bits 0:15 - COUNT"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff) as u16) + } + } + impl W { + #[doc = "Bits 0:15 - COUNT"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + } + } + #[doc = "Standard Speed Clock SCL Low Count Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ss_scl_lcnt](ss_scl_lcnt) module"] + pub type SS_SCL_LCNT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SS_SCL_LCNT; + #[doc = "`read()` method returns [ss_scl_lcnt::R](ss_scl_lcnt::R) reader structure"] + impl crate::Readable for SS_SCL_LCNT {} + #[doc = "`write(|w| ..)` method takes [ss_scl_lcnt::W](ss_scl_lcnt::W) writer structure"] + impl crate::Writable for SS_SCL_LCNT {} + #[doc = "Standard Speed Clock SCL Low Count Register"] + pub mod ss_scl_lcnt { + #[doc = "Reader of register ss_scl_lcnt"] + pub type R = crate::R; + #[doc = "Writer for register ss_scl_lcnt"] + pub type W = crate::W; + #[doc = "Register ss_scl_lcnt `reset()`'s with value 0"] + impl crate::ResetValue for super::SS_SCL_LCNT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `count`"] + pub type COUNT_R = crate::R; + #[doc = "Write proxy for field `count`"] + pub struct COUNT_W<'a> { + w: &'a mut W, + } + impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + impl R { + #[doc = "Bits 0:15 - COUNT"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff) as u16) + } + } + impl W { + #[doc = "Bits 0:15 - COUNT"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + } + } + #[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intr_stat](intr_stat) module"] + pub type INTR_STAT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTR_STAT; + #[doc = "`read()` method returns [intr_stat::R](intr_stat::R) reader structure"] + impl crate::Readable for INTR_STAT {} + #[doc = "Interrupt Status Register"] + pub mod intr_stat { + #[doc = "Reader of register intr_stat"] + pub type R = crate::R; + #[doc = "Reader of field `rx_under`"] + pub type RX_UNDER_R = crate::R; + #[doc = "Reader of field `rx_over`"] + pub type RX_OVER_R = crate::R; + #[doc = "Reader of field `rx_full`"] + pub type RX_FULL_R = crate::R; + #[doc = "Reader of field `tx_over`"] + pub type TX_OVER_R = crate::R; + #[doc = "Reader of field `tx_empty`"] + pub type TX_EMPTY_R = crate::R; + #[doc = "Reader of field `rd_req`"] + pub type RD_REQ_R = crate::R; + #[doc = "Reader of field `tx_abrt`"] + pub type TX_ABRT_R = crate::R; + #[doc = "Reader of field `rx_done`"] + pub type RX_DONE_R = crate::R; + #[doc = "Reader of field `activity`"] + pub type ACTIVITY_R = crate::R; + #[doc = "Reader of field `stop_det`"] + pub type STOP_DET_R = crate::R; + #[doc = "Reader of field `start_det`"] + pub type START_DET_R = crate::R; + #[doc = "Reader of field `gen_call`"] + pub type GEN_CALL_R = crate::R; + impl R { + #[doc = "Bit 0 - RX_UNDER"] + #[inline(always)] + pub fn rx_under(&self) -> RX_UNDER_R { + RX_UNDER_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - RX_OVER"] + #[inline(always)] + pub fn rx_over(&self) -> RX_OVER_R { + RX_OVER_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - RX_FULL"] + #[inline(always)] + pub fn rx_full(&self) -> RX_FULL_R { + RX_FULL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - TX_OVER"] + #[inline(always)] + pub fn tx_over(&self) -> TX_OVER_R { + TX_OVER_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - TX_EMPTY"] + #[inline(always)] + pub fn tx_empty(&self) -> TX_EMPTY_R { + TX_EMPTY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - RD_REQ"] + #[inline(always)] + pub fn rd_req(&self) -> RD_REQ_R { + RD_REQ_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - TX_ABRT"] + #[inline(always)] + pub fn tx_abrt(&self) -> TX_ABRT_R { + TX_ABRT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - RX_DONE"] + #[inline(always)] + pub fn rx_done(&self) -> RX_DONE_R { + RX_DONE_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - ACTIVITY"] + #[inline(always)] + pub fn activity(&self) -> ACTIVITY_R { + ACTIVITY_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - STOP_DET"] + #[inline(always)] + pub fn stop_det(&self) -> STOP_DET_R { + STOP_DET_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - START_DET"] + #[inline(always)] + pub fn start_det(&self) -> START_DET_R { + START_DET_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - GEN_CALL"] + #[inline(always)] + pub fn gen_call(&self) -> GEN_CALL_R { + GEN_CALL_R::new(((self.bits >> 11) & 0x01) != 0) + } + } + } + #[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intr_mask](intr_mask) module"] + pub type INTR_MASK = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTR_MASK; + #[doc = "`read()` method returns [intr_mask::R](intr_mask::R) reader structure"] + impl crate::Readable for INTR_MASK {} + #[doc = "`write(|w| ..)` method takes [intr_mask::W](intr_mask::W) writer structure"] + impl crate::Writable for INTR_MASK {} + #[doc = "Interrupt Mask Register"] + pub mod intr_mask { + #[doc = "Reader of register intr_mask"] + pub type R = crate::R; + #[doc = "Writer for register intr_mask"] + pub type W = crate::W; + #[doc = "Register intr_mask `reset()`'s with value 0"] + impl crate::ResetValue for super::INTR_MASK { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `rx_under`"] + pub type RX_UNDER_R = crate::R; + #[doc = "Write proxy for field `rx_under`"] + pub struct RX_UNDER_W<'a> { + w: &'a mut W, + } + impl<'a> RX_UNDER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `rx_over`"] + pub type RX_OVER_R = crate::R; + #[doc = "Write proxy for field `rx_over`"] + pub struct RX_OVER_W<'a> { + w: &'a mut W, + } + impl<'a> RX_OVER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `rx_full`"] + pub type RX_FULL_R = crate::R; + #[doc = "Write proxy for field `rx_full`"] + pub struct RX_FULL_W<'a> { + w: &'a mut W, + } + impl<'a> RX_FULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `tx_over`"] + pub type TX_OVER_R = crate::R; + #[doc = "Write proxy for field `tx_over`"] + pub struct TX_OVER_W<'a> { + w: &'a mut W, + } + impl<'a> TX_OVER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `tx_empty`"] + pub type TX_EMPTY_R = crate::R; + #[doc = "Write proxy for field `tx_empty`"] + pub struct TX_EMPTY_W<'a> { + w: &'a mut W, + } + impl<'a> TX_EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `rd_req`"] + pub type RD_REQ_R = crate::R; + #[doc = "Write proxy for field `rd_req`"] + pub struct RD_REQ_W<'a> { + w: &'a mut W, + } + impl<'a> RD_REQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `tx_abrt`"] + pub type TX_ABRT_R = crate::R; + #[doc = "Write proxy for field `tx_abrt`"] + pub struct TX_ABRT_W<'a> { + w: &'a mut W, + } + impl<'a> TX_ABRT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `rx_done`"] + pub type RX_DONE_R = crate::R; + #[doc = "Write proxy for field `rx_done`"] + pub struct RX_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> RX_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `activity`"] + pub type ACTIVITY_R = crate::R; + #[doc = "Write proxy for field `activity`"] + pub struct ACTIVITY_W<'a> { + w: &'a mut W, + } + impl<'a> ACTIVITY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `stop_det`"] + pub type STOP_DET_R = crate::R; + #[doc = "Write proxy for field `stop_det`"] + pub struct STOP_DET_W<'a> { + w: &'a mut W, + } + impl<'a> STOP_DET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `start_det`"] + pub type START_DET_R = crate::R; + #[doc = "Write proxy for field `start_det`"] + pub struct START_DET_W<'a> { + w: &'a mut W, + } + impl<'a> START_DET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `gen_call`"] + pub type GEN_CALL_R = crate::R; + #[doc = "Write proxy for field `gen_call`"] + pub struct GEN_CALL_W<'a> { + w: &'a mut W, + } + impl<'a> GEN_CALL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); + self.w + } + } + impl R { + #[doc = "Bit 0 - RX_UNDER"] + #[inline(always)] + pub fn rx_under(&self) -> RX_UNDER_R { + RX_UNDER_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - RX_OVER"] + #[inline(always)] + pub fn rx_over(&self) -> RX_OVER_R { + RX_OVER_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - RX_FULL"] + #[inline(always)] + pub fn rx_full(&self) -> RX_FULL_R { + RX_FULL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - TX_OVER"] + #[inline(always)] + pub fn tx_over(&self) -> TX_OVER_R { + TX_OVER_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - TX_EMPTY"] + #[inline(always)] + pub fn tx_empty(&self) -> TX_EMPTY_R { + TX_EMPTY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - RD_REQ"] + #[inline(always)] + pub fn rd_req(&self) -> RD_REQ_R { + RD_REQ_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - TX_ABRT"] + #[inline(always)] + pub fn tx_abrt(&self) -> TX_ABRT_R { + TX_ABRT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - RX_DONE"] + #[inline(always)] + pub fn rx_done(&self) -> RX_DONE_R { + RX_DONE_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - ACTIVITY"] + #[inline(always)] + pub fn activity(&self) -> ACTIVITY_R { + ACTIVITY_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - STOP_DET"] + #[inline(always)] + pub fn stop_det(&self) -> STOP_DET_R { + STOP_DET_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - START_DET"] + #[inline(always)] + pub fn start_det(&self) -> START_DET_R { + START_DET_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - GEN_CALL"] + #[inline(always)] + pub fn gen_call(&self) -> GEN_CALL_R { + GEN_CALL_R::new(((self.bits >> 11) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - RX_UNDER"] + #[inline(always)] + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W { w: self } + } + #[doc = "Bit 1 - RX_OVER"] + #[inline(always)] + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W { w: self } + } + #[doc = "Bit 2 - RX_FULL"] + #[inline(always)] + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W { w: self } + } + #[doc = "Bit 3 - TX_OVER"] + #[inline(always)] + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W { w: self } + } + #[doc = "Bit 4 - TX_EMPTY"] + #[inline(always)] + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W { w: self } + } + #[doc = "Bit 5 - RD_REQ"] + #[inline(always)] + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W { w: self } + } + #[doc = "Bit 6 - TX_ABRT"] + #[inline(always)] + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W { w: self } + } + #[doc = "Bit 7 - RX_DONE"] + #[inline(always)] + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W { w: self } + } + #[doc = "Bit 8 - ACTIVITY"] + #[inline(always)] + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W { w: self } + } + #[doc = "Bit 9 - STOP_DET"] + #[inline(always)] + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W { w: self } + } + #[doc = "Bit 10 - START_DET"] + #[inline(always)] + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W { w: self } + } + #[doc = "Bit 11 - GEN_CALL"] + #[inline(always)] + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W { w: self } + } + } + } + #[doc = "Raw Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [raw_intr_stat](raw_intr_stat) module"] + pub type RAW_INTR_STAT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RAW_INTR_STAT; + #[doc = "`read()` method returns [raw_intr_stat::R](raw_intr_stat::R) reader structure"] + impl crate::Readable for RAW_INTR_STAT {} + #[doc = "`write(|w| ..)` method takes [raw_intr_stat::W](raw_intr_stat::W) writer structure"] + impl crate::Writable for RAW_INTR_STAT {} + #[doc = "Raw Interrupt Status Register"] + pub mod raw_intr_stat { + #[doc = "Reader of register raw_intr_stat"] + pub type R = crate::R; + #[doc = "Writer for register raw_intr_stat"] + pub type W = crate::W; + #[doc = "Register raw_intr_stat `reset()`'s with value 0"] + impl crate::ResetValue for super::RAW_INTR_STAT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `rx_under`"] + pub type RX_UNDER_R = crate::R; + #[doc = "Write proxy for field `rx_under`"] + pub struct RX_UNDER_W<'a> { + w: &'a mut W, + } + impl<'a> RX_UNDER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `rx_over`"] + pub type RX_OVER_R = crate::R; + #[doc = "Write proxy for field `rx_over`"] + pub struct RX_OVER_W<'a> { + w: &'a mut W, + } + impl<'a> RX_OVER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `rx_full`"] + pub type RX_FULL_R = crate::R; + #[doc = "Write proxy for field `rx_full`"] + pub struct RX_FULL_W<'a> { + w: &'a mut W, + } + impl<'a> RX_FULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `tx_over`"] + pub type TX_OVER_R = crate::R; + #[doc = "Write proxy for field `tx_over`"] + pub struct TX_OVER_W<'a> { + w: &'a mut W, + } + impl<'a> TX_OVER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `tx_empty`"] + pub type TX_EMPTY_R = crate::R; + #[doc = "Write proxy for field `tx_empty`"] + pub struct TX_EMPTY_W<'a> { + w: &'a mut W, + } + impl<'a> TX_EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `rd_req`"] + pub type RD_REQ_R = crate::R; + #[doc = "Write proxy for field `rd_req`"] + pub struct RD_REQ_W<'a> { + w: &'a mut W, + } + impl<'a> RD_REQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `tx_abrt`"] + pub type TX_ABRT_R = crate::R; + #[doc = "Write proxy for field `tx_abrt`"] + pub struct TX_ABRT_W<'a> { + w: &'a mut W, + } + impl<'a> TX_ABRT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `rx_done`"] + pub type RX_DONE_R = crate::R; + #[doc = "Write proxy for field `rx_done`"] + pub struct RX_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> RX_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `activity`"] + pub type ACTIVITY_R = crate::R; + #[doc = "Write proxy for field `activity`"] + pub struct ACTIVITY_W<'a> { + w: &'a mut W, + } + impl<'a> ACTIVITY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `stop_det`"] + pub type STOP_DET_R = crate::R; + #[doc = "Write proxy for field `stop_det`"] + pub struct STOP_DET_W<'a> { + w: &'a mut W, + } + impl<'a> STOP_DET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `start_det`"] + pub type START_DET_R = crate::R; + #[doc = "Write proxy for field `start_det`"] + pub struct START_DET_W<'a> { + w: &'a mut W, + } + impl<'a> START_DET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `gen_call`"] + pub type GEN_CALL_R = crate::R; + #[doc = "Write proxy for field `gen_call`"] + pub struct GEN_CALL_W<'a> { + w: &'a mut W, + } + impl<'a> GEN_CALL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); + self.w + } + } + impl R { + #[doc = "Bit 0 - RX_UNDER"] + #[inline(always)] + pub fn rx_under(&self) -> RX_UNDER_R { + RX_UNDER_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - RX_OVER"] + #[inline(always)] + pub fn rx_over(&self) -> RX_OVER_R { + RX_OVER_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - RX_FULL"] + #[inline(always)] + pub fn rx_full(&self) -> RX_FULL_R { + RX_FULL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - TX_OVER"] + #[inline(always)] + pub fn tx_over(&self) -> TX_OVER_R { + TX_OVER_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - TX_EMPTY"] + #[inline(always)] + pub fn tx_empty(&self) -> TX_EMPTY_R { + TX_EMPTY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - RD_REQ"] + #[inline(always)] + pub fn rd_req(&self) -> RD_REQ_R { + RD_REQ_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - TX_ABRT"] + #[inline(always)] + pub fn tx_abrt(&self) -> TX_ABRT_R { + TX_ABRT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - RX_DONE"] + #[inline(always)] + pub fn rx_done(&self) -> RX_DONE_R { + RX_DONE_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - ACTIVITY"] + #[inline(always)] + pub fn activity(&self) -> ACTIVITY_R { + ACTIVITY_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - STOP_DET"] + #[inline(always)] + pub fn stop_det(&self) -> STOP_DET_R { + STOP_DET_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - START_DET"] + #[inline(always)] + pub fn start_det(&self) -> START_DET_R { + START_DET_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - GEN_CALL"] + #[inline(always)] + pub fn gen_call(&self) -> GEN_CALL_R { + GEN_CALL_R::new(((self.bits >> 11) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - RX_UNDER"] + #[inline(always)] + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W { w: self } + } + #[doc = "Bit 1 - RX_OVER"] + #[inline(always)] + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W { w: self } + } + #[doc = "Bit 2 - RX_FULL"] + #[inline(always)] + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W { w: self } + } + #[doc = "Bit 3 - TX_OVER"] + #[inline(always)] + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W { w: self } + } + #[doc = "Bit 4 - TX_EMPTY"] + #[inline(always)] + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W { w: self } + } + #[doc = "Bit 5 - RD_REQ"] + #[inline(always)] + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W { w: self } + } + #[doc = "Bit 6 - TX_ABRT"] + #[inline(always)] + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W { w: self } + } + #[doc = "Bit 7 - RX_DONE"] + #[inline(always)] + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W { w: self } + } + #[doc = "Bit 8 - ACTIVITY"] + #[inline(always)] + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W { w: self } + } + #[doc = "Bit 9 - STOP_DET"] + #[inline(always)] + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W { w: self } + } + #[doc = "Bit 10 - START_DET"] + #[inline(always)] + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W { w: self } + } + #[doc = "Bit 11 - GEN_CALL"] + #[inline(always)] + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W { w: self } + } + } + } + #[doc = "Receive FIFO Threshold Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rx_tl](rx_tl) module"] + pub type RX_TL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RX_TL; + #[doc = "`read()` method returns [rx_tl::R](rx_tl::R) reader structure"] + impl crate::Readable for RX_TL {} + #[doc = "`write(|w| ..)` method takes [rx_tl::W](rx_tl::W) writer structure"] + impl crate::Writable for RX_TL {} + #[doc = "Receive FIFO Threshold Register"] + pub mod rx_tl { + #[doc = "Reader of register rx_tl"] + pub type R = crate::R; + #[doc = "Writer for register rx_tl"] + pub type W = crate::W; + #[doc = "Register rx_tl `reset()`'s with value 0"] + impl crate::ResetValue for super::RX_TL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `value`"] + pub type VALUE_R = crate::R; + #[doc = "Write proxy for field `value`"] + pub struct VALUE_W<'a> { + w: &'a mut W, + } + impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x07) as u8) + } + } + impl W { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + } + } + #[doc = "Transmit FIFO Threshold Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tx_tl](tx_tl) module"] + pub type TX_TL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TX_TL; + #[doc = "`read()` method returns [tx_tl::R](tx_tl::R) reader structure"] + impl crate::Readable for TX_TL {} + #[doc = "`write(|w| ..)` method takes [tx_tl::W](tx_tl::W) writer structure"] + impl crate::Writable for TX_TL {} + #[doc = "Transmit FIFO Threshold Register"] + pub mod tx_tl { + #[doc = "Reader of register tx_tl"] + pub type R = crate::R; + #[doc = "Writer for register tx_tl"] + pub type W = crate::W; + #[doc = "Register tx_tl `reset()`'s with value 0"] + impl crate::ResetValue for super::TX_TL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `value`"] + pub type VALUE_R = crate::R; + #[doc = "Write proxy for field `value`"] + pub struct VALUE_W<'a> { + w: &'a mut W, + } + impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x07) as u8) + } + } + impl W { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + } + } + #[doc = "Clear Combined and Individual Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clr_intr](clr_intr) module"] + pub type CLR_INTR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLR_INTR; + #[doc = "`read()` method returns [clr_intr::R](clr_intr::R) reader structure"] + impl crate::Readable for CLR_INTR {} + #[doc = "Clear Combined and Individual Interrupt Register"] + pub mod clr_intr { + #[doc = "Reader of register clr_intr"] + pub type R = crate::R; + #[doc = "Reader of field `clr`"] + pub type CLR_R = crate::R; + impl R { + #[doc = "Bit 0 - CLR"] + #[inline(always)] + pub fn clr(&self) -> CLR_R { + CLR_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Clear RX_UNDER Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clr_rx_under](clr_rx_under) module"] + pub type CLR_RX_UNDER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLR_RX_UNDER; + #[doc = "`read()` method returns [clr_rx_under::R](clr_rx_under::R) reader structure"] + impl crate::Readable for CLR_RX_UNDER {} + #[doc = "Clear RX_UNDER Interrupt Register"] + pub mod clr_rx_under { + #[doc = "Reader of register clr_rx_under"] + pub type R = crate::R; + #[doc = "Reader of field `clr`"] + pub type CLR_R = crate::R; + impl R { + #[doc = "Bit 0 - CLR"] + #[inline(always)] + pub fn clr(&self) -> CLR_R { + CLR_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Clear RX_OVER Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clr_rx_over](clr_rx_over) module"] + pub type CLR_RX_OVER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLR_RX_OVER; + #[doc = "`read()` method returns [clr_rx_over::R](clr_rx_over::R) reader structure"] + impl crate::Readable for CLR_RX_OVER {} + #[doc = "Clear RX_OVER Interrupt Register"] + pub mod clr_rx_over { + #[doc = "Reader of register clr_rx_over"] + pub type R = crate::R; + #[doc = "Reader of field `clr`"] + pub type CLR_R = crate::R; + impl R { + #[doc = "Bit 0 - CLR"] + #[inline(always)] + pub fn clr(&self) -> CLR_R { + CLR_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Clear TX_OVER Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clr_tx_over](clr_tx_over) module"] + pub type CLR_TX_OVER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLR_TX_OVER; + #[doc = "`read()` method returns [clr_tx_over::R](clr_tx_over::R) reader structure"] + impl crate::Readable for CLR_TX_OVER {} + #[doc = "Clear TX_OVER Interrupt Register"] + pub mod clr_tx_over { + #[doc = "Reader of register clr_tx_over"] + pub type R = crate::R; + #[doc = "Reader of field `clr`"] + pub type CLR_R = crate::R; + impl R { + #[doc = "Bit 0 - CLR"] + #[inline(always)] + pub fn clr(&self) -> CLR_R { + CLR_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Clear RD_REQ Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clr_rd_req](clr_rd_req) module"] + pub type CLR_RD_REQ = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLR_RD_REQ; + #[doc = "`read()` method returns [clr_rd_req::R](clr_rd_req::R) reader structure"] + impl crate::Readable for CLR_RD_REQ {} + #[doc = "Clear RD_REQ Interrupt Register"] + pub mod clr_rd_req { + #[doc = "Reader of register clr_rd_req"] + pub type R = crate::R; + #[doc = "Reader of field `clr`"] + pub type CLR_R = crate::R; + impl R { + #[doc = "Bit 0 - CLR"] + #[inline(always)] + pub fn clr(&self) -> CLR_R { + CLR_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Clear TX_ABRT Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clr_tx_abrt](clr_tx_abrt) module"] + pub type CLR_TX_ABRT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLR_TX_ABRT; + #[doc = "`read()` method returns [clr_tx_abrt::R](clr_tx_abrt::R) reader structure"] + impl crate::Readable for CLR_TX_ABRT {} + #[doc = "Clear TX_ABRT Interrupt Register"] + pub mod clr_tx_abrt { + #[doc = "Reader of register clr_tx_abrt"] + pub type R = crate::R; + #[doc = "Reader of field `clr`"] + pub type CLR_R = crate::R; + impl R { + #[doc = "Bit 0 - CLR"] + #[inline(always)] + pub fn clr(&self) -> CLR_R { + CLR_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Clear RX_DONE Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clr_rx_done](clr_rx_done) module"] + pub type CLR_RX_DONE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLR_RX_DONE; + #[doc = "`read()` method returns [clr_rx_done::R](clr_rx_done::R) reader structure"] + impl crate::Readable for CLR_RX_DONE {} + #[doc = "Clear RX_DONE Interrupt Register"] + pub mod clr_rx_done { + #[doc = "Reader of register clr_rx_done"] + pub type R = crate::R; + #[doc = "Reader of field `clr`"] + pub type CLR_R = crate::R; + impl R { + #[doc = "Bit 0 - CLR"] + #[inline(always)] + pub fn clr(&self) -> CLR_R { + CLR_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Clear ACTIVITY Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clr_activity](clr_activity) module"] + pub type CLR_ACTIVITY = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLR_ACTIVITY; + #[doc = "`read()` method returns [clr_activity::R](clr_activity::R) reader structure"] + impl crate::Readable for CLR_ACTIVITY {} + #[doc = "Clear ACTIVITY Interrupt Register"] + pub mod clr_activity { + #[doc = "Reader of register clr_activity"] + pub type R = crate::R; + #[doc = "Reader of field `clr`"] + pub type CLR_R = crate::R; + impl R { + #[doc = "Bit 0 - CLR"] + #[inline(always)] + pub fn clr(&self) -> CLR_R { + CLR_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Clear STOP_DET Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clr_stop_det](clr_stop_det) module"] + pub type CLR_STOP_DET = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLR_STOP_DET; + #[doc = "`read()` method returns [clr_stop_det::R](clr_stop_det::R) reader structure"] + impl crate::Readable for CLR_STOP_DET {} + #[doc = "Clear STOP_DET Interrupt Register"] + pub mod clr_stop_det { + #[doc = "Reader of register clr_stop_det"] + pub type R = crate::R; + #[doc = "Reader of field `clr`"] + pub type CLR_R = crate::R; + impl R { + #[doc = "Bit 0 - CLR"] + #[inline(always)] + pub fn clr(&self) -> CLR_R { + CLR_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Clear START_DET Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clr_start_det](clr_start_det) module"] + pub type CLR_START_DET = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLR_START_DET; + #[doc = "`read()` method returns [clr_start_det::R](clr_start_det::R) reader structure"] + impl crate::Readable for CLR_START_DET {} + #[doc = "Clear START_DET Interrupt Register"] + pub mod clr_start_det { + #[doc = "Reader of register clr_start_det"] + pub type R = crate::R; + #[doc = "Reader of field `clr`"] + pub type CLR_R = crate::R; + impl R { + #[doc = "Bit 0 - CLR"] + #[inline(always)] + pub fn clr(&self) -> CLR_R { + CLR_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "I2C Clear GEN_CALL Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clr_gen_call](clr_gen_call) module"] + pub type CLR_GEN_CALL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLR_GEN_CALL; + #[doc = "`read()` method returns [clr_gen_call::R](clr_gen_call::R) reader structure"] + impl crate::Readable for CLR_GEN_CALL {} + #[doc = "I2C Clear GEN_CALL Interrupt Register"] + pub mod clr_gen_call { + #[doc = "Reader of register clr_gen_call"] + pub type R = crate::R; + #[doc = "Reader of field `clr`"] + pub type CLR_R = crate::R; + impl R { + #[doc = "Bit 0 - CLR"] + #[inline(always)] + pub fn clr(&self) -> CLR_R { + CLR_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](enable) module"] + pub type ENABLE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ENABLE; + #[doc = "`read()` method returns [enable::R](enable::R) reader structure"] + impl crate::Readable for ENABLE {} + #[doc = "`write(|w| ..)` method takes [enable::W](enable::W) writer structure"] + impl crate::Writable for ENABLE {} + #[doc = "Enable Register"] + pub mod enable { + #[doc = "Reader of register enable"] + pub type R = crate::R; + #[doc = "Writer for register enable"] + pub type W = crate::W; + #[doc = "Register enable `reset()`'s with value 0"] + impl crate::ResetValue for super::ENABLE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `enable`"] + pub type ENABLE_R = crate::R; + #[doc = "Write proxy for field `enable`"] + pub struct ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `abort`"] + pub type ABORT_R = crate::R; + #[doc = "Write proxy for field `abort`"] + pub struct ABORT_W<'a> { + w: &'a mut W, + } + impl<'a> ABORT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `tx_cmd_block`"] + pub type TX_CMD_BLOCK_R = crate::R; + #[doc = "Write proxy for field `tx_cmd_block`"] + pub struct TX_CMD_BLOCK_W<'a> { + w: &'a mut W, + } + impl<'a> TX_CMD_BLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + impl R { + #[doc = "Bit 0 - ENABLE"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ABORT"] + #[inline(always)] + pub fn abort(&self) -> ABORT_R { + ABORT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - TX_CMD_BLOCK"] + #[inline(always)] + pub fn tx_cmd_block(&self) -> TX_CMD_BLOCK_R { + TX_CMD_BLOCK_R::new(((self.bits >> 2) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - ENABLE"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 1 - ABORT"] + #[inline(always)] + pub fn abort(&mut self) -> ABORT_W { + ABORT_W { w: self } + } + #[doc = "Bit 2 - TX_CMD_BLOCK"] + #[inline(always)] + pub fn tx_cmd_block(&mut self) -> TX_CMD_BLOCK_W { + TX_CMD_BLOCK_W { w: self } + } + } + } + #[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](status) module"] + pub type STATUS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _STATUS; + #[doc = "`read()` method returns [status::R](status::R) reader structure"] + impl crate::Readable for STATUS {} + #[doc = "Status Register"] + pub mod status { + #[doc = "Reader of register status"] + pub type R = crate::R; + #[doc = "Reader of field `activity`"] + pub type ACTIVITY_R = crate::R; + #[doc = "Reader of field `tfnf`"] + pub type TFNF_R = crate::R; + #[doc = "Reader of field `tfe`"] + pub type TFE_R = crate::R; + #[doc = "Reader of field `rfne`"] + pub type RFNE_R = crate::R; + #[doc = "Reader of field `rff`"] + pub type RFF_R = crate::R; + #[doc = "Reader of field `mst_activity`"] + pub type MST_ACTIVITY_R = crate::R; + #[doc = "Reader of field `slv_activity`"] + pub type SLV_ACTIVITY_R = crate::R; + impl R { + #[doc = "Bit 0 - ACTIVITY"] + #[inline(always)] + pub fn activity(&self) -> ACTIVITY_R { + ACTIVITY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - TFNF"] + #[inline(always)] + pub fn tfnf(&self) -> TFNF_R { + TFNF_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - TFE"] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RFNE"] + #[inline(always)] + pub fn rfne(&self) -> RFNE_R { + RFNE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - RFF"] + #[inline(always)] + pub fn rff(&self) -> RFF_R { + RFF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MST_ACTIVITY"] + #[inline(always)] + pub fn mst_activity(&self) -> MST_ACTIVITY_R { + MST_ACTIVITY_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SLV_ACTIVITY"] + #[inline(always)] + pub fn slv_activity(&self) -> SLV_ACTIVITY_R { + SLV_ACTIVITY_R::new(((self.bits >> 6) & 0x01) != 0) + } + } + } + #[doc = "Transmit FIFO Level Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txflr](txflr) module"] + pub type TXFLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TXFLR; + #[doc = "`read()` method returns [txflr::R](txflr::R) reader structure"] + impl crate::Readable for TXFLR {} + #[doc = "`write(|w| ..)` method takes [txflr::W](txflr::W) writer structure"] + impl crate::Writable for TXFLR {} + #[doc = "Transmit FIFO Level Register"] + pub mod txflr { + #[doc = "Reader of register txflr"] + pub type R = crate::R; + #[doc = "Writer for register txflr"] + pub type W = crate::W; + #[doc = "Register txflr `reset()`'s with value 0"] + impl crate::ResetValue for super::TXFLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `value`"] + pub type VALUE_R = crate::R; + #[doc = "Write proxy for field `value`"] + pub struct VALUE_W<'a> { + w: &'a mut W, + } + impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x07) as u8) + } + } + impl W { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + } + } + #[doc = "Receive FIFO Level Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxflr](rxflr) module"] + pub type RXFLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXFLR; + #[doc = "`read()` method returns [rxflr::R](rxflr::R) reader structure"] + impl crate::Readable for RXFLR {} + #[doc = "`write(|w| ..)` method takes [rxflr::W](rxflr::W) writer structure"] + impl crate::Writable for RXFLR {} + #[doc = "Receive FIFO Level Register"] + pub mod rxflr { + #[doc = "Reader of register rxflr"] + pub type R = crate::R; + #[doc = "Writer for register rxflr"] + pub type W = crate::W; + #[doc = "Register rxflr `reset()`'s with value 0"] + impl crate::ResetValue for super::RXFLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `value`"] + pub type VALUE_R = crate::R; + #[doc = "Write proxy for field `value`"] + pub struct VALUE_W<'a> { + w: &'a mut W, + } + impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x07) as u8) + } + } + impl W { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + } + } + #[doc = "SDA Hold Time Length Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sda_hold](sda_hold) module"] + pub type SDA_HOLD = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SDA_HOLD; + #[doc = "`read()` method returns [sda_hold::R](sda_hold::R) reader structure"] + impl crate::Readable for SDA_HOLD {} + #[doc = "`write(|w| ..)` method takes [sda_hold::W](sda_hold::W) writer structure"] + impl crate::Writable for SDA_HOLD {} + #[doc = "SDA Hold Time Length Register"] + pub mod sda_hold { + #[doc = "Reader of register sda_hold"] + pub type R = crate::R; + #[doc = "Writer for register sda_hold"] + pub type W = crate::W; + #[doc = "Register sda_hold `reset()`'s with value 0"] + impl crate::ResetValue for super::SDA_HOLD { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `tx`"] + pub type TX_R = crate::R; + #[doc = "Write proxy for field `tx`"] + pub struct TX_W<'a> { + w: &'a mut W, + } + impl<'a> TX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + #[doc = "Reader of field `rx`"] + pub type RX_R = crate::R; + #[doc = "Write proxy for field `rx`"] + pub struct RX_W<'a> { + w: &'a mut W, + } + impl<'a> RX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16); + self.w + } + } + impl R { + #[doc = "Bits 0:15 - TX"] + #[inline(always)] + pub fn tx(&self) -> TX_R { + TX_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - RX"] + #[inline(always)] + pub fn rx(&self) -> RX_R { + RX_R::new(((self.bits >> 16) & 0xff) as u8) + } + } + impl W { + #[doc = "Bits 0:15 - TX"] + #[inline(always)] + pub fn tx(&mut self) -> TX_W { + TX_W { w: self } + } + #[doc = "Bits 16:23 - RX"] + #[inline(always)] + pub fn rx(&mut self) -> RX_W { + RX_W { w: self } + } + } + } + #[doc = "Transmit Abort Source Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tx_abrt_source](tx_abrt_source) module"] + pub type TX_ABRT_SOURCE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TX_ABRT_SOURCE; + #[doc = "`read()` method returns [tx_abrt_source::R](tx_abrt_source::R) reader structure"] + impl crate::Readable for TX_ABRT_SOURCE {} + #[doc = "`write(|w| ..)` method takes [tx_abrt_source::W](tx_abrt_source::W) writer structure"] + impl crate::Writable for TX_ABRT_SOURCE {} + #[doc = "Transmit Abort Source Register"] + pub mod tx_abrt_source { + #[doc = "Reader of register tx_abrt_source"] + pub type R = crate::R; + #[doc = "Writer for register tx_abrt_source"] + pub type W = crate::W; + #[doc = "Register tx_abrt_source `reset()`'s with value 0"] + impl crate::ResetValue for super::TX_ABRT_SOURCE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `addr7_noack`"] + pub type ADDR7_NOACK_R = crate::R; + #[doc = "Write proxy for field `addr7_noack`"] + pub struct ADDR7_NOACK_W<'a> { + w: &'a mut W, + } + impl<'a> ADDR7_NOACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `addr1_10_noack`"] + pub type ADDR1_10_NOACK_R = crate::R; + #[doc = "Write proxy for field `addr1_10_noack`"] + pub struct ADDR1_10_NOACK_W<'a> { + w: &'a mut W, + } + impl<'a> ADDR1_10_NOACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `addr2_10_noack`"] + pub type ADDR2_10_NOACK_R = crate::R; + #[doc = "Write proxy for field `addr2_10_noack`"] + pub struct ADDR2_10_NOACK_W<'a> { + w: &'a mut W, + } + impl<'a> ADDR2_10_NOACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `txdata_noack`"] + pub type TXDATA_NOACK_R = crate::R; + #[doc = "Write proxy for field `txdata_noack`"] + pub struct TXDATA_NOACK_W<'a> { + w: &'a mut W, + } + impl<'a> TXDATA_NOACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `gcall_noack`"] + pub type GCALL_NOACK_R = crate::R; + #[doc = "Write proxy for field `gcall_noack`"] + pub struct GCALL_NOACK_W<'a> { + w: &'a mut W, + } + impl<'a> GCALL_NOACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `gcall_read`"] + pub type GCALL_READ_R = crate::R; + #[doc = "Write proxy for field `gcall_read`"] + pub struct GCALL_READ_W<'a> { + w: &'a mut W, + } + impl<'a> GCALL_READ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `hs_ackdet`"] + pub type HS_ACKDET_R = crate::R; + #[doc = "Write proxy for field `hs_ackdet`"] + pub struct HS_ACKDET_W<'a> { + w: &'a mut W, + } + impl<'a> HS_ACKDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `sbyte_ackdet`"] + pub type SBYTE_ACKDET_R = crate::R; + #[doc = "Write proxy for field `sbyte_ackdet`"] + pub struct SBYTE_ACKDET_W<'a> { + w: &'a mut W, + } + impl<'a> SBYTE_ACKDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `hs_norstrt`"] + pub type HS_NORSTRT_R = crate::R; + #[doc = "Write proxy for field `hs_norstrt`"] + pub struct HS_NORSTRT_W<'a> { + w: &'a mut W, + } + impl<'a> HS_NORSTRT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `sbyte_norstrt`"] + pub type SBYTE_NORSTRT_R = crate::R; + #[doc = "Write proxy for field `sbyte_norstrt`"] + pub struct SBYTE_NORSTRT_W<'a> { + w: &'a mut W, + } + impl<'a> SBYTE_NORSTRT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `rd_10_norstrt`"] + pub type RD_10_NORSTRT_R = crate::R; + #[doc = "Write proxy for field `rd_10_norstrt`"] + pub struct RD_10_NORSTRT_W<'a> { + w: &'a mut W, + } + impl<'a> RD_10_NORSTRT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `master_dis`"] + pub type MASTER_DIS_R = crate::R; + #[doc = "Write proxy for field `master_dis`"] + pub struct MASTER_DIS_W<'a> { + w: &'a mut W, + } + impl<'a> MASTER_DIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); + self.w + } + } + #[doc = "Reader of field `mst_arblost`"] + pub type MST_ARBLOST_R = crate::R; + #[doc = "Write proxy for field `mst_arblost`"] + pub struct MST_ARBLOST_W<'a> { + w: &'a mut W, + } + impl<'a> MST_ARBLOST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); + self.w + } + } + #[doc = "Reader of field `slvflush_txfifo`"] + pub type SLVFLUSH_TXFIFO_R = crate::R; + #[doc = "Write proxy for field `slvflush_txfifo`"] + pub struct SLVFLUSH_TXFIFO_W<'a> { + w: &'a mut W, + } + impl<'a> SLVFLUSH_TXFIFO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13); + self.w + } + } + #[doc = "Reader of field `slv_arblost`"] + pub type SLV_ARBLOST_R = crate::R; + #[doc = "Write proxy for field `slv_arblost`"] + pub struct SLV_ARBLOST_W<'a> { + w: &'a mut W, + } + impl<'a> SLV_ARBLOST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14); + self.w + } + } + #[doc = "Reader of field `slvrd_intx`"] + pub type SLVRD_INTX_R = crate::R; + #[doc = "Write proxy for field `slvrd_intx`"] + pub struct SLVRD_INTX_W<'a> { + w: &'a mut W, + } + impl<'a> SLVRD_INTX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); + self.w + } + } + #[doc = "Reader of field `user_abrt`"] + pub type USER_ABRT_R = crate::R; + #[doc = "Write proxy for field `user_abrt`"] + pub struct USER_ABRT_W<'a> { + w: &'a mut W, + } + impl<'a> USER_ABRT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); + self.w + } + } + impl R { + #[doc = "Bit 0 - 7B_ADDR_NOACK"] + #[inline(always)] + pub fn addr7_noack(&self) -> ADDR7_NOACK_R { + ADDR7_NOACK_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - 10B_ADDR1_NOACK"] + #[inline(always)] + pub fn addr1_10_noack(&self) -> ADDR1_10_NOACK_R { + ADDR1_10_NOACK_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - 10B_ADDR2_NOACK"] + #[inline(always)] + pub fn addr2_10_noack(&self) -> ADDR2_10_NOACK_R { + ADDR2_10_NOACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - TXDATA_NOACK"] + #[inline(always)] + pub fn txdata_noack(&self) -> TXDATA_NOACK_R { + TXDATA_NOACK_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - GCALL_NOACK"] + #[inline(always)] + pub fn gcall_noack(&self) -> GCALL_NOACK_R { + GCALL_NOACK_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - GCALL_READ"] + #[inline(always)] + pub fn gcall_read(&self) -> GCALL_READ_R { + GCALL_READ_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - HS_ACKDET"] + #[inline(always)] + pub fn hs_ackdet(&self) -> HS_ACKDET_R { + HS_ACKDET_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - SBYTE_ACKDET"] + #[inline(always)] + pub fn sbyte_ackdet(&self) -> SBYTE_ACKDET_R { + SBYTE_ACKDET_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - HS_NORSTRT"] + #[inline(always)] + pub fn hs_norstrt(&self) -> HS_NORSTRT_R { + HS_NORSTRT_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - SBYTE_NORSTRT"] + #[inline(always)] + pub fn sbyte_norstrt(&self) -> SBYTE_NORSTRT_R { + SBYTE_NORSTRT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - 10B_RD_NORSTRT"] + #[inline(always)] + pub fn rd_10_norstrt(&self) -> RD_10_NORSTRT_R { + RD_10_NORSTRT_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - MASTER_DIS"] + #[inline(always)] + pub fn master_dis(&self) -> MASTER_DIS_R { + MASTER_DIS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - MST_ARBLOST"] + #[inline(always)] + pub fn mst_arblost(&self) -> MST_ARBLOST_R { + MST_ARBLOST_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - SLVFLUSH_TXFIFO"] + #[inline(always)] + pub fn slvflush_txfifo(&self) -> SLVFLUSH_TXFIFO_R { + SLVFLUSH_TXFIFO_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - SLV_ARBLOST"] + #[inline(always)] + pub fn slv_arblost(&self) -> SLV_ARBLOST_R { + SLV_ARBLOST_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - SLVRD_INTX"] + #[inline(always)] + pub fn slvrd_intx(&self) -> SLVRD_INTX_R { + SLVRD_INTX_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - USER_ABRT"] + #[inline(always)] + pub fn user_abrt(&self) -> USER_ABRT_R { + USER_ABRT_R::new(((self.bits >> 16) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - 7B_ADDR_NOACK"] + #[inline(always)] + pub fn addr7_noack(&mut self) -> ADDR7_NOACK_W { + ADDR7_NOACK_W { w: self } + } + #[doc = "Bit 1 - 10B_ADDR1_NOACK"] + #[inline(always)] + pub fn addr1_10_noack(&mut self) -> ADDR1_10_NOACK_W { + ADDR1_10_NOACK_W { w: self } + } + #[doc = "Bit 2 - 10B_ADDR2_NOACK"] + #[inline(always)] + pub fn addr2_10_noack(&mut self) -> ADDR2_10_NOACK_W { + ADDR2_10_NOACK_W { w: self } + } + #[doc = "Bit 3 - TXDATA_NOACK"] + #[inline(always)] + pub fn txdata_noack(&mut self) -> TXDATA_NOACK_W { + TXDATA_NOACK_W { w: self } + } + #[doc = "Bit 4 - GCALL_NOACK"] + #[inline(always)] + pub fn gcall_noack(&mut self) -> GCALL_NOACK_W { + GCALL_NOACK_W { w: self } + } + #[doc = "Bit 5 - GCALL_READ"] + #[inline(always)] + pub fn gcall_read(&mut self) -> GCALL_READ_W { + GCALL_READ_W { w: self } + } + #[doc = "Bit 6 - HS_ACKDET"] + #[inline(always)] + pub fn hs_ackdet(&mut self) -> HS_ACKDET_W { + HS_ACKDET_W { w: self } + } + #[doc = "Bit 7 - SBYTE_ACKDET"] + #[inline(always)] + pub fn sbyte_ackdet(&mut self) -> SBYTE_ACKDET_W { + SBYTE_ACKDET_W { w: self } + } + #[doc = "Bit 8 - HS_NORSTRT"] + #[inline(always)] + pub fn hs_norstrt(&mut self) -> HS_NORSTRT_W { + HS_NORSTRT_W { w: self } + } + #[doc = "Bit 9 - SBYTE_NORSTRT"] + #[inline(always)] + pub fn sbyte_norstrt(&mut self) -> SBYTE_NORSTRT_W { + SBYTE_NORSTRT_W { w: self } + } + #[doc = "Bit 10 - 10B_RD_NORSTRT"] + #[inline(always)] + pub fn rd_10_norstrt(&mut self) -> RD_10_NORSTRT_W { + RD_10_NORSTRT_W { w: self } + } + #[doc = "Bit 11 - MASTER_DIS"] + #[inline(always)] + pub fn master_dis(&mut self) -> MASTER_DIS_W { + MASTER_DIS_W { w: self } + } + #[doc = "Bit 12 - MST_ARBLOST"] + #[inline(always)] + pub fn mst_arblost(&mut self) -> MST_ARBLOST_W { + MST_ARBLOST_W { w: self } + } + #[doc = "Bit 13 - SLVFLUSH_TXFIFO"] + #[inline(always)] + pub fn slvflush_txfifo(&mut self) -> SLVFLUSH_TXFIFO_W { + SLVFLUSH_TXFIFO_W { w: self } + } + #[doc = "Bit 14 - SLV_ARBLOST"] + #[inline(always)] + pub fn slv_arblost(&mut self) -> SLV_ARBLOST_W { + SLV_ARBLOST_W { w: self } + } + #[doc = "Bit 15 - SLVRD_INTX"] + #[inline(always)] + pub fn slvrd_intx(&mut self) -> SLVRD_INTX_W { + SLVRD_INTX_W { w: self } + } + #[doc = "Bit 16 - USER_ABRT"] + #[inline(always)] + pub fn user_abrt(&mut self) -> USER_ABRT_W { + USER_ABRT_W { w: self } + } + } + } + #[doc = "I2C DMA Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_cr](dma_cr) module"] + pub type DMA_CR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMA_CR; + #[doc = "`read()` method returns [dma_cr::R](dma_cr::R) reader structure"] + impl crate::Readable for DMA_CR {} + #[doc = "`write(|w| ..)` method takes [dma_cr::W](dma_cr::W) writer structure"] + impl crate::Writable for DMA_CR {} + #[doc = "I2C DMA Control Register"] + pub mod dma_cr { + #[doc = "Reader of register dma_cr"] + pub type R = crate::R; + #[doc = "Writer for register dma_cr"] + pub type W = crate::W; + #[doc = "Register dma_cr `reset()`'s with value 0"] + impl crate::ResetValue for super::DMA_CR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `RDMAE`"] + pub type RDMAE_R = crate::R; + #[doc = "Write proxy for field `RDMAE`"] + pub struct RDMAE_W<'a> { + w: &'a mut W, + } + impl<'a> RDMAE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `TDMAE`"] + pub type TDMAE_R = crate::R; + #[doc = "Write proxy for field `TDMAE`"] + pub struct TDMAE_W<'a> { + w: &'a mut W, + } + impl<'a> TDMAE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + impl R { + #[doc = "Bit 0 - RDMAE"] + #[inline(always)] + pub fn rdmae(&self) -> RDMAE_R { + RDMAE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - TDMAE"] + #[inline(always)] + pub fn tdmae(&self) -> TDMAE_R { + TDMAE_R::new(((self.bits >> 1) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - RDMAE"] + #[inline(always)] + pub fn rdmae(&mut self) -> RDMAE_W { + RDMAE_W { w: self } + } + #[doc = "Bit 1 - TDMAE"] + #[inline(always)] + pub fn tdmae(&mut self) -> TDMAE_W { + TDMAE_W { w: self } + } + } + } + #[doc = "DMA Transmit Data Level Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_tdlr](dma_tdlr) module"] + pub type DMA_TDLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMA_TDLR; + #[doc = "`read()` method returns [dma_tdlr::R](dma_tdlr::R) reader structure"] + impl crate::Readable for DMA_TDLR {} + #[doc = "`write(|w| ..)` method takes [dma_tdlr::W](dma_tdlr::W) writer structure"] + impl crate::Writable for DMA_TDLR {} + #[doc = "DMA Transmit Data Level Register"] + pub mod dma_tdlr { + #[doc = "Reader of register dma_tdlr"] + pub type R = crate::R; + #[doc = "Writer for register dma_tdlr"] + pub type W = crate::W; + #[doc = "Register dma_tdlr `reset()`'s with value 0"] + impl crate::ResetValue for super::DMA_TDLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `value`"] + pub type VALUE_R = crate::R; + #[doc = "Write proxy for field `value`"] + pub struct VALUE_W<'a> { + w: &'a mut W, + } + impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x07) as u8) + } + } + impl W { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + } + } + #[doc = "DMA Receive Data Level Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_rdlr](dma_rdlr) module"] + pub type DMA_RDLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMA_RDLR; + #[doc = "`read()` method returns [dma_rdlr::R](dma_rdlr::R) reader structure"] + impl crate::Readable for DMA_RDLR {} + #[doc = "`write(|w| ..)` method takes [dma_rdlr::W](dma_rdlr::W) writer structure"] + impl crate::Writable for DMA_RDLR {} + #[doc = "DMA Receive Data Level Register"] + pub mod dma_rdlr { + #[doc = "Reader of register dma_rdlr"] + pub type R = crate::R; + #[doc = "Writer for register dma_rdlr"] + pub type W = crate::W; + #[doc = "Register dma_rdlr `reset()`'s with value 0"] + impl crate::ResetValue for super::DMA_RDLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `value`"] + pub type VALUE_R = crate::R; + #[doc = "Write proxy for field `value`"] + pub struct VALUE_W<'a> { + w: &'a mut W, + } + impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x07) as u8) + } + } + impl W { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + } + } + #[doc = "SDA Setup Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sda_setup](sda_setup) module"] + pub type SDA_SETUP = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SDA_SETUP; + #[doc = "`read()` method returns [sda_setup::R](sda_setup::R) reader structure"] + impl crate::Readable for SDA_SETUP {} + #[doc = "`write(|w| ..)` method takes [sda_setup::W](sda_setup::W) writer structure"] + impl crate::Writable for SDA_SETUP {} + #[doc = "SDA Setup Register"] + pub mod sda_setup { + #[doc = "Reader of register sda_setup"] + pub type R = crate::R; + #[doc = "Writer for register sda_setup"] + pub type W = crate::W; + #[doc = "Register sda_setup `reset()`'s with value 0"] + impl crate::ResetValue for super::SDA_SETUP { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `value`"] + pub type VALUE_R = crate::R; + #[doc = "Write proxy for field `value`"] + pub struct VALUE_W<'a> { + w: &'a mut W, + } + impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + impl R { + #[doc = "Bits 0:7 - VALUE"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0xff) as u8) + } + } + impl W { + #[doc = "Bits 0:7 - VALUE"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + } + } + #[doc = "ACK General Call Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [general_call](general_call) module"] + pub type GENERAL_CALL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _GENERAL_CALL; + #[doc = "`read()` method returns [general_call::R](general_call::R) reader structure"] + impl crate::Readable for GENERAL_CALL {} + #[doc = "`write(|w| ..)` method takes [general_call::W](general_call::W) writer structure"] + impl crate::Writable for GENERAL_CALL {} + #[doc = "ACK General Call Register"] + pub mod general_call { + #[doc = "Reader of register general_call"] + pub type R = crate::R; + #[doc = "Writer for register general_call"] + pub type W = crate::W; + #[doc = "Register general_call `reset()`'s with value 0"] + impl crate::ResetValue for super::GENERAL_CALL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `call_enable`"] + pub type CALL_ENABLE_R = crate::R; + #[doc = "Write proxy for field `call_enable`"] + pub struct CALL_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> CALL_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - CALL_ENABLE"] + #[inline(always)] + pub fn call_enable(&self) -> CALL_ENABLE_R { + CALL_ENABLE_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - CALL_ENABLE"] + #[inline(always)] + pub fn call_enable(&mut self) -> CALL_ENABLE_W { + CALL_ENABLE_W { w: self } + } + } + } + #[doc = "Enable Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable_status](enable_status) module"] + pub type ENABLE_STATUS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ENABLE_STATUS; + #[doc = "`read()` method returns [enable_status::R](enable_status::R) reader structure"] + impl crate::Readable for ENABLE_STATUS {} + #[doc = "Enable Status Register"] + pub mod enable_status { + #[doc = "Reader of register enable_status"] + pub type R = crate::R; + #[doc = "Reader of field `ic_enable`"] + pub type IC_ENABLE_R = crate::R; + #[doc = "Reader of field `slv_dis_busy`"] + pub type SLV_DIS_BUSY_R = crate::R; + #[doc = "Reader of field `slv_rx_data_lost`"] + pub type SLV_RX_DATA_LOST_R = crate::R; + impl R { + #[doc = "Bit 0 - IC_ENABLE"] + #[inline(always)] + pub fn ic_enable(&self) -> IC_ENABLE_R { + IC_ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SLV_DIS_BUSY"] + #[inline(always)] + pub fn slv_dis_busy(&self) -> SLV_DIS_BUSY_R { + SLV_DIS_BUSY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SLV_RX_DATA_LOST"] + #[inline(always)] + pub fn slv_rx_data_lost(&self) -> SLV_RX_DATA_LOST_R { + SLV_RX_DATA_LOST_R::new(((self.bits >> 2) & 0x01) != 0) + } + } + } + #[doc = "SS, FS or FM+ spike suppression limit\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fs_spklen](fs_spklen) module"] + pub type FS_SPKLEN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FS_SPKLEN; + #[doc = "`read()` method returns [fs_spklen::R](fs_spklen::R) reader structure"] + impl crate::Readable for FS_SPKLEN {} + #[doc = "`write(|w| ..)` method takes [fs_spklen::W](fs_spklen::W) writer structure"] + impl crate::Writable for FS_SPKLEN {} + #[doc = "SS, FS or FM+ spike suppression limit"] + pub mod fs_spklen { + #[doc = "Reader of register fs_spklen"] + pub type R = crate::R; + #[doc = "Writer for register fs_spklen"] + pub type W = crate::W; + #[doc = "Register fs_spklen `reset()`'s with value 0"] + impl crate::ResetValue for super::FS_SPKLEN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `value`"] + pub type VALUE_R = crate::R; + #[doc = "Write proxy for field `value`"] + pub struct VALUE_W<'a> { + w: &'a mut W, + } + impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + impl R { + #[doc = "Bits 0:7 - VALUE"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0xff) as u8) + } + } + impl W { + #[doc = "Bits 0:7 - VALUE"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + } + } + #[doc = "Component Parameter Register 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_param_1](comp_param_1) module"] + pub type COMP_PARAM_1 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMP_PARAM_1; + #[doc = "`read()` method returns [comp_param_1::R](comp_param_1::R) reader structure"] + impl crate::Readable for COMP_PARAM_1 {} + #[doc = "Component Parameter Register 1"] + pub mod comp_param_1 { + #[doc = "Reader of register comp_param_1"] + pub type R = crate::R; + #[doc = "Reader of field `apb_data_width`"] + pub type APB_DATA_WIDTH_R = crate::R; + #[doc = "Reader of field `max_speed_mode`"] + pub type MAX_SPEED_MODE_R = crate::R; + #[doc = "Reader of field `hc_count_values`"] + pub type HC_COUNT_VALUES_R = crate::R; + #[doc = "Reader of field `intr_io`"] + pub type INTR_IO_R = crate::R; + #[doc = "Reader of field `has_dma`"] + pub type HAS_DMA_R = crate::R; + #[doc = "Reader of field `encoded_params`"] + pub type ENCODED_PARAMS_R = crate::R; + #[doc = "Reader of field `rx_buffer_depth`"] + pub type RX_BUFFER_DEPTH_R = crate::R; + #[doc = "Reader of field `tx_buffer_depth`"] + pub type TX_BUFFER_DEPTH_R = crate::R; + impl R { + #[doc = "Bits 0:1 - APB_DATA_WIDTH"] + #[inline(always)] + pub fn apb_data_width(&self) -> APB_DATA_WIDTH_R { + APB_DATA_WIDTH_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - MAX_SPEED_MODE"] + #[inline(always)] + pub fn max_speed_mode(&self) -> MAX_SPEED_MODE_R { + MAX_SPEED_MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 4 - HC_COUNT_VALUES"] + #[inline(always)] + pub fn hc_count_values(&self) -> HC_COUNT_VALUES_R { + HC_COUNT_VALUES_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - INTR_IO"] + #[inline(always)] + pub fn intr_io(&self) -> INTR_IO_R { + INTR_IO_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - HAS_DMA"] + #[inline(always)] + pub fn has_dma(&self) -> HAS_DMA_R { + HAS_DMA_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - ENCODED_PARAMS"] + #[inline(always)] + pub fn encoded_params(&self) -> ENCODED_PARAMS_R { + ENCODED_PARAMS_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:15 - RX_BUFFER_DEPTH"] + #[inline(always)] + pub fn rx_buffer_depth(&self) -> RX_BUFFER_DEPTH_R { + RX_BUFFER_DEPTH_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - TX_BUFFER_DEPTH"] + #[inline(always)] + pub fn tx_buffer_depth(&self) -> TX_BUFFER_DEPTH_R { + TX_BUFFER_DEPTH_R::new(((self.bits >> 16) & 0xff) as u8) + } + } + } + #[doc = "Component Version Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_version](comp_version) module"] + pub type COMP_VERSION = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMP_VERSION; + #[doc = "`read()` method returns [comp_version::R](comp_version::R) reader structure"] + impl crate::Readable for COMP_VERSION {} + #[doc = "Component Version Register"] + pub mod comp_version { + #[doc = "Reader of register comp_version"] + pub type R = crate::R; + #[doc = "Reader of field `value`"] + pub type VALUE_R = crate::R; + impl R { + #[doc = "Bits 0:31 - VALUE"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0xffff_ffff) as u32) + } + } + } + #[doc = "Component Type Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_type](comp_type) module"] + pub type COMP_TYPE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMP_TYPE; + #[doc = "`read()` method returns [comp_type::R](comp_type::R) reader structure"] + impl crate::Readable for COMP_TYPE {} + #[doc = "Component Type Register"] + pub mod comp_type { + #[doc = "Reader of register comp_type"] + pub type R = crate::R; + #[doc = "Reader of field `value`"] + pub type VALUE_R = crate::R; + impl R { + #[doc = "Bits 0:31 - VALUE"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0xffff_ffff) as u32) + } + } + } +} +#[doc = "Inter-Integrated Circuit Bus 1"] +pub struct I2C1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2C1 {} +impl I2C1 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2c0::RegisterBlock { + 0x5029_0000 as *const _ + } +} +impl Deref for I2C1 { + type Target = i2c0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*I2C1::ptr() } + } +} +#[doc = "Inter-Integrated Circuit Bus 2"] +pub struct I2C2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2C2 {} +impl I2C2 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2c0::RegisterBlock { + 0x502a_0000 as *const _ + } +} +impl Deref for I2C2 { + type Target = i2c0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*I2C2::ptr() } + } +} +#[doc = "Field Programmable IO Array"] +pub struct FPIOA { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for FPIOA {} +impl FPIOA { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const fpioa::RegisterBlock { + 0x502b_0000 as *const _ + } +} +impl Deref for FPIOA { + type Target = fpioa::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*FPIOA::ptr() } + } +} +#[doc = "Field Programmable IO Array"] +pub mod fpioa { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - FPIOA GPIO multiplexer io array"] + pub io: [IO; 48], + #[doc = "0xc0 - FPIOA GPIO multiplexer tie enable array"] + pub tie_en: [TIE_EN; 8], + #[doc = "0xe0 - FPIOA GPIO multiplexer tie value array"] + pub tie_val: [TIE_VAL; 8], + } + #[doc = "FPIOA GPIO multiplexer io array\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [io](io) module"] + pub type IO = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IO; + #[doc = "`read()` method returns [io::R](io::R) reader structure"] + impl crate::Readable for IO {} + #[doc = "`write(|w| ..)` method takes [io::W](io::W) writer structure"] + impl crate::Writable for IO {} + #[doc = "FPIOA GPIO multiplexer io array"] + pub mod io { + #[doc = "Reader of register io[%s]"] + pub type R = crate::R; + #[doc = "Writer for register io[%s]"] + pub type W = crate::W; + #[doc = "Register io[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::IO { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `ch_sel`"] + pub type CH_SEL_R = crate::R; + #[doc = "Write proxy for field `ch_sel`"] + pub struct CH_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> CH_SEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + #[doc = "Reader of field `ds`"] + pub type DS_R = crate::R; + #[doc = "Write proxy for field `ds`"] + pub struct DS_W<'a> { + w: &'a mut W, + } + impl<'a> DS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8); + self.w + } + } + #[doc = "Reader of field `oe_en`"] + pub type OE_EN_R = crate::R; + #[doc = "Write proxy for field `oe_en`"] + pub struct OE_EN_W<'a> { + w: &'a mut W, + } + impl<'a> OE_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); + self.w + } + } + #[doc = "Reader of field `oe_inv`"] + pub type OE_INV_R = crate::R; + #[doc = "Write proxy for field `oe_inv`"] + pub struct OE_INV_W<'a> { + w: &'a mut W, + } + impl<'a> OE_INV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13); + self.w + } + } + #[doc = "Reader of field `do_sel`"] + pub type DO_SEL_R = crate::R; + #[doc = "Write proxy for field `do_sel`"] + pub struct DO_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> DO_SEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14); + self.w + } + } + #[doc = "Reader of field `do_inv`"] + pub type DO_INV_R = crate::R; + #[doc = "Write proxy for field `do_inv`"] + pub struct DO_INV_W<'a> { + w: &'a mut W, + } + impl<'a> DO_INV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); + self.w + } + } + #[doc = "Reader of field `pu`"] + pub type PU_R = crate::R; + #[doc = "Write proxy for field `pu`"] + pub struct PU_W<'a> { + w: &'a mut W, + } + impl<'a> PU_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); + self.w + } + } + #[doc = "Reader of field `pd`"] + pub type PD_R = crate::R; + #[doc = "Write proxy for field `pd`"] + pub struct PD_W<'a> { + w: &'a mut W, + } + impl<'a> PD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17); + self.w + } + } + #[doc = "Reader of field `sl`"] + pub type SL_R = crate::R; + #[doc = "Write proxy for field `sl`"] + pub struct SL_W<'a> { + w: &'a mut W, + } + impl<'a> SL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19); + self.w + } + } + #[doc = "Reader of field `ie_en`"] + pub type IE_EN_R = crate::R; + #[doc = "Write proxy for field `ie_en`"] + pub struct IE_EN_W<'a> { + w: &'a mut W, + } + impl<'a> IE_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20); + self.w + } + } + #[doc = "Reader of field `ie_inv`"] + pub type IE_INV_R = crate::R; + #[doc = "Write proxy for field `ie_inv`"] + pub struct IE_INV_W<'a> { + w: &'a mut W, + } + impl<'a> IE_INV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21); + self.w + } + } + #[doc = "Reader of field `di_inv`"] + pub type DI_INV_R = crate::R; + #[doc = "Write proxy for field `di_inv`"] + pub struct DI_INV_W<'a> { + w: &'a mut W, + } + impl<'a> DI_INV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22); + self.w + } + } + #[doc = "Reader of field `st`"] + pub type ST_R = crate::R; + #[doc = "Write proxy for field `st`"] + pub struct ST_W<'a> { + w: &'a mut W, + } + impl<'a> ST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23); + self.w + } + } + #[doc = "Reader of field `pad_di`"] + pub type PAD_DI_R = crate::R; + #[doc = "Write proxy for field `pad_di`"] + pub struct PAD_DI_W<'a> { + w: &'a mut W, + } + impl<'a> PAD_DI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31); + self.w + } + } + impl R { + #[doc = "Bits 0:7 - Channel select from 256 input"] + #[inline(always)] + pub fn ch_sel(&self) -> CH_SEL_R { + CH_SEL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:11 - Driving selector"] + #[inline(always)] + pub fn ds(&self) -> DS_R { + DS_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Static output enable, will AND with OE_INV"] + #[inline(always)] + pub fn oe_en(&self) -> OE_EN_R { + OE_EN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Invert output enable"] + #[inline(always)] + pub fn oe_inv(&self) -> OE_INV_R { + OE_INV_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Data output select: 0 for DO, 1 for OE"] + #[inline(always)] + pub fn do_sel(&self) -> DO_SEL_R { + DO_SEL_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Invert the result of data output select (DO_SEL)"] + #[inline(always)] + pub fn do_inv(&self) -> DO_INV_R { + DO_INV_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Pull up enable. 0 for nothing, 1 for pull up"] + #[inline(always)] + pub fn pu(&self) -> PU_R { + PU_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Pull down enable. 0 for nothing, 1 for pull down"] + #[inline(always)] + pub fn pd(&self) -> PD_R { + PD_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 19 - Slew rate control enable"] + #[inline(always)] + pub fn sl(&self) -> SL_R { + SL_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Static input enable, will AND with IE_INV"] + #[inline(always)] + pub fn ie_en(&self) -> IE_EN_R { + IE_EN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Invert input enable"] + #[inline(always)] + pub fn ie_inv(&self) -> IE_INV_R { + IE_INV_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Invert Data input"] + #[inline(always)] + pub fn di_inv(&self) -> DI_INV_R { + DI_INV_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Schmitt trigger"] + #[inline(always)] + pub fn st(&self) -> ST_R { + ST_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 31 - Read current IO's data input"] + #[inline(always)] + pub fn pad_di(&self) -> PAD_DI_R { + PAD_DI_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:7 - Channel select from 256 input"] + #[inline(always)] + pub fn ch_sel(&mut self) -> CH_SEL_W { + CH_SEL_W { w: self } + } + #[doc = "Bits 8:11 - Driving selector"] + #[inline(always)] + pub fn ds(&mut self) -> DS_W { + DS_W { w: self } + } + #[doc = "Bit 12 - Static output enable, will AND with OE_INV"] + #[inline(always)] + pub fn oe_en(&mut self) -> OE_EN_W { + OE_EN_W { w: self } + } + #[doc = "Bit 13 - Invert output enable"] + #[inline(always)] + pub fn oe_inv(&mut self) -> OE_INV_W { + OE_INV_W { w: self } + } + #[doc = "Bit 14 - Data output select: 0 for DO, 1 for OE"] + #[inline(always)] + pub fn do_sel(&mut self) -> DO_SEL_W { + DO_SEL_W { w: self } + } + #[doc = "Bit 15 - Invert the result of data output select (DO_SEL)"] + #[inline(always)] + pub fn do_inv(&mut self) -> DO_INV_W { + DO_INV_W { w: self } + } + #[doc = "Bit 16 - Pull up enable. 0 for nothing, 1 for pull up"] + #[inline(always)] + pub fn pu(&mut self) -> PU_W { + PU_W { w: self } + } + #[doc = "Bit 17 - Pull down enable. 0 for nothing, 1 for pull down"] + #[inline(always)] + pub fn pd(&mut self) -> PD_W { + PD_W { w: self } + } + #[doc = "Bit 19 - Slew rate control enable"] + #[inline(always)] + pub fn sl(&mut self) -> SL_W { + SL_W { w: self } + } + #[doc = "Bit 20 - Static input enable, will AND with IE_INV"] + #[inline(always)] + pub fn ie_en(&mut self) -> IE_EN_W { + IE_EN_W { w: self } + } + #[doc = "Bit 21 - Invert input enable"] + #[inline(always)] + pub fn ie_inv(&mut self) -> IE_INV_W { + IE_INV_W { w: self } + } + #[doc = "Bit 22 - Invert Data input"] + #[inline(always)] + pub fn di_inv(&mut self) -> DI_INV_W { + DI_INV_W { w: self } + } + #[doc = "Bit 23 - Schmitt trigger"] + #[inline(always)] + pub fn st(&mut self) -> ST_W { + ST_W { w: self } + } + #[doc = "Bit 31 - Read current IO's data input"] + #[inline(always)] + pub fn pad_di(&mut self) -> PAD_DI_W { + PAD_DI_W { w: self } + } + } + } + #[doc = "FPIOA GPIO multiplexer tie enable array\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tie_en](tie_en) module"] + pub type TIE_EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TIE_EN; + #[doc = "`read()` method returns [tie_en::R](tie_en::R) reader structure"] + impl crate::Readable for TIE_EN {} + #[doc = "`write(|w| ..)` method takes [tie_en::W](tie_en::W) writer structure"] + impl crate::Writable for TIE_EN {} + #[doc = "FPIOA GPIO multiplexer tie enable array"] + pub mod tie_en { + #[doc = "Reader of register tie_en[%s]"] + pub type R = crate::R; + #[doc = "Writer for register tie_en[%s]"] + pub type W = crate::W; + #[doc = "Register tie_en[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::TIE_EN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "FPIOA GPIO multiplexer tie value array\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tie_val](tie_val) module"] + pub type TIE_VAL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TIE_VAL; + #[doc = "`read()` method returns [tie_val::R](tie_val::R) reader structure"] + impl crate::Readable for TIE_VAL {} + #[doc = "`write(|w| ..)` method takes [tie_val::W](tie_val::W) writer structure"] + impl crate::Writable for TIE_VAL {} + #[doc = "FPIOA GPIO multiplexer tie value array"] + pub mod tie_val { + #[doc = "Reader of register tie_val[%s]"] + pub type R = crate::R; + #[doc = "Writer for register tie_val[%s]"] + pub type W = crate::W; + #[doc = "Register tie_val[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::TIE_VAL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "SHA256 Accelerator"] +pub struct SHA256 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SHA256 {} +impl SHA256 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sha256::RegisterBlock { + 0x502c_0000 as *const _ + } +} +impl Deref for SHA256 { + type Target = sha256::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*SHA256::ptr() } + } +} +#[doc = "SHA256 Accelerator"] +pub mod sha256 { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Calculated SHA256 return value"] + pub result: [RESULT; 8], + #[doc = "0x20 - SHA256 input data is written to this register"] + pub data_in: DATA_IN, + _reserved2: [u8; 4usize], + #[doc = "0x28 - Counters register"] + pub num_reg: NUM_REG, + #[doc = "0x2c - Function configuration register 0"] + pub function_reg_0: FUNCTION_REG_0, + _reserved4: [u8; 4usize], + #[doc = "0x34 - Function configuration register 1"] + pub function_reg_1: FUNCTION_REG_1, + } + #[doc = "Calculated SHA256 return value\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](result) module"] + pub type RESULT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RESULT; + #[doc = "`read()` method returns [result::R](result::R) reader structure"] + impl crate::Readable for RESULT {} + #[doc = "`write(|w| ..)` method takes [result::W](result::W) writer structure"] + impl crate::Writable for RESULT {} + #[doc = "Calculated SHA256 return value"] + pub mod result { + #[doc = "Reader of register result[%s]"] + pub type R = crate::R; + #[doc = "Writer for register result[%s]"] + pub type W = crate::W; + #[doc = "Register result[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::RESULT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "SHA256 input data is written to this register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data_in](data_in) module"] + pub type DATA_IN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DATA_IN; + #[doc = "`read()` method returns [data_in::R](data_in::R) reader structure"] + impl crate::Readable for DATA_IN {} + #[doc = "`write(|w| ..)` method takes [data_in::W](data_in::W) writer structure"] + impl crate::Writable for DATA_IN {} + #[doc = "SHA256 input data is written to this register"] + pub mod data_in { + #[doc = "Reader of register data_in"] + pub type R = crate::R; + #[doc = "Writer for register data_in"] + pub type W = crate::W; + #[doc = "Register data_in `reset()`'s with value 0"] + impl crate::ResetValue for super::DATA_IN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Counters register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [num_reg](num_reg) module"] + pub type NUM_REG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _NUM_REG; + #[doc = "`read()` method returns [num_reg::R](num_reg::R) reader structure"] + impl crate::Readable for NUM_REG {} + #[doc = "`write(|w| ..)` method takes [num_reg::W](num_reg::W) writer structure"] + impl crate::Writable for NUM_REG {} + #[doc = "Counters register"] + pub mod num_reg { + #[doc = "Reader of register num_reg"] + pub type R = crate::R; + #[doc = "Writer for register num_reg"] + pub type W = crate::W; + #[doc = "Register num_reg `reset()`'s with value 0"] + impl crate::ResetValue for super::NUM_REG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `data_cnt`"] + pub type DATA_CNT_R = crate::R; + #[doc = "Write proxy for field `data_cnt`"] + pub struct DATA_CNT_W<'a> { + w: &'a mut W, + } + impl<'a> DATA_CNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + #[doc = "Reader of field `data_num`"] + pub type DATA_NUM_R = crate::R; + #[doc = "Write proxy for field `data_num`"] + pub struct DATA_NUM_W<'a> { + w: &'a mut W, + } + impl<'a> DATA_NUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16); + self.w + } + } + impl R { + #[doc = "Bits 0:15 - The total amount of data calculated by SHA256 is set by this register, and the smallest unit is 512bit"] + #[inline(always)] + pub fn data_cnt(&self) -> DATA_CNT_R { + DATA_CNT_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Currently calculated block number. 512bit=1block"] + #[inline(always)] + pub fn data_num(&self) -> DATA_NUM_R { + DATA_NUM_R::new(((self.bits >> 16) & 0xffff) as u16) + } + } + impl W { + #[doc = "Bits 0:15 - The total amount of data calculated by SHA256 is set by this register, and the smallest unit is 512bit"] + #[inline(always)] + pub fn data_cnt(&mut self) -> DATA_CNT_W { + DATA_CNT_W { w: self } + } + #[doc = "Bits 16:31 - Currently calculated block number. 512bit=1block"] + #[inline(always)] + pub fn data_num(&mut self) -> DATA_NUM_W { + DATA_NUM_W { w: self } + } + } + } + #[doc = "Function configuration register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [function_reg_0](function_reg_0) module"] + pub type FUNCTION_REG_0 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FUNCTION_REG_0; + #[doc = "`read()` method returns [function_reg_0::R](function_reg_0::R) reader structure"] + impl crate::Readable for FUNCTION_REG_0 {} + #[doc = "`write(|w| ..)` method takes [function_reg_0::W](function_reg_0::W) writer structure"] + impl crate::Writable for FUNCTION_REG_0 {} + #[doc = "Function configuration register 0"] + pub mod function_reg_0 { + #[doc = "Reader of register function_reg_0"] + pub type R = crate::R; + #[doc = "Writer for register function_reg_0"] + pub type W = crate::W; + #[doc = "Register function_reg_0 `reset()`'s with value 0"] + impl crate::ResetValue for super::FUNCTION_REG_0 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `en`"] + pub type EN_R = crate::R; + #[doc = "Write proxy for field `en`"] + pub struct EN_W<'a> { + w: &'a mut W, + } + impl<'a> EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `overflow`"] + pub type OVERFLOW_R = crate::R; + #[doc = "Write proxy for field `overflow`"] + pub struct OVERFLOW_W<'a> { + w: &'a mut W, + } + impl<'a> OVERFLOW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Endian setting\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum ENDIAN_A { + #[doc = "0: Little endian"] + LE = 0, + #[doc = "1: Big endian"] + BE = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: ENDIAN_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `endian`"] + pub type ENDIAN_R = crate::R; + impl ENDIAN_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDIAN_A { + match self.bits { + false => ENDIAN_A::LE, + true => ENDIAN_A::BE, + } + } + #[doc = "Checks if the value of the field is `LE`"] + #[inline(always)] + pub fn is_le(&self) -> bool { + *self == ENDIAN_A::LE + } + #[doc = "Checks if the value of the field is `BE`"] + #[inline(always)] + pub fn is_be(&self) -> bool { + *self == ENDIAN_A::BE + } + } + #[doc = "Write proxy for field `endian`"] + pub struct ENDIAN_W<'a> { + w: &'a mut W, + } + impl<'a> ENDIAN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENDIAN_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Little endian"] + #[inline(always)] + pub fn le(self) -> &'a mut W { + self.variant(ENDIAN_A::LE) + } + #[doc = "Big endian"] + #[inline(always)] + pub fn be(self) -> &'a mut W { + self.variant(ENDIAN_A::BE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); + self.w + } + } + impl R { + #[doc = "Bit 0 - write:SHA256 enable register. read:Calculation completed flag"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 8 - SHA256 calculation overflow flag"] + #[inline(always)] + pub fn overflow(&self) -> OVERFLOW_R { + OVERFLOW_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 16 - Endian setting"] + #[inline(always)] + pub fn endian(&self) -> ENDIAN_R { + ENDIAN_R::new(((self.bits >> 16) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - write:SHA256 enable register. read:Calculation completed flag"] + #[inline(always)] + pub fn en(&mut self) -> EN_W { + EN_W { w: self } + } + #[doc = "Bit 8 - SHA256 calculation overflow flag"] + #[inline(always)] + pub fn overflow(&mut self) -> OVERFLOW_W { + OVERFLOW_W { w: self } + } + #[doc = "Bit 16 - Endian setting"] + #[inline(always)] + pub fn endian(&mut self) -> ENDIAN_W { + ENDIAN_W { w: self } + } + } + } + #[doc = "Function configuration register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [function_reg_1](function_reg_1) module"] + pub type FUNCTION_REG_1 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FUNCTION_REG_1; + #[doc = "`read()` method returns [function_reg_1::R](function_reg_1::R) reader structure"] + impl crate::Readable for FUNCTION_REG_1 {} + #[doc = "`write(|w| ..)` method takes [function_reg_1::W](function_reg_1::W) writer structure"] + impl crate::Writable for FUNCTION_REG_1 {} + #[doc = "Function configuration register 1"] + pub mod function_reg_1 { + #[doc = "Reader of register function_reg_1"] + pub type R = crate::R; + #[doc = "Writer for register function_reg_1"] + pub type W = crate::W; + #[doc = "Register function_reg_1 `reset()`'s with value 0"] + impl crate::ResetValue for super::FUNCTION_REG_1 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `dma_en`"] + pub type DMA_EN_R = crate::R; + #[doc = "Write proxy for field `dma_en`"] + pub struct DMA_EN_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `fifo_in_full`"] + pub type FIFO_IN_FULL_R = crate::R; + #[doc = "Write proxy for field `fifo_in_full`"] + pub struct FIFO_IN_FULL_W<'a> { + w: &'a mut W, + } + impl<'a> FIFO_IN_FULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + impl R { + #[doc = "Bit 0 - SHA and DMA handshake signals enable. 1:enable; 0:disable"] + #[inline(always)] + pub fn dma_en(&self) -> DMA_EN_R { + DMA_EN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 8 - 1:SHA256 input fifo is full; 0:not full"] + #[inline(always)] + pub fn fifo_in_full(&self) -> FIFO_IN_FULL_R { + FIFO_IN_FULL_R::new(((self.bits >> 8) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - SHA and DMA handshake signals enable. 1:enable; 0:disable"] + #[inline(always)] + pub fn dma_en(&mut self) -> DMA_EN_W { + DMA_EN_W { w: self } + } + #[doc = "Bit 8 - 1:SHA256 input fifo is full; 0:not full"] + #[inline(always)] + pub fn fifo_in_full(&mut self) -> FIFO_IN_FULL_W { + FIFO_IN_FULL_W { w: self } + } + } + } +} +#[doc = "Timer 0"] +pub struct TIMER0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIMER0 {} +impl TIMER0 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const timer0::RegisterBlock { + 0x502d_0000 as *const _ + } +} +impl Deref for TIMER0 { + type Target = timer0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*TIMER0::ptr() } + } +} +#[doc = "Timer 0"] +pub mod timer0 { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Channel cluster: load_count, current_value, control, eoi and intr_stat registers"] + pub channel: [CHANNEL; 4], + _reserved1: [u8; 80usize], + #[doc = "0xa0 - Interrupt Status Register"] + pub intr_stat: INTR_STAT, + #[doc = "0xa4 - Interrupt Clear Register"] + pub eoi: EOI, + #[doc = "0xa8 - Raw Interrupt Status Register"] + pub raw_intr_stat: RAW_INTR_STAT, + #[doc = "0xac - Component Version Register"] + pub comp_version: COMP_VERSION, + #[doc = "0xb0 - Load Count2 Register"] + pub load_count2: [LOAD_COUNT2; 4], + } + #[doc = r"Register block"] + #[repr(C)] + pub struct CHANNEL { + #[doc = "0x00 - Load Count Register"] + pub load_count: self::channel::LOAD_COUNT, + #[doc = "0x04 - Current Value Register"] + pub current_value: self::channel::CURRENT_VALUE, + #[doc = "0x08 - Control Register"] + pub control: self::channel::CONTROL, + #[doc = "0x0c - Interrupt Clear Register"] + pub eoi: self::channel::EOI, + #[doc = "0x10 - Interrupt Status Register"] + pub intr_stat: self::channel::INTR_STAT, + } + #[doc = r"Register block"] + #[doc = "Channel cluster: load_count, current_value, control, eoi and intr_stat registers"] + pub mod channel { + #[doc = "Load Count Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [load_count](load_count) module"] + pub type LOAD_COUNT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LOAD_COUNT; + #[doc = "`read()` method returns [load_count::R](load_count::R) reader structure"] + impl crate::Readable for LOAD_COUNT {} + #[doc = "`write(|w| ..)` method takes [load_count::W](load_count::W) writer structure"] + impl crate::Writable for LOAD_COUNT {} + #[doc = "Load Count Register"] + pub mod load_count { + #[doc = "Reader of register load_count"] + pub type R = crate::R; + #[doc = "Writer for register load_count"] + pub type W = crate::W; + #[doc = "Register load_count `reset()`'s with value 0"] + impl crate::ResetValue for super::LOAD_COUNT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Current Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [current_value](current_value) module"] + pub type CURRENT_VALUE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CURRENT_VALUE; + #[doc = "`read()` method returns [current_value::R](current_value::R) reader structure"] + impl crate::Readable for CURRENT_VALUE {} + #[doc = "`write(|w| ..)` method takes [current_value::W](current_value::W) writer structure"] + impl crate::Writable for CURRENT_VALUE {} + #[doc = "Current Value Register"] + pub mod current_value { + #[doc = "Reader of register current_value"] + pub type R = crate::R; + #[doc = "Writer for register current_value"] + pub type W = crate::W; + #[doc = "Register current_value `reset()`'s with value 0"] + impl crate::ResetValue for super::CURRENT_VALUE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [control](control) module"] + pub type CONTROL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CONTROL; + #[doc = "`read()` method returns [control::R](control::R) reader structure"] + impl crate::Readable for CONTROL {} + #[doc = "`write(|w| ..)` method takes [control::W](control::W) writer structure"] + impl crate::Writable for CONTROL {} + #[doc = "Control Register"] + pub mod control { + #[doc = "Reader of register control"] + pub type R = crate::R; + #[doc = "Writer for register control"] + pub type W = crate::W; + #[doc = "Register control `reset()`'s with value 0"] + impl crate::ResetValue for super::CONTROL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `enable`"] + pub type ENABLE_R = crate::R; + #[doc = "Write proxy for field `enable`"] + pub struct ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "MODE\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum MODE_A { + #[doc = "0: FREE_MODE"] + FREE = 0, + #[doc = "1: USER_MODE"] + USER = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `mode`"] + pub type MODE_R = crate::R; + impl MODE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MODE_A { + match self.bits { + false => MODE_A::FREE, + true => MODE_A::USER, + } + } + #[doc = "Checks if the value of the field is `FREE`"] + #[inline(always)] + pub fn is_free(&self) -> bool { + *self == MODE_A::FREE + } + #[doc = "Checks if the value of the field is `USER`"] + #[inline(always)] + pub fn is_user(&self) -> bool { + *self == MODE_A::USER + } + } + #[doc = "Write proxy for field `mode`"] + pub struct MODE_W<'a> { + w: &'a mut W, + } + impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "FREE_MODE"] + #[inline(always)] + pub fn free(self) -> &'a mut W { + self.variant(MODE_A::FREE) + } + #[doc = "USER_MODE"] + #[inline(always)] + pub fn user(self) -> &'a mut W { + self.variant(MODE_A::USER) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `interrupt`"] + pub type INTERRUPT_R = crate::R; + #[doc = "Write proxy for field `interrupt`"] + pub struct INTERRUPT_W<'a> { + w: &'a mut W, + } + impl<'a> INTERRUPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `pwm_enable`"] + pub type PWM_ENABLE_R = crate::R; + #[doc = "Write proxy for field `pwm_enable`"] + pub struct PWM_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> PWM_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + impl R { + #[doc = "Bit 0 - ENABLE"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - MODE"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - INTERRUPT_MASK"] + #[inline(always)] + pub fn interrupt(&self) -> INTERRUPT_R { + INTERRUPT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - PWM_ENABLE"] + #[inline(always)] + pub fn pwm_enable(&self) -> PWM_ENABLE_R { + PWM_ENABLE_R::new(((self.bits >> 3) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - ENABLE"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 1 - MODE"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 2 - INTERRUPT_MASK"] + #[inline(always)] + pub fn interrupt(&mut self) -> INTERRUPT_W { + INTERRUPT_W { w: self } + } + #[doc = "Bit 3 - PWM_ENABLE"] + #[inline(always)] + pub fn pwm_enable(&mut self) -> PWM_ENABLE_W { + PWM_ENABLE_W { w: self } + } + } + } + #[doc = "Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [eoi](eoi) module"] + pub type EOI = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _EOI; + #[doc = "`read()` method returns [eoi::R](eoi::R) reader structure"] + impl crate::Readable for EOI {} + #[doc = "`write(|w| ..)` method takes [eoi::W](eoi::W) writer structure"] + impl crate::Writable for EOI {} + #[doc = "Interrupt Clear Register"] + pub mod eoi { + #[doc = "Reader of register eoi"] + pub type R = crate::R; + #[doc = "Writer for register eoi"] + pub type W = crate::W; + #[doc = "Register eoi `reset()`'s with value 0"] + impl crate::ResetValue for super::EOI { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intr_stat](intr_stat) module"] + pub type INTR_STAT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTR_STAT; + #[doc = "`read()` method returns [intr_stat::R](intr_stat::R) reader structure"] + impl crate::Readable for INTR_STAT {} + #[doc = "`write(|w| ..)` method takes [intr_stat::W](intr_stat::W) writer structure"] + impl crate::Writable for INTR_STAT {} + #[doc = "Interrupt Status Register"] + pub mod intr_stat { + #[doc = "Reader of register intr_stat"] + pub type R = crate::R; + #[doc = "Writer for register intr_stat"] + pub type W = crate::W; + #[doc = "Register intr_stat `reset()`'s with value 0"] + impl crate::ResetValue for super::INTR_STAT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + } + #[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intr_stat](intr_stat) module"] + pub type INTR_STAT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTR_STAT; + #[doc = "`read()` method returns [intr_stat::R](intr_stat::R) reader structure"] + impl crate::Readable for INTR_STAT {} + #[doc = "`write(|w| ..)` method takes [intr_stat::W](intr_stat::W) writer structure"] + impl crate::Writable for INTR_STAT {} + #[doc = "Interrupt Status Register"] + pub mod intr_stat { + #[doc = "Reader of register intr_stat"] + pub type R = crate::R; + #[doc = "Writer for register intr_stat"] + pub type W = crate::W; + #[doc = "Register intr_stat `reset()`'s with value 0"] + impl crate::ResetValue for super::INTR_STAT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [eoi](eoi) module"] + pub type EOI = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _EOI; + #[doc = "`read()` method returns [eoi::R](eoi::R) reader structure"] + impl crate::Readable for EOI {} + #[doc = "`write(|w| ..)` method takes [eoi::W](eoi::W) writer structure"] + impl crate::Writable for EOI {} + #[doc = "Interrupt Clear Register"] + pub mod eoi { + #[doc = "Reader of register eoi"] + pub type R = crate::R; + #[doc = "Writer for register eoi"] + pub type W = crate::W; + #[doc = "Register eoi `reset()`'s with value 0"] + impl crate::ResetValue for super::EOI { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Raw Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [raw_intr_stat](raw_intr_stat) module"] + pub type RAW_INTR_STAT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RAW_INTR_STAT; + #[doc = "`read()` method returns [raw_intr_stat::R](raw_intr_stat::R) reader structure"] + impl crate::Readable for RAW_INTR_STAT {} + #[doc = "`write(|w| ..)` method takes [raw_intr_stat::W](raw_intr_stat::W) writer structure"] + impl crate::Writable for RAW_INTR_STAT {} + #[doc = "Raw Interrupt Status Register"] + pub mod raw_intr_stat { + #[doc = "Reader of register raw_intr_stat"] + pub type R = crate::R; + #[doc = "Writer for register raw_intr_stat"] + pub type W = crate::W; + #[doc = "Register raw_intr_stat `reset()`'s with value 0"] + impl crate::ResetValue for super::RAW_INTR_STAT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Component Version Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_version](comp_version) module"] + pub type COMP_VERSION = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMP_VERSION; + #[doc = "`read()` method returns [comp_version::R](comp_version::R) reader structure"] + impl crate::Readable for COMP_VERSION {} + #[doc = "`write(|w| ..)` method takes [comp_version::W](comp_version::W) writer structure"] + impl crate::Writable for COMP_VERSION {} + #[doc = "Component Version Register"] + pub mod comp_version { + #[doc = "Reader of register comp_version"] + pub type R = crate::R; + #[doc = "Writer for register comp_version"] + pub type W = crate::W; + #[doc = "Register comp_version `reset()`'s with value 0"] + impl crate::ResetValue for super::COMP_VERSION { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Load Count2 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [load_count2](load_count2) module"] + pub type LOAD_COUNT2 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LOAD_COUNT2; + #[doc = "`read()` method returns [load_count2::R](load_count2::R) reader structure"] + impl crate::Readable for LOAD_COUNT2 {} + #[doc = "`write(|w| ..)` method takes [load_count2::W](load_count2::W) writer structure"] + impl crate::Writable for LOAD_COUNT2 {} + #[doc = "Load Count2 Register"] + pub mod load_count2 { + #[doc = "Reader of register load_count2%s"] + pub type R = crate::R; + #[doc = "Writer for register load_count2%s"] + pub type W = crate::W; + #[doc = "Register load_count2%s `reset()`'s with value 0"] + impl crate::ResetValue for super::LOAD_COUNT2 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Timer 1"] +pub struct TIMER1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIMER1 {} +impl TIMER1 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const timer0::RegisterBlock { + 0x502e_0000 as *const _ + } +} +impl Deref for TIMER1 { + type Target = timer0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*TIMER1::ptr() } + } +} +#[doc = "Timer 2"] +pub struct TIMER2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIMER2 {} +impl TIMER2 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const timer0::RegisterBlock { + 0x502f_0000 as *const _ + } +} +impl Deref for TIMER2 { + type Target = timer0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*TIMER2::ptr() } + } +} +#[doc = "Watchdog Timer 0"] +pub struct WDT0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WDT0 {} +impl WDT0 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const wdt0::RegisterBlock { + 0x5040_0000 as *const _ + } +} +impl Deref for WDT0 { + type Target = wdt0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*WDT0::ptr() } + } +} +#[doc = "Watchdog Timer 0"] +pub mod wdt0 { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Control Register"] + pub cr: CR, + #[doc = "0x04 - Timeout Range Register"] + pub torr: TORR, + #[doc = "0x08 - Current Counter Value Register"] + pub ccvr: CCVR, + #[doc = "0x0c - Counter Restart Register"] + pub crr: CRR, + #[doc = "0x10 - Interrupt Status Register"] + pub stat: STAT, + #[doc = "0x14 - Interrupt Clear Register"] + pub eoi: EOI, + _reserved6: [u8; 4usize], + #[doc = "0x1c - Protection level Register"] + pub prot_level: PROT_LEVEL, + _reserved7: [u8; 196usize], + #[doc = "0xe4 - Component Parameters Register 5"] + pub comp_param_5: COMP_PARAM_5, + #[doc = "0xe8 - Component Parameters Register 4"] + pub comp_param_4: COMP_PARAM_4, + #[doc = "0xec - Component Parameters Register 3"] + pub comp_param_3: COMP_PARAM_3, + #[doc = "0xf0 - Component Parameters Register 2"] + pub comp_param_2: COMP_PARAM_2, + #[doc = "0xf4 - Component Parameters Register 1"] + pub comp_param_1: COMP_PARAM_1, + #[doc = "0xf8 - Component Version Register"] + pub comp_version: COMP_VERSION, + #[doc = "0xfc - Component Type Register"] + pub comp_type: COMP_TYPE, + } + #[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](cr) module"] + pub type CR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CR; + #[doc = "`read()` method returns [cr::R](cr::R) reader structure"] + impl crate::Readable for CR {} + #[doc = "`write(|w| ..)` method takes [cr::W](cr::W) writer structure"] + impl crate::Writable for CR {} + #[doc = "Control Register"] + pub mod cr { + #[doc = "Reader of register cr"] + pub type R = crate::R; + #[doc = "Writer for register cr"] + pub type W = crate::W; + #[doc = "Register cr `reset()`'s with value 0"] + impl crate::ResetValue for super::CR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `enable`"] + pub type ENABLE_R = crate::R; + #[doc = "Write proxy for field `enable`"] + pub struct ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "rmod\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum RMOD_A { + #[doc = "0: RESET"] + RESET = 0, + #[doc = "1: INTERRUPT"] + INTERRUPT = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: RMOD_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `rmod`"] + pub type RMOD_R = crate::R; + impl RMOD_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RMOD_A { + match self.bits { + false => RMOD_A::RESET, + true => RMOD_A::INTERRUPT, + } + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + *self == RMOD_A::RESET + } + #[doc = "Checks if the value of the field is `INTERRUPT`"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == RMOD_A::INTERRUPT + } + } + #[doc = "Write proxy for field `rmod`"] + pub struct RMOD_W<'a> { + w: &'a mut W, + } + impl<'a> RMOD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RMOD_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "RESET"] + #[inline(always)] + pub fn reset(self) -> &'a mut W { + self.variant(RMOD_A::RESET) + } + #[doc = "INTERRUPT"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut W { + self.variant(RMOD_A::INTERRUPT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `rpl`"] + pub type RPL_R = crate::R; + #[doc = "Write proxy for field `rpl`"] + pub struct RPL_W<'a> { + w: &'a mut W, + } + impl<'a> RPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | (((value as u32) & 0x07) << 2); + self.w + } + } + impl R { + #[doc = "Bit 0 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - rmod"] + #[inline(always)] + pub fn rmod(&self) -> RMOD_R { + RMOD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - rpl"] + #[inline(always)] + pub fn rpl(&self) -> RPL_R { + RPL_R::new(((self.bits >> 2) & 0x07) as u8) + } + } + impl W { + #[doc = "Bit 0 - enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 1 - rmod"] + #[inline(always)] + pub fn rmod(&mut self) -> RMOD_W { + RMOD_W { w: self } + } + #[doc = "Bits 2:4 - rpl"] + #[inline(always)] + pub fn rpl(&mut self) -> RPL_W { + RPL_W { w: self } + } + } + } + #[doc = "Timeout Range Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [torr](torr) module"] + pub type TORR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TORR; + #[doc = "`read()` method returns [torr::R](torr::R) reader structure"] + impl crate::Readable for TORR {} + #[doc = "`write(|w| ..)` method takes [torr::W](torr::W) writer structure"] + impl crate::Writable for TORR {} + #[doc = "Timeout Range Register"] + pub mod torr { + #[doc = "Reader of register torr"] + pub type R = crate::R; + #[doc = "Writer for register torr"] + pub type W = crate::W; + #[doc = "Register torr `reset()`'s with value 0"] + impl crate::ResetValue for super::TORR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `top0`"] + pub type TOP0_R = crate::R; + #[doc = "Write proxy for field `top0`"] + pub struct TOP0_W<'a> { + w: &'a mut W, + } + impl<'a> TOP0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f); + self.w + } + } + #[doc = "Reader of field `top1`"] + pub type TOP1_R = crate::R; + #[doc = "Write proxy for field `top1`"] + pub struct TOP1_W<'a> { + w: &'a mut W, + } + impl<'a> TOP1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4); + self.w + } + } + impl R { + #[doc = "Bits 0:3 - top (lower half)"] + #[inline(always)] + pub fn top0(&self) -> TOP0_R { + TOP0_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - top (upper half)"] + #[inline(always)] + pub fn top1(&self) -> TOP1_R { + TOP1_R::new(((self.bits >> 4) & 0x0f) as u8) + } + } + impl W { + #[doc = "Bits 0:3 - top (lower half)"] + #[inline(always)] + pub fn top0(&mut self) -> TOP0_W { + TOP0_W { w: self } + } + #[doc = "Bits 4:7 - top (upper half)"] + #[inline(always)] + pub fn top1(&mut self) -> TOP1_W { + TOP1_W { w: self } + } + } + } + #[doc = "Current Counter Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccvr](ccvr) module"] + pub type CCVR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CCVR; + #[doc = "`read()` method returns [ccvr::R](ccvr::R) reader structure"] + impl crate::Readable for CCVR {} + #[doc = "`write(|w| ..)` method takes [ccvr::W](ccvr::W) writer structure"] + impl crate::Writable for CCVR {} + #[doc = "Current Counter Value Register"] + pub mod ccvr { + #[doc = "Reader of register ccvr"] + pub type R = crate::R; + #[doc = "Writer for register ccvr"] + pub type W = crate::W; + #[doc = "Register ccvr `reset()`'s with value 0"] + impl crate::ResetValue for super::CCVR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Counter Restart Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crr](crr) module"] + pub type CRR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CRR; + #[doc = "`read()` method returns [crr::R](crr::R) reader structure"] + impl crate::Readable for CRR {} + #[doc = "`write(|w| ..)` method takes [crr::W](crr::W) writer structure"] + impl crate::Writable for CRR {} + #[doc = "Counter Restart Register"] + pub mod crr { + #[doc = "Reader of register crr"] + pub type R = crate::R; + #[doc = "Writer for register crr"] + pub type W = crate::W; + #[doc = "Register crr `reset()`'s with value 0"] + impl crate::ResetValue for super::CRR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stat](stat) module"] + pub type STAT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _STAT; + #[doc = "`read()` method returns [stat::R](stat::R) reader structure"] + impl crate::Readable for STAT {} + #[doc = "`write(|w| ..)` method takes [stat::W](stat::W) writer structure"] + impl crate::Writable for STAT {} + #[doc = "Interrupt Status Register"] + pub mod stat { + #[doc = "Reader of register stat"] + pub type R = crate::R; + #[doc = "Writer for register stat"] + pub type W = crate::W; + #[doc = "Register stat `reset()`'s with value 0"] + impl crate::ResetValue for super::STAT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `stat`"] + pub type STAT_R = crate::R; + #[doc = "Write proxy for field `stat`"] + pub struct STAT_W<'a> { + w: &'a mut W, + } + impl<'a> STAT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - stat"] + #[inline(always)] + pub fn stat(&self) -> STAT_R { + STAT_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - stat"] + #[inline(always)] + pub fn stat(&mut self) -> STAT_W { + STAT_W { w: self } + } + } + } + #[doc = "Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [eoi](eoi) module"] + pub type EOI = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _EOI; + #[doc = "`read()` method returns [eoi::R](eoi::R) reader structure"] + impl crate::Readable for EOI {} + #[doc = "`write(|w| ..)` method takes [eoi::W](eoi::W) writer structure"] + impl crate::Writable for EOI {} + #[doc = "Interrupt Clear Register"] + pub mod eoi { + #[doc = "Reader of register eoi"] + pub type R = crate::R; + #[doc = "Writer for register eoi"] + pub type W = crate::W; + #[doc = "Register eoi `reset()`'s with value 0"] + impl crate::ResetValue for super::EOI { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `eoi`"] + pub type EOI_R = crate::R; + #[doc = "Write proxy for field `eoi`"] + pub struct EOI_W<'a> { + w: &'a mut W, + } + impl<'a> EOI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - eoi"] + #[inline(always)] + pub fn eoi(&self) -> EOI_R { + EOI_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - eoi"] + #[inline(always)] + pub fn eoi(&mut self) -> EOI_W { + EOI_W { w: self } + } + } + } + #[doc = "Protection level Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prot_level](prot_level) module"] + pub type PROT_LEVEL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PROT_LEVEL; + #[doc = "`read()` method returns [prot_level::R](prot_level::R) reader structure"] + impl crate::Readable for PROT_LEVEL {} + #[doc = "`write(|w| ..)` method takes [prot_level::W](prot_level::W) writer structure"] + impl crate::Writable for PROT_LEVEL {} + #[doc = "Protection level Register"] + pub mod prot_level { + #[doc = "Reader of register prot_level"] + pub type R = crate::R; + #[doc = "Writer for register prot_level"] + pub type W = crate::W; + #[doc = "Register prot_level `reset()`'s with value 0"] + impl crate::ResetValue for super::PROT_LEVEL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `prot_level`"] + pub type PROT_LEVEL_R = crate::R; + #[doc = "Write proxy for field `prot_level`"] + pub struct PROT_LEVEL_W<'a> { + w: &'a mut W, + } + impl<'a> PROT_LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - prot_level"] + #[inline(always)] + pub fn prot_level(&self) -> PROT_LEVEL_R { + PROT_LEVEL_R::new((self.bits & 0x07) as u8) + } + } + impl W { + #[doc = "Bits 0:2 - prot_level"] + #[inline(always)] + pub fn prot_level(&mut self) -> PROT_LEVEL_W { + PROT_LEVEL_W { w: self } + } + } + } + #[doc = "Component Parameters Register 5\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_param_5](comp_param_5) module"] + pub type COMP_PARAM_5 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMP_PARAM_5; + #[doc = "`read()` method returns [comp_param_5::R](comp_param_5::R) reader structure"] + impl crate::Readable for COMP_PARAM_5 {} + #[doc = "`write(|w| ..)` method takes [comp_param_5::W](comp_param_5::W) writer structure"] + impl crate::Writable for COMP_PARAM_5 {} + #[doc = "Component Parameters Register 5"] + pub mod comp_param_5 { + #[doc = "Reader of register comp_param_5"] + pub type R = crate::R; + #[doc = "Writer for register comp_param_5"] + pub type W = crate::W; + #[doc = "Register comp_param_5 `reset()`'s with value 0"] + impl crate::ResetValue for super::COMP_PARAM_5 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `user_top_max`"] + pub type USER_TOP_MAX_R = crate::R; + #[doc = "Write proxy for field `user_top_max`"] + pub struct USER_TOP_MAX_W<'a> { + w: &'a mut W, + } + impl<'a> USER_TOP_MAX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff); + self.w + } + } + impl R { + #[doc = "Bits 0:31 - user_top_max"] + #[inline(always)] + pub fn user_top_max(&self) -> USER_TOP_MAX_R { + USER_TOP_MAX_R::new((self.bits & 0xffff_ffff) as u32) + } + } + impl W { + #[doc = "Bits 0:31 - user_top_max"] + #[inline(always)] + pub fn user_top_max(&mut self) -> USER_TOP_MAX_W { + USER_TOP_MAX_W { w: self } + } + } + } + #[doc = "Component Parameters Register 4\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_param_4](comp_param_4) module"] + pub type COMP_PARAM_4 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMP_PARAM_4; + #[doc = "`read()` method returns [comp_param_4::R](comp_param_4::R) reader structure"] + impl crate::Readable for COMP_PARAM_4 {} + #[doc = "`write(|w| ..)` method takes [comp_param_4::W](comp_param_4::W) writer structure"] + impl crate::Writable for COMP_PARAM_4 {} + #[doc = "Component Parameters Register 4"] + pub mod comp_param_4 { + #[doc = "Reader of register comp_param_4"] + pub type R = crate::R; + #[doc = "Writer for register comp_param_4"] + pub type W = crate::W; + #[doc = "Register comp_param_4 `reset()`'s with value 0"] + impl crate::ResetValue for super::COMP_PARAM_4 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `user_top_init_max`"] + pub type USER_TOP_INIT_MAX_R = crate::R; + #[doc = "Write proxy for field `user_top_init_max`"] + pub struct USER_TOP_INIT_MAX_W<'a> { + w: &'a mut W, + } + impl<'a> USER_TOP_INIT_MAX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff); + self.w + } + } + impl R { + #[doc = "Bits 0:31 - user_top_init_max"] + #[inline(always)] + pub fn user_top_init_max(&self) -> USER_TOP_INIT_MAX_R { + USER_TOP_INIT_MAX_R::new((self.bits & 0xffff_ffff) as u32) + } + } + impl W { + #[doc = "Bits 0:31 - user_top_init_max"] + #[inline(always)] + pub fn user_top_init_max(&mut self) -> USER_TOP_INIT_MAX_W { + USER_TOP_INIT_MAX_W { w: self } + } + } + } + #[doc = "Component Parameters Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_param_3](comp_param_3) module"] + pub type COMP_PARAM_3 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMP_PARAM_3; + #[doc = "`read()` method returns [comp_param_3::R](comp_param_3::R) reader structure"] + impl crate::Readable for COMP_PARAM_3 {} + #[doc = "`write(|w| ..)` method takes [comp_param_3::W](comp_param_3::W) writer structure"] + impl crate::Writable for COMP_PARAM_3 {} + #[doc = "Component Parameters Register 3"] + pub mod comp_param_3 { + #[doc = "Reader of register comp_param_3"] + pub type R = crate::R; + #[doc = "Writer for register comp_param_3"] + pub type W = crate::W; + #[doc = "Register comp_param_3 `reset()`'s with value 0"] + impl crate::ResetValue for super::COMP_PARAM_3 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `top_rst`"] + pub type TOP_RST_R = crate::R; + #[doc = "Write proxy for field `top_rst`"] + pub struct TOP_RST_W<'a> { + w: &'a mut W, + } + impl<'a> TOP_RST_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff); + self.w + } + } + impl R { + #[doc = "Bits 0:31 - top_rst"] + #[inline(always)] + pub fn top_rst(&self) -> TOP_RST_R { + TOP_RST_R::new((self.bits & 0xffff_ffff) as u32) + } + } + impl W { + #[doc = "Bits 0:31 - top_rst"] + #[inline(always)] + pub fn top_rst(&mut self) -> TOP_RST_W { + TOP_RST_W { w: self } + } + } + } + #[doc = "Component Parameters Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_param_2](comp_param_2) module"] + pub type COMP_PARAM_2 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMP_PARAM_2; + #[doc = "`read()` method returns [comp_param_2::R](comp_param_2::R) reader structure"] + impl crate::Readable for COMP_PARAM_2 {} + #[doc = "`write(|w| ..)` method takes [comp_param_2::W](comp_param_2::W) writer structure"] + impl crate::Writable for COMP_PARAM_2 {} + #[doc = "Component Parameters Register 2"] + pub mod comp_param_2 { + #[doc = "Reader of register comp_param_2"] + pub type R = crate::R; + #[doc = "Writer for register comp_param_2"] + pub type W = crate::W; + #[doc = "Register comp_param_2 `reset()`'s with value 0"] + impl crate::ResetValue for super::COMP_PARAM_2 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `cnt_rst`"] + pub type CNT_RST_R = crate::R; + #[doc = "Write proxy for field `cnt_rst`"] + pub struct CNT_RST_W<'a> { + w: &'a mut W, + } + impl<'a> CNT_RST_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff); + self.w + } + } + impl R { + #[doc = "Bits 0:31 - cnt_rst"] + #[inline(always)] + pub fn cnt_rst(&self) -> CNT_RST_R { + CNT_RST_R::new((self.bits & 0xffff_ffff) as u32) + } + } + impl W { + #[doc = "Bits 0:31 - cnt_rst"] + #[inline(always)] + pub fn cnt_rst(&mut self) -> CNT_RST_W { + CNT_RST_W { w: self } + } + } + } + #[doc = "Component Parameters Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_param_1](comp_param_1) module"] + pub type COMP_PARAM_1 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMP_PARAM_1; + #[doc = "`read()` method returns [comp_param_1::R](comp_param_1::R) reader structure"] + impl crate::Readable for COMP_PARAM_1 {} + #[doc = "`write(|w| ..)` method takes [comp_param_1::W](comp_param_1::W) writer structure"] + impl crate::Writable for COMP_PARAM_1 {} + #[doc = "Component Parameters Register 1"] + pub mod comp_param_1 { + #[doc = "Reader of register comp_param_1"] + pub type R = crate::R; + #[doc = "Writer for register comp_param_1"] + pub type W = crate::W; + #[doc = "Register comp_param_1 `reset()`'s with value 0"] + impl crate::ResetValue for super::COMP_PARAM_1 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `always_en`"] + pub type ALWAYS_EN_R = crate::R; + #[doc = "Write proxy for field `always_en`"] + pub struct ALWAYS_EN_W<'a> { + w: &'a mut W, + } + impl<'a> ALWAYS_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `dflt_rmod`"] + pub type DFLT_RMOD_R = crate::R; + #[doc = "Write proxy for field `dflt_rmod`"] + pub struct DFLT_RMOD_W<'a> { + w: &'a mut W, + } + impl<'a> DFLT_RMOD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `dual_top`"] + pub type DUAL_TOP_R = crate::R; + #[doc = "Write proxy for field `dual_top`"] + pub struct DUAL_TOP_W<'a> { + w: &'a mut W, + } + impl<'a> DUAL_TOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `hc_rmod`"] + pub type HC_RMOD_R = crate::R; + #[doc = "Write proxy for field `hc_rmod`"] + pub struct HC_RMOD_W<'a> { + w: &'a mut W, + } + impl<'a> HC_RMOD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `hc_rpl`"] + pub type HC_RPL_R = crate::R; + #[doc = "Write proxy for field `hc_rpl`"] + pub struct HC_RPL_W<'a> { + w: &'a mut W, + } + impl<'a> HC_RPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `hc_top`"] + pub type HC_TOP_R = crate::R; + #[doc = "Write proxy for field `hc_top`"] + pub struct HC_TOP_W<'a> { + w: &'a mut W, + } + impl<'a> HC_TOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `use_fix_top`"] + pub type USE_FIX_TOP_R = crate::R; + #[doc = "Write proxy for field `use_fix_top`"] + pub struct USE_FIX_TOP_W<'a> { + w: &'a mut W, + } + impl<'a> USE_FIX_TOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `pause`"] + pub type PAUSE_R = crate::R; + #[doc = "Write proxy for field `pause`"] + pub struct PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `apb_data_width`"] + pub type APB_DATA_WIDTH_R = crate::R; + #[doc = "Write proxy for field `apb_data_width`"] + pub struct APB_DATA_WIDTH_W<'a> { + w: &'a mut W, + } + impl<'a> APB_DATA_WIDTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8); + self.w + } + } + #[doc = "Reader of field `dflt_rpl`"] + pub type DFLT_RPL_R = crate::R; + #[doc = "Write proxy for field `dflt_rpl`"] + pub struct DFLT_RPL_W<'a> { + w: &'a mut W, + } + impl<'a> DFLT_RPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 10)) | (((value as u32) & 0x07) << 10); + self.w + } + } + #[doc = "Reader of field `dflt_top`"] + pub type DFLT_TOP_R = crate::R; + #[doc = "Write proxy for field `dflt_top`"] + pub struct DFLT_TOP_W<'a> { + w: &'a mut W, + } + impl<'a> DFLT_TOP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16); + self.w + } + } + #[doc = "Reader of field `dflt_top_init`"] + pub type DFLT_TOP_INIT_R = crate::R; + #[doc = "Write proxy for field `dflt_top_init`"] + pub struct DFLT_TOP_INIT_W<'a> { + w: &'a mut W, + } + impl<'a> DFLT_TOP_INIT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 20)) | (((value as u32) & 0x0f) << 20); + self.w + } + } + #[doc = "Reader of field `cnt_width`"] + pub type CNT_WIDTH_R = crate::R; + #[doc = "Write proxy for field `cnt_width`"] + pub struct CNT_WIDTH_W<'a> { + w: &'a mut W, + } + impl<'a> CNT_WIDTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24); + self.w + } + } + impl R { + #[doc = "Bit 0 - always_en"] + #[inline(always)] + pub fn always_en(&self) -> ALWAYS_EN_R { + ALWAYS_EN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - dflt_rmod"] + #[inline(always)] + pub fn dflt_rmod(&self) -> DFLT_RMOD_R { + DFLT_RMOD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - dual_top"] + #[inline(always)] + pub fn dual_top(&self) -> DUAL_TOP_R { + DUAL_TOP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - hc_rmod"] + #[inline(always)] + pub fn hc_rmod(&self) -> HC_RMOD_R { + HC_RMOD_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - hc_rpl"] + #[inline(always)] + pub fn hc_rpl(&self) -> HC_RPL_R { + HC_RPL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - hc_top"] + #[inline(always)] + pub fn hc_top(&self) -> HC_TOP_R { + HC_TOP_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - use_fix_top"] + #[inline(always)] + pub fn use_fix_top(&self) -> USE_FIX_TOP_R { + USE_FIX_TOP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - pause"] + #[inline(always)] + pub fn pause(&self) -> PAUSE_R { + PAUSE_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - apb_data_width"] + #[inline(always)] + pub fn apb_data_width(&self) -> APB_DATA_WIDTH_R { + APB_DATA_WIDTH_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:12 - dflt_rpl"] + #[inline(always)] + pub fn dflt_rpl(&self) -> DFLT_RPL_R { + DFLT_RPL_R::new(((self.bits >> 10) & 0x07) as u8) + } + #[doc = "Bits 16:19 - dflt_top"] + #[inline(always)] + pub fn dflt_top(&self) -> DFLT_TOP_R { + DFLT_TOP_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - dflt_top_init"] + #[inline(always)] + pub fn dflt_top_init(&self) -> DFLT_TOP_INIT_R { + DFLT_TOP_INIT_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:28 - cnt_width"] + #[inline(always)] + pub fn cnt_width(&self) -> CNT_WIDTH_R { + CNT_WIDTH_R::new(((self.bits >> 24) & 0x1f) as u8) + } + } + impl W { + #[doc = "Bit 0 - always_en"] + #[inline(always)] + pub fn always_en(&mut self) -> ALWAYS_EN_W { + ALWAYS_EN_W { w: self } + } + #[doc = "Bit 1 - dflt_rmod"] + #[inline(always)] + pub fn dflt_rmod(&mut self) -> DFLT_RMOD_W { + DFLT_RMOD_W { w: self } + } + #[doc = "Bit 2 - dual_top"] + #[inline(always)] + pub fn dual_top(&mut self) -> DUAL_TOP_W { + DUAL_TOP_W { w: self } + } + #[doc = "Bit 3 - hc_rmod"] + #[inline(always)] + pub fn hc_rmod(&mut self) -> HC_RMOD_W { + HC_RMOD_W { w: self } + } + #[doc = "Bit 4 - hc_rpl"] + #[inline(always)] + pub fn hc_rpl(&mut self) -> HC_RPL_W { + HC_RPL_W { w: self } + } + #[doc = "Bit 5 - hc_top"] + #[inline(always)] + pub fn hc_top(&mut self) -> HC_TOP_W { + HC_TOP_W { w: self } + } + #[doc = "Bit 6 - use_fix_top"] + #[inline(always)] + pub fn use_fix_top(&mut self) -> USE_FIX_TOP_W { + USE_FIX_TOP_W { w: self } + } + #[doc = "Bit 7 - pause"] + #[inline(always)] + pub fn pause(&mut self) -> PAUSE_W { + PAUSE_W { w: self } + } + #[doc = "Bits 8:9 - apb_data_width"] + #[inline(always)] + pub fn apb_data_width(&mut self) -> APB_DATA_WIDTH_W { + APB_DATA_WIDTH_W { w: self } + } + #[doc = "Bits 10:12 - dflt_rpl"] + #[inline(always)] + pub fn dflt_rpl(&mut self) -> DFLT_RPL_W { + DFLT_RPL_W { w: self } + } + #[doc = "Bits 16:19 - dflt_top"] + #[inline(always)] + pub fn dflt_top(&mut self) -> DFLT_TOP_W { + DFLT_TOP_W { w: self } + } + #[doc = "Bits 20:23 - dflt_top_init"] + #[inline(always)] + pub fn dflt_top_init(&mut self) -> DFLT_TOP_INIT_W { + DFLT_TOP_INIT_W { w: self } + } + #[doc = "Bits 24:28 - cnt_width"] + #[inline(always)] + pub fn cnt_width(&mut self) -> CNT_WIDTH_W { + CNT_WIDTH_W { w: self } + } + } + } + #[doc = "Component Version Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_version](comp_version) module"] + pub type COMP_VERSION = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMP_VERSION; + #[doc = "`read()` method returns [comp_version::R](comp_version::R) reader structure"] + impl crate::Readable for COMP_VERSION {} + #[doc = "`write(|w| ..)` method takes [comp_version::W](comp_version::W) writer structure"] + impl crate::Writable for COMP_VERSION {} + #[doc = "Component Version Register"] + pub mod comp_version { + #[doc = "Reader of register comp_version"] + pub type R = crate::R; + #[doc = "Writer for register comp_version"] + pub type W = crate::W; + #[doc = "Register comp_version `reset()`'s with value 0"] + impl crate::ResetValue for super::COMP_VERSION { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Component Type Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_type](comp_type) module"] + pub type COMP_TYPE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMP_TYPE; + #[doc = "`read()` method returns [comp_type::R](comp_type::R) reader structure"] + impl crate::Readable for COMP_TYPE {} + #[doc = "`write(|w| ..)` method takes [comp_type::W](comp_type::W) writer structure"] + impl crate::Writable for COMP_TYPE {} + #[doc = "Component Type Register"] + pub mod comp_type { + #[doc = "Reader of register comp_type"] + pub type R = crate::R; + #[doc = "Writer for register comp_type"] + pub type W = crate::W; + #[doc = "Register comp_type `reset()`'s with value 0"] + impl crate::ResetValue for super::COMP_TYPE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Watchdog Timer 1"] +pub struct WDT1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WDT1 {} +impl WDT1 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const wdt0::RegisterBlock { + 0x5041_0000 as *const _ + } +} +impl Deref for WDT1 { + type Target = wdt0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*WDT1::ptr() } + } +} +#[doc = "One-Time Programmable Memory Controller"] +pub struct OTP { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OTP {} +impl OTP { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const otp::RegisterBlock { + 0x5042_0000 as *const _ + } +} +impl Deref for OTP { + type Target = otp::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*OTP::ptr() } + } +} +#[doc = "One-Time Programmable Memory Controller"] +pub mod otp { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Dummy register: this peripheral is not implemented yet"] + pub dummy: DUMMY, + } + #[doc = "Dummy register: this peripheral is not implemented yet\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dummy](dummy) module"] + pub type DUMMY = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DUMMY; + #[doc = "`read()` method returns [dummy::R](dummy::R) reader structure"] + impl crate::Readable for DUMMY {} + #[doc = "`write(|w| ..)` method takes [dummy::W](dummy::W) writer structure"] + impl crate::Writable for DUMMY {} + #[doc = "Dummy register: this peripheral is not implemented yet"] + pub mod dummy { + #[doc = "Reader of register dummy"] + pub type R = crate::R; + #[doc = "Writer for register dummy"] + pub type W = crate::W; + #[doc = "Register dummy `reset()`'s with value 0"] + impl crate::ResetValue for super::DUMMY { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Digital Video Port"] +pub struct DVP { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DVP {} +impl DVP { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dvp::RegisterBlock { + 0x5043_0000 as *const _ + } +} +impl Deref for DVP { + type Target = dvp::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*DVP::ptr() } + } +} +#[doc = "Digital Video Port"] +pub mod dvp { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Config Register"] + pub dvp_cfg: DVP_CFG, + #[doc = "0x04 - R_ADDR"] + pub r_addr: R_ADDR, + #[doc = "0x08 - G_ADDR"] + pub g_addr: G_ADDR, + #[doc = "0x0c - B_ADDR"] + pub b_addr: B_ADDR, + #[doc = "0x10 - CMOS Config Register"] + pub cmos_cfg: CMOS_CFG, + #[doc = "0x14 - SCCB Config Register"] + pub sccb_cfg: SCCB_CFG, + #[doc = "0x18 - SCCB Control Register"] + pub sccb_ctl: SCCB_CTL, + #[doc = "0x1c - AXI Register"] + pub axi: AXI, + #[doc = "0x20 - STS Register"] + pub sts: STS, + #[doc = "0x24 - REVERSE"] + pub reverse: REVERSE, + #[doc = "0x28 - RGB_ADDR"] + pub rgb_addr: RGB_ADDR, + } + #[doc = "Config Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dvp_cfg](dvp_cfg) module"] + pub type DVP_CFG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DVP_CFG; + #[doc = "`read()` method returns [dvp_cfg::R](dvp_cfg::R) reader structure"] + impl crate::Readable for DVP_CFG {} + #[doc = "`write(|w| ..)` method takes [dvp_cfg::W](dvp_cfg::W) writer structure"] + impl crate::Writable for DVP_CFG {} + #[doc = "Config Register"] + pub mod dvp_cfg { + #[doc = "Reader of register dvp_cfg"] + pub type R = crate::R; + #[doc = "Writer for register dvp_cfg"] + pub type W = crate::W; + #[doc = "Register dvp_cfg `reset()`'s with value 0"] + impl crate::ResetValue for super::DVP_CFG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `start_int_enable`"] + pub type START_INT_ENABLE_R = crate::R; + #[doc = "Write proxy for field `start_int_enable`"] + pub struct START_INT_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> START_INT_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `finish_int_enable`"] + pub type FINISH_INT_ENABLE_R = crate::R; + #[doc = "Write proxy for field `finish_int_enable`"] + pub struct FINISH_INT_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> FINISH_INT_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `ai_output_enable`"] + pub type AI_OUTPUT_ENABLE_R = crate::R; + #[doc = "Write proxy for field `ai_output_enable`"] + pub struct AI_OUTPUT_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> AI_OUTPUT_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `display_output_enable`"] + pub type DISPLAY_OUTPUT_ENABLE_R = crate::R; + #[doc = "Write proxy for field `display_output_enable`"] + pub struct DISPLAY_OUTPUT_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> DISPLAY_OUTPUT_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `auto_enable`"] + pub type AUTO_ENABLE_R = crate::R; + #[doc = "Write proxy for field `auto_enable`"] + pub struct AUTO_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> AUTO_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `burst_size_4beats`"] + pub type BURST_SIZE_4BEATS_R = crate::R; + #[doc = "Write proxy for field `burst_size_4beats`"] + pub struct BURST_SIZE_4BEATS_W<'a> { + w: &'a mut W, + } + impl<'a> BURST_SIZE_4BEATS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "FORMAT\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum FORMAT_A { + #[doc = "0: RGB_FORMAT"] + RGB = 0, + #[doc = "1: YUV_FORMAT"] + YUV = 1, + #[doc = "3: Y_FORMAT"] + Y = 3, + } + impl From for u8 { + #[inline(always)] + fn from(variant: FORMAT_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `format`"] + pub type FORMAT_R = crate::R; + impl FORMAT_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(FORMAT_A::RGB), + 1 => Val(FORMAT_A::YUV), + 3 => Val(FORMAT_A::Y), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `RGB`"] + #[inline(always)] + pub fn is_rgb(&self) -> bool { + *self == FORMAT_A::RGB + } + #[doc = "Checks if the value of the field is `YUV`"] + #[inline(always)] + pub fn is_yuv(&self) -> bool { + *self == FORMAT_A::YUV + } + #[doc = "Checks if the value of the field is `Y`"] + #[inline(always)] + pub fn is_y(&self) -> bool { + *self == FORMAT_A::Y + } + } + #[doc = "Write proxy for field `format`"] + pub struct FORMAT_W<'a> { + w: &'a mut W, + } + impl<'a> FORMAT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORMAT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "RGB_FORMAT"] + #[inline(always)] + pub fn rgb(self) -> &'a mut W { + self.variant(FORMAT_A::RGB) + } + #[doc = "YUV_FORMAT"] + #[inline(always)] + pub fn yuv(self) -> &'a mut W { + self.variant(FORMAT_A::YUV) + } + #[doc = "Y_FORMAT"] + #[inline(always)] + pub fn y(self) -> &'a mut W { + self.variant(FORMAT_A::Y) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 9)) | (((value as u32) & 0x03) << 9); + self.w + } + } + #[doc = "Reader of field `href_burst_num`"] + pub type HREF_BURST_NUM_R = crate::R; + #[doc = "Write proxy for field `href_burst_num`"] + pub struct HREF_BURST_NUM_W<'a> { + w: &'a mut W, + } + impl<'a> HREF_BURST_NUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 12)) | (((value as u32) & 0xff) << 12); + self.w + } + } + #[doc = "Reader of field `line_num`"] + pub type LINE_NUM_R = crate::R; + #[doc = "Write proxy for field `line_num`"] + pub struct LINE_NUM_W<'a> { + w: &'a mut W, + } + impl<'a> LINE_NUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 20)) | (((value as u32) & 0x03ff) << 20); + self.w + } + } + impl R { + #[doc = "Bit 0 - START_INT_ENABLE"] + #[inline(always)] + pub fn start_int_enable(&self) -> START_INT_ENABLE_R { + START_INT_ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - FINISH_INT_ENABLE"] + #[inline(always)] + pub fn finish_int_enable(&self) -> FINISH_INT_ENABLE_R { + FINISH_INT_ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - AI_OUTPUT_ENABLE"] + #[inline(always)] + pub fn ai_output_enable(&self) -> AI_OUTPUT_ENABLE_R { + AI_OUTPUT_ENABLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DISPLAY_OUTPUT_ENABLE"] + #[inline(always)] + pub fn display_output_enable(&self) -> DISPLAY_OUTPUT_ENABLE_R { + DISPLAY_OUTPUT_ENABLE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - AUTO_ENABLE"] + #[inline(always)] + pub fn auto_enable(&self) -> AUTO_ENABLE_R { + AUTO_ENABLE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - BURST_SIZE_4BEATS"] + #[inline(always)] + pub fn burst_size_4beats(&self) -> BURST_SIZE_4BEATS_R { + BURST_SIZE_4BEATS_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 9:10 - FORMAT"] + #[inline(always)] + pub fn format(&self) -> FORMAT_R { + FORMAT_R::new(((self.bits >> 9) & 0x03) as u8) + } + #[doc = "Bits 12:19 - HREF_BURST_NUM"] + #[inline(always)] + pub fn href_burst_num(&self) -> HREF_BURST_NUM_R { + HREF_BURST_NUM_R::new(((self.bits >> 12) & 0xff) as u8) + } + #[doc = "Bits 20:29 - LINE_NUM"] + #[inline(always)] + pub fn line_num(&self) -> LINE_NUM_R { + LINE_NUM_R::new(((self.bits >> 20) & 0x03ff) as u16) + } + } + impl W { + #[doc = "Bit 0 - START_INT_ENABLE"] + #[inline(always)] + pub fn start_int_enable(&mut self) -> START_INT_ENABLE_W { + START_INT_ENABLE_W { w: self } + } + #[doc = "Bit 1 - FINISH_INT_ENABLE"] + #[inline(always)] + pub fn finish_int_enable(&mut self) -> FINISH_INT_ENABLE_W { + FINISH_INT_ENABLE_W { w: self } + } + #[doc = "Bit 2 - AI_OUTPUT_ENABLE"] + #[inline(always)] + pub fn ai_output_enable(&mut self) -> AI_OUTPUT_ENABLE_W { + AI_OUTPUT_ENABLE_W { w: self } + } + #[doc = "Bit 3 - DISPLAY_OUTPUT_ENABLE"] + #[inline(always)] + pub fn display_output_enable(&mut self) -> DISPLAY_OUTPUT_ENABLE_W { + DISPLAY_OUTPUT_ENABLE_W { w: self } + } + #[doc = "Bit 4 - AUTO_ENABLE"] + #[inline(always)] + pub fn auto_enable(&mut self) -> AUTO_ENABLE_W { + AUTO_ENABLE_W { w: self } + } + #[doc = "Bit 8 - BURST_SIZE_4BEATS"] + #[inline(always)] + pub fn burst_size_4beats(&mut self) -> BURST_SIZE_4BEATS_W { + BURST_SIZE_4BEATS_W { w: self } + } + #[doc = "Bits 9:10 - FORMAT"] + #[inline(always)] + pub fn format(&mut self) -> FORMAT_W { + FORMAT_W { w: self } + } + #[doc = "Bits 12:19 - HREF_BURST_NUM"] + #[inline(always)] + pub fn href_burst_num(&mut self) -> HREF_BURST_NUM_W { + HREF_BURST_NUM_W { w: self } + } + #[doc = "Bits 20:29 - LINE_NUM"] + #[inline(always)] + pub fn line_num(&mut self) -> LINE_NUM_W { + LINE_NUM_W { w: self } + } + } + } + #[doc = "R_ADDR\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r_addr](r_addr) module"] + pub type R_ADDR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _R_ADDR; + #[doc = "`read()` method returns [r_addr::R](r_addr::R) reader structure"] + impl crate::Readable for R_ADDR {} + #[doc = "`write(|w| ..)` method takes [r_addr::W](r_addr::W) writer structure"] + impl crate::Writable for R_ADDR {} + #[doc = "R_ADDR"] + pub mod r_addr { + #[doc = "Reader of register r_addr"] + pub type R = crate::R; + #[doc = "Writer for register r_addr"] + pub type W = crate::W; + #[doc = "Register r_addr `reset()`'s with value 0"] + impl crate::ResetValue for super::R_ADDR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "G_ADDR\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [g_addr](g_addr) module"] + pub type G_ADDR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _G_ADDR; + #[doc = "`read()` method returns [g_addr::R](g_addr::R) reader structure"] + impl crate::Readable for G_ADDR {} + #[doc = "`write(|w| ..)` method takes [g_addr::W](g_addr::W) writer structure"] + impl crate::Writable for G_ADDR {} + #[doc = "G_ADDR"] + pub mod g_addr { + #[doc = "Reader of register g_addr"] + pub type R = crate::R; + #[doc = "Writer for register g_addr"] + pub type W = crate::W; + #[doc = "Register g_addr `reset()`'s with value 0"] + impl crate::ResetValue for super::G_ADDR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "B_ADDR\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [b_addr](b_addr) module"] + pub type B_ADDR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _B_ADDR; + #[doc = "`read()` method returns [b_addr::R](b_addr::R) reader structure"] + impl crate::Readable for B_ADDR {} + #[doc = "`write(|w| ..)` method takes [b_addr::W](b_addr::W) writer structure"] + impl crate::Writable for B_ADDR {} + #[doc = "B_ADDR"] + pub mod b_addr { + #[doc = "Reader of register b_addr"] + pub type R = crate::R; + #[doc = "Writer for register b_addr"] + pub type W = crate::W; + #[doc = "Register b_addr `reset()`'s with value 0"] + impl crate::ResetValue for super::B_ADDR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "CMOS Config Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmos_cfg](cmos_cfg) module"] + pub type CMOS_CFG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CMOS_CFG; + #[doc = "`read()` method returns [cmos_cfg::R](cmos_cfg::R) reader structure"] + impl crate::Readable for CMOS_CFG {} + #[doc = "`write(|w| ..)` method takes [cmos_cfg::W](cmos_cfg::W) writer structure"] + impl crate::Writable for CMOS_CFG {} + #[doc = "CMOS Config Register"] + pub mod cmos_cfg { + #[doc = "Reader of register cmos_cfg"] + pub type R = crate::R; + #[doc = "Writer for register cmos_cfg"] + pub type W = crate::W; + #[doc = "Register cmos_cfg `reset()`'s with value 0"] + impl crate::ResetValue for super::CMOS_CFG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `clk_div`"] + pub type CLK_DIV_R = crate::R; + #[doc = "Write proxy for field `clk_div`"] + pub struct CLK_DIV_W<'a> { + w: &'a mut W, + } + impl<'a> CLK_DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + #[doc = "Reader of field `clk_enable`"] + pub type CLK_ENABLE_R = crate::R; + #[doc = "Write proxy for field `clk_enable`"] + pub struct CLK_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> CLK_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `reset`"] + pub type RESET_R = crate::R; + #[doc = "Write proxy for field `reset`"] + pub struct RESET_W<'a> { + w: &'a mut W, + } + impl<'a> RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); + self.w + } + } + #[doc = "Reader of field `power_down`"] + pub type POWER_DOWN_R = crate::R; + #[doc = "Write proxy for field `power_down`"] + pub struct POWER_DOWN_W<'a> { + w: &'a mut W, + } + impl<'a> POWER_DOWN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); + self.w + } + } + impl R { + #[doc = "Bits 0:7 - CLK_DIV"] + #[inline(always)] + pub fn clk_div(&self) -> CLK_DIV_R { + CLK_DIV_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - CLK_ENABLE"] + #[inline(always)] + pub fn clk_enable(&self) -> CLK_ENABLE_R { + CLK_ENABLE_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 16 - RESET"] + #[inline(always)] + pub fn reset(&self) -> RESET_R { + RESET_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 24 - POWER_DOWN"] + #[inline(always)] + pub fn power_down(&self) -> POWER_DOWN_R { + POWER_DOWN_R::new(((self.bits >> 24) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:7 - CLK_DIV"] + #[inline(always)] + pub fn clk_div(&mut self) -> CLK_DIV_W { + CLK_DIV_W { w: self } + } + #[doc = "Bit 8 - CLK_ENABLE"] + #[inline(always)] + pub fn clk_enable(&mut self) -> CLK_ENABLE_W { + CLK_ENABLE_W { w: self } + } + #[doc = "Bit 16 - RESET"] + #[inline(always)] + pub fn reset(&mut self) -> RESET_W { + RESET_W { w: self } + } + #[doc = "Bit 24 - POWER_DOWN"] + #[inline(always)] + pub fn power_down(&mut self) -> POWER_DOWN_W { + POWER_DOWN_W { w: self } + } + } + } + #[doc = "SCCB Config Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sccb_cfg](sccb_cfg) module"] + pub type SCCB_CFG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SCCB_CFG; + #[doc = "`read()` method returns [sccb_cfg::R](sccb_cfg::R) reader structure"] + impl crate::Readable for SCCB_CFG {} + #[doc = "`write(|w| ..)` method takes [sccb_cfg::W](sccb_cfg::W) writer structure"] + impl crate::Writable for SCCB_CFG {} + #[doc = "SCCB Config Register"] + pub mod sccb_cfg { + #[doc = "Reader of register sccb_cfg"] + pub type R = crate::R; + #[doc = "Writer for register sccb_cfg"] + pub type W = crate::W; + #[doc = "Register sccb_cfg `reset()`'s with value 0"] + impl crate::ResetValue for super::SCCB_CFG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "BYTE_NUM\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum BYTE_NUM_A { + #[doc = "1: BYTE_NUM_2"] + NUM2 = 1, + #[doc = "2: BYTE_NUM_3"] + NUM3 = 2, + #[doc = "3: BYTE_NUM_4"] + NUM4 = 3, + } + impl From for u8 { + #[inline(always)] + fn from(variant: BYTE_NUM_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `byte_num`"] + pub type BYTE_NUM_R = crate::R; + impl BYTE_NUM_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 1 => Val(BYTE_NUM_A::NUM2), + 2 => Val(BYTE_NUM_A::NUM3), + 3 => Val(BYTE_NUM_A::NUM4), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `NUM2`"] + #[inline(always)] + pub fn is_num2(&self) -> bool { + *self == BYTE_NUM_A::NUM2 + } + #[doc = "Checks if the value of the field is `NUM3`"] + #[inline(always)] + pub fn is_num3(&self) -> bool { + *self == BYTE_NUM_A::NUM3 + } + #[doc = "Checks if the value of the field is `NUM4`"] + #[inline(always)] + pub fn is_num4(&self) -> bool { + *self == BYTE_NUM_A::NUM4 + } + } + #[doc = "Write proxy for field `byte_num`"] + pub struct BYTE_NUM_W<'a> { + w: &'a mut W, + } + impl<'a> BYTE_NUM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BYTE_NUM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "BYTE_NUM_2"] + #[inline(always)] + pub fn num2(self) -> &'a mut W { + self.variant(BYTE_NUM_A::NUM2) + } + #[doc = "BYTE_NUM_3"] + #[inline(always)] + pub fn num3(self) -> &'a mut W { + self.variant(BYTE_NUM_A::NUM3) + } + #[doc = "BYTE_NUM_4"] + #[inline(always)] + pub fn num4(self) -> &'a mut W { + self.variant(BYTE_NUM_A::NUM4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03); + self.w + } + } + #[doc = "Reader of field `scl_lcnt`"] + pub type SCL_LCNT_R = crate::R; + #[doc = "Write proxy for field `scl_lcnt`"] + pub struct SCL_LCNT_W<'a> { + w: &'a mut W, + } + impl<'a> SCL_LCNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8); + self.w + } + } + #[doc = "Reader of field `scl_hcnt`"] + pub type SCL_HCNT_R = crate::R; + #[doc = "Write proxy for field `scl_hcnt`"] + pub struct SCL_HCNT_W<'a> { + w: &'a mut W, + } + impl<'a> SCL_HCNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16); + self.w + } + } + #[doc = "Reader of field `rdata`"] + pub type RDATA_R = crate::R; + impl R { + #[doc = "Bits 0:1 - BYTE_NUM"] + #[inline(always)] + pub fn byte_num(&self) -> BYTE_NUM_R { + BYTE_NUM_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 8:15 - SCL_LCNT"] + #[inline(always)] + pub fn scl_lcnt(&self) -> SCL_LCNT_R { + SCL_LCNT_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - SCL_HCNT"] + #[inline(always)] + pub fn scl_hcnt(&self) -> SCL_HCNT_R { + SCL_HCNT_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - RDATA"] + #[inline(always)] + pub fn rdata(&self) -> RDATA_R { + RDATA_R::new(((self.bits >> 24) & 0xff) as u8) + } + } + impl W { + #[doc = "Bits 0:1 - BYTE_NUM"] + #[inline(always)] + pub fn byte_num(&mut self) -> BYTE_NUM_W { + BYTE_NUM_W { w: self } + } + #[doc = "Bits 8:15 - SCL_LCNT"] + #[inline(always)] + pub fn scl_lcnt(&mut self) -> SCL_LCNT_W { + SCL_LCNT_W { w: self } + } + #[doc = "Bits 16:23 - SCL_HCNT"] + #[inline(always)] + pub fn scl_hcnt(&mut self) -> SCL_HCNT_W { + SCL_HCNT_W { w: self } + } + } + } + #[doc = "SCCB Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sccb_ctl](sccb_ctl) module"] + pub type SCCB_CTL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SCCB_CTL; + #[doc = "`read()` method returns [sccb_ctl::R](sccb_ctl::R) reader structure"] + impl crate::Readable for SCCB_CTL {} + #[doc = "`write(|w| ..)` method takes [sccb_ctl::W](sccb_ctl::W) writer structure"] + impl crate::Writable for SCCB_CTL {} + #[doc = "SCCB Control Register"] + pub mod sccb_ctl { + #[doc = "Reader of register sccb_ctl"] + pub type R = crate::R; + #[doc = "Writer for register sccb_ctl"] + pub type W = crate::W; + #[doc = "Register sccb_ctl `reset()`'s with value 0"] + impl crate::ResetValue for super::SCCB_CTL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `device_address`"] + pub type DEVICE_ADDRESS_R = crate::R; + #[doc = "Write proxy for field `device_address`"] + pub struct DEVICE_ADDRESS_W<'a> { + w: &'a mut W, + } + impl<'a> DEVICE_ADDRESS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + #[doc = "Reader of field `reg_address`"] + pub type REG_ADDRESS_R = crate::R; + #[doc = "Write proxy for field `reg_address`"] + pub struct REG_ADDRESS_W<'a> { + w: &'a mut W, + } + impl<'a> REG_ADDRESS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8); + self.w + } + } + #[doc = "Reader of field `wdata_byte0`"] + pub type WDATA_BYTE0_R = crate::R; + #[doc = "Write proxy for field `wdata_byte0`"] + pub struct WDATA_BYTE0_W<'a> { + w: &'a mut W, + } + impl<'a> WDATA_BYTE0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16); + self.w + } + } + #[doc = "Reader of field `wdata_byte1`"] + pub type WDATA_BYTE1_R = crate::R; + #[doc = "Write proxy for field `wdata_byte1`"] + pub struct WDATA_BYTE1_W<'a> { + w: &'a mut W, + } + impl<'a> WDATA_BYTE1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | (((value as u32) & 0xff) << 24); + self.w + } + } + impl R { + #[doc = "Bits 0:7 - DEVICE_ADDRESS"] + #[inline(always)] + pub fn device_address(&self) -> DEVICE_ADDRESS_R { + DEVICE_ADDRESS_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - REG_ADDRESS"] + #[inline(always)] + pub fn reg_address(&self) -> REG_ADDRESS_R { + REG_ADDRESS_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - WDATA_BYTE0"] + #[inline(always)] + pub fn wdata_byte0(&self) -> WDATA_BYTE0_R { + WDATA_BYTE0_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - WDATA_BYTE1"] + #[inline(always)] + pub fn wdata_byte1(&self) -> WDATA_BYTE1_R { + WDATA_BYTE1_R::new(((self.bits >> 24) & 0xff) as u8) + } + } + impl W { + #[doc = "Bits 0:7 - DEVICE_ADDRESS"] + #[inline(always)] + pub fn device_address(&mut self) -> DEVICE_ADDRESS_W { + DEVICE_ADDRESS_W { w: self } + } + #[doc = "Bits 8:15 - REG_ADDRESS"] + #[inline(always)] + pub fn reg_address(&mut self) -> REG_ADDRESS_W { + REG_ADDRESS_W { w: self } + } + #[doc = "Bits 16:23 - WDATA_BYTE0"] + #[inline(always)] + pub fn wdata_byte0(&mut self) -> WDATA_BYTE0_W { + WDATA_BYTE0_W { w: self } + } + #[doc = "Bits 24:31 - WDATA_BYTE1"] + #[inline(always)] + pub fn wdata_byte1(&mut self) -> WDATA_BYTE1_W { + WDATA_BYTE1_W { w: self } + } + } + } + #[doc = "AXI Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [axi](axi) module"] + pub type AXI = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _AXI; + #[doc = "`read()` method returns [axi::R](axi::R) reader structure"] + impl crate::Readable for AXI {} + #[doc = "`write(|w| ..)` method takes [axi::W](axi::W) writer structure"] + impl crate::Writable for AXI {} + #[doc = "AXI Register"] + pub mod axi { + #[doc = "Reader of register axi"] + pub type R = crate::R; + #[doc = "Writer for register axi"] + pub type W = crate::W; + #[doc = "Register axi `reset()`'s with value 0"] + impl crate::ResetValue for super::AXI { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "GM_MLEN\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum GM_MLEN_A { + #[doc = "0: GM_MLEN_1BYTE"] + BYTE1 = 0, + #[doc = "3: GM_MLEN_4BYTE"] + BYTE4 = 3, + } + impl From for u8 { + #[inline(always)] + fn from(variant: GM_MLEN_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `gm_mlen`"] + pub type GM_MLEN_R = crate::R; + impl GM_MLEN_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(GM_MLEN_A::BYTE1), + 3 => Val(GM_MLEN_A::BYTE4), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `BYTE1`"] + #[inline(always)] + pub fn is_byte1(&self) -> bool { + *self == GM_MLEN_A::BYTE1 + } + #[doc = "Checks if the value of the field is `BYTE4`"] + #[inline(always)] + pub fn is_byte4(&self) -> bool { + *self == GM_MLEN_A::BYTE4 + } + } + #[doc = "Write proxy for field `gm_mlen`"] + pub struct GM_MLEN_W<'a> { + w: &'a mut W, + } + impl<'a> GM_MLEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GM_MLEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "GM_MLEN_1BYTE"] + #[inline(always)] + pub fn byte1(self) -> &'a mut W { + self.variant(GM_MLEN_A::BYTE1) + } + #[doc = "GM_MLEN_4BYTE"] + #[inline(always)] + pub fn byte4(self) -> &'a mut W { + self.variant(GM_MLEN_A::BYTE4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + impl R { + #[doc = "Bits 0:7 - GM_MLEN"] + #[inline(always)] + pub fn gm_mlen(&self) -> GM_MLEN_R { + GM_MLEN_R::new((self.bits & 0xff) as u8) + } + } + impl W { + #[doc = "Bits 0:7 - GM_MLEN"] + #[inline(always)] + pub fn gm_mlen(&mut self) -> GM_MLEN_W { + GM_MLEN_W { w: self } + } + } + } + #[doc = "STS Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sts](sts) module"] + pub type STS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _STS; + #[doc = "`read()` method returns [sts::R](sts::R) reader structure"] + impl crate::Readable for STS {} + #[doc = "`write(|w| ..)` method takes [sts::W](sts::W) writer structure"] + impl crate::Writable for STS {} + #[doc = "STS Register"] + pub mod sts { + #[doc = "Reader of register sts"] + pub type R = crate::R; + #[doc = "Writer for register sts"] + pub type W = crate::W; + #[doc = "Register sts `reset()`'s with value 0"] + impl crate::ResetValue for super::STS { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `frame_start`"] + pub type FRAME_START_R = crate::R; + #[doc = "Write proxy for field `frame_start`"] + pub struct FRAME_START_W<'a> { + w: &'a mut W, + } + impl<'a> FRAME_START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `frame_start_we`"] + pub type FRAME_START_WE_R = crate::R; + #[doc = "Write proxy for field `frame_start_we`"] + pub struct FRAME_START_WE_W<'a> { + w: &'a mut W, + } + impl<'a> FRAME_START_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `frame_finish`"] + pub type FRAME_FINISH_R = crate::R; + #[doc = "Write proxy for field `frame_finish`"] + pub struct FRAME_FINISH_W<'a> { + w: &'a mut W, + } + impl<'a> FRAME_FINISH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `frame_finish_we`"] + pub type FRAME_FINISH_WE_R = crate::R; + #[doc = "Write proxy for field `frame_finish_we`"] + pub struct FRAME_FINISH_WE_W<'a> { + w: &'a mut W, + } + impl<'a> FRAME_FINISH_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `dvp_en`"] + pub type DVP_EN_R = crate::R; + #[doc = "Write proxy for field `dvp_en`"] + pub struct DVP_EN_W<'a> { + w: &'a mut W, + } + impl<'a> DVP_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); + self.w + } + } + #[doc = "Reader of field `dvp_en_we`"] + pub type DVP_EN_WE_R = crate::R; + #[doc = "Write proxy for field `dvp_en_we`"] + pub struct DVP_EN_WE_W<'a> { + w: &'a mut W, + } + impl<'a> DVP_EN_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17); + self.w + } + } + #[doc = "Reader of field `sccb_en`"] + pub type SCCB_EN_R = crate::R; + #[doc = "Write proxy for field `sccb_en`"] + pub struct SCCB_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SCCB_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); + self.w + } + } + #[doc = "Reader of field `sccb_en_we`"] + pub type SCCB_EN_WE_R = crate::R; + #[doc = "Write proxy for field `sccb_en_we`"] + pub struct SCCB_EN_WE_W<'a> { + w: &'a mut W, + } + impl<'a> SCCB_EN_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25); + self.w + } + } + impl R { + #[doc = "Bit 0 - FRAME_START"] + #[inline(always)] + pub fn frame_start(&self) -> FRAME_START_R { + FRAME_START_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - FRAME_START_WE"] + #[inline(always)] + pub fn frame_start_we(&self) -> FRAME_START_WE_R { + FRAME_START_WE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 8 - FRAME_FINISH"] + #[inline(always)] + pub fn frame_finish(&self) -> FRAME_FINISH_R { + FRAME_FINISH_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - FRAME_FINISH_WE"] + #[inline(always)] + pub fn frame_finish_we(&self) -> FRAME_FINISH_WE_R { + FRAME_FINISH_WE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 16 - DVP_EN"] + #[inline(always)] + pub fn dvp_en(&self) -> DVP_EN_R { + DVP_EN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - DVP_EN_WE"] + #[inline(always)] + pub fn dvp_en_we(&self) -> DVP_EN_WE_R { + DVP_EN_WE_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 24 - SCCB_EN"] + #[inline(always)] + pub fn sccb_en(&self) -> SCCB_EN_R { + SCCB_EN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - SCCB_EN_WE"] + #[inline(always)] + pub fn sccb_en_we(&self) -> SCCB_EN_WE_R { + SCCB_EN_WE_R::new(((self.bits >> 25) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - FRAME_START"] + #[inline(always)] + pub fn frame_start(&mut self) -> FRAME_START_W { + FRAME_START_W { w: self } + } + #[doc = "Bit 1 - FRAME_START_WE"] + #[inline(always)] + pub fn frame_start_we(&mut self) -> FRAME_START_WE_W { + FRAME_START_WE_W { w: self } + } + #[doc = "Bit 8 - FRAME_FINISH"] + #[inline(always)] + pub fn frame_finish(&mut self) -> FRAME_FINISH_W { + FRAME_FINISH_W { w: self } + } + #[doc = "Bit 9 - FRAME_FINISH_WE"] + #[inline(always)] + pub fn frame_finish_we(&mut self) -> FRAME_FINISH_WE_W { + FRAME_FINISH_WE_W { w: self } + } + #[doc = "Bit 16 - DVP_EN"] + #[inline(always)] + pub fn dvp_en(&mut self) -> DVP_EN_W { + DVP_EN_W { w: self } + } + #[doc = "Bit 17 - DVP_EN_WE"] + #[inline(always)] + pub fn dvp_en_we(&mut self) -> DVP_EN_WE_W { + DVP_EN_WE_W { w: self } + } + #[doc = "Bit 24 - SCCB_EN"] + #[inline(always)] + pub fn sccb_en(&mut self) -> SCCB_EN_W { + SCCB_EN_W { w: self } + } + #[doc = "Bit 25 - SCCB_EN_WE"] + #[inline(always)] + pub fn sccb_en_we(&mut self) -> SCCB_EN_WE_W { + SCCB_EN_WE_W { w: self } + } + } + } + #[doc = "REVERSE\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [reverse](reverse) module"] + pub type REVERSE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _REVERSE; + #[doc = "`read()` method returns [reverse::R](reverse::R) reader structure"] + impl crate::Readable for REVERSE {} + #[doc = "`write(|w| ..)` method takes [reverse::W](reverse::W) writer structure"] + impl crate::Writable for REVERSE {} + #[doc = "REVERSE"] + pub mod reverse { + #[doc = "Reader of register reverse"] + pub type R = crate::R; + #[doc = "Writer for register reverse"] + pub type W = crate::W; + #[doc = "Register reverse `reset()`'s with value 0"] + impl crate::ResetValue for super::REVERSE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "RGB_ADDR\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rgb_addr](rgb_addr) module"] + pub type RGB_ADDR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RGB_ADDR; + #[doc = "`read()` method returns [rgb_addr::R](rgb_addr::R) reader structure"] + impl crate::Readable for RGB_ADDR {} + #[doc = "`write(|w| ..)` method takes [rgb_addr::W](rgb_addr::W) writer structure"] + impl crate::Writable for RGB_ADDR {} + #[doc = "RGB_ADDR"] + pub mod rgb_addr { + #[doc = "Reader of register rgb_addr"] + pub type R = crate::R; + #[doc = "Writer for register rgb_addr"] + pub type W = crate::W; + #[doc = "Register rgb_addr `reset()`'s with value 0"] + impl crate::ResetValue for super::RGB_ADDR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "System Controller"] +pub struct SYSCTL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSCTL {} +impl SYSCTL { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sysctl::RegisterBlock { + 0x5044_0000 as *const _ + } +} +impl Deref for SYSCTL { + type Target = sysctl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*SYSCTL::ptr() } + } +} +#[doc = "System Controller"] +pub mod sysctl { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Git short commit id"] + pub git_id: GIT_ID, + #[doc = "0x04 - System clock base frequency"] + pub clk_freq: CLK_FREQ, + #[doc = "0x08 - PLL0 controller"] + pub pll0: PLL0, + #[doc = "0x0c - PLL1 controller"] + pub pll1: PLL1, + #[doc = "0x10 - PLL2 controller"] + pub pll2: PLL2, + _reserved5: [u8; 4usize], + #[doc = "0x18 - PLL lock tester"] + pub pll_lock: PLL_LOCK, + #[doc = "0x1c - AXI ROM detector"] + pub rom_error: ROM_ERROR, + #[doc = "0x20 - Clock select controller 0"] + pub clk_sel0: CLK_SEL0, + #[doc = "0x24 - Clock select controller 1"] + pub clk_sel1: CLK_SEL1, + #[doc = "0x28 - Central clock enable"] + pub clk_en_cent: CLK_EN_CENT, + #[doc = "0x2c - Peripheral clock enable"] + pub clk_en_peri: CLK_EN_PERI, + #[doc = "0x30 - Soft reset ctrl"] + pub soft_reset: SOFT_RESET, + #[doc = "0x34 - Peripheral reset controller"] + pub peri_reset: PERI_RESET, + #[doc = "0x38 - Clock threshold controller 0"] + pub clk_th0: CLK_TH0, + #[doc = "0x3c - Clock threshold controller 1"] + pub clk_th1: CLK_TH1, + #[doc = "0x40 - Clock threshold controller 2"] + pub clk_th2: CLK_TH2, + #[doc = "0x44 - Clock threshold controller 3"] + pub clk_th3: CLK_TH3, + #[doc = "0x48 - Clock threshold controller 4"] + pub clk_th4: CLK_TH4, + #[doc = "0x4c - Clock threshold controller 5"] + pub clk_th5: CLK_TH5, + #[doc = "0x50 - Clock threshold controller 6"] + pub clk_th6: CLK_TH6, + #[doc = "0x54 - Miscellaneous controller"] + pub misc: MISC, + #[doc = "0x58 - Peripheral controller"] + pub peri: PERI, + #[doc = "0x5c - SPI sleep controller"] + pub spi_sleep: SPI_SLEEP, + #[doc = "0x60 - Reset source status"] + pub reset_status: RESET_STATUS, + #[doc = "0x64 - DMA handshake selector"] + pub dma_sel0: DMA_SEL0, + #[doc = "0x68 - DMA handshake selector"] + pub dma_sel1: DMA_SEL1, + #[doc = "0x6c - IO Power Mode Select controller"] + pub power_sel: POWER_SEL, + } + #[doc = "Git short commit id\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [git_id](git_id) module"] + pub type GIT_ID = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _GIT_ID; + #[doc = "`read()` method returns [git_id::R](git_id::R) reader structure"] + impl crate::Readable for GIT_ID {} + #[doc = "`write(|w| ..)` method takes [git_id::W](git_id::W) writer structure"] + impl crate::Writable for GIT_ID {} + #[doc = "Git short commit id"] + pub mod git_id { + #[doc = "Reader of register git_id"] + pub type R = crate::R; + #[doc = "Writer for register git_id"] + pub type W = crate::W; + #[doc = "Register git_id `reset()`'s with value 0"] + impl crate::ResetValue for super::GIT_ID { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "System clock base frequency\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_freq](clk_freq) module"] + pub type CLK_FREQ = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_FREQ; + #[doc = "`read()` method returns [clk_freq::R](clk_freq::R) reader structure"] + impl crate::Readable for CLK_FREQ {} + #[doc = "`write(|w| ..)` method takes [clk_freq::W](clk_freq::W) writer structure"] + impl crate::Writable for CLK_FREQ {} + #[doc = "System clock base frequency"] + pub mod clk_freq { + #[doc = "Reader of register clk_freq"] + pub type R = crate::R; + #[doc = "Writer for register clk_freq"] + pub type W = crate::W; + #[doc = "Register clk_freq `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_FREQ { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "PLL0 controller\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll0](pll0) module"] + pub type PLL0 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PLL0; + #[doc = "`read()` method returns [pll0::R](pll0::R) reader structure"] + impl crate::Readable for PLL0 {} + #[doc = "`write(|w| ..)` method takes [pll0::W](pll0::W) writer structure"] + impl crate::Writable for PLL0 {} + #[doc = "PLL0 controller"] + pub mod pll0 { + #[doc = "Reader of register pll0"] + pub type R = crate::R; + #[doc = "Writer for register pll0"] + pub type W = crate::W; + #[doc = "Register pll0 `reset()`'s with value 0"] + impl crate::ResetValue for super::PLL0 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `clkr`"] + pub type CLKR_R = crate::R; + #[doc = "Write proxy for field `clkr`"] + pub struct CLKR_W<'a> { + w: &'a mut W, + } + impl<'a> CLKR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f); + self.w + } + } + #[doc = "Reader of field `clkf`"] + pub type CLKF_R = crate::R; + #[doc = "Write proxy for field `clkf`"] + pub struct CLKF_W<'a> { + w: &'a mut W, + } + impl<'a> CLKF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 4)) | (((value as u32) & 0x3f) << 4); + self.w + } + } + #[doc = "Reader of field `clkod`"] + pub type CLKOD_R = crate::R; + #[doc = "Write proxy for field `clkod`"] + pub struct CLKOD_W<'a> { + w: &'a mut W, + } + impl<'a> CLKOD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 10)) | (((value as u32) & 0x0f) << 10); + self.w + } + } + #[doc = "Reader of field `bwadj`"] + pub type BWADJ_R = crate::R; + #[doc = "Write proxy for field `bwadj`"] + pub struct BWADJ_W<'a> { + w: &'a mut W, + } + impl<'a> BWADJ_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 14)) | (((value as u32) & 0x3f) << 14); + self.w + } + } + #[doc = "Reader of field `reset`"] + pub type RESET_R = crate::R; + #[doc = "Write proxy for field `reset`"] + pub struct RESET_W<'a> { + w: &'a mut W, + } + impl<'a> RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20); + self.w + } + } + #[doc = "Reader of field `pwrd`"] + pub type PWRD_R = crate::R; + #[doc = "Write proxy for field `pwrd`"] + pub struct PWRD_W<'a> { + w: &'a mut W, + } + impl<'a> PWRD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21); + self.w + } + } + #[doc = "Reader of field `intfb`"] + pub type INTFB_R = crate::R; + #[doc = "Write proxy for field `intfb`"] + pub struct INTFB_W<'a> { + w: &'a mut W, + } + impl<'a> INTFB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22); + self.w + } + } + #[doc = "Reader of field `bypass`"] + pub type BYPASS_R = crate::R; + #[doc = "Write proxy for field `bypass`"] + pub struct BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23); + self.w + } + } + #[doc = "Reader of field `test`"] + pub type TEST_R = crate::R; + #[doc = "Write proxy for field `test`"] + pub struct TEST_W<'a> { + w: &'a mut W, + } + impl<'a> TEST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); + self.w + } + } + #[doc = "Reader of field `out_en`"] + pub type OUT_EN_R = crate::R; + #[doc = "Write proxy for field `out_en`"] + pub struct OUT_EN_W<'a> { + w: &'a mut W, + } + impl<'a> OUT_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25); + self.w + } + } + #[doc = "Reader of field `test_en`"] + pub type TEST_EN_R = crate::R; + #[doc = "Write proxy for field `test_en`"] + pub struct TEST_EN_W<'a> { + w: &'a mut W, + } + impl<'a> TEST_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26); + self.w + } + } + impl R { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn clkr(&self) -> CLKR_R { + CLKR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:9"] + #[inline(always)] + pub fn clkf(&self) -> CLKF_R { + CLKF_R::new(((self.bits >> 4) & 0x3f) as u8) + } + #[doc = "Bits 10:13"] + #[inline(always)] + pub fn clkod(&self) -> CLKOD_R { + CLKOD_R::new(((self.bits >> 10) & 0x0f) as u8) + } + #[doc = "Bits 14:19"] + #[inline(always)] + pub fn bwadj(&self) -> BWADJ_R { + BWADJ_R::new(((self.bits >> 14) & 0x3f) as u8) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn reset(&self) -> RESET_R { + RESET_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pwrd(&self) -> PWRD_R { + PWRD_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn intfb(&self) -> INTFB_R { + INTFB_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn bypass(&self) -> BYPASS_R { + BYPASS_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn test(&self) -> TEST_R { + TEST_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn out_en(&self) -> OUT_EN_R { + OUT_EN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn test_en(&self) -> TEST_EN_R { + TEST_EN_R::new(((self.bits >> 26) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn clkr(&mut self) -> CLKR_W { + CLKR_W { w: self } + } + #[doc = "Bits 4:9"] + #[inline(always)] + pub fn clkf(&mut self) -> CLKF_W { + CLKF_W { w: self } + } + #[doc = "Bits 10:13"] + #[inline(always)] + pub fn clkod(&mut self) -> CLKOD_W { + CLKOD_W { w: self } + } + #[doc = "Bits 14:19"] + #[inline(always)] + pub fn bwadj(&mut self) -> BWADJ_W { + BWADJ_W { w: self } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn reset(&mut self) -> RESET_W { + RESET_W { w: self } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pwrd(&mut self) -> PWRD_W { + PWRD_W { w: self } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn intfb(&mut self) -> INTFB_W { + INTFB_W { w: self } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn bypass(&mut self) -> BYPASS_W { + BYPASS_W { w: self } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn test(&mut self) -> TEST_W { + TEST_W { w: self } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn out_en(&mut self) -> OUT_EN_W { + OUT_EN_W { w: self } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn test_en(&mut self) -> TEST_EN_W { + TEST_EN_W { w: self } + } + } + } + #[doc = "PLL1 controller\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll1](pll1) module"] + pub type PLL1 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PLL1; + #[doc = "`read()` method returns [pll1::R](pll1::R) reader structure"] + impl crate::Readable for PLL1 {} + #[doc = "`write(|w| ..)` method takes [pll1::W](pll1::W) writer structure"] + impl crate::Writable for PLL1 {} + #[doc = "PLL1 controller"] + pub mod pll1 { + #[doc = "Reader of register pll1"] + pub type R = crate::R; + #[doc = "Writer for register pll1"] + pub type W = crate::W; + #[doc = "Register pll1 `reset()`'s with value 0"] + impl crate::ResetValue for super::PLL1 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `clkr`"] + pub type CLKR_R = crate::R; + #[doc = "Write proxy for field `clkr`"] + pub struct CLKR_W<'a> { + w: &'a mut W, + } + impl<'a> CLKR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f); + self.w + } + } + #[doc = "Reader of field `clkf`"] + pub type CLKF_R = crate::R; + #[doc = "Write proxy for field `clkf`"] + pub struct CLKF_W<'a> { + w: &'a mut W, + } + impl<'a> CLKF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 4)) | (((value as u32) & 0x3f) << 4); + self.w + } + } + #[doc = "Reader of field `clkod`"] + pub type CLKOD_R = crate::R; + #[doc = "Write proxy for field `clkod`"] + pub struct CLKOD_W<'a> { + w: &'a mut W, + } + impl<'a> CLKOD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 10)) | (((value as u32) & 0x0f) << 10); + self.w + } + } + #[doc = "Reader of field `bwadj`"] + pub type BWADJ_R = crate::R; + #[doc = "Write proxy for field `bwadj`"] + pub struct BWADJ_W<'a> { + w: &'a mut W, + } + impl<'a> BWADJ_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 14)) | (((value as u32) & 0x3f) << 14); + self.w + } + } + #[doc = "Reader of field `reset`"] + pub type RESET_R = crate::R; + #[doc = "Write proxy for field `reset`"] + pub struct RESET_W<'a> { + w: &'a mut W, + } + impl<'a> RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20); + self.w + } + } + #[doc = "Reader of field `pwrd`"] + pub type PWRD_R = crate::R; + #[doc = "Write proxy for field `pwrd`"] + pub struct PWRD_W<'a> { + w: &'a mut W, + } + impl<'a> PWRD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21); + self.w + } + } + #[doc = "Reader of field `intfb`"] + pub type INTFB_R = crate::R; + #[doc = "Write proxy for field `intfb`"] + pub struct INTFB_W<'a> { + w: &'a mut W, + } + impl<'a> INTFB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22); + self.w + } + } + #[doc = "Reader of field `bypass`"] + pub type BYPASS_R = crate::R; + #[doc = "Write proxy for field `bypass`"] + pub struct BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23); + self.w + } + } + #[doc = "Reader of field `test`"] + pub type TEST_R = crate::R; + #[doc = "Write proxy for field `test`"] + pub struct TEST_W<'a> { + w: &'a mut W, + } + impl<'a> TEST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); + self.w + } + } + #[doc = "Reader of field `out_en`"] + pub type OUT_EN_R = crate::R; + #[doc = "Write proxy for field `out_en`"] + pub struct OUT_EN_W<'a> { + w: &'a mut W, + } + impl<'a> OUT_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25); + self.w + } + } + impl R { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn clkr(&self) -> CLKR_R { + CLKR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:9"] + #[inline(always)] + pub fn clkf(&self) -> CLKF_R { + CLKF_R::new(((self.bits >> 4) & 0x3f) as u8) + } + #[doc = "Bits 10:13"] + #[inline(always)] + pub fn clkod(&self) -> CLKOD_R { + CLKOD_R::new(((self.bits >> 10) & 0x0f) as u8) + } + #[doc = "Bits 14:19"] + #[inline(always)] + pub fn bwadj(&self) -> BWADJ_R { + BWADJ_R::new(((self.bits >> 14) & 0x3f) as u8) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn reset(&self) -> RESET_R { + RESET_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pwrd(&self) -> PWRD_R { + PWRD_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn intfb(&self) -> INTFB_R { + INTFB_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn bypass(&self) -> BYPASS_R { + BYPASS_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn test(&self) -> TEST_R { + TEST_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn out_en(&self) -> OUT_EN_R { + OUT_EN_R::new(((self.bits >> 25) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn clkr(&mut self) -> CLKR_W { + CLKR_W { w: self } + } + #[doc = "Bits 4:9"] + #[inline(always)] + pub fn clkf(&mut self) -> CLKF_W { + CLKF_W { w: self } + } + #[doc = "Bits 10:13"] + #[inline(always)] + pub fn clkod(&mut self) -> CLKOD_W { + CLKOD_W { w: self } + } + #[doc = "Bits 14:19"] + #[inline(always)] + pub fn bwadj(&mut self) -> BWADJ_W { + BWADJ_W { w: self } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn reset(&mut self) -> RESET_W { + RESET_W { w: self } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pwrd(&mut self) -> PWRD_W { + PWRD_W { w: self } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn intfb(&mut self) -> INTFB_W { + INTFB_W { w: self } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn bypass(&mut self) -> BYPASS_W { + BYPASS_W { w: self } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn test(&mut self) -> TEST_W { + TEST_W { w: self } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn out_en(&mut self) -> OUT_EN_W { + OUT_EN_W { w: self } + } + } + } + #[doc = "PLL2 controller\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll2](pll2) module"] + pub type PLL2 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PLL2; + #[doc = "`read()` method returns [pll2::R](pll2::R) reader structure"] + impl crate::Readable for PLL2 {} + #[doc = "`write(|w| ..)` method takes [pll2::W](pll2::W) writer structure"] + impl crate::Writable for PLL2 {} + #[doc = "PLL2 controller"] + pub mod pll2 { + #[doc = "Reader of register pll2"] + pub type R = crate::R; + #[doc = "Writer for register pll2"] + pub type W = crate::W; + #[doc = "Register pll2 `reset()`'s with value 0"] + impl crate::ResetValue for super::PLL2 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `clkr`"] + pub type CLKR_R = crate::R; + #[doc = "Write proxy for field `clkr`"] + pub struct CLKR_W<'a> { + w: &'a mut W, + } + impl<'a> CLKR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f); + self.w + } + } + #[doc = "Reader of field `clkf`"] + pub type CLKF_R = crate::R; + #[doc = "Write proxy for field `clkf`"] + pub struct CLKF_W<'a> { + w: &'a mut W, + } + impl<'a> CLKF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 4)) | (((value as u32) & 0x3f) << 4); + self.w + } + } + #[doc = "Reader of field `clkod`"] + pub type CLKOD_R = crate::R; + #[doc = "Write proxy for field `clkod`"] + pub struct CLKOD_W<'a> { + w: &'a mut W, + } + impl<'a> CLKOD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 10)) | (((value as u32) & 0x0f) << 10); + self.w + } + } + #[doc = "Reader of field `bwadj`"] + pub type BWADJ_R = crate::R; + #[doc = "Write proxy for field `bwadj`"] + pub struct BWADJ_W<'a> { + w: &'a mut W, + } + impl<'a> BWADJ_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 14)) | (((value as u32) & 0x3f) << 14); + self.w + } + } + #[doc = "Reader of field `reset`"] + pub type RESET_R = crate::R; + #[doc = "Write proxy for field `reset`"] + pub struct RESET_W<'a> { + w: &'a mut W, + } + impl<'a> RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20); + self.w + } + } + #[doc = "Reader of field `pwrd`"] + pub type PWRD_R = crate::R; + #[doc = "Write proxy for field `pwrd`"] + pub struct PWRD_W<'a> { + w: &'a mut W, + } + impl<'a> PWRD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21); + self.w + } + } + #[doc = "Reader of field `intfb`"] + pub type INTFB_R = crate::R; + #[doc = "Write proxy for field `intfb`"] + pub struct INTFB_W<'a> { + w: &'a mut W, + } + impl<'a> INTFB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22); + self.w + } + } + #[doc = "Reader of field `bypass`"] + pub type BYPASS_R = crate::R; + #[doc = "Write proxy for field `bypass`"] + pub struct BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23); + self.w + } + } + #[doc = "Reader of field `test`"] + pub type TEST_R = crate::R; + #[doc = "Write proxy for field `test`"] + pub struct TEST_W<'a> { + w: &'a mut W, + } + impl<'a> TEST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); + self.w + } + } + #[doc = "Reader of field `out_en`"] + pub type OUT_EN_R = crate::R; + #[doc = "Write proxy for field `out_en`"] + pub struct OUT_EN_W<'a> { + w: &'a mut W, + } + impl<'a> OUT_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25); + self.w + } + } + #[doc = "Reader of field `ckin_sel`"] + pub type CKIN_SEL_R = crate::R; + #[doc = "Write proxy for field `ckin_sel`"] + pub struct CKIN_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> CKIN_SEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 26)) | (((value as u32) & 0x03) << 26); + self.w + } + } + impl R { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn clkr(&self) -> CLKR_R { + CLKR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:9"] + #[inline(always)] + pub fn clkf(&self) -> CLKF_R { + CLKF_R::new(((self.bits >> 4) & 0x3f) as u8) + } + #[doc = "Bits 10:13"] + #[inline(always)] + pub fn clkod(&self) -> CLKOD_R { + CLKOD_R::new(((self.bits >> 10) & 0x0f) as u8) + } + #[doc = "Bits 14:19"] + #[inline(always)] + pub fn bwadj(&self) -> BWADJ_R { + BWADJ_R::new(((self.bits >> 14) & 0x3f) as u8) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn reset(&self) -> RESET_R { + RESET_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pwrd(&self) -> PWRD_R { + PWRD_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn intfb(&self) -> INTFB_R { + INTFB_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn bypass(&self) -> BYPASS_R { + BYPASS_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn test(&self) -> TEST_R { + TEST_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn out_en(&self) -> OUT_EN_R { + OUT_EN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bits 26:27"] + #[inline(always)] + pub fn ckin_sel(&self) -> CKIN_SEL_R { + CKIN_SEL_R::new(((self.bits >> 26) & 0x03) as u8) + } + } + impl W { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn clkr(&mut self) -> CLKR_W { + CLKR_W { w: self } + } + #[doc = "Bits 4:9"] + #[inline(always)] + pub fn clkf(&mut self) -> CLKF_W { + CLKF_W { w: self } + } + #[doc = "Bits 10:13"] + #[inline(always)] + pub fn clkod(&mut self) -> CLKOD_W { + CLKOD_W { w: self } + } + #[doc = "Bits 14:19"] + #[inline(always)] + pub fn bwadj(&mut self) -> BWADJ_W { + BWADJ_W { w: self } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn reset(&mut self) -> RESET_W { + RESET_W { w: self } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pwrd(&mut self) -> PWRD_W { + PWRD_W { w: self } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn intfb(&mut self) -> INTFB_W { + INTFB_W { w: self } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn bypass(&mut self) -> BYPASS_W { + BYPASS_W { w: self } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn test(&mut self) -> TEST_W { + TEST_W { w: self } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn out_en(&mut self) -> OUT_EN_W { + OUT_EN_W { w: self } + } + #[doc = "Bits 26:27"] + #[inline(always)] + pub fn ckin_sel(&mut self) -> CKIN_SEL_W { + CKIN_SEL_W { w: self } + } + } + } + #[doc = "PLL lock tester\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll_lock](pll_lock) module"] + pub type PLL_LOCK = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PLL_LOCK; + #[doc = "`read()` method returns [pll_lock::R](pll_lock::R) reader structure"] + impl crate::Readable for PLL_LOCK {} + #[doc = "`write(|w| ..)` method takes [pll_lock::W](pll_lock::W) writer structure"] + impl crate::Writable for PLL_LOCK {} + #[doc = "PLL lock tester"] + pub mod pll_lock { + #[doc = "Reader of register pll_lock"] + pub type R = crate::R; + #[doc = "Writer for register pll_lock"] + pub type W = crate::W; + #[doc = "Register pll_lock `reset()`'s with value 0"] + impl crate::ResetValue for super::PLL_LOCK { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `pll_lock0`"] + pub type PLL_LOCK0_R = crate::R; + #[doc = "Write proxy for field `pll_lock0`"] + pub struct PLL_LOCK0_W<'a> { + w: &'a mut W, + } + impl<'a> PLL_LOCK0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03); + self.w + } + } + #[doc = "Reader of field `pll_slip_clear0`"] + pub type PLL_SLIP_CLEAR0_R = crate::R; + #[doc = "Write proxy for field `pll_slip_clear0`"] + pub struct PLL_SLIP_CLEAR0_W<'a> { + w: &'a mut W, + } + impl<'a> PLL_SLIP_CLEAR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `test_clk_out0`"] + pub type TEST_CLK_OUT0_R = crate::R; + #[doc = "Write proxy for field `test_clk_out0`"] + pub struct TEST_CLK_OUT0_W<'a> { + w: &'a mut W, + } + impl<'a> TEST_CLK_OUT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `pll_lock1`"] + pub type PLL_LOCK1_R = crate::R; + #[doc = "Write proxy for field `pll_lock1`"] + pub struct PLL_LOCK1_W<'a> { + w: &'a mut W, + } + impl<'a> PLL_LOCK1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8); + self.w + } + } + #[doc = "Reader of field `pll_slip_clear1`"] + pub type PLL_SLIP_CLEAR1_R = crate::R; + #[doc = "Write proxy for field `pll_slip_clear1`"] + pub struct PLL_SLIP_CLEAR1_W<'a> { + w: &'a mut W, + } + impl<'a> PLL_SLIP_CLEAR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `test_clk_out1`"] + pub type TEST_CLK_OUT1_R = crate::R; + #[doc = "Write proxy for field `test_clk_out1`"] + pub struct TEST_CLK_OUT1_W<'a> { + w: &'a mut W, + } + impl<'a> TEST_CLK_OUT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); + self.w + } + } + #[doc = "Reader of field `pll_lock2`"] + pub type PLL_LOCK2_R = crate::R; + #[doc = "Write proxy for field `pll_lock2`"] + pub struct PLL_LOCK2_W<'a> { + w: &'a mut W, + } + impl<'a> PLL_LOCK2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16); + self.w + } + } + #[doc = "Reader of field `pll_slip_clear2`"] + pub type PLL_SLIP_CLEAR2_R = crate::R; + #[doc = "Write proxy for field `pll_slip_clear2`"] + pub struct PLL_SLIP_CLEAR2_W<'a> { + w: &'a mut W, + } + impl<'a> PLL_SLIP_CLEAR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18); + self.w + } + } + #[doc = "Reader of field `test_clk_out2`"] + pub type TEST_CLK_OUT2_R = crate::R; + #[doc = "Write proxy for field `test_clk_out2`"] + pub struct TEST_CLK_OUT2_W<'a> { + w: &'a mut W, + } + impl<'a> TEST_CLK_OUT2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19); + self.w + } + } + impl R { + #[doc = "Bits 0:1"] + #[inline(always)] + pub fn pll_lock0(&self) -> PLL_LOCK0_R { + PLL_LOCK0_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pll_slip_clear0(&self) -> PLL_SLIP_CLEAR0_R { + PLL_SLIP_CLEAR0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn test_clk_out0(&self) -> TEST_CLK_OUT0_R { + TEST_CLK_OUT0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 8:9"] + #[inline(always)] + pub fn pll_lock1(&self) -> PLL_LOCK1_R { + PLL_LOCK1_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pll_slip_clear1(&self) -> PLL_SLIP_CLEAR1_R { + PLL_SLIP_CLEAR1_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn test_clk_out1(&self) -> TEST_CLK_OUT1_R { + TEST_CLK_OUT1_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 16:17"] + #[inline(always)] + pub fn pll_lock2(&self) -> PLL_LOCK2_R { + PLL_LOCK2_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pll_slip_clear2(&self) -> PLL_SLIP_CLEAR2_R { + PLL_SLIP_CLEAR2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn test_clk_out2(&self) -> TEST_CLK_OUT2_R { + TEST_CLK_OUT2_R::new(((self.bits >> 19) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:1"] + #[inline(always)] + pub fn pll_lock0(&mut self) -> PLL_LOCK0_W { + PLL_LOCK0_W { w: self } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pll_slip_clear0(&mut self) -> PLL_SLIP_CLEAR0_W { + PLL_SLIP_CLEAR0_W { w: self } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn test_clk_out0(&mut self) -> TEST_CLK_OUT0_W { + TEST_CLK_OUT0_W { w: self } + } + #[doc = "Bits 8:9"] + #[inline(always)] + pub fn pll_lock1(&mut self) -> PLL_LOCK1_W { + PLL_LOCK1_W { w: self } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pll_slip_clear1(&mut self) -> PLL_SLIP_CLEAR1_W { + PLL_SLIP_CLEAR1_W { w: self } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn test_clk_out1(&mut self) -> TEST_CLK_OUT1_W { + TEST_CLK_OUT1_W { w: self } + } + #[doc = "Bits 16:17"] + #[inline(always)] + pub fn pll_lock2(&mut self) -> PLL_LOCK2_W { + PLL_LOCK2_W { w: self } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pll_slip_clear2(&mut self) -> PLL_SLIP_CLEAR2_W { + PLL_SLIP_CLEAR2_W { w: self } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn test_clk_out2(&mut self) -> TEST_CLK_OUT2_W { + TEST_CLK_OUT2_W { w: self } + } + } + } + #[doc = "AXI ROM detector\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rom_error](rom_error) module"] + pub type ROM_ERROR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ROM_ERROR; + #[doc = "`read()` method returns [rom_error::R](rom_error::R) reader structure"] + impl crate::Readable for ROM_ERROR {} + #[doc = "`write(|w| ..)` method takes [rom_error::W](rom_error::W) writer structure"] + impl crate::Writable for ROM_ERROR {} + #[doc = "AXI ROM detector"] + pub mod rom_error { + #[doc = "Reader of register rom_error"] + pub type R = crate::R; + #[doc = "Writer for register rom_error"] + pub type W = crate::W; + #[doc = "Register rom_error `reset()`'s with value 0"] + impl crate::ResetValue for super::ROM_ERROR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `rom_mul_error`"] + pub type ROM_MUL_ERROR_R = crate::R; + #[doc = "Write proxy for field `rom_mul_error`"] + pub struct ROM_MUL_ERROR_W<'a> { + w: &'a mut W, + } + impl<'a> ROM_MUL_ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `rom_one_error`"] + pub type ROM_ONE_ERROR_R = crate::R; + #[doc = "Write proxy for field `rom_one_error`"] + pub struct ROM_ONE_ERROR_W<'a> { + w: &'a mut W, + } + impl<'a> ROM_ONE_ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn rom_mul_error(&self) -> ROM_MUL_ERROR_R { + ROM_MUL_ERROR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn rom_one_error(&self) -> ROM_ONE_ERROR_R { + ROM_ONE_ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn rom_mul_error(&mut self) -> ROM_MUL_ERROR_W { + ROM_MUL_ERROR_W { w: self } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn rom_one_error(&mut self) -> ROM_ONE_ERROR_W { + ROM_ONE_ERROR_W { w: self } + } + } + } + #[doc = "Clock select controller 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_sel0](clk_sel0) module"] + pub type CLK_SEL0 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_SEL0; + #[doc = "`read()` method returns [clk_sel0::R](clk_sel0::R) reader structure"] + impl crate::Readable for CLK_SEL0 {} + #[doc = "`write(|w| ..)` method takes [clk_sel0::W](clk_sel0::W) writer structure"] + impl crate::Writable for CLK_SEL0 {} + #[doc = "Clock select controller 0"] + pub mod clk_sel0 { + #[doc = "Reader of register clk_sel0"] + pub type R = crate::R; + #[doc = "Writer for register clk_sel0"] + pub type W = crate::W; + #[doc = "Register clk_sel0 `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_SEL0 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `aclk_sel`"] + pub type ACLK_SEL_R = crate::R; + #[doc = "Write proxy for field `aclk_sel`"] + pub struct ACLK_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> ACLK_SEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `aclk_divider_sel`"] + pub type ACLK_DIVIDER_SEL_R = crate::R; + #[doc = "Write proxy for field `aclk_divider_sel`"] + pub struct ACLK_DIVIDER_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> ACLK_DIVIDER_SEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 1)) | (((value as u32) & 0x03) << 1); + self.w + } + } + #[doc = "Reader of field `apb0_clk_sel`"] + pub type APB0_CLK_SEL_R = crate::R; + #[doc = "Write proxy for field `apb0_clk_sel`"] + pub struct APB0_CLK_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> APB0_CLK_SEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | (((value as u32) & 0x07) << 3); + self.w + } + } + #[doc = "Reader of field `apb1_clk_sel`"] + pub type APB1_CLK_SEL_R = crate::R; + #[doc = "Write proxy for field `apb1_clk_sel`"] + pub struct APB1_CLK_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> APB1_CLK_SEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 6)) | (((value as u32) & 0x07) << 6); + self.w + } + } + #[doc = "Reader of field `apb2_clk_sel`"] + pub type APB2_CLK_SEL_R = crate::R; + #[doc = "Write proxy for field `apb2_clk_sel`"] + pub struct APB2_CLK_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> APB2_CLK_SEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 9)) | (((value as u32) & 0x07) << 9); + self.w + } + } + #[doc = "Reader of field `spi3_clk_sel`"] + pub type SPI3_CLK_SEL_R = crate::R; + #[doc = "Write proxy for field `spi3_clk_sel`"] + pub struct SPI3_CLK_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> SPI3_CLK_SEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); + self.w + } + } + #[doc = "Reader of field `timer0_clk_sel`"] + pub type TIMER0_CLK_SEL_R = crate::R; + #[doc = "Write proxy for field `timer0_clk_sel`"] + pub struct TIMER0_CLK_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER0_CLK_SEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13); + self.w + } + } + #[doc = "Reader of field `timer1_clk_sel`"] + pub type TIMER1_CLK_SEL_R = crate::R; + #[doc = "Write proxy for field `timer1_clk_sel`"] + pub struct TIMER1_CLK_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER1_CLK_SEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14); + self.w + } + } + #[doc = "Reader of field `timer2_clk_sel`"] + pub type TIMER2_CLK_SEL_R = crate::R; + #[doc = "Write proxy for field `timer2_clk_sel`"] + pub struct TIMER2_CLK_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER2_CLK_SEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); + self.w + } + } + impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn aclk_sel(&self) -> ACLK_SEL_R { + ACLK_SEL_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:2"] + #[inline(always)] + pub fn aclk_divider_sel(&self) -> ACLK_DIVIDER_SEL_R { + ACLK_DIVIDER_SEL_R::new(((self.bits >> 1) & 0x03) as u8) + } + #[doc = "Bits 3:5"] + #[inline(always)] + pub fn apb0_clk_sel(&self) -> APB0_CLK_SEL_R { + APB0_CLK_SEL_R::new(((self.bits >> 3) & 0x07) as u8) + } + #[doc = "Bits 6:8"] + #[inline(always)] + pub fn apb1_clk_sel(&self) -> APB1_CLK_SEL_R { + APB1_CLK_SEL_R::new(((self.bits >> 6) & 0x07) as u8) + } + #[doc = "Bits 9:11"] + #[inline(always)] + pub fn apb2_clk_sel(&self) -> APB2_CLK_SEL_R { + APB2_CLK_SEL_R::new(((self.bits >> 9) & 0x07) as u8) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn spi3_clk_sel(&self) -> SPI3_CLK_SEL_R { + SPI3_CLK_SEL_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn timer0_clk_sel(&self) -> TIMER0_CLK_SEL_R { + TIMER0_CLK_SEL_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn timer1_clk_sel(&self) -> TIMER1_CLK_SEL_R { + TIMER1_CLK_SEL_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn timer2_clk_sel(&self) -> TIMER2_CLK_SEL_R { + TIMER2_CLK_SEL_R::new(((self.bits >> 15) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn aclk_sel(&mut self) -> ACLK_SEL_W { + ACLK_SEL_W { w: self } + } + #[doc = "Bits 1:2"] + #[inline(always)] + pub fn aclk_divider_sel(&mut self) -> ACLK_DIVIDER_SEL_W { + ACLK_DIVIDER_SEL_W { w: self } + } + #[doc = "Bits 3:5"] + #[inline(always)] + pub fn apb0_clk_sel(&mut self) -> APB0_CLK_SEL_W { + APB0_CLK_SEL_W { w: self } + } + #[doc = "Bits 6:8"] + #[inline(always)] + pub fn apb1_clk_sel(&mut self) -> APB1_CLK_SEL_W { + APB1_CLK_SEL_W { w: self } + } + #[doc = "Bits 9:11"] + #[inline(always)] + pub fn apb2_clk_sel(&mut self) -> APB2_CLK_SEL_W { + APB2_CLK_SEL_W { w: self } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn spi3_clk_sel(&mut self) -> SPI3_CLK_SEL_W { + SPI3_CLK_SEL_W { w: self } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn timer0_clk_sel(&mut self) -> TIMER0_CLK_SEL_W { + TIMER0_CLK_SEL_W { w: self } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn timer1_clk_sel(&mut self) -> TIMER1_CLK_SEL_W { + TIMER1_CLK_SEL_W { w: self } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn timer2_clk_sel(&mut self) -> TIMER2_CLK_SEL_W { + TIMER2_CLK_SEL_W { w: self } + } + } + } + #[doc = "Clock select controller 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_sel1](clk_sel1) module"] + pub type CLK_SEL1 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_SEL1; + #[doc = "`read()` method returns [clk_sel1::R](clk_sel1::R) reader structure"] + impl crate::Readable for CLK_SEL1 {} + #[doc = "`write(|w| ..)` method takes [clk_sel1::W](clk_sel1::W) writer structure"] + impl crate::Writable for CLK_SEL1 {} + #[doc = "Clock select controller 1"] + pub mod clk_sel1 { + #[doc = "Reader of register clk_sel1"] + pub type R = crate::R; + #[doc = "Writer for register clk_sel1"] + pub type W = crate::W; + #[doc = "Register clk_sel1 `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_SEL1 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `spi3_sample_clk_sel`"] + pub type SPI3_SAMPLE_CLK_SEL_R = crate::R; + #[doc = "Write proxy for field `spi3_sample_clk_sel`"] + pub struct SPI3_SAMPLE_CLK_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> SPI3_SAMPLE_CLK_SEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn spi3_sample_clk_sel(&self) -> SPI3_SAMPLE_CLK_SEL_R { + SPI3_SAMPLE_CLK_SEL_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn spi3_sample_clk_sel(&mut self) -> SPI3_SAMPLE_CLK_SEL_W { + SPI3_SAMPLE_CLK_SEL_W { w: self } + } + } + } + #[doc = "Central clock enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_en_cent](clk_en_cent) module"] + pub type CLK_EN_CENT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_EN_CENT; + #[doc = "`read()` method returns [clk_en_cent::R](clk_en_cent::R) reader structure"] + impl crate::Readable for CLK_EN_CENT {} + #[doc = "`write(|w| ..)` method takes [clk_en_cent::W](clk_en_cent::W) writer structure"] + impl crate::Writable for CLK_EN_CENT {} + #[doc = "Central clock enable"] + pub mod clk_en_cent { + #[doc = "Reader of register clk_en_cent"] + pub type R = crate::R; + #[doc = "Writer for register clk_en_cent"] + pub type W = crate::W; + #[doc = "Register clk_en_cent `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_EN_CENT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `cpu_clk_en`"] + pub type CPU_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `cpu_clk_en`"] + pub struct CPU_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> CPU_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `sram0_clk_en`"] + pub type SRAM0_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `sram0_clk_en`"] + pub struct SRAM0_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SRAM0_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `sram1_clk_en`"] + pub type SRAM1_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `sram1_clk_en`"] + pub struct SRAM1_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SRAM1_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `apb0_clk_en`"] + pub type APB0_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `apb0_clk_en`"] + pub struct APB0_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> APB0_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `apb1_clk_en`"] + pub type APB1_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `apb1_clk_en`"] + pub struct APB1_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> APB1_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `apb2_clk_en`"] + pub type APB2_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `apb2_clk_en`"] + pub struct APB2_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> APB2_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn cpu_clk_en(&self) -> CPU_CLK_EN_R { + CPU_CLK_EN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn sram0_clk_en(&self) -> SRAM0_CLK_EN_R { + SRAM0_CLK_EN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn sram1_clk_en(&self) -> SRAM1_CLK_EN_R { + SRAM1_CLK_EN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn apb0_clk_en(&self) -> APB0_CLK_EN_R { + APB0_CLK_EN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn apb1_clk_en(&self) -> APB1_CLK_EN_R { + APB1_CLK_EN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn apb2_clk_en(&self) -> APB2_CLK_EN_R { + APB2_CLK_EN_R::new(((self.bits >> 5) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn cpu_clk_en(&mut self) -> CPU_CLK_EN_W { + CPU_CLK_EN_W { w: self } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn sram0_clk_en(&mut self) -> SRAM0_CLK_EN_W { + SRAM0_CLK_EN_W { w: self } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn sram1_clk_en(&mut self) -> SRAM1_CLK_EN_W { + SRAM1_CLK_EN_W { w: self } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn apb0_clk_en(&mut self) -> APB0_CLK_EN_W { + APB0_CLK_EN_W { w: self } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn apb1_clk_en(&mut self) -> APB1_CLK_EN_W { + APB1_CLK_EN_W { w: self } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn apb2_clk_en(&mut self) -> APB2_CLK_EN_W { + APB2_CLK_EN_W { w: self } + } + } + } + #[doc = "Peripheral clock enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_en_peri](clk_en_peri) module"] + pub type CLK_EN_PERI = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_EN_PERI; + #[doc = "`read()` method returns [clk_en_peri::R](clk_en_peri::R) reader structure"] + impl crate::Readable for CLK_EN_PERI {} + #[doc = "`write(|w| ..)` method takes [clk_en_peri::W](clk_en_peri::W) writer structure"] + impl crate::Writable for CLK_EN_PERI {} + #[doc = "Peripheral clock enable"] + pub mod clk_en_peri { + #[doc = "Reader of register clk_en_peri"] + pub type R = crate::R; + #[doc = "Writer for register clk_en_peri"] + pub type W = crate::W; + #[doc = "Register clk_en_peri `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_EN_PERI { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `rom_clk_en`"] + pub type ROM_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `rom_clk_en`"] + pub struct ROM_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> ROM_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `dma_clk_en`"] + pub type DMA_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `dma_clk_en`"] + pub struct DMA_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `ai_clk_en`"] + pub type AI_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `ai_clk_en`"] + pub struct AI_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> AI_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `dvp_clk_en`"] + pub type DVP_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `dvp_clk_en`"] + pub struct DVP_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> DVP_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `fft_clk_en`"] + pub type FFT_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `fft_clk_en`"] + pub struct FFT_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> FFT_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `gpio_clk_en`"] + pub type GPIO_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `gpio_clk_en`"] + pub struct GPIO_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> GPIO_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `spi0_clk_en`"] + pub type SPI0_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `spi0_clk_en`"] + pub struct SPI0_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SPI0_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `spi1_clk_en`"] + pub type SPI1_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `spi1_clk_en`"] + pub struct SPI1_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SPI1_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `spi2_clk_en`"] + pub type SPI2_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `spi2_clk_en`"] + pub struct SPI2_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SPI2_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `spi3_clk_en`"] + pub type SPI3_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `spi3_clk_en`"] + pub struct SPI3_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SPI3_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `i2s0_clk_en`"] + pub type I2S0_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `i2s0_clk_en`"] + pub struct I2S0_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> I2S0_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `i2s1_clk_en`"] + pub type I2S1_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `i2s1_clk_en`"] + pub struct I2S1_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> I2S1_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); + self.w + } + } + #[doc = "Reader of field `i2s2_clk_en`"] + pub type I2S2_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `i2s2_clk_en`"] + pub struct I2S2_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> I2S2_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); + self.w + } + } + #[doc = "Reader of field `i2c0_clk_en`"] + pub type I2C0_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `i2c0_clk_en`"] + pub struct I2C0_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> I2C0_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13); + self.w + } + } + #[doc = "Reader of field `i2c1_clk_en`"] + pub type I2C1_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `i2c1_clk_en`"] + pub struct I2C1_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> I2C1_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14); + self.w + } + } + #[doc = "Reader of field `i2c2_clk_en`"] + pub type I2C2_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `i2c2_clk_en`"] + pub struct I2C2_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> I2C2_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); + self.w + } + } + #[doc = "Reader of field `uart1_clk_en`"] + pub type UART1_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `uart1_clk_en`"] + pub struct UART1_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> UART1_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); + self.w + } + } + #[doc = "Reader of field `uart2_clk_en`"] + pub type UART2_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `uart2_clk_en`"] + pub struct UART2_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> UART2_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17); + self.w + } + } + #[doc = "Reader of field `uart3_clk_en`"] + pub type UART3_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `uart3_clk_en`"] + pub struct UART3_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> UART3_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18); + self.w + } + } + #[doc = "Reader of field `aes_clk_en`"] + pub type AES_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `aes_clk_en`"] + pub struct AES_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> AES_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19); + self.w + } + } + #[doc = "Reader of field `fpioa_clk_en`"] + pub type FPIOA_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `fpioa_clk_en`"] + pub struct FPIOA_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> FPIOA_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20); + self.w + } + } + #[doc = "Reader of field `timer0_clk_en`"] + pub type TIMER0_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `timer0_clk_en`"] + pub struct TIMER0_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER0_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21); + self.w + } + } + #[doc = "Reader of field `timer1_clk_en`"] + pub type TIMER1_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `timer1_clk_en`"] + pub struct TIMER1_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER1_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22); + self.w + } + } + #[doc = "Reader of field `timer2_clk_en`"] + pub type TIMER2_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `timer2_clk_en`"] + pub struct TIMER2_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER2_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23); + self.w + } + } + #[doc = "Reader of field `wdt0_clk_en`"] + pub type WDT0_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `wdt0_clk_en`"] + pub struct WDT0_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> WDT0_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); + self.w + } + } + #[doc = "Reader of field `wdt1_clk_en`"] + pub type WDT1_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `wdt1_clk_en`"] + pub struct WDT1_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> WDT1_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25); + self.w + } + } + #[doc = "Reader of field `sha_clk_en`"] + pub type SHA_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `sha_clk_en`"] + pub struct SHA_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SHA_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26); + self.w + } + } + #[doc = "Reader of field `otp_clk_en`"] + pub type OTP_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `otp_clk_en`"] + pub struct OTP_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> OTP_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27); + self.w + } + } + #[doc = "Reader of field `rtc_clk_en`"] + pub type RTC_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `rtc_clk_en`"] + pub struct RTC_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> RTC_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29); + self.w + } + } + impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn rom_clk_en(&self) -> ROM_CLK_EN_R { + ROM_CLK_EN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn dma_clk_en(&self) -> DMA_CLK_EN_R { + DMA_CLK_EN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ai_clk_en(&self) -> AI_CLK_EN_R { + AI_CLK_EN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn dvp_clk_en(&self) -> DVP_CLK_EN_R { + DVP_CLK_EN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn fft_clk_en(&self) -> FFT_CLK_EN_R { + FFT_CLK_EN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio_clk_en(&self) -> GPIO_CLK_EN_R { + GPIO_CLK_EN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn spi0_clk_en(&self) -> SPI0_CLK_EN_R { + SPI0_CLK_EN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn spi1_clk_en(&self) -> SPI1_CLK_EN_R { + SPI1_CLK_EN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn spi2_clk_en(&self) -> SPI2_CLK_EN_R { + SPI2_CLK_EN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn spi3_clk_en(&self) -> SPI3_CLK_EN_R { + SPI3_CLK_EN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn i2s0_clk_en(&self) -> I2S0_CLK_EN_R { + I2S0_CLK_EN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn i2s1_clk_en(&self) -> I2S1_CLK_EN_R { + I2S1_CLK_EN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn i2s2_clk_en(&self) -> I2S2_CLK_EN_R { + I2S2_CLK_EN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn i2c0_clk_en(&self) -> I2C0_CLK_EN_R { + I2C0_CLK_EN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn i2c1_clk_en(&self) -> I2C1_CLK_EN_R { + I2C1_CLK_EN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn i2c2_clk_en(&self) -> I2C2_CLK_EN_R { + I2C2_CLK_EN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn uart1_clk_en(&self) -> UART1_CLK_EN_R { + UART1_CLK_EN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn uart2_clk_en(&self) -> UART2_CLK_EN_R { + UART2_CLK_EN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn uart3_clk_en(&self) -> UART3_CLK_EN_R { + UART3_CLK_EN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn aes_clk_en(&self) -> AES_CLK_EN_R { + AES_CLK_EN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn fpioa_clk_en(&self) -> FPIOA_CLK_EN_R { + FPIOA_CLK_EN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn timer0_clk_en(&self) -> TIMER0_CLK_EN_R { + TIMER0_CLK_EN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn timer1_clk_en(&self) -> TIMER1_CLK_EN_R { + TIMER1_CLK_EN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn timer2_clk_en(&self) -> TIMER2_CLK_EN_R { + TIMER2_CLK_EN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn wdt0_clk_en(&self) -> WDT0_CLK_EN_R { + WDT0_CLK_EN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn wdt1_clk_en(&self) -> WDT1_CLK_EN_R { + WDT1_CLK_EN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn sha_clk_en(&self) -> SHA_CLK_EN_R { + SHA_CLK_EN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn otp_clk_en(&self) -> OTP_CLK_EN_R { + OTP_CLK_EN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn rtc_clk_en(&self) -> RTC_CLK_EN_R { + RTC_CLK_EN_R::new(((self.bits >> 29) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn rom_clk_en(&mut self) -> ROM_CLK_EN_W { + ROM_CLK_EN_W { w: self } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn dma_clk_en(&mut self) -> DMA_CLK_EN_W { + DMA_CLK_EN_W { w: self } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ai_clk_en(&mut self) -> AI_CLK_EN_W { + AI_CLK_EN_W { w: self } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn dvp_clk_en(&mut self) -> DVP_CLK_EN_W { + DVP_CLK_EN_W { w: self } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn fft_clk_en(&mut self) -> FFT_CLK_EN_W { + FFT_CLK_EN_W { w: self } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio_clk_en(&mut self) -> GPIO_CLK_EN_W { + GPIO_CLK_EN_W { w: self } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn spi0_clk_en(&mut self) -> SPI0_CLK_EN_W { + SPI0_CLK_EN_W { w: self } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn spi1_clk_en(&mut self) -> SPI1_CLK_EN_W { + SPI1_CLK_EN_W { w: self } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn spi2_clk_en(&mut self) -> SPI2_CLK_EN_W { + SPI2_CLK_EN_W { w: self } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn spi3_clk_en(&mut self) -> SPI3_CLK_EN_W { + SPI3_CLK_EN_W { w: self } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn i2s0_clk_en(&mut self) -> I2S0_CLK_EN_W { + I2S0_CLK_EN_W { w: self } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn i2s1_clk_en(&mut self) -> I2S1_CLK_EN_W { + I2S1_CLK_EN_W { w: self } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn i2s2_clk_en(&mut self) -> I2S2_CLK_EN_W { + I2S2_CLK_EN_W { w: self } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn i2c0_clk_en(&mut self) -> I2C0_CLK_EN_W { + I2C0_CLK_EN_W { w: self } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn i2c1_clk_en(&mut self) -> I2C1_CLK_EN_W { + I2C1_CLK_EN_W { w: self } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn i2c2_clk_en(&mut self) -> I2C2_CLK_EN_W { + I2C2_CLK_EN_W { w: self } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn uart1_clk_en(&mut self) -> UART1_CLK_EN_W { + UART1_CLK_EN_W { w: self } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn uart2_clk_en(&mut self) -> UART2_CLK_EN_W { + UART2_CLK_EN_W { w: self } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn uart3_clk_en(&mut self) -> UART3_CLK_EN_W { + UART3_CLK_EN_W { w: self } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn aes_clk_en(&mut self) -> AES_CLK_EN_W { + AES_CLK_EN_W { w: self } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn fpioa_clk_en(&mut self) -> FPIOA_CLK_EN_W { + FPIOA_CLK_EN_W { w: self } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn timer0_clk_en(&mut self) -> TIMER0_CLK_EN_W { + TIMER0_CLK_EN_W { w: self } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn timer1_clk_en(&mut self) -> TIMER1_CLK_EN_W { + TIMER1_CLK_EN_W { w: self } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn timer2_clk_en(&mut self) -> TIMER2_CLK_EN_W { + TIMER2_CLK_EN_W { w: self } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn wdt0_clk_en(&mut self) -> WDT0_CLK_EN_W { + WDT0_CLK_EN_W { w: self } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn wdt1_clk_en(&mut self) -> WDT1_CLK_EN_W { + WDT1_CLK_EN_W { w: self } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn sha_clk_en(&mut self) -> SHA_CLK_EN_W { + SHA_CLK_EN_W { w: self } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn otp_clk_en(&mut self) -> OTP_CLK_EN_W { + OTP_CLK_EN_W { w: self } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn rtc_clk_en(&mut self) -> RTC_CLK_EN_W { + RTC_CLK_EN_W { w: self } + } + } + } + #[doc = "Soft reset ctrl\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [soft_reset](soft_reset) module"] + pub type SOFT_RESET = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SOFT_RESET; + #[doc = "`read()` method returns [soft_reset::R](soft_reset::R) reader structure"] + impl crate::Readable for SOFT_RESET {} + #[doc = "`write(|w| ..)` method takes [soft_reset::W](soft_reset::W) writer structure"] + impl crate::Writable for SOFT_RESET {} + #[doc = "Soft reset ctrl"] + pub mod soft_reset { + #[doc = "Reader of register soft_reset"] + pub type R = crate::R; + #[doc = "Writer for register soft_reset"] + pub type W = crate::W; + #[doc = "Register soft_reset `reset()`'s with value 0"] + impl crate::ResetValue for super::SOFT_RESET { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `soft_reset`"] + pub type SOFT_RESET_R = crate::R; + #[doc = "Write proxy for field `soft_reset`"] + pub struct SOFT_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> SOFT_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn soft_reset(&self) -> SOFT_RESET_R { + SOFT_RESET_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn soft_reset(&mut self) -> SOFT_RESET_W { + SOFT_RESET_W { w: self } + } + } + } + #[doc = "Peripheral reset controller\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peri_reset](peri_reset) module"] + pub type PERI_RESET = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PERI_RESET; + #[doc = "`read()` method returns [peri_reset::R](peri_reset::R) reader structure"] + impl crate::Readable for PERI_RESET {} + #[doc = "`write(|w| ..)` method takes [peri_reset::W](peri_reset::W) writer structure"] + impl crate::Writable for PERI_RESET {} + #[doc = "Peripheral reset controller"] + pub mod peri_reset { + #[doc = "Reader of register peri_reset"] + pub type R = crate::R; + #[doc = "Writer for register peri_reset"] + pub type W = crate::W; + #[doc = "Register peri_reset `reset()`'s with value 0"] + impl crate::ResetValue for super::PERI_RESET { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `rom_reset`"] + pub type ROM_RESET_R = crate::R; + #[doc = "Write proxy for field `rom_reset`"] + pub struct ROM_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> ROM_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `dma_reset`"] + pub type DMA_RESET_R = crate::R; + #[doc = "Write proxy for field `dma_reset`"] + pub struct DMA_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `ai_reset`"] + pub type AI_RESET_R = crate::R; + #[doc = "Write proxy for field `ai_reset`"] + pub struct AI_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> AI_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `dvp_reset`"] + pub type DVP_RESET_R = crate::R; + #[doc = "Write proxy for field `dvp_reset`"] + pub struct DVP_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> DVP_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `fft_reset`"] + pub type FFT_RESET_R = crate::R; + #[doc = "Write proxy for field `fft_reset`"] + pub struct FFT_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> FFT_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `gpio_reset`"] + pub type GPIO_RESET_R = crate::R; + #[doc = "Write proxy for field `gpio_reset`"] + pub struct GPIO_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> GPIO_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `spi0_reset`"] + pub type SPI0_RESET_R = crate::R; + #[doc = "Write proxy for field `spi0_reset`"] + pub struct SPI0_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> SPI0_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `spi1_reset`"] + pub type SPI1_RESET_R = crate::R; + #[doc = "Write proxy for field `spi1_reset`"] + pub struct SPI1_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> SPI1_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `spi2_reset`"] + pub type SPI2_RESET_R = crate::R; + #[doc = "Write proxy for field `spi2_reset`"] + pub struct SPI2_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> SPI2_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `spi3_reset`"] + pub type SPI3_RESET_R = crate::R; + #[doc = "Write proxy for field `spi3_reset`"] + pub struct SPI3_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> SPI3_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `i2s0_reset`"] + pub type I2S0_RESET_R = crate::R; + #[doc = "Write proxy for field `i2s0_reset`"] + pub struct I2S0_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> I2S0_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `i2s1_reset`"] + pub type I2S1_RESET_R = crate::R; + #[doc = "Write proxy for field `i2s1_reset`"] + pub struct I2S1_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> I2S1_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); + self.w + } + } + #[doc = "Reader of field `i2s2_reset`"] + pub type I2S2_RESET_R = crate::R; + #[doc = "Write proxy for field `i2s2_reset`"] + pub struct I2S2_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> I2S2_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); + self.w + } + } + #[doc = "Reader of field `i2c0_reset`"] + pub type I2C0_RESET_R = crate::R; + #[doc = "Write proxy for field `i2c0_reset`"] + pub struct I2C0_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> I2C0_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13); + self.w + } + } + #[doc = "Reader of field `i2c1_reset`"] + pub type I2C1_RESET_R = crate::R; + #[doc = "Write proxy for field `i2c1_reset`"] + pub struct I2C1_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> I2C1_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14); + self.w + } + } + #[doc = "Reader of field `i2c2_reset`"] + pub type I2C2_RESET_R = crate::R; + #[doc = "Write proxy for field `i2c2_reset`"] + pub struct I2C2_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> I2C2_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); + self.w + } + } + #[doc = "Reader of field `uart1_reset`"] + pub type UART1_RESET_R = crate::R; + #[doc = "Write proxy for field `uart1_reset`"] + pub struct UART1_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> UART1_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); + self.w + } + } + #[doc = "Reader of field `uart2_reset`"] + pub type UART2_RESET_R = crate::R; + #[doc = "Write proxy for field `uart2_reset`"] + pub struct UART2_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> UART2_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17); + self.w + } + } + #[doc = "Reader of field `uart3_reset`"] + pub type UART3_RESET_R = crate::R; + #[doc = "Write proxy for field `uart3_reset`"] + pub struct UART3_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> UART3_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18); + self.w + } + } + #[doc = "Reader of field `aes_reset`"] + pub type AES_RESET_R = crate::R; + #[doc = "Write proxy for field `aes_reset`"] + pub struct AES_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> AES_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19); + self.w + } + } + #[doc = "Reader of field `fpioa_reset`"] + pub type FPIOA_RESET_R = crate::R; + #[doc = "Write proxy for field `fpioa_reset`"] + pub struct FPIOA_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> FPIOA_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20); + self.w + } + } + #[doc = "Reader of field `timer0_reset`"] + pub type TIMER0_RESET_R = crate::R; + #[doc = "Write proxy for field `timer0_reset`"] + pub struct TIMER0_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER0_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21); + self.w + } + } + #[doc = "Reader of field `timer1_reset`"] + pub type TIMER1_RESET_R = crate::R; + #[doc = "Write proxy for field `timer1_reset`"] + pub struct TIMER1_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER1_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22); + self.w + } + } + #[doc = "Reader of field `timer2_reset`"] + pub type TIMER2_RESET_R = crate::R; + #[doc = "Write proxy for field `timer2_reset`"] + pub struct TIMER2_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER2_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23); + self.w + } + } + #[doc = "Reader of field `wdt0_reset`"] + pub type WDT0_RESET_R = crate::R; + #[doc = "Write proxy for field `wdt0_reset`"] + pub struct WDT0_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> WDT0_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); + self.w + } + } + #[doc = "Reader of field `wdt1_reset`"] + pub type WDT1_RESET_R = crate::R; + #[doc = "Write proxy for field `wdt1_reset`"] + pub struct WDT1_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> WDT1_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25); + self.w + } + } + #[doc = "Reader of field `sha_reset`"] + pub type SHA_RESET_R = crate::R; + #[doc = "Write proxy for field `sha_reset`"] + pub struct SHA_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> SHA_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26); + self.w + } + } + #[doc = "Reader of field `rtc_reset`"] + pub type RTC_RESET_R = crate::R; + #[doc = "Write proxy for field `rtc_reset`"] + pub struct RTC_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> RTC_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29); + self.w + } + } + impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn rom_reset(&self) -> ROM_RESET_R { + ROM_RESET_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn dma_reset(&self) -> DMA_RESET_R { + DMA_RESET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ai_reset(&self) -> AI_RESET_R { + AI_RESET_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn dvp_reset(&self) -> DVP_RESET_R { + DVP_RESET_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn fft_reset(&self) -> FFT_RESET_R { + FFT_RESET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio_reset(&self) -> GPIO_RESET_R { + GPIO_RESET_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn spi0_reset(&self) -> SPI0_RESET_R { + SPI0_RESET_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn spi1_reset(&self) -> SPI1_RESET_R { + SPI1_RESET_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn spi2_reset(&self) -> SPI2_RESET_R { + SPI2_RESET_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn spi3_reset(&self) -> SPI3_RESET_R { + SPI3_RESET_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn i2s0_reset(&self) -> I2S0_RESET_R { + I2S0_RESET_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn i2s1_reset(&self) -> I2S1_RESET_R { + I2S1_RESET_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn i2s2_reset(&self) -> I2S2_RESET_R { + I2S2_RESET_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn i2c0_reset(&self) -> I2C0_RESET_R { + I2C0_RESET_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn i2c1_reset(&self) -> I2C1_RESET_R { + I2C1_RESET_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn i2c2_reset(&self) -> I2C2_RESET_R { + I2C2_RESET_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn uart1_reset(&self) -> UART1_RESET_R { + UART1_RESET_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn uart2_reset(&self) -> UART2_RESET_R { + UART2_RESET_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn uart3_reset(&self) -> UART3_RESET_R { + UART3_RESET_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn aes_reset(&self) -> AES_RESET_R { + AES_RESET_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn fpioa_reset(&self) -> FPIOA_RESET_R { + FPIOA_RESET_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn timer0_reset(&self) -> TIMER0_RESET_R { + TIMER0_RESET_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn timer1_reset(&self) -> TIMER1_RESET_R { + TIMER1_RESET_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn timer2_reset(&self) -> TIMER2_RESET_R { + TIMER2_RESET_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn wdt0_reset(&self) -> WDT0_RESET_R { + WDT0_RESET_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn wdt1_reset(&self) -> WDT1_RESET_R { + WDT1_RESET_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn sha_reset(&self) -> SHA_RESET_R { + SHA_RESET_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn rtc_reset(&self) -> RTC_RESET_R { + RTC_RESET_R::new(((self.bits >> 29) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn rom_reset(&mut self) -> ROM_RESET_W { + ROM_RESET_W { w: self } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn dma_reset(&mut self) -> DMA_RESET_W { + DMA_RESET_W { w: self } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ai_reset(&mut self) -> AI_RESET_W { + AI_RESET_W { w: self } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn dvp_reset(&mut self) -> DVP_RESET_W { + DVP_RESET_W { w: self } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn fft_reset(&mut self) -> FFT_RESET_W { + FFT_RESET_W { w: self } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio_reset(&mut self) -> GPIO_RESET_W { + GPIO_RESET_W { w: self } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn spi0_reset(&mut self) -> SPI0_RESET_W { + SPI0_RESET_W { w: self } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn spi1_reset(&mut self) -> SPI1_RESET_W { + SPI1_RESET_W { w: self } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn spi2_reset(&mut self) -> SPI2_RESET_W { + SPI2_RESET_W { w: self } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn spi3_reset(&mut self) -> SPI3_RESET_W { + SPI3_RESET_W { w: self } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn i2s0_reset(&mut self) -> I2S0_RESET_W { + I2S0_RESET_W { w: self } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn i2s1_reset(&mut self) -> I2S1_RESET_W { + I2S1_RESET_W { w: self } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn i2s2_reset(&mut self) -> I2S2_RESET_W { + I2S2_RESET_W { w: self } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn i2c0_reset(&mut self) -> I2C0_RESET_W { + I2C0_RESET_W { w: self } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn i2c1_reset(&mut self) -> I2C1_RESET_W { + I2C1_RESET_W { w: self } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn i2c2_reset(&mut self) -> I2C2_RESET_W { + I2C2_RESET_W { w: self } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn uart1_reset(&mut self) -> UART1_RESET_W { + UART1_RESET_W { w: self } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn uart2_reset(&mut self) -> UART2_RESET_W { + UART2_RESET_W { w: self } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn uart3_reset(&mut self) -> UART3_RESET_W { + UART3_RESET_W { w: self } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn aes_reset(&mut self) -> AES_RESET_W { + AES_RESET_W { w: self } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn fpioa_reset(&mut self) -> FPIOA_RESET_W { + FPIOA_RESET_W { w: self } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn timer0_reset(&mut self) -> TIMER0_RESET_W { + TIMER0_RESET_W { w: self } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn timer1_reset(&mut self) -> TIMER1_RESET_W { + TIMER1_RESET_W { w: self } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn timer2_reset(&mut self) -> TIMER2_RESET_W { + TIMER2_RESET_W { w: self } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn wdt0_reset(&mut self) -> WDT0_RESET_W { + WDT0_RESET_W { w: self } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn wdt1_reset(&mut self) -> WDT1_RESET_W { + WDT1_RESET_W { w: self } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn sha_reset(&mut self) -> SHA_RESET_W { + SHA_RESET_W { w: self } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn rtc_reset(&mut self) -> RTC_RESET_W { + RTC_RESET_W { w: self } + } + } + } + #[doc = "Clock threshold controller 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_th0](clk_th0) module"] + pub type CLK_TH0 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_TH0; + #[doc = "`read()` method returns [clk_th0::R](clk_th0::R) reader structure"] + impl crate::Readable for CLK_TH0 {} + #[doc = "`write(|w| ..)` method takes [clk_th0::W](clk_th0::W) writer structure"] + impl crate::Writable for CLK_TH0 {} + #[doc = "Clock threshold controller 0"] + pub mod clk_th0 { + #[doc = "Reader of register clk_th0"] + pub type R = crate::R; + #[doc = "Writer for register clk_th0"] + pub type W = crate::W; + #[doc = "Register clk_th0 `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_TH0 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `sram0_gclk`"] + pub type SRAM0_GCLK_R = crate::R; + #[doc = "Write proxy for field `sram0_gclk`"] + pub struct SRAM0_GCLK_W<'a> { + w: &'a mut W, + } + impl<'a> SRAM0_GCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f); + self.w + } + } + #[doc = "Reader of field `sram1_gclk`"] + pub type SRAM1_GCLK_R = crate::R; + #[doc = "Write proxy for field `sram1_gclk`"] + pub struct SRAM1_GCLK_W<'a> { + w: &'a mut W, + } + impl<'a> SRAM1_GCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4); + self.w + } + } + #[doc = "Reader of field `ai_gclk`"] + pub type AI_GCLK_R = crate::R; + #[doc = "Write proxy for field `ai_gclk`"] + pub struct AI_GCLK_W<'a> { + w: &'a mut W, + } + impl<'a> AI_GCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8); + self.w + } + } + #[doc = "Reader of field `dvp_gclk`"] + pub type DVP_GCLK_R = crate::R; + #[doc = "Write proxy for field `dvp_gclk`"] + pub struct DVP_GCLK_W<'a> { + w: &'a mut W, + } + impl<'a> DVP_GCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12); + self.w + } + } + #[doc = "Reader of field `rom_gclk`"] + pub type ROM_GCLK_R = crate::R; + #[doc = "Write proxy for field `rom_gclk`"] + pub struct ROM_GCLK_W<'a> { + w: &'a mut W, + } + impl<'a> ROM_GCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16); + self.w + } + } + impl R { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn sram0_gclk(&self) -> SRAM0_GCLK_R { + SRAM0_GCLK_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7"] + #[inline(always)] + pub fn sram1_gclk(&self) -> SRAM1_GCLK_R { + SRAM1_GCLK_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11"] + #[inline(always)] + pub fn ai_gclk(&self) -> AI_GCLK_R { + AI_GCLK_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15"] + #[inline(always)] + pub fn dvp_gclk(&self) -> DVP_GCLK_R { + DVP_GCLK_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19"] + #[inline(always)] + pub fn rom_gclk(&self) -> ROM_GCLK_R { + ROM_GCLK_R::new(((self.bits >> 16) & 0x0f) as u8) + } + } + impl W { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn sram0_gclk(&mut self) -> SRAM0_GCLK_W { + SRAM0_GCLK_W { w: self } + } + #[doc = "Bits 4:7"] + #[inline(always)] + pub fn sram1_gclk(&mut self) -> SRAM1_GCLK_W { + SRAM1_GCLK_W { w: self } + } + #[doc = "Bits 8:11"] + #[inline(always)] + pub fn ai_gclk(&mut self) -> AI_GCLK_W { + AI_GCLK_W { w: self } + } + #[doc = "Bits 12:15"] + #[inline(always)] + pub fn dvp_gclk(&mut self) -> DVP_GCLK_W { + DVP_GCLK_W { w: self } + } + #[doc = "Bits 16:19"] + #[inline(always)] + pub fn rom_gclk(&mut self) -> ROM_GCLK_W { + ROM_GCLK_W { w: self } + } + } + } + #[doc = "Clock threshold controller 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_th1](clk_th1) module"] + pub type CLK_TH1 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_TH1; + #[doc = "`read()` method returns [clk_th1::R](clk_th1::R) reader structure"] + impl crate::Readable for CLK_TH1 {} + #[doc = "`write(|w| ..)` method takes [clk_th1::W](clk_th1::W) writer structure"] + impl crate::Writable for CLK_TH1 {} + #[doc = "Clock threshold controller 1"] + pub mod clk_th1 { + #[doc = "Reader of register clk_th1"] + pub type R = crate::R; + #[doc = "Writer for register clk_th1"] + pub type W = crate::W; + #[doc = "Register clk_th1 `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_TH1 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `spi0_clk`"] + pub type SPI0_CLK_R = crate::R; + #[doc = "Write proxy for field `spi0_clk`"] + pub struct SPI0_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> SPI0_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + #[doc = "Reader of field `spi1_clk`"] + pub type SPI1_CLK_R = crate::R; + #[doc = "Write proxy for field `spi1_clk`"] + pub struct SPI1_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> SPI1_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8); + self.w + } + } + #[doc = "Reader of field `spi2_clk`"] + pub type SPI2_CLK_R = crate::R; + #[doc = "Write proxy for field `spi2_clk`"] + pub struct SPI2_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> SPI2_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16); + self.w + } + } + #[doc = "Reader of field `spi3_clk`"] + pub type SPI3_CLK_R = crate::R; + #[doc = "Write proxy for field `spi3_clk`"] + pub struct SPI3_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> SPI3_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | (((value as u32) & 0xff) << 24); + self.w + } + } + impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn spi0_clk(&self) -> SPI0_CLK_R { + SPI0_CLK_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15"] + #[inline(always)] + pub fn spi1_clk(&self) -> SPI1_CLK_R { + SPI1_CLK_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23"] + #[inline(always)] + pub fn spi2_clk(&self) -> SPI2_CLK_R { + SPI2_CLK_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31"] + #[inline(always)] + pub fn spi3_clk(&self) -> SPI3_CLK_R { + SPI3_CLK_R::new(((self.bits >> 24) & 0xff) as u8) + } + } + impl W { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn spi0_clk(&mut self) -> SPI0_CLK_W { + SPI0_CLK_W { w: self } + } + #[doc = "Bits 8:15"] + #[inline(always)] + pub fn spi1_clk(&mut self) -> SPI1_CLK_W { + SPI1_CLK_W { w: self } + } + #[doc = "Bits 16:23"] + #[inline(always)] + pub fn spi2_clk(&mut self) -> SPI2_CLK_W { + SPI2_CLK_W { w: self } + } + #[doc = "Bits 24:31"] + #[inline(always)] + pub fn spi3_clk(&mut self) -> SPI3_CLK_W { + SPI3_CLK_W { w: self } + } + } + } + #[doc = "Clock threshold controller 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_th2](clk_th2) module"] + pub type CLK_TH2 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_TH2; + #[doc = "`read()` method returns [clk_th2::R](clk_th2::R) reader structure"] + impl crate::Readable for CLK_TH2 {} + #[doc = "`write(|w| ..)` method takes [clk_th2::W](clk_th2::W) writer structure"] + impl crate::Writable for CLK_TH2 {} + #[doc = "Clock threshold controller 2"] + pub mod clk_th2 { + #[doc = "Reader of register clk_th2"] + pub type R = crate::R; + #[doc = "Writer for register clk_th2"] + pub type W = crate::W; + #[doc = "Register clk_th2 `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_TH2 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `timer0_clk`"] + pub type TIMER0_CLK_R = crate::R; + #[doc = "Write proxy for field `timer0_clk`"] + pub struct TIMER0_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER0_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + #[doc = "Reader of field `timer1_clk`"] + pub type TIMER1_CLK_R = crate::R; + #[doc = "Write proxy for field `timer1_clk`"] + pub struct TIMER1_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER1_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8); + self.w + } + } + #[doc = "Reader of field `timer2_clk`"] + pub type TIMER2_CLK_R = crate::R; + #[doc = "Write proxy for field `timer2_clk`"] + pub struct TIMER2_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER2_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16); + self.w + } + } + impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn timer0_clk(&self) -> TIMER0_CLK_R { + TIMER0_CLK_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15"] + #[inline(always)] + pub fn timer1_clk(&self) -> TIMER1_CLK_R { + TIMER1_CLK_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23"] + #[inline(always)] + pub fn timer2_clk(&self) -> TIMER2_CLK_R { + TIMER2_CLK_R::new(((self.bits >> 16) & 0xff) as u8) + } + } + impl W { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn timer0_clk(&mut self) -> TIMER0_CLK_W { + TIMER0_CLK_W { w: self } + } + #[doc = "Bits 8:15"] + #[inline(always)] + pub fn timer1_clk(&mut self) -> TIMER1_CLK_W { + TIMER1_CLK_W { w: self } + } + #[doc = "Bits 16:23"] + #[inline(always)] + pub fn timer2_clk(&mut self) -> TIMER2_CLK_W { + TIMER2_CLK_W { w: self } + } + } + } + #[doc = "Clock threshold controller 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_th3](clk_th3) module"] + pub type CLK_TH3 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_TH3; + #[doc = "`read()` method returns [clk_th3::R](clk_th3::R) reader structure"] + impl crate::Readable for CLK_TH3 {} + #[doc = "`write(|w| ..)` method takes [clk_th3::W](clk_th3::W) writer structure"] + impl crate::Writable for CLK_TH3 {} + #[doc = "Clock threshold controller 3"] + pub mod clk_th3 { + #[doc = "Reader of register clk_th3"] + pub type R = crate::R; + #[doc = "Writer for register clk_th3"] + pub type W = crate::W; + #[doc = "Register clk_th3 `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_TH3 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `i2s0_clk`"] + pub type I2S0_CLK_R = crate::R; + #[doc = "Write proxy for field `i2s0_clk`"] + pub struct I2S0_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> I2S0_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + #[doc = "Reader of field `i2s1_clk`"] + pub type I2S1_CLK_R = crate::R; + #[doc = "Write proxy for field `i2s1_clk`"] + pub struct I2S1_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> I2S1_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16); + self.w + } + } + impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn i2s0_clk(&self) -> I2S0_CLK_R { + I2S0_CLK_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31"] + #[inline(always)] + pub fn i2s1_clk(&self) -> I2S1_CLK_R { + I2S1_CLK_R::new(((self.bits >> 16) & 0xffff) as u16) + } + } + impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn i2s0_clk(&mut self) -> I2S0_CLK_W { + I2S0_CLK_W { w: self } + } + #[doc = "Bits 16:31"] + #[inline(always)] + pub fn i2s1_clk(&mut self) -> I2S1_CLK_W { + I2S1_CLK_W { w: self } + } + } + } + #[doc = "Clock threshold controller 4\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_th4](clk_th4) module"] + pub type CLK_TH4 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_TH4; + #[doc = "`read()` method returns [clk_th4::R](clk_th4::R) reader structure"] + impl crate::Readable for CLK_TH4 {} + #[doc = "`write(|w| ..)` method takes [clk_th4::W](clk_th4::W) writer structure"] + impl crate::Writable for CLK_TH4 {} + #[doc = "Clock threshold controller 4"] + pub mod clk_th4 { + #[doc = "Reader of register clk_th4"] + pub type R = crate::R; + #[doc = "Writer for register clk_th4"] + pub type W = crate::W; + #[doc = "Register clk_th4 `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_TH4 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `i2s2_clk`"] + pub type I2S2_CLK_R = crate::R; + #[doc = "Write proxy for field `i2s2_clk`"] + pub struct I2S2_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> I2S2_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + #[doc = "Reader of field `i2s0_mclk`"] + pub type I2S0_MCLK_R = crate::R; + #[doc = "Write proxy for field `i2s0_mclk`"] + pub struct I2S0_MCLK_W<'a> { + w: &'a mut W, + } + impl<'a> I2S0_MCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16); + self.w + } + } + #[doc = "Reader of field `i2s1_mclk`"] + pub type I2S1_MCLK_R = crate::R; + #[doc = "Write proxy for field `i2s1_mclk`"] + pub struct I2S1_MCLK_W<'a> { + w: &'a mut W, + } + impl<'a> I2S1_MCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | (((value as u32) & 0xff) << 24); + self.w + } + } + impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn i2s2_clk(&self) -> I2S2_CLK_R { + I2S2_CLK_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23"] + #[inline(always)] + pub fn i2s0_mclk(&self) -> I2S0_MCLK_R { + I2S0_MCLK_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31"] + #[inline(always)] + pub fn i2s1_mclk(&self) -> I2S1_MCLK_R { + I2S1_MCLK_R::new(((self.bits >> 24) & 0xff) as u8) + } + } + impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn i2s2_clk(&mut self) -> I2S2_CLK_W { + I2S2_CLK_W { w: self } + } + #[doc = "Bits 16:23"] + #[inline(always)] + pub fn i2s0_mclk(&mut self) -> I2S0_MCLK_W { + I2S0_MCLK_W { w: self } + } + #[doc = "Bits 24:31"] + #[inline(always)] + pub fn i2s1_mclk(&mut self) -> I2S1_MCLK_W { + I2S1_MCLK_W { w: self } + } + } + } + #[doc = "Clock threshold controller 5\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_th5](clk_th5) module"] + pub type CLK_TH5 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_TH5; + #[doc = "`read()` method returns [clk_th5::R](clk_th5::R) reader structure"] + impl crate::Readable for CLK_TH5 {} + #[doc = "`write(|w| ..)` method takes [clk_th5::W](clk_th5::W) writer structure"] + impl crate::Writable for CLK_TH5 {} + #[doc = "Clock threshold controller 5"] + pub mod clk_th5 { + #[doc = "Reader of register clk_th5"] + pub type R = crate::R; + #[doc = "Writer for register clk_th5"] + pub type W = crate::W; + #[doc = "Register clk_th5 `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_TH5 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `i2s2_mclk`"] + pub type I2S2_MCLK_R = crate::R; + #[doc = "Write proxy for field `i2s2_mclk`"] + pub struct I2S2_MCLK_W<'a> { + w: &'a mut W, + } + impl<'a> I2S2_MCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + #[doc = "Reader of field `i2c0_clk`"] + pub type I2C0_CLK_R = crate::R; + #[doc = "Write proxy for field `i2c0_clk`"] + pub struct I2C0_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> I2C0_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8); + self.w + } + } + #[doc = "Reader of field `i2c1_clk`"] + pub type I2C1_CLK_R = crate::R; + #[doc = "Write proxy for field `i2c1_clk`"] + pub struct I2C1_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> I2C1_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16); + self.w + } + } + #[doc = "Reader of field `i2c2_clk`"] + pub type I2C2_CLK_R = crate::R; + #[doc = "Write proxy for field `i2c2_clk`"] + pub struct I2C2_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> I2C2_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | (((value as u32) & 0xff) << 24); + self.w + } + } + impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn i2s2_mclk(&self) -> I2S2_MCLK_R { + I2S2_MCLK_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15"] + #[inline(always)] + pub fn i2c0_clk(&self) -> I2C0_CLK_R { + I2C0_CLK_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23"] + #[inline(always)] + pub fn i2c1_clk(&self) -> I2C1_CLK_R { + I2C1_CLK_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31"] + #[inline(always)] + pub fn i2c2_clk(&self) -> I2C2_CLK_R { + I2C2_CLK_R::new(((self.bits >> 24) & 0xff) as u8) + } + } + impl W { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn i2s2_mclk(&mut self) -> I2S2_MCLK_W { + I2S2_MCLK_W { w: self } + } + #[doc = "Bits 8:15"] + #[inline(always)] + pub fn i2c0_clk(&mut self) -> I2C0_CLK_W { + I2C0_CLK_W { w: self } + } + #[doc = "Bits 16:23"] + #[inline(always)] + pub fn i2c1_clk(&mut self) -> I2C1_CLK_W { + I2C1_CLK_W { w: self } + } + #[doc = "Bits 24:31"] + #[inline(always)] + pub fn i2c2_clk(&mut self) -> I2C2_CLK_W { + I2C2_CLK_W { w: self } + } + } + } + #[doc = "Clock threshold controller 6\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_th6](clk_th6) module"] + pub type CLK_TH6 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_TH6; + #[doc = "`read()` method returns [clk_th6::R](clk_th6::R) reader structure"] + impl crate::Readable for CLK_TH6 {} + #[doc = "`write(|w| ..)` method takes [clk_th6::W](clk_th6::W) writer structure"] + impl crate::Writable for CLK_TH6 {} + #[doc = "Clock threshold controller 6"] + pub mod clk_th6 { + #[doc = "Reader of register clk_th6"] + pub type R = crate::R; + #[doc = "Writer for register clk_th6"] + pub type W = crate::W; + #[doc = "Register clk_th6 `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_TH6 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `wdt0_clk`"] + pub type WDT0_CLK_R = crate::R; + #[doc = "Write proxy for field `wdt0_clk`"] + pub struct WDT0_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> WDT0_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + #[doc = "Reader of field `wdt1_clk`"] + pub type WDT1_CLK_R = crate::R; + #[doc = "Write proxy for field `wdt1_clk`"] + pub struct WDT1_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> WDT1_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8); + self.w + } + } + impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn wdt0_clk(&self) -> WDT0_CLK_R { + WDT0_CLK_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15"] + #[inline(always)] + pub fn wdt1_clk(&self) -> WDT1_CLK_R { + WDT1_CLK_R::new(((self.bits >> 8) & 0xff) as u8) + } + } + impl W { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn wdt0_clk(&mut self) -> WDT0_CLK_W { + WDT0_CLK_W { w: self } + } + #[doc = "Bits 8:15"] + #[inline(always)] + pub fn wdt1_clk(&mut self) -> WDT1_CLK_W { + WDT1_CLK_W { w: self } + } + } + } + #[doc = "Miscellaneous controller\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [misc](misc) module"] + pub type MISC = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _MISC; + #[doc = "`read()` method returns [misc::R](misc::R) reader structure"] + impl crate::Readable for MISC {} + #[doc = "`write(|w| ..)` method takes [misc::W](misc::W) writer structure"] + impl crate::Writable for MISC {} + #[doc = "Miscellaneous controller"] + pub mod misc { + #[doc = "Reader of register misc"] + pub type R = crate::R; + #[doc = "Writer for register misc"] + pub type W = crate::W; + #[doc = "Register misc `reset()`'s with value 0"] + impl crate::ResetValue for super::MISC { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `debug_sel`"] + pub type DEBUG_SEL_R = crate::R; + #[doc = "Write proxy for field `debug_sel`"] + pub struct DEBUG_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> DEBUG_SEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | ((value as u32) & 0x3f); + self.w + } + } + #[doc = "Reader of field `spi_dvp_data_enable`"] + pub type SPI_DVP_DATA_ENABLE_R = crate::R; + #[doc = "Write proxy for field `spi_dvp_data_enable`"] + pub struct SPI_DVP_DATA_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> SPI_DVP_DATA_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); + self.w + } + } + impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn debug_sel(&self) -> DEBUG_SEL_R { + DEBUG_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn spi_dvp_data_enable(&self) -> SPI_DVP_DATA_ENABLE_R { + SPI_DVP_DATA_ENABLE_R::new(((self.bits >> 10) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn debug_sel(&mut self) -> DEBUG_SEL_W { + DEBUG_SEL_W { w: self } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn spi_dvp_data_enable(&mut self) -> SPI_DVP_DATA_ENABLE_W { + SPI_DVP_DATA_ENABLE_W { w: self } + } + } + } + #[doc = "Peripheral controller\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peri](peri) module"] + pub type PERI = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PERI; + #[doc = "`read()` method returns [peri::R](peri::R) reader structure"] + impl crate::Readable for PERI {} + #[doc = "`write(|w| ..)` method takes [peri::W](peri::W) writer structure"] + impl crate::Writable for PERI {} + #[doc = "Peripheral controller"] + pub mod peri { + #[doc = "Reader of register peri"] + pub type R = crate::R; + #[doc = "Writer for register peri"] + pub type W = crate::W; + #[doc = "Register peri `reset()`'s with value 0"] + impl crate::ResetValue for super::PERI { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `timer0_pause`"] + pub type TIMER0_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer0_pause`"] + pub struct TIMER0_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER0_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `timer1_pause`"] + pub type TIMER1_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer1_pause`"] + pub struct TIMER1_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER1_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `timer2_pause`"] + pub type TIMER2_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer2_pause`"] + pub struct TIMER2_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER2_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `timer3_pause`"] + pub type TIMER3_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer3_pause`"] + pub struct TIMER3_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER3_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `timer4_pause`"] + pub type TIMER4_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer4_pause`"] + pub struct TIMER4_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER4_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `timer5_pause`"] + pub type TIMER5_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer5_pause`"] + pub struct TIMER5_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER5_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `timer6_pause`"] + pub type TIMER6_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer6_pause`"] + pub struct TIMER6_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER6_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `timer7_pause`"] + pub type TIMER7_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer7_pause`"] + pub struct TIMER7_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER7_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `timer8_pause`"] + pub type TIMER8_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer8_pause`"] + pub struct TIMER8_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER8_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `timer9_pause`"] + pub type TIMER9_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer9_pause`"] + pub struct TIMER9_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER9_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `timer10_pause`"] + pub type TIMER10_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer10_pause`"] + pub struct TIMER10_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER10_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `timer11_pause`"] + pub type TIMER11_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer11_pause`"] + pub struct TIMER11_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER11_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); + self.w + } + } + #[doc = "Reader of field `spi0_xip_en`"] + pub type SPI0_XIP_EN_R = crate::R; + #[doc = "Write proxy for field `spi0_xip_en`"] + pub struct SPI0_XIP_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SPI0_XIP_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); + self.w + } + } + #[doc = "Reader of field `spi1_xip_en`"] + pub type SPI1_XIP_EN_R = crate::R; + #[doc = "Write proxy for field `spi1_xip_en`"] + pub struct SPI1_XIP_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SPI1_XIP_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13); + self.w + } + } + #[doc = "Reader of field `spi2_xip_en`"] + pub type SPI2_XIP_EN_R = crate::R; + #[doc = "Write proxy for field `spi2_xip_en`"] + pub struct SPI2_XIP_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SPI2_XIP_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14); + self.w + } + } + #[doc = "Reader of field `spi3_xip_en`"] + pub type SPI3_XIP_EN_R = crate::R; + #[doc = "Write proxy for field `spi3_xip_en`"] + pub struct SPI3_XIP_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SPI3_XIP_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); + self.w + } + } + #[doc = "Reader of field `spi0_clk_bypass`"] + pub type SPI0_CLK_BYPASS_R = crate::R; + #[doc = "Write proxy for field `spi0_clk_bypass`"] + pub struct SPI0_CLK_BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> SPI0_CLK_BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); + self.w + } + } + #[doc = "Reader of field `spi1_clk_bypass`"] + pub type SPI1_CLK_BYPASS_R = crate::R; + #[doc = "Write proxy for field `spi1_clk_bypass`"] + pub struct SPI1_CLK_BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> SPI1_CLK_BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17); + self.w + } + } + #[doc = "Reader of field `spi2_clk_bypass`"] + pub type SPI2_CLK_BYPASS_R = crate::R; + #[doc = "Write proxy for field `spi2_clk_bypass`"] + pub struct SPI2_CLK_BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> SPI2_CLK_BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18); + self.w + } + } + #[doc = "Reader of field `i2s0_clk_bypass`"] + pub type I2S0_CLK_BYPASS_R = crate::R; + #[doc = "Write proxy for field `i2s0_clk_bypass`"] + pub struct I2S0_CLK_BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> I2S0_CLK_BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19); + self.w + } + } + #[doc = "Reader of field `i2s1_clk_bypass`"] + pub type I2S1_CLK_BYPASS_R = crate::R; + #[doc = "Write proxy for field `i2s1_clk_bypass`"] + pub struct I2S1_CLK_BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> I2S1_CLK_BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20); + self.w + } + } + #[doc = "Reader of field `i2s2_clk_bypass`"] + pub type I2S2_CLK_BYPASS_R = crate::R; + #[doc = "Write proxy for field `i2s2_clk_bypass`"] + pub struct I2S2_CLK_BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> I2S2_CLK_BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21); + self.w + } + } + #[doc = "Reader of field `jtag_clk_bypass`"] + pub type JTAG_CLK_BYPASS_R = crate::R; + #[doc = "Write proxy for field `jtag_clk_bypass`"] + pub struct JTAG_CLK_BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> JTAG_CLK_BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22); + self.w + } + } + #[doc = "Reader of field `dvp_clk_bypass`"] + pub type DVP_CLK_BYPASS_R = crate::R; + #[doc = "Write proxy for field `dvp_clk_bypass`"] + pub struct DVP_CLK_BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> DVP_CLK_BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23); + self.w + } + } + #[doc = "Reader of field `debug_clk_bypass`"] + pub type DEBUG_CLK_BYPASS_R = crate::R; + #[doc = "Write proxy for field `debug_clk_bypass`"] + pub struct DEBUG_CLK_BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> DEBUG_CLK_BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); + self.w + } + } + impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn timer0_pause(&self) -> TIMER0_PAUSE_R { + TIMER0_PAUSE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn timer1_pause(&self) -> TIMER1_PAUSE_R { + TIMER1_PAUSE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn timer2_pause(&self) -> TIMER2_PAUSE_R { + TIMER2_PAUSE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn timer3_pause(&self) -> TIMER3_PAUSE_R { + TIMER3_PAUSE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn timer4_pause(&self) -> TIMER4_PAUSE_R { + TIMER4_PAUSE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn timer5_pause(&self) -> TIMER5_PAUSE_R { + TIMER5_PAUSE_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn timer6_pause(&self) -> TIMER6_PAUSE_R { + TIMER6_PAUSE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn timer7_pause(&self) -> TIMER7_PAUSE_R { + TIMER7_PAUSE_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn timer8_pause(&self) -> TIMER8_PAUSE_R { + TIMER8_PAUSE_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn timer9_pause(&self) -> TIMER9_PAUSE_R { + TIMER9_PAUSE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn timer10_pause(&self) -> TIMER10_PAUSE_R { + TIMER10_PAUSE_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn timer11_pause(&self) -> TIMER11_PAUSE_R { + TIMER11_PAUSE_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn spi0_xip_en(&self) -> SPI0_XIP_EN_R { + SPI0_XIP_EN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn spi1_xip_en(&self) -> SPI1_XIP_EN_R { + SPI1_XIP_EN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn spi2_xip_en(&self) -> SPI2_XIP_EN_R { + SPI2_XIP_EN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn spi3_xip_en(&self) -> SPI3_XIP_EN_R { + SPI3_XIP_EN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn spi0_clk_bypass(&self) -> SPI0_CLK_BYPASS_R { + SPI0_CLK_BYPASS_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn spi1_clk_bypass(&self) -> SPI1_CLK_BYPASS_R { + SPI1_CLK_BYPASS_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn spi2_clk_bypass(&self) -> SPI2_CLK_BYPASS_R { + SPI2_CLK_BYPASS_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn i2s0_clk_bypass(&self) -> I2S0_CLK_BYPASS_R { + I2S0_CLK_BYPASS_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn i2s1_clk_bypass(&self) -> I2S1_CLK_BYPASS_R { + I2S1_CLK_BYPASS_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn i2s2_clk_bypass(&self) -> I2S2_CLK_BYPASS_R { + I2S2_CLK_BYPASS_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn jtag_clk_bypass(&self) -> JTAG_CLK_BYPASS_R { + JTAG_CLK_BYPASS_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn dvp_clk_bypass(&self) -> DVP_CLK_BYPASS_R { + DVP_CLK_BYPASS_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn debug_clk_bypass(&self) -> DEBUG_CLK_BYPASS_R { + DEBUG_CLK_BYPASS_R::new(((self.bits >> 24) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn timer0_pause(&mut self) -> TIMER0_PAUSE_W { + TIMER0_PAUSE_W { w: self } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn timer1_pause(&mut self) -> TIMER1_PAUSE_W { + TIMER1_PAUSE_W { w: self } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn timer2_pause(&mut self) -> TIMER2_PAUSE_W { + TIMER2_PAUSE_W { w: self } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn timer3_pause(&mut self) -> TIMER3_PAUSE_W { + TIMER3_PAUSE_W { w: self } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn timer4_pause(&mut self) -> TIMER4_PAUSE_W { + TIMER4_PAUSE_W { w: self } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn timer5_pause(&mut self) -> TIMER5_PAUSE_W { + TIMER5_PAUSE_W { w: self } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn timer6_pause(&mut self) -> TIMER6_PAUSE_W { + TIMER6_PAUSE_W { w: self } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn timer7_pause(&mut self) -> TIMER7_PAUSE_W { + TIMER7_PAUSE_W { w: self } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn timer8_pause(&mut self) -> TIMER8_PAUSE_W { + TIMER8_PAUSE_W { w: self } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn timer9_pause(&mut self) -> TIMER9_PAUSE_W { + TIMER9_PAUSE_W { w: self } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn timer10_pause(&mut self) -> TIMER10_PAUSE_W { + TIMER10_PAUSE_W { w: self } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn timer11_pause(&mut self) -> TIMER11_PAUSE_W { + TIMER11_PAUSE_W { w: self } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn spi0_xip_en(&mut self) -> SPI0_XIP_EN_W { + SPI0_XIP_EN_W { w: self } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn spi1_xip_en(&mut self) -> SPI1_XIP_EN_W { + SPI1_XIP_EN_W { w: self } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn spi2_xip_en(&mut self) -> SPI2_XIP_EN_W { + SPI2_XIP_EN_W { w: self } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn spi3_xip_en(&mut self) -> SPI3_XIP_EN_W { + SPI3_XIP_EN_W { w: self } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn spi0_clk_bypass(&mut self) -> SPI0_CLK_BYPASS_W { + SPI0_CLK_BYPASS_W { w: self } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn spi1_clk_bypass(&mut self) -> SPI1_CLK_BYPASS_W { + SPI1_CLK_BYPASS_W { w: self } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn spi2_clk_bypass(&mut self) -> SPI2_CLK_BYPASS_W { + SPI2_CLK_BYPASS_W { w: self } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn i2s0_clk_bypass(&mut self) -> I2S0_CLK_BYPASS_W { + I2S0_CLK_BYPASS_W { w: self } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn i2s1_clk_bypass(&mut self) -> I2S1_CLK_BYPASS_W { + I2S1_CLK_BYPASS_W { w: self } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn i2s2_clk_bypass(&mut self) -> I2S2_CLK_BYPASS_W { + I2S2_CLK_BYPASS_W { w: self } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn jtag_clk_bypass(&mut self) -> JTAG_CLK_BYPASS_W { + JTAG_CLK_BYPASS_W { w: self } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn dvp_clk_bypass(&mut self) -> DVP_CLK_BYPASS_W { + DVP_CLK_BYPASS_W { w: self } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn debug_clk_bypass(&mut self) -> DEBUG_CLK_BYPASS_W { + DEBUG_CLK_BYPASS_W { w: self } + } + } + } + #[doc = "SPI sleep controller\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spi_sleep](spi_sleep) module"] + pub type SPI_SLEEP = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SPI_SLEEP; + #[doc = "`read()` method returns [spi_sleep::R](spi_sleep::R) reader structure"] + impl crate::Readable for SPI_SLEEP {} + #[doc = "`write(|w| ..)` method takes [spi_sleep::W](spi_sleep::W) writer structure"] + impl crate::Writable for SPI_SLEEP {} + #[doc = "SPI sleep controller"] + pub mod spi_sleep { + #[doc = "Reader of register spi_sleep"] + pub type R = crate::R; + #[doc = "Writer for register spi_sleep"] + pub type W = crate::W; + #[doc = "Register spi_sleep `reset()`'s with value 0"] + impl crate::ResetValue for super::SPI_SLEEP { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `ssi0_sleep`"] + pub type SSI0_SLEEP_R = crate::R; + #[doc = "Write proxy for field `ssi0_sleep`"] + pub struct SSI0_SLEEP_W<'a> { + w: &'a mut W, + } + impl<'a> SSI0_SLEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `ssi1_sleep`"] + pub type SSI1_SLEEP_R = crate::R; + #[doc = "Write proxy for field `ssi1_sleep`"] + pub struct SSI1_SLEEP_W<'a> { + w: &'a mut W, + } + impl<'a> SSI1_SLEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `ssi2_sleep`"] + pub type SSI2_SLEEP_R = crate::R; + #[doc = "Write proxy for field `ssi2_sleep`"] + pub struct SSI2_SLEEP_W<'a> { + w: &'a mut W, + } + impl<'a> SSI2_SLEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `ssi3_sleep`"] + pub type SSI3_SLEEP_R = crate::R; + #[doc = "Write proxy for field `ssi3_sleep`"] + pub struct SSI3_SLEEP_W<'a> { + w: &'a mut W, + } + impl<'a> SSI3_SLEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn ssi0_sleep(&self) -> SSI0_SLEEP_R { + SSI0_SLEEP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn ssi1_sleep(&self) -> SSI1_SLEEP_R { + SSI1_SLEEP_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ssi2_sleep(&self) -> SSI2_SLEEP_R { + SSI2_SLEEP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn ssi3_sleep(&self) -> SSI3_SLEEP_R { + SSI3_SLEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn ssi0_sleep(&mut self) -> SSI0_SLEEP_W { + SSI0_SLEEP_W { w: self } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn ssi1_sleep(&mut self) -> SSI1_SLEEP_W { + SSI1_SLEEP_W { w: self } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ssi2_sleep(&mut self) -> SSI2_SLEEP_W { + SSI2_SLEEP_W { w: self } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn ssi3_sleep(&mut self) -> SSI3_SLEEP_W { + SSI3_SLEEP_W { w: self } + } + } + } + #[doc = "Reset source status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [reset_status](reset_status) module"] + pub type RESET_STATUS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RESET_STATUS; + #[doc = "`read()` method returns [reset_status::R](reset_status::R) reader structure"] + impl crate::Readable for RESET_STATUS {} + #[doc = "`write(|w| ..)` method takes [reset_status::W](reset_status::W) writer structure"] + impl crate::Writable for RESET_STATUS {} + #[doc = "Reset source status"] + pub mod reset_status { + #[doc = "Reader of register reset_status"] + pub type R = crate::R; + #[doc = "Writer for register reset_status"] + pub type W = crate::W; + #[doc = "Register reset_status `reset()`'s with value 0"] + impl crate::ResetValue for super::RESET_STATUS { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `reset_sts_clr`"] + pub type RESET_STS_CLR_R = crate::R; + #[doc = "Write proxy for field `reset_sts_clr`"] + pub struct RESET_STS_CLR_W<'a> { + w: &'a mut W, + } + impl<'a> RESET_STS_CLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `pin_reset_sts`"] + pub type PIN_RESET_STS_R = crate::R; + #[doc = "Write proxy for field `pin_reset_sts`"] + pub struct PIN_RESET_STS_W<'a> { + w: &'a mut W, + } + impl<'a> PIN_RESET_STS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `wdt0_reset_sts`"] + pub type WDT0_RESET_STS_R = crate::R; + #[doc = "Write proxy for field `wdt0_reset_sts`"] + pub struct WDT0_RESET_STS_W<'a> { + w: &'a mut W, + } + impl<'a> WDT0_RESET_STS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `wdt1_reset_sts`"] + pub type WDT1_RESET_STS_R = crate::R; + #[doc = "Write proxy for field `wdt1_reset_sts`"] + pub struct WDT1_RESET_STS_W<'a> { + w: &'a mut W, + } + impl<'a> WDT1_RESET_STS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `soft_reset_sts`"] + pub type SOFT_RESET_STS_R = crate::R; + #[doc = "Write proxy for field `soft_reset_sts`"] + pub struct SOFT_RESET_STS_W<'a> { + w: &'a mut W, + } + impl<'a> SOFT_RESET_STS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn reset_sts_clr(&self) -> RESET_STS_CLR_R { + RESET_STS_CLR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin_reset_sts(&self) -> PIN_RESET_STS_R { + PIN_RESET_STS_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn wdt0_reset_sts(&self) -> WDT0_RESET_STS_R { + WDT0_RESET_STS_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn wdt1_reset_sts(&self) -> WDT1_RESET_STS_R { + WDT1_RESET_STS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn soft_reset_sts(&self) -> SOFT_RESET_STS_R { + SOFT_RESET_STS_R::new(((self.bits >> 4) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn reset_sts_clr(&mut self) -> RESET_STS_CLR_W { + RESET_STS_CLR_W { w: self } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin_reset_sts(&mut self) -> PIN_RESET_STS_W { + PIN_RESET_STS_W { w: self } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn wdt0_reset_sts(&mut self) -> WDT0_RESET_STS_W { + WDT0_RESET_STS_W { w: self } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn wdt1_reset_sts(&mut self) -> WDT1_RESET_STS_W { + WDT1_RESET_STS_W { w: self } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn soft_reset_sts(&mut self) -> SOFT_RESET_STS_W { + SOFT_RESET_STS_W { w: self } + } + } + } + #[doc = "DMA handshake selector\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_sel0](dma_sel0) module"] + pub type DMA_SEL0 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMA_SEL0; + #[doc = "`read()` method returns [dma_sel0::R](dma_sel0::R) reader structure"] + impl crate::Readable for DMA_SEL0 {} + #[doc = "`write(|w| ..)` method takes [dma_sel0::W](dma_sel0::W) writer structure"] + impl crate::Writable for DMA_SEL0 {} + #[doc = "DMA handshake selector"] + pub mod dma_sel0 { + #[doc = "Reader of register dma_sel0"] + pub type R = crate::R; + #[doc = "Writer for register dma_sel0"] + pub type W = crate::W; + #[doc = "Register dma_sel0 `reset()`'s with value 0"] + impl crate::ResetValue for super::DMA_SEL0 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum DMA_SEL0_A { + #[doc = "0: `0`"] + SSI0_RX_REQ = 0, + #[doc = "1: `1`"] + SSI0_TX_REQ = 1, + #[doc = "2: `10`"] + SSI1_RX_REQ = 2, + #[doc = "3: `11`"] + SSI1_TX_REQ = 3, + #[doc = "4: `100`"] + SSI2_RX_REQ = 4, + #[doc = "5: `101`"] + SSI2_TX_REQ = 5, + #[doc = "6: `110`"] + SSI3_RX_REQ = 6, + #[doc = "7: `111`"] + SSI3_TX_REQ = 7, + #[doc = "8: `1000`"] + I2C0_RX_REQ = 8, + #[doc = "9: `1001`"] + I2C0_TX_REQ = 9, + #[doc = "10: `1010`"] + I2C1_RX_REQ = 10, + #[doc = "11: `1011`"] + I2C1_TX_REQ = 11, + #[doc = "12: `1100`"] + I2C2_RX_REQ = 12, + #[doc = "13: `1101`"] + I2C2_TX_REQ = 13, + #[doc = "14: `1110`"] + UART1_RX_REQ = 14, + #[doc = "15: `1111`"] + UART1_TX_REQ = 15, + #[doc = "16: `10000`"] + UART2_RX_REQ = 16, + #[doc = "17: `10001`"] + UART2_TX_REQ = 17, + #[doc = "18: `10010`"] + UART3_RX_REQ = 18, + #[doc = "19: `10011`"] + UART3_TX_REQ = 19, + #[doc = "20: `10100`"] + AES_REQ = 20, + #[doc = "21: `10101`"] + SHA_RX_REQ = 21, + #[doc = "22: `10110`"] + AI_RX_REQ = 22, + #[doc = "23: `10111`"] + FFT_RX_REQ = 23, + #[doc = "24: `11000`"] + FFT_TX_REQ = 24, + #[doc = "25: `11001`"] + I2S0_TX_REQ = 25, + #[doc = "26: `11010`"] + I2S0_RX_REQ = 26, + #[doc = "27: `11011`"] + I2S1_TX_REQ = 27, + #[doc = "28: `11100`"] + I2S1_RX_REQ = 28, + #[doc = "29: `11101`"] + I2S2_TX_REQ = 29, + #[doc = "30: `11110`"] + I2S2_RX_REQ = 30, + #[doc = "31: `11111`"] + I2S0_BF_DIR_REQ = 31, + #[doc = "32: `100000`"] + I2S0_BF_VOICE_REQ = 32, + } + impl From for u8 { + #[inline(always)] + fn from(variant: DMA_SEL0_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `dma_sel0`"] + pub type DMA_SEL0_R = crate::R; + impl DMA_SEL0_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(DMA_SEL0_A::SSI0_RX_REQ), + 1 => Val(DMA_SEL0_A::SSI0_TX_REQ), + 2 => Val(DMA_SEL0_A::SSI1_RX_REQ), + 3 => Val(DMA_SEL0_A::SSI1_TX_REQ), + 4 => Val(DMA_SEL0_A::SSI2_RX_REQ), + 5 => Val(DMA_SEL0_A::SSI2_TX_REQ), + 6 => Val(DMA_SEL0_A::SSI3_RX_REQ), + 7 => Val(DMA_SEL0_A::SSI3_TX_REQ), + 8 => Val(DMA_SEL0_A::I2C0_RX_REQ), + 9 => Val(DMA_SEL0_A::I2C0_TX_REQ), + 10 => Val(DMA_SEL0_A::I2C1_RX_REQ), + 11 => Val(DMA_SEL0_A::I2C1_TX_REQ), + 12 => Val(DMA_SEL0_A::I2C2_RX_REQ), + 13 => Val(DMA_SEL0_A::I2C2_TX_REQ), + 14 => Val(DMA_SEL0_A::UART1_RX_REQ), + 15 => Val(DMA_SEL0_A::UART1_TX_REQ), + 16 => Val(DMA_SEL0_A::UART2_RX_REQ), + 17 => Val(DMA_SEL0_A::UART2_TX_REQ), + 18 => Val(DMA_SEL0_A::UART3_RX_REQ), + 19 => Val(DMA_SEL0_A::UART3_TX_REQ), + 20 => Val(DMA_SEL0_A::AES_REQ), + 21 => Val(DMA_SEL0_A::SHA_RX_REQ), + 22 => Val(DMA_SEL0_A::AI_RX_REQ), + 23 => Val(DMA_SEL0_A::FFT_RX_REQ), + 24 => Val(DMA_SEL0_A::FFT_TX_REQ), + 25 => Val(DMA_SEL0_A::I2S0_TX_REQ), + 26 => Val(DMA_SEL0_A::I2S0_RX_REQ), + 27 => Val(DMA_SEL0_A::I2S1_TX_REQ), + 28 => Val(DMA_SEL0_A::I2S1_RX_REQ), + 29 => Val(DMA_SEL0_A::I2S2_TX_REQ), + 30 => Val(DMA_SEL0_A::I2S2_RX_REQ), + 31 => Val(DMA_SEL0_A::I2S0_BF_DIR_REQ), + 32 => Val(DMA_SEL0_A::I2S0_BF_VOICE_REQ), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `SSI0_RX_REQ`"] + #[inline(always)] + pub fn is_ssi0_rx_req(&self) -> bool { + *self == DMA_SEL0_A::SSI0_RX_REQ + } + #[doc = "Checks if the value of the field is `SSI0_TX_REQ`"] + #[inline(always)] + pub fn is_ssi0_tx_req(&self) -> bool { + *self == DMA_SEL0_A::SSI0_TX_REQ + } + #[doc = "Checks if the value of the field is `SSI1_RX_REQ`"] + #[inline(always)] + pub fn is_ssi1_rx_req(&self) -> bool { + *self == DMA_SEL0_A::SSI1_RX_REQ + } + #[doc = "Checks if the value of the field is `SSI1_TX_REQ`"] + #[inline(always)] + pub fn is_ssi1_tx_req(&self) -> bool { + *self == DMA_SEL0_A::SSI1_TX_REQ + } + #[doc = "Checks if the value of the field is `SSI2_RX_REQ`"] + #[inline(always)] + pub fn is_ssi2_rx_req(&self) -> bool { + *self == DMA_SEL0_A::SSI2_RX_REQ + } + #[doc = "Checks if the value of the field is `SSI2_TX_REQ`"] + #[inline(always)] + pub fn is_ssi2_tx_req(&self) -> bool { + *self == DMA_SEL0_A::SSI2_TX_REQ + } + #[doc = "Checks if the value of the field is `SSI3_RX_REQ`"] + #[inline(always)] + pub fn is_ssi3_rx_req(&self) -> bool { + *self == DMA_SEL0_A::SSI3_RX_REQ + } + #[doc = "Checks if the value of the field is `SSI3_TX_REQ`"] + #[inline(always)] + pub fn is_ssi3_tx_req(&self) -> bool { + *self == DMA_SEL0_A::SSI3_TX_REQ + } + #[doc = "Checks if the value of the field is `I2C0_RX_REQ`"] + #[inline(always)] + pub fn is_i2c0_rx_req(&self) -> bool { + *self == DMA_SEL0_A::I2C0_RX_REQ + } + #[doc = "Checks if the value of the field is `I2C0_TX_REQ`"] + #[inline(always)] + pub fn is_i2c0_tx_req(&self) -> bool { + *self == DMA_SEL0_A::I2C0_TX_REQ + } + #[doc = "Checks if the value of the field is `I2C1_RX_REQ`"] + #[inline(always)] + pub fn is_i2c1_rx_req(&self) -> bool { + *self == DMA_SEL0_A::I2C1_RX_REQ + } + #[doc = "Checks if the value of the field is `I2C1_TX_REQ`"] + #[inline(always)] + pub fn is_i2c1_tx_req(&self) -> bool { + *self == DMA_SEL0_A::I2C1_TX_REQ + } + #[doc = "Checks if the value of the field is `I2C2_RX_REQ`"] + #[inline(always)] + pub fn is_i2c2_rx_req(&self) -> bool { + *self == DMA_SEL0_A::I2C2_RX_REQ + } + #[doc = "Checks if the value of the field is `I2C2_TX_REQ`"] + #[inline(always)] + pub fn is_i2c2_tx_req(&self) -> bool { + *self == DMA_SEL0_A::I2C2_TX_REQ + } + #[doc = "Checks if the value of the field is `UART1_RX_REQ`"] + #[inline(always)] + pub fn is_uart1_rx_req(&self) -> bool { + *self == DMA_SEL0_A::UART1_RX_REQ + } + #[doc = "Checks if the value of the field is `UART1_TX_REQ`"] + #[inline(always)] + pub fn is_uart1_tx_req(&self) -> bool { + *self == DMA_SEL0_A::UART1_TX_REQ + } + #[doc = "Checks if the value of the field is `UART2_RX_REQ`"] + #[inline(always)] + pub fn is_uart2_rx_req(&self) -> bool { + *self == DMA_SEL0_A::UART2_RX_REQ + } + #[doc = "Checks if the value of the field is `UART2_TX_REQ`"] + #[inline(always)] + pub fn is_uart2_tx_req(&self) -> bool { + *self == DMA_SEL0_A::UART2_TX_REQ + } + #[doc = "Checks if the value of the field is `UART3_RX_REQ`"] + #[inline(always)] + pub fn is_uart3_rx_req(&self) -> bool { + *self == DMA_SEL0_A::UART3_RX_REQ + } + #[doc = "Checks if the value of the field is `UART3_TX_REQ`"] + #[inline(always)] + pub fn is_uart3_tx_req(&self) -> bool { + *self == DMA_SEL0_A::UART3_TX_REQ + } + #[doc = "Checks if the value of the field is `AES_REQ`"] + #[inline(always)] + pub fn is_aes_req(&self) -> bool { + *self == DMA_SEL0_A::AES_REQ + } + #[doc = "Checks if the value of the field is `SHA_RX_REQ`"] + #[inline(always)] + pub fn is_sha_rx_req(&self) -> bool { + *self == DMA_SEL0_A::SHA_RX_REQ + } + #[doc = "Checks if the value of the field is `AI_RX_REQ`"] + #[inline(always)] + pub fn is_ai_rx_req(&self) -> bool { + *self == DMA_SEL0_A::AI_RX_REQ + } + #[doc = "Checks if the value of the field is `FFT_RX_REQ`"] + #[inline(always)] + pub fn is_fft_rx_req(&self) -> bool { + *self == DMA_SEL0_A::FFT_RX_REQ + } + #[doc = "Checks if the value of the field is `FFT_TX_REQ`"] + #[inline(always)] + pub fn is_fft_tx_req(&self) -> bool { + *self == DMA_SEL0_A::FFT_TX_REQ + } + #[doc = "Checks if the value of the field is `I2S0_TX_REQ`"] + #[inline(always)] + pub fn is_i2s0_tx_req(&self) -> bool { + *self == DMA_SEL0_A::I2S0_TX_REQ + } + #[doc = "Checks if the value of the field is `I2S0_RX_REQ`"] + #[inline(always)] + pub fn is_i2s0_rx_req(&self) -> bool { + *self == DMA_SEL0_A::I2S0_RX_REQ + } + #[doc = "Checks if the value of the field is `I2S1_TX_REQ`"] + #[inline(always)] + pub fn is_i2s1_tx_req(&self) -> bool { + *self == DMA_SEL0_A::I2S1_TX_REQ + } + #[doc = "Checks if the value of the field is `I2S1_RX_REQ`"] + #[inline(always)] + pub fn is_i2s1_rx_req(&self) -> bool { + *self == DMA_SEL0_A::I2S1_RX_REQ + } + #[doc = "Checks if the value of the field is `I2S2_TX_REQ`"] + #[inline(always)] + pub fn is_i2s2_tx_req(&self) -> bool { + *self == DMA_SEL0_A::I2S2_TX_REQ + } + #[doc = "Checks if the value of the field is `I2S2_RX_REQ`"] + #[inline(always)] + pub fn is_i2s2_rx_req(&self) -> bool { + *self == DMA_SEL0_A::I2S2_RX_REQ + } + #[doc = "Checks if the value of the field is `I2S0_BF_DIR_REQ`"] + #[inline(always)] + pub fn is_i2s0_bf_dir_req(&self) -> bool { + *self == DMA_SEL0_A::I2S0_BF_DIR_REQ + } + #[doc = "Checks if the value of the field is `I2S0_BF_VOICE_REQ`"] + #[inline(always)] + pub fn is_i2s0_bf_voice_req(&self) -> bool { + *self == DMA_SEL0_A::I2S0_BF_VOICE_REQ + } + } + #[doc = "Write proxy for field `dma_sel0`"] + pub struct DMA_SEL0_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_SEL0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DMA_SEL0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "`0`"] + #[inline(always)] + pub fn ssi0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::SSI0_RX_REQ) + } + #[doc = "`1`"] + #[inline(always)] + pub fn ssi0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::SSI0_TX_REQ) + } + #[doc = "`10`"] + #[inline(always)] + pub fn ssi1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::SSI1_RX_REQ) + } + #[doc = "`11`"] + #[inline(always)] + pub fn ssi1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::SSI1_TX_REQ) + } + #[doc = "`100`"] + #[inline(always)] + pub fn ssi2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::SSI2_RX_REQ) + } + #[doc = "`101`"] + #[inline(always)] + pub fn ssi2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::SSI2_TX_REQ) + } + #[doc = "`110`"] + #[inline(always)] + pub fn ssi3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::SSI3_RX_REQ) + } + #[doc = "`111`"] + #[inline(always)] + pub fn ssi3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::SSI3_TX_REQ) + } + #[doc = "`1000`"] + #[inline(always)] + pub fn i2c0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2C0_RX_REQ) + } + #[doc = "`1001`"] + #[inline(always)] + pub fn i2c0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2C0_TX_REQ) + } + #[doc = "`1010`"] + #[inline(always)] + pub fn i2c1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2C1_RX_REQ) + } + #[doc = "`1011`"] + #[inline(always)] + pub fn i2c1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2C1_TX_REQ) + } + #[doc = "`1100`"] + #[inline(always)] + pub fn i2c2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2C2_RX_REQ) + } + #[doc = "`1101`"] + #[inline(always)] + pub fn i2c2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2C2_TX_REQ) + } + #[doc = "`1110`"] + #[inline(always)] + pub fn uart1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::UART1_RX_REQ) + } + #[doc = "`1111`"] + #[inline(always)] + pub fn uart1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::UART1_TX_REQ) + } + #[doc = "`10000`"] + #[inline(always)] + pub fn uart2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::UART2_RX_REQ) + } + #[doc = "`10001`"] + #[inline(always)] + pub fn uart2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::UART2_TX_REQ) + } + #[doc = "`10010`"] + #[inline(always)] + pub fn uart3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::UART3_RX_REQ) + } + #[doc = "`10011`"] + #[inline(always)] + pub fn uart3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::UART3_TX_REQ) + } + #[doc = "`10100`"] + #[inline(always)] + pub fn aes_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::AES_REQ) + } + #[doc = "`10101`"] + #[inline(always)] + pub fn sha_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::SHA_RX_REQ) + } + #[doc = "`10110`"] + #[inline(always)] + pub fn ai_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::AI_RX_REQ) + } + #[doc = "`10111`"] + #[inline(always)] + pub fn fft_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::FFT_RX_REQ) + } + #[doc = "`11000`"] + #[inline(always)] + pub fn fft_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::FFT_TX_REQ) + } + #[doc = "`11001`"] + #[inline(always)] + pub fn i2s0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2S0_TX_REQ) + } + #[doc = "`11010`"] + #[inline(always)] + pub fn i2s0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2S0_RX_REQ) + } + #[doc = "`11011`"] + #[inline(always)] + pub fn i2s1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2S1_TX_REQ) + } + #[doc = "`11100`"] + #[inline(always)] + pub fn i2s1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2S1_RX_REQ) + } + #[doc = "`11101`"] + #[inline(always)] + pub fn i2s2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2S2_TX_REQ) + } + #[doc = "`11110`"] + #[inline(always)] + pub fn i2s2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2S2_RX_REQ) + } + #[doc = "`11111`"] + #[inline(always)] + pub fn i2s0_bf_dir_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2S0_BF_DIR_REQ) + } + #[doc = "`100000`"] + #[inline(always)] + pub fn i2s0_bf_voice_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2S0_BF_VOICE_REQ) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | ((value as u32) & 0x3f); + self.w + } + } + #[doc = ""] + pub type DMA_SEL1_A = DMA_SEL0_A; + #[doc = "Reader of field `dma_sel1`"] + pub type DMA_SEL1_R = crate::R; + #[doc = "Write proxy for field `dma_sel1`"] + pub struct DMA_SEL1_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_SEL1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DMA_SEL1_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "`0`"] + #[inline(always)] + pub fn ssi0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::SSI0_RX_REQ) + } + #[doc = "`1`"] + #[inline(always)] + pub fn ssi0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::SSI0_TX_REQ) + } + #[doc = "`10`"] + #[inline(always)] + pub fn ssi1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::SSI1_RX_REQ) + } + #[doc = "`11`"] + #[inline(always)] + pub fn ssi1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::SSI1_TX_REQ) + } + #[doc = "`100`"] + #[inline(always)] + pub fn ssi2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::SSI2_RX_REQ) + } + #[doc = "`101`"] + #[inline(always)] + pub fn ssi2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::SSI2_TX_REQ) + } + #[doc = "`110`"] + #[inline(always)] + pub fn ssi3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::SSI3_RX_REQ) + } + #[doc = "`111`"] + #[inline(always)] + pub fn ssi3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::SSI3_TX_REQ) + } + #[doc = "`1000`"] + #[inline(always)] + pub fn i2c0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2C0_RX_REQ) + } + #[doc = "`1001`"] + #[inline(always)] + pub fn i2c0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2C0_TX_REQ) + } + #[doc = "`1010`"] + #[inline(always)] + pub fn i2c1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2C1_RX_REQ) + } + #[doc = "`1011`"] + #[inline(always)] + pub fn i2c1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2C1_TX_REQ) + } + #[doc = "`1100`"] + #[inline(always)] + pub fn i2c2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2C2_RX_REQ) + } + #[doc = "`1101`"] + #[inline(always)] + pub fn i2c2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2C2_TX_REQ) + } + #[doc = "`1110`"] + #[inline(always)] + pub fn uart1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::UART1_RX_REQ) + } + #[doc = "`1111`"] + #[inline(always)] + pub fn uart1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::UART1_TX_REQ) + } + #[doc = "`10000`"] + #[inline(always)] + pub fn uart2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::UART2_RX_REQ) + } + #[doc = "`10001`"] + #[inline(always)] + pub fn uart2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::UART2_TX_REQ) + } + #[doc = "`10010`"] + #[inline(always)] + pub fn uart3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::UART3_RX_REQ) + } + #[doc = "`10011`"] + #[inline(always)] + pub fn uart3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::UART3_TX_REQ) + } + #[doc = "`10100`"] + #[inline(always)] + pub fn aes_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::AES_REQ) + } + #[doc = "`10101`"] + #[inline(always)] + pub fn sha_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::SHA_RX_REQ) + } + #[doc = "`10110`"] + #[inline(always)] + pub fn ai_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::AI_RX_REQ) + } + #[doc = "`10111`"] + #[inline(always)] + pub fn fft_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::FFT_RX_REQ) + } + #[doc = "`11000`"] + #[inline(always)] + pub fn fft_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::FFT_TX_REQ) + } + #[doc = "`11001`"] + #[inline(always)] + pub fn i2s0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2S0_TX_REQ) + } + #[doc = "`11010`"] + #[inline(always)] + pub fn i2s0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2S0_RX_REQ) + } + #[doc = "`11011`"] + #[inline(always)] + pub fn i2s1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2S1_TX_REQ) + } + #[doc = "`11100`"] + #[inline(always)] + pub fn i2s1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2S1_RX_REQ) + } + #[doc = "`11101`"] + #[inline(always)] + pub fn i2s2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2S2_TX_REQ) + } + #[doc = "`11110`"] + #[inline(always)] + pub fn i2s2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2S2_RX_REQ) + } + #[doc = "`11111`"] + #[inline(always)] + pub fn i2s0_bf_dir_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2S0_BF_DIR_REQ) + } + #[doc = "`100000`"] + #[inline(always)] + pub fn i2s0_bf_voice_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2S0_BF_VOICE_REQ) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | (((value as u32) & 0x3f) << 6); + self.w + } + } + #[doc = ""] + pub type DMA_SEL2_A = DMA_SEL0_A; + #[doc = "Reader of field `dma_sel2`"] + pub type DMA_SEL2_R = crate::R; + #[doc = "Write proxy for field `dma_sel2`"] + pub struct DMA_SEL2_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_SEL2_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DMA_SEL2_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "`0`"] + #[inline(always)] + pub fn ssi0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::SSI0_RX_REQ) + } + #[doc = "`1`"] + #[inline(always)] + pub fn ssi0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::SSI0_TX_REQ) + } + #[doc = "`10`"] + #[inline(always)] + pub fn ssi1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::SSI1_RX_REQ) + } + #[doc = "`11`"] + #[inline(always)] + pub fn ssi1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::SSI1_TX_REQ) + } + #[doc = "`100`"] + #[inline(always)] + pub fn ssi2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::SSI2_RX_REQ) + } + #[doc = "`101`"] + #[inline(always)] + pub fn ssi2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::SSI2_TX_REQ) + } + #[doc = "`110`"] + #[inline(always)] + pub fn ssi3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::SSI3_RX_REQ) + } + #[doc = "`111`"] + #[inline(always)] + pub fn ssi3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::SSI3_TX_REQ) + } + #[doc = "`1000`"] + #[inline(always)] + pub fn i2c0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2C0_RX_REQ) + } + #[doc = "`1001`"] + #[inline(always)] + pub fn i2c0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2C0_TX_REQ) + } + #[doc = "`1010`"] + #[inline(always)] + pub fn i2c1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2C1_RX_REQ) + } + #[doc = "`1011`"] + #[inline(always)] + pub fn i2c1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2C1_TX_REQ) + } + #[doc = "`1100`"] + #[inline(always)] + pub fn i2c2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2C2_RX_REQ) + } + #[doc = "`1101`"] + #[inline(always)] + pub fn i2c2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2C2_TX_REQ) + } + #[doc = "`1110`"] + #[inline(always)] + pub fn uart1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::UART1_RX_REQ) + } + #[doc = "`1111`"] + #[inline(always)] + pub fn uart1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::UART1_TX_REQ) + } + #[doc = "`10000`"] + #[inline(always)] + pub fn uart2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::UART2_RX_REQ) + } + #[doc = "`10001`"] + #[inline(always)] + pub fn uart2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::UART2_TX_REQ) + } + #[doc = "`10010`"] + #[inline(always)] + pub fn uart3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::UART3_RX_REQ) + } + #[doc = "`10011`"] + #[inline(always)] + pub fn uart3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::UART3_TX_REQ) + } + #[doc = "`10100`"] + #[inline(always)] + pub fn aes_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::AES_REQ) + } + #[doc = "`10101`"] + #[inline(always)] + pub fn sha_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::SHA_RX_REQ) + } + #[doc = "`10110`"] + #[inline(always)] + pub fn ai_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::AI_RX_REQ) + } + #[doc = "`10111`"] + #[inline(always)] + pub fn fft_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::FFT_RX_REQ) + } + #[doc = "`11000`"] + #[inline(always)] + pub fn fft_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::FFT_TX_REQ) + } + #[doc = "`11001`"] + #[inline(always)] + pub fn i2s0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2S0_TX_REQ) + } + #[doc = "`11010`"] + #[inline(always)] + pub fn i2s0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2S0_RX_REQ) + } + #[doc = "`11011`"] + #[inline(always)] + pub fn i2s1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2S1_TX_REQ) + } + #[doc = "`11100`"] + #[inline(always)] + pub fn i2s1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2S1_RX_REQ) + } + #[doc = "`11101`"] + #[inline(always)] + pub fn i2s2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2S2_TX_REQ) + } + #[doc = "`11110`"] + #[inline(always)] + pub fn i2s2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2S2_RX_REQ) + } + #[doc = "`11111`"] + #[inline(always)] + pub fn i2s0_bf_dir_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2S0_BF_DIR_REQ) + } + #[doc = "`100000`"] + #[inline(always)] + pub fn i2s0_bf_voice_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2S0_BF_VOICE_REQ) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 12)) | (((value as u32) & 0x3f) << 12); + self.w + } + } + #[doc = ""] + pub type DMA_SEL3_A = DMA_SEL0_A; + #[doc = "Reader of field `dma_sel3`"] + pub type DMA_SEL3_R = crate::R; + #[doc = "Write proxy for field `dma_sel3`"] + pub struct DMA_SEL3_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_SEL3_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DMA_SEL3_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "`0`"] + #[inline(always)] + pub fn ssi0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::SSI0_RX_REQ) + } + #[doc = "`1`"] + #[inline(always)] + pub fn ssi0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::SSI0_TX_REQ) + } + #[doc = "`10`"] + #[inline(always)] + pub fn ssi1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::SSI1_RX_REQ) + } + #[doc = "`11`"] + #[inline(always)] + pub fn ssi1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::SSI1_TX_REQ) + } + #[doc = "`100`"] + #[inline(always)] + pub fn ssi2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::SSI2_RX_REQ) + } + #[doc = "`101`"] + #[inline(always)] + pub fn ssi2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::SSI2_TX_REQ) + } + #[doc = "`110`"] + #[inline(always)] + pub fn ssi3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::SSI3_RX_REQ) + } + #[doc = "`111`"] + #[inline(always)] + pub fn ssi3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::SSI3_TX_REQ) + } + #[doc = "`1000`"] + #[inline(always)] + pub fn i2c0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2C0_RX_REQ) + } + #[doc = "`1001`"] + #[inline(always)] + pub fn i2c0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2C0_TX_REQ) + } + #[doc = "`1010`"] + #[inline(always)] + pub fn i2c1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2C1_RX_REQ) + } + #[doc = "`1011`"] + #[inline(always)] + pub fn i2c1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2C1_TX_REQ) + } + #[doc = "`1100`"] + #[inline(always)] + pub fn i2c2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2C2_RX_REQ) + } + #[doc = "`1101`"] + #[inline(always)] + pub fn i2c2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2C2_TX_REQ) + } + #[doc = "`1110`"] + #[inline(always)] + pub fn uart1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::UART1_RX_REQ) + } + #[doc = "`1111`"] + #[inline(always)] + pub fn uart1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::UART1_TX_REQ) + } + #[doc = "`10000`"] + #[inline(always)] + pub fn uart2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::UART2_RX_REQ) + } + #[doc = "`10001`"] + #[inline(always)] + pub fn uart2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::UART2_TX_REQ) + } + #[doc = "`10010`"] + #[inline(always)] + pub fn uart3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::UART3_RX_REQ) + } + #[doc = "`10011`"] + #[inline(always)] + pub fn uart3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::UART3_TX_REQ) + } + #[doc = "`10100`"] + #[inline(always)] + pub fn aes_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::AES_REQ) + } + #[doc = "`10101`"] + #[inline(always)] + pub fn sha_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::SHA_RX_REQ) + } + #[doc = "`10110`"] + #[inline(always)] + pub fn ai_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::AI_RX_REQ) + } + #[doc = "`10111`"] + #[inline(always)] + pub fn fft_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::FFT_RX_REQ) + } + #[doc = "`11000`"] + #[inline(always)] + pub fn fft_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::FFT_TX_REQ) + } + #[doc = "`11001`"] + #[inline(always)] + pub fn i2s0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2S0_TX_REQ) + } + #[doc = "`11010`"] + #[inline(always)] + pub fn i2s0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2S0_RX_REQ) + } + #[doc = "`11011`"] + #[inline(always)] + pub fn i2s1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2S1_TX_REQ) + } + #[doc = "`11100`"] + #[inline(always)] + pub fn i2s1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2S1_RX_REQ) + } + #[doc = "`11101`"] + #[inline(always)] + pub fn i2s2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2S2_TX_REQ) + } + #[doc = "`11110`"] + #[inline(always)] + pub fn i2s2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2S2_RX_REQ) + } + #[doc = "`11111`"] + #[inline(always)] + pub fn i2s0_bf_dir_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2S0_BF_DIR_REQ) + } + #[doc = "`100000`"] + #[inline(always)] + pub fn i2s0_bf_voice_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2S0_BF_VOICE_REQ) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 18)) | (((value as u32) & 0x3f) << 18); + self.w + } + } + #[doc = ""] + pub type DMA_SEL4_A = DMA_SEL0_A; + #[doc = "Reader of field `dma_sel4`"] + pub type DMA_SEL4_R = crate::R; + #[doc = "Write proxy for field `dma_sel4`"] + pub struct DMA_SEL4_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_SEL4_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DMA_SEL4_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "`0`"] + #[inline(always)] + pub fn ssi0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::SSI0_RX_REQ) + } + #[doc = "`1`"] + #[inline(always)] + pub fn ssi0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::SSI0_TX_REQ) + } + #[doc = "`10`"] + #[inline(always)] + pub fn ssi1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::SSI1_RX_REQ) + } + #[doc = "`11`"] + #[inline(always)] + pub fn ssi1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::SSI1_TX_REQ) + } + #[doc = "`100`"] + #[inline(always)] + pub fn ssi2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::SSI2_RX_REQ) + } + #[doc = "`101`"] + #[inline(always)] + pub fn ssi2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::SSI2_TX_REQ) + } + #[doc = "`110`"] + #[inline(always)] + pub fn ssi3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::SSI3_RX_REQ) + } + #[doc = "`111`"] + #[inline(always)] + pub fn ssi3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::SSI3_TX_REQ) + } + #[doc = "`1000`"] + #[inline(always)] + pub fn i2c0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2C0_RX_REQ) + } + #[doc = "`1001`"] + #[inline(always)] + pub fn i2c0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2C0_TX_REQ) + } + #[doc = "`1010`"] + #[inline(always)] + pub fn i2c1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2C1_RX_REQ) + } + #[doc = "`1011`"] + #[inline(always)] + pub fn i2c1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2C1_TX_REQ) + } + #[doc = "`1100`"] + #[inline(always)] + pub fn i2c2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2C2_RX_REQ) + } + #[doc = "`1101`"] + #[inline(always)] + pub fn i2c2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2C2_TX_REQ) + } + #[doc = "`1110`"] + #[inline(always)] + pub fn uart1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::UART1_RX_REQ) + } + #[doc = "`1111`"] + #[inline(always)] + pub fn uart1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::UART1_TX_REQ) + } + #[doc = "`10000`"] + #[inline(always)] + pub fn uart2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::UART2_RX_REQ) + } + #[doc = "`10001`"] + #[inline(always)] + pub fn uart2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::UART2_TX_REQ) + } + #[doc = "`10010`"] + #[inline(always)] + pub fn uart3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::UART3_RX_REQ) + } + #[doc = "`10011`"] + #[inline(always)] + pub fn uart3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::UART3_TX_REQ) + } + #[doc = "`10100`"] + #[inline(always)] + pub fn aes_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::AES_REQ) + } + #[doc = "`10101`"] + #[inline(always)] + pub fn sha_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::SHA_RX_REQ) + } + #[doc = "`10110`"] + #[inline(always)] + pub fn ai_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::AI_RX_REQ) + } + #[doc = "`10111`"] + #[inline(always)] + pub fn fft_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::FFT_RX_REQ) + } + #[doc = "`11000`"] + #[inline(always)] + pub fn fft_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::FFT_TX_REQ) + } + #[doc = "`11001`"] + #[inline(always)] + pub fn i2s0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2S0_TX_REQ) + } + #[doc = "`11010`"] + #[inline(always)] + pub fn i2s0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2S0_RX_REQ) + } + #[doc = "`11011`"] + #[inline(always)] + pub fn i2s1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2S1_TX_REQ) + } + #[doc = "`11100`"] + #[inline(always)] + pub fn i2s1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2S1_RX_REQ) + } + #[doc = "`11101`"] + #[inline(always)] + pub fn i2s2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2S2_TX_REQ) + } + #[doc = "`11110`"] + #[inline(always)] + pub fn i2s2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2S2_RX_REQ) + } + #[doc = "`11111`"] + #[inline(always)] + pub fn i2s0_bf_dir_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2S0_BF_DIR_REQ) + } + #[doc = "`100000`"] + #[inline(always)] + pub fn i2s0_bf_voice_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2S0_BF_VOICE_REQ) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 24)) | (((value as u32) & 0x3f) << 24); + self.w + } + } + impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn dma_sel0(&self) -> DMA_SEL0_R { + DMA_SEL0_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11"] + #[inline(always)] + pub fn dma_sel1(&self) -> DMA_SEL1_R { + DMA_SEL1_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:17"] + #[inline(always)] + pub fn dma_sel2(&self) -> DMA_SEL2_R { + DMA_SEL2_R::new(((self.bits >> 12) & 0x3f) as u8) + } + #[doc = "Bits 18:23"] + #[inline(always)] + pub fn dma_sel3(&self) -> DMA_SEL3_R { + DMA_SEL3_R::new(((self.bits >> 18) & 0x3f) as u8) + } + #[doc = "Bits 24:29"] + #[inline(always)] + pub fn dma_sel4(&self) -> DMA_SEL4_R { + DMA_SEL4_R::new(((self.bits >> 24) & 0x3f) as u8) + } + } + impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn dma_sel0(&mut self) -> DMA_SEL0_W { + DMA_SEL0_W { w: self } + } + #[doc = "Bits 6:11"] + #[inline(always)] + pub fn dma_sel1(&mut self) -> DMA_SEL1_W { + DMA_SEL1_W { w: self } + } + #[doc = "Bits 12:17"] + #[inline(always)] + pub fn dma_sel2(&mut self) -> DMA_SEL2_W { + DMA_SEL2_W { w: self } + } + #[doc = "Bits 18:23"] + #[inline(always)] + pub fn dma_sel3(&mut self) -> DMA_SEL3_W { + DMA_SEL3_W { w: self } + } + #[doc = "Bits 24:29"] + #[inline(always)] + pub fn dma_sel4(&mut self) -> DMA_SEL4_W { + DMA_SEL4_W { w: self } + } + } + } + #[doc = "DMA handshake selector\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_sel1](dma_sel1) module"] + pub type DMA_SEL1 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMA_SEL1; + #[doc = "`read()` method returns [dma_sel1::R](dma_sel1::R) reader structure"] + impl crate::Readable for DMA_SEL1 {} + #[doc = "`write(|w| ..)` method takes [dma_sel1::W](dma_sel1::W) writer structure"] + impl crate::Writable for DMA_SEL1 {} + #[doc = "DMA handshake selector"] + pub mod dma_sel1 { + #[doc = "Reader of register dma_sel1"] + pub type R = crate::R; + #[doc = "Writer for register dma_sel1"] + pub type W = crate::W; + #[doc = "Register dma_sel1 `reset()`'s with value 0"] + impl crate::ResetValue for super::DMA_SEL1 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = ""] + pub type DMA_SEL5_A = super::dma_sel0::DMA_SEL0_A; + #[doc = "Reader of field `dma_sel5`"] + pub type DMA_SEL5_R = crate::R; + #[doc = "Write proxy for field `dma_sel5`"] + pub struct DMA_SEL5_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_SEL5_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DMA_SEL5_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "`0`"] + #[inline(always)] + pub fn ssi0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::SSI0_RX_REQ) + } + #[doc = "`1`"] + #[inline(always)] + pub fn ssi0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::SSI0_TX_REQ) + } + #[doc = "`10`"] + #[inline(always)] + pub fn ssi1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::SSI1_RX_REQ) + } + #[doc = "`11`"] + #[inline(always)] + pub fn ssi1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::SSI1_TX_REQ) + } + #[doc = "`100`"] + #[inline(always)] + pub fn ssi2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::SSI2_RX_REQ) + } + #[doc = "`101`"] + #[inline(always)] + pub fn ssi2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::SSI2_TX_REQ) + } + #[doc = "`110`"] + #[inline(always)] + pub fn ssi3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::SSI3_RX_REQ) + } + #[doc = "`111`"] + #[inline(always)] + pub fn ssi3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::SSI3_TX_REQ) + } + #[doc = "`1000`"] + #[inline(always)] + pub fn i2c0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2C0_RX_REQ) + } + #[doc = "`1001`"] + #[inline(always)] + pub fn i2c0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2C0_TX_REQ) + } + #[doc = "`1010`"] + #[inline(always)] + pub fn i2c1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2C1_RX_REQ) + } + #[doc = "`1011`"] + #[inline(always)] + pub fn i2c1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2C1_TX_REQ) + } + #[doc = "`1100`"] + #[inline(always)] + pub fn i2c2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2C2_RX_REQ) + } + #[doc = "`1101`"] + #[inline(always)] + pub fn i2c2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2C2_TX_REQ) + } + #[doc = "`1110`"] + #[inline(always)] + pub fn uart1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::UART1_RX_REQ) + } + #[doc = "`1111`"] + #[inline(always)] + pub fn uart1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::UART1_TX_REQ) + } + #[doc = "`10000`"] + #[inline(always)] + pub fn uart2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::UART2_RX_REQ) + } + #[doc = "`10001`"] + #[inline(always)] + pub fn uart2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::UART2_TX_REQ) + } + #[doc = "`10010`"] + #[inline(always)] + pub fn uart3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::UART3_RX_REQ) + } + #[doc = "`10011`"] + #[inline(always)] + pub fn uart3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::UART3_TX_REQ) + } + #[doc = "`10100`"] + #[inline(always)] + pub fn aes_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::AES_REQ) + } + #[doc = "`10101`"] + #[inline(always)] + pub fn sha_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::SHA_RX_REQ) + } + #[doc = "`10110`"] + #[inline(always)] + pub fn ai_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::AI_RX_REQ) + } + #[doc = "`10111`"] + #[inline(always)] + pub fn fft_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::FFT_RX_REQ) + } + #[doc = "`11000`"] + #[inline(always)] + pub fn fft_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::FFT_TX_REQ) + } + #[doc = "`11001`"] + #[inline(always)] + pub fn i2s0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2S0_TX_REQ) + } + #[doc = "`11010`"] + #[inline(always)] + pub fn i2s0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2S0_RX_REQ) + } + #[doc = "`11011`"] + #[inline(always)] + pub fn i2s1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2S1_TX_REQ) + } + #[doc = "`11100`"] + #[inline(always)] + pub fn i2s1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2S1_RX_REQ) + } + #[doc = "`11101`"] + #[inline(always)] + pub fn i2s2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2S2_TX_REQ) + } + #[doc = "`11110`"] + #[inline(always)] + pub fn i2s2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2S2_RX_REQ) + } + #[doc = "`11111`"] + #[inline(always)] + pub fn i2s0_bf_dir_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2S0_BF_DIR_REQ) + } + #[doc = "`100000`"] + #[inline(always)] + pub fn i2s0_bf_voice_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2S0_BF_VOICE_REQ) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | ((value as u32) & 0x3f); + self.w + } + } + impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn dma_sel5(&self) -> DMA_SEL5_R { + DMA_SEL5_R::new((self.bits & 0x3f) as u8) + } + } + impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn dma_sel5(&mut self) -> DMA_SEL5_W { + DMA_SEL5_W { w: self } + } + } + } + #[doc = "IO Power Mode Select controller\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [power_sel](power_sel) module"] + pub type POWER_SEL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _POWER_SEL; + #[doc = "`read()` method returns [power_sel::R](power_sel::R) reader structure"] + impl crate::Readable for POWER_SEL {} + #[doc = "`write(|w| ..)` method takes [power_sel::W](power_sel::W) writer structure"] + impl crate::Writable for POWER_SEL {} + #[doc = "IO Power Mode Select controller"] + pub mod power_sel { + #[doc = "Reader of register power_sel"] + pub type R = crate::R; + #[doc = "Writer for register power_sel"] + pub type W = crate::W; + #[doc = "Register power_sel `reset()`'s with value 0"] + impl crate::ResetValue for super::POWER_SEL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `power_mode_sel0`"] + pub type POWER_MODE_SEL0_R = crate::R; + #[doc = "Write proxy for field `power_mode_sel0`"] + pub struct POWER_MODE_SEL0_W<'a> { + w: &'a mut W, + } + impl<'a> POWER_MODE_SEL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `power_mode_sel1`"] + pub type POWER_MODE_SEL1_R = crate::R; + #[doc = "Write proxy for field `power_mode_sel1`"] + pub struct POWER_MODE_SEL1_W<'a> { + w: &'a mut W, + } + impl<'a> POWER_MODE_SEL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `power_mode_sel2`"] + pub type POWER_MODE_SEL2_R = crate::R; + #[doc = "Write proxy for field `power_mode_sel2`"] + pub struct POWER_MODE_SEL2_W<'a> { + w: &'a mut W, + } + impl<'a> POWER_MODE_SEL2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `power_mode_sel3`"] + pub type POWER_MODE_SEL3_R = crate::R; + #[doc = "Write proxy for field `power_mode_sel3`"] + pub struct POWER_MODE_SEL3_W<'a> { + w: &'a mut W, + } + impl<'a> POWER_MODE_SEL3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `power_mode_sel4`"] + pub type POWER_MODE_SEL4_R = crate::R; + #[doc = "Write proxy for field `power_mode_sel4`"] + pub struct POWER_MODE_SEL4_W<'a> { + w: &'a mut W, + } + impl<'a> POWER_MODE_SEL4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `power_mode_sel5`"] + pub type POWER_MODE_SEL5_R = crate::R; + #[doc = "Write proxy for field `power_mode_sel5`"] + pub struct POWER_MODE_SEL5_W<'a> { + w: &'a mut W, + } + impl<'a> POWER_MODE_SEL5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `power_mode_sel6`"] + pub type POWER_MODE_SEL6_R = crate::R; + #[doc = "Write proxy for field `power_mode_sel6`"] + pub struct POWER_MODE_SEL6_W<'a> { + w: &'a mut W, + } + impl<'a> POWER_MODE_SEL6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `power_mode_sel7`"] + pub type POWER_MODE_SEL7_R = crate::R; + #[doc = "Write proxy for field `power_mode_sel7`"] + pub struct POWER_MODE_SEL7_W<'a> { + w: &'a mut W, + } + impl<'a> POWER_MODE_SEL7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); + self.w + } + } + impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn power_mode_sel0(&self) -> POWER_MODE_SEL0_R { + POWER_MODE_SEL0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn power_mode_sel1(&self) -> POWER_MODE_SEL1_R { + POWER_MODE_SEL1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn power_mode_sel2(&self) -> POWER_MODE_SEL2_R { + POWER_MODE_SEL2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn power_mode_sel3(&self) -> POWER_MODE_SEL3_R { + POWER_MODE_SEL3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn power_mode_sel4(&self) -> POWER_MODE_SEL4_R { + POWER_MODE_SEL4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn power_mode_sel5(&self) -> POWER_MODE_SEL5_R { + POWER_MODE_SEL5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn power_mode_sel6(&self) -> POWER_MODE_SEL6_R { + POWER_MODE_SEL6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn power_mode_sel7(&self) -> POWER_MODE_SEL7_R { + POWER_MODE_SEL7_R::new(((self.bits >> 7) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn power_mode_sel0(&mut self) -> POWER_MODE_SEL0_W { + POWER_MODE_SEL0_W { w: self } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn power_mode_sel1(&mut self) -> POWER_MODE_SEL1_W { + POWER_MODE_SEL1_W { w: self } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn power_mode_sel2(&mut self) -> POWER_MODE_SEL2_W { + POWER_MODE_SEL2_W { w: self } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn power_mode_sel3(&mut self) -> POWER_MODE_SEL3_W { + POWER_MODE_SEL3_W { w: self } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn power_mode_sel4(&mut self) -> POWER_MODE_SEL4_W { + POWER_MODE_SEL4_W { w: self } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn power_mode_sel5(&mut self) -> POWER_MODE_SEL5_W { + POWER_MODE_SEL5_W { w: self } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn power_mode_sel6(&mut self) -> POWER_MODE_SEL6_W { + POWER_MODE_SEL6_W { w: self } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn power_mode_sel7(&mut self) -> POWER_MODE_SEL7_W { + POWER_MODE_SEL7_W { w: self } + } + } + } +} +#[doc = "AES Accelerator"] +pub struct AES { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for AES {} +impl AES { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const aes::RegisterBlock { + 0x5045_0000 as *const _ + } +} +impl Deref for AES { + type Target = aes::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*AES::ptr() } + } +} +#[doc = "AES Accelerator"] +pub mod aes { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - 1st-4th word of key"] + pub key: [KEY; 4], + #[doc = "0x10 - Encryption or decryption select"] + pub encrypt_sel: ENCRYPT_SEL, + #[doc = "0x14 - AES mode register"] + pub mode_ctl: MODE_CTL, + #[doc = "0x18 - Initialisation Vector (96 bit for GCM, 128 bit for CBC)"] + pub iv: [IV; 4], + #[doc = "0x28 - Endian control"] + pub endian: ENDIAN, + #[doc = "0x2c - Finished status"] + pub finish: FINISH, + #[doc = "0x30 - DMA select"] + pub dma_sel: DMA_SEL, + #[doc = "0x34 - GCM additional authenticated data count in bytes, minus one"] + pub aad_num: AAD_NUM, + _reserved8: [u8; 4usize], + #[doc = "0x3c - Plaintext/ciphertext input data count in bytes, minus one"] + pub pc_num: PC_NUM, + #[doc = "0x40 - Plaintext/ciphertext input data"] + pub text_data: TEXT_DATA, + #[doc = "0x44 - Additional authenticated data"] + pub aad_data: AAD_DATA, + #[doc = "0x48 - Tag check status"] + pub tag_chk: TAG_CHK, + #[doc = "0x4c - Data can input flag"] + pub data_in_flag: DATA_IN_FLAG, + #[doc = "0x50 - GCM input tag for comparison with the calculated tag"] + pub gcm_in_tag: [GCM_IN_TAG; 4], + #[doc = "0x60 - Plaintext/ciphertext output data"] + pub out_data: OUT_DATA, + #[doc = "0x64 - AES module enable"] + pub en: EN, + #[doc = "0x68 - Data can output flag"] + pub data_out_flag: DATA_OUT_FLAG, + #[doc = "0x6c - Can input tag (when using GCM)"] + pub tag_in_flag: TAG_IN_FLAG, + #[doc = "0x70 - Tag clear (a write to this register clears the tag_chk status)"] + pub tag_clear: TAG_CLEAR, + #[doc = "0x74 - Computed GCM output tag"] + pub gcm_out_tag: [GCM_OUT_TAG; 4], + #[doc = "0x84 - 5th-8th word of key"] + pub key_ext: [KEY_EXT; 4], + } + #[doc = "1st-4th word of key\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [key](key) module"] + pub type KEY = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _KEY; + #[doc = "`read()` method returns [key::R](key::R) reader structure"] + impl crate::Readable for KEY {} + #[doc = "`write(|w| ..)` method takes [key::W](key::W) writer structure"] + impl crate::Writable for KEY {} + #[doc = "1st-4th word of key"] + pub mod key { + #[doc = "Reader of register key[%s]"] + pub type R = crate::R; + #[doc = "Writer for register key[%s]"] + pub type W = crate::W; + #[doc = "Register key[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::KEY { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Encryption or decryption select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [encrypt_sel](encrypt_sel) module"] + pub type ENCRYPT_SEL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ENCRYPT_SEL; + #[doc = "`read()` method returns [encrypt_sel::R](encrypt_sel::R) reader structure"] + impl crate::Readable for ENCRYPT_SEL {} + #[doc = "`write(|w| ..)` method takes [encrypt_sel::W](encrypt_sel::W) writer structure"] + impl crate::Writable for ENCRYPT_SEL {} + #[doc = "Encryption or decryption select"] + pub mod encrypt_sel { + #[doc = "Reader of register encrypt_sel"] + pub type R = crate::R; + #[doc = "Writer for register encrypt_sel"] + pub type W = crate::W; + #[doc = "Register encrypt_sel `reset()`'s with value 0"] + impl crate::ResetValue for super::ENCRYPT_SEL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Select encryption or decryption mode\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum ENCRYPT_SEL_A { + #[doc = "0: Sets encryption mode"] + ENCRYPTION = 0, + #[doc = "1: Sets decryption mode"] + DECRYPTION = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: ENCRYPT_SEL_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `encrypt_sel`"] + pub type ENCRYPT_SEL_R = crate::R; + impl ENCRYPT_SEL_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENCRYPT_SEL_A { + match self.bits { + false => ENCRYPT_SEL_A::ENCRYPTION, + true => ENCRYPT_SEL_A::DECRYPTION, + } + } + #[doc = "Checks if the value of the field is `ENCRYPTION`"] + #[inline(always)] + pub fn is_encryption(&self) -> bool { + *self == ENCRYPT_SEL_A::ENCRYPTION + } + #[doc = "Checks if the value of the field is `DECRYPTION`"] + #[inline(always)] + pub fn is_decryption(&self) -> bool { + *self == ENCRYPT_SEL_A::DECRYPTION + } + } + #[doc = "Write proxy for field `encrypt_sel`"] + pub struct ENCRYPT_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> ENCRYPT_SEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENCRYPT_SEL_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Sets encryption mode"] + #[inline(always)] + pub fn encryption(self) -> &'a mut W { + self.variant(ENCRYPT_SEL_A::ENCRYPTION) + } + #[doc = "Sets decryption mode"] + #[inline(always)] + pub fn decryption(self) -> &'a mut W { + self.variant(ENCRYPT_SEL_A::DECRYPTION) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Select encryption or decryption mode"] + #[inline(always)] + pub fn encrypt_sel(&self) -> ENCRYPT_SEL_R { + ENCRYPT_SEL_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Select encryption or decryption mode"] + #[inline(always)] + pub fn encrypt_sel(&mut self) -> ENCRYPT_SEL_W { + ENCRYPT_SEL_W { w: self } + } + } + } + #[doc = "AES mode register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mode_ctl](mode_ctl) module"] + pub type MODE_CTL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _MODE_CTL; + #[doc = "`read()` method returns [mode_ctl::R](mode_ctl::R) reader structure"] + impl crate::Readable for MODE_CTL {} + #[doc = "`write(|w| ..)` method takes [mode_ctl::W](mode_ctl::W) writer structure"] + impl crate::Writable for MODE_CTL {} + #[doc = "AES mode register"] + pub mod mode_ctl { + #[doc = "Reader of register mode_ctl"] + pub type R = crate::R; + #[doc = "Writer for register mode_ctl"] + pub type W = crate::W; + #[doc = "Register mode_ctl `reset()`'s with value 0"] + impl crate::ResetValue for super::MODE_CTL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Cipher mode\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum CIPHER_MODE_A { + #[doc = "0: Electronic Codebook"] + ECB = 0, + #[doc = "1: Cipher Block Chaining"] + CBC = 1, + #[doc = "2: Galois/Counter Mode"] + GCM = 2, + } + impl From for u8 { + #[inline(always)] + fn from(variant: CIPHER_MODE_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `cipher_mode`"] + pub type CIPHER_MODE_R = crate::R; + impl CIPHER_MODE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(CIPHER_MODE_A::ECB), + 1 => Val(CIPHER_MODE_A::CBC), + 2 => Val(CIPHER_MODE_A::GCM), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `ECB`"] + #[inline(always)] + pub fn is_ecb(&self) -> bool { + *self == CIPHER_MODE_A::ECB + } + #[doc = "Checks if the value of the field is `CBC`"] + #[inline(always)] + pub fn is_cbc(&self) -> bool { + *self == CIPHER_MODE_A::CBC + } + #[doc = "Checks if the value of the field is `GCM`"] + #[inline(always)] + pub fn is_gcm(&self) -> bool { + *self == CIPHER_MODE_A::GCM + } + } + #[doc = "Write proxy for field `cipher_mode`"] + pub struct CIPHER_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> CIPHER_MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CIPHER_MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Electronic Codebook"] + #[inline(always)] + pub fn ecb(self) -> &'a mut W { + self.variant(CIPHER_MODE_A::ECB) + } + #[doc = "Cipher Block Chaining"] + #[inline(always)] + pub fn cbc(self) -> &'a mut W { + self.variant(CIPHER_MODE_A::CBC) + } + #[doc = "Galois/Counter Mode"] + #[inline(always)] + pub fn gcm(self) -> &'a mut W { + self.variant(CIPHER_MODE_A::GCM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + #[doc = "Key mode\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum KEY_MODE_A { + #[doc = "0: AES-128"] + AES128 = 0, + #[doc = "1: AES-192"] + AES192 = 1, + #[doc = "2: AES-256"] + AES256 = 2, + } + impl From for u8 { + #[inline(always)] + fn from(variant: KEY_MODE_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `key_mode`"] + pub type KEY_MODE_R = crate::R; + impl KEY_MODE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(KEY_MODE_A::AES128), + 1 => Val(KEY_MODE_A::AES192), + 2 => Val(KEY_MODE_A::AES256), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `AES128`"] + #[inline(always)] + pub fn is_aes128(&self) -> bool { + *self == KEY_MODE_A::AES128 + } + #[doc = "Checks if the value of the field is `AES192`"] + #[inline(always)] + pub fn is_aes192(&self) -> bool { + *self == KEY_MODE_A::AES192 + } + #[doc = "Checks if the value of the field is `AES256`"] + #[inline(always)] + pub fn is_aes256(&self) -> bool { + *self == KEY_MODE_A::AES256 + } + } + #[doc = "Write proxy for field `key_mode`"] + pub struct KEY_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> KEY_MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: KEY_MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "AES-128"] + #[inline(always)] + pub fn aes128(self) -> &'a mut W { + self.variant(KEY_MODE_A::AES128) + } + #[doc = "AES-192"] + #[inline(always)] + pub fn aes192(self) -> &'a mut W { + self.variant(KEY_MODE_A::AES192) + } + #[doc = "AES-256"] + #[inline(always)] + pub fn aes256(self) -> &'a mut W { + self.variant(KEY_MODE_A::AES256) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | (((value as u32) & 0x03) << 3); + self.w + } + } + #[doc = "Input key order\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum KEY_ORDER_A { + #[doc = "0: Big Endian"] + BE = 0, + #[doc = "1: Little Endian"] + LE = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: KEY_ORDER_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `key_order`"] + pub type KEY_ORDER_R = crate::R; + impl KEY_ORDER_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> KEY_ORDER_A { + match self.bits { + false => KEY_ORDER_A::BE, + true => KEY_ORDER_A::LE, + } + } + #[doc = "Checks if the value of the field is `BE`"] + #[inline(always)] + pub fn is_be(&self) -> bool { + *self == KEY_ORDER_A::BE + } + #[doc = "Checks if the value of the field is `LE`"] + #[inline(always)] + pub fn is_le(&self) -> bool { + *self == KEY_ORDER_A::LE + } + } + #[doc = "Write proxy for field `key_order`"] + pub struct KEY_ORDER_W<'a> { + w: &'a mut W, + } + impl<'a> KEY_ORDER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: KEY_ORDER_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Big Endian"] + #[inline(always)] + pub fn be(self) -> &'a mut W { + self.variant(KEY_ORDER_A::BE) + } + #[doc = "Little Endian"] + #[inline(always)] + pub fn le(self) -> &'a mut W { + self.variant(KEY_ORDER_A::LE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + #[doc = "Input data order"] + pub type INPUT_ORDER_A = KEY_ORDER_A; + #[doc = "Reader of field `input_order`"] + pub type INPUT_ORDER_R = crate::R; + #[doc = "Write proxy for field `input_order`"] + pub struct INPUT_ORDER_W<'a> { + w: &'a mut W, + } + impl<'a> INPUT_ORDER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INPUT_ORDER_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Big Endian"] + #[inline(always)] + pub fn be(self) -> &'a mut W { + self.variant(INPUT_ORDER_A::BE) + } + #[doc = "Little Endian"] + #[inline(always)] + pub fn le(self) -> &'a mut W { + self.variant(INPUT_ORDER_A::LE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); + self.w + } + } + #[doc = "Output data order"] + pub type OUTPUT_ORDER_A = KEY_ORDER_A; + #[doc = "Reader of field `output_order`"] + pub type OUTPUT_ORDER_R = crate::R; + #[doc = "Write proxy for field `output_order`"] + pub struct OUTPUT_ORDER_W<'a> { + w: &'a mut W, + } + impl<'a> OUTPUT_ORDER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: OUTPUT_ORDER_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Big Endian"] + #[inline(always)] + pub fn be(self) -> &'a mut W { + self.variant(OUTPUT_ORDER_A::BE) + } + #[doc = "Little Endian"] + #[inline(always)] + pub fn le(self) -> &'a mut W { + self.variant(OUTPUT_ORDER_A::LE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - Cipher mode"] + #[inline(always)] + pub fn cipher_mode(&self) -> CIPHER_MODE_R { + CIPHER_MODE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:4 - Key mode"] + #[inline(always)] + pub fn key_mode(&self) -> KEY_MODE_R { + KEY_MODE_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 5 - Input key order"] + #[inline(always)] + pub fn key_order(&self) -> KEY_ORDER_R { + KEY_ORDER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Input data order"] + #[inline(always)] + pub fn input_order(&self) -> INPUT_ORDER_R { + INPUT_ORDER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 9 - Output data order"] + #[inline(always)] + pub fn output_order(&self) -> OUTPUT_ORDER_R { + OUTPUT_ORDER_R::new(((self.bits >> 9) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:2 - Cipher mode"] + #[inline(always)] + pub fn cipher_mode(&mut self) -> CIPHER_MODE_W { + CIPHER_MODE_W { w: self } + } + #[doc = "Bits 3:4 - Key mode"] + #[inline(always)] + pub fn key_mode(&mut self) -> KEY_MODE_W { + KEY_MODE_W { w: self } + } + #[doc = "Bit 5 - Input key order"] + #[inline(always)] + pub fn key_order(&mut self) -> KEY_ORDER_W { + KEY_ORDER_W { w: self } + } + #[doc = "Bit 7 - Input data order"] + #[inline(always)] + pub fn input_order(&mut self) -> INPUT_ORDER_W { + INPUT_ORDER_W { w: self } + } + #[doc = "Bit 9 - Output data order"] + #[inline(always)] + pub fn output_order(&mut self) -> OUTPUT_ORDER_W { + OUTPUT_ORDER_W { w: self } + } + } + } + #[doc = "Initialisation Vector (96 bit for GCM, 128 bit for CBC)\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iv](iv) module"] + pub type IV = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IV; + #[doc = "`read()` method returns [iv::R](iv::R) reader structure"] + impl crate::Readable for IV {} + #[doc = "`write(|w| ..)` method takes [iv::W](iv::W) writer structure"] + impl crate::Writable for IV {} + #[doc = "Initialisation Vector (96 bit for GCM, 128 bit for CBC)"] + pub mod iv { + #[doc = "Reader of register iv[%s]"] + pub type R = crate::R; + #[doc = "Writer for register iv[%s]"] + pub type W = crate::W; + #[doc = "Register iv[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::IV { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Endian control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [endian](endian) module"] + pub type ENDIAN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ENDIAN; + #[doc = "`read()` method returns [endian::R](endian::R) reader structure"] + impl crate::Readable for ENDIAN {} + #[doc = "`write(|w| ..)` method takes [endian::W](endian::W) writer structure"] + impl crate::Writable for ENDIAN {} + #[doc = "Endian control"] + pub mod endian { + #[doc = "Reader of register endian"] + pub type R = crate::R; + #[doc = "Writer for register endian"] + pub type W = crate::W; + #[doc = "Register endian `reset()`'s with value 0"] + impl crate::ResetValue for super::ENDIAN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Input data endian"] + pub type ENDIAN_A = super::mode_ctl::KEY_ORDER_A; + #[doc = "Reader of field `endian`"] + pub type ENDIAN_R = crate::R; + #[doc = "Write proxy for field `endian`"] + pub struct ENDIAN_W<'a> { + w: &'a mut W, + } + impl<'a> ENDIAN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENDIAN_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Big Endian"] + #[inline(always)] + pub fn be(self) -> &'a mut W { + self.variant(ENDIAN_A::BE) + } + #[doc = "Little Endian"] + #[inline(always)] + pub fn le(self) -> &'a mut W { + self.variant(ENDIAN_A::LE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Input data endian"] + #[inline(always)] + pub fn endian(&self) -> ENDIAN_R { + ENDIAN_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Input data endian"] + #[inline(always)] + pub fn endian(&mut self) -> ENDIAN_W { + ENDIAN_W { w: self } + } + } + } + #[doc = "Finished status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [finish](finish) module"] + pub type FINISH = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FINISH; + #[doc = "`read()` method returns [finish::R](finish::R) reader structure"] + impl crate::Readable for FINISH {} + #[doc = "`write(|w| ..)` method takes [finish::W](finish::W) writer structure"] + impl crate::Writable for FINISH {} + #[doc = "Finished status"] + pub mod finish { + #[doc = "Reader of register finish"] + pub type R = crate::R; + #[doc = "Writer for register finish"] + pub type W = crate::W; + #[doc = "Register finish `reset()`'s with value 0"] + impl crate::ResetValue for super::FINISH { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "AES operation finished status\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum FINISH_A { + #[doc = "0: Operation not finished"] + NOT_FINISHED = 0, + #[doc = "1: Operation finished"] + FINISHED = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: FINISH_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `finish`"] + pub type FINISH_R = crate::R; + impl FINISH_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FINISH_A { + match self.bits { + false => FINISH_A::NOT_FINISHED, + true => FINISH_A::FINISHED, + } + } + #[doc = "Checks if the value of the field is `NOT_FINISHED`"] + #[inline(always)] + pub fn is_not_finished(&self) -> bool { + *self == FINISH_A::NOT_FINISHED + } + #[doc = "Checks if the value of the field is `FINISHED`"] + #[inline(always)] + pub fn is_finished(&self) -> bool { + *self == FINISH_A::FINISHED + } + } + #[doc = "Write proxy for field `finish`"] + pub struct FINISH_W<'a> { + w: &'a mut W, + } + impl<'a> FINISH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FINISH_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Operation not finished"] + #[inline(always)] + pub fn not_finished(self) -> &'a mut W { + self.variant(FINISH_A::NOT_FINISHED) + } + #[doc = "Operation finished"] + #[inline(always)] + pub fn finished(self) -> &'a mut W { + self.variant(FINISH_A::FINISHED) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - AES operation finished status"] + #[inline(always)] + pub fn finish(&self) -> FINISH_R { + FINISH_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - AES operation finished status"] + #[inline(always)] + pub fn finish(&mut self) -> FINISH_W { + FINISH_W { w: self } + } + } + } + #[doc = "DMA select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_sel](dma_sel) module"] + pub type DMA_SEL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMA_SEL; + #[doc = "`read()` method returns [dma_sel::R](dma_sel::R) reader structure"] + impl crate::Readable for DMA_SEL {} + #[doc = "`write(|w| ..)` method takes [dma_sel::W](dma_sel::W) writer structure"] + impl crate::Writable for DMA_SEL {} + #[doc = "DMA select"] + pub mod dma_sel { + #[doc = "Reader of register dma_sel"] + pub type R = crate::R; + #[doc = "Writer for register dma_sel"] + pub type W = crate::W; + #[doc = "Register dma_sel `reset()`'s with value 0"] + impl crate::ResetValue for super::DMA_SEL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `dma_sel`"] + pub type DMA_SEL_R = crate::R; + #[doc = "Write proxy for field `dma_sel`"] + pub struct DMA_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_SEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Output to DMA if set, to CPU otherwise"] + #[inline(always)] + pub fn dma_sel(&self) -> DMA_SEL_R { + DMA_SEL_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Output to DMA if set, to CPU otherwise"] + #[inline(always)] + pub fn dma_sel(&mut self) -> DMA_SEL_W { + DMA_SEL_W { w: self } + } + } + } + #[doc = "GCM additional authenticated data count in bytes, minus one\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [aad_num](aad_num) module"] + pub type AAD_NUM = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _AAD_NUM; + #[doc = "`read()` method returns [aad_num::R](aad_num::R) reader structure"] + impl crate::Readable for AAD_NUM {} + #[doc = "`write(|w| ..)` method takes [aad_num::W](aad_num::W) writer structure"] + impl crate::Writable for AAD_NUM {} + #[doc = "GCM additional authenticated data count in bytes, minus one"] + pub mod aad_num { + #[doc = "Reader of register aad_num"] + pub type R = crate::R; + #[doc = "Writer for register aad_num"] + pub type W = crate::W; + #[doc = "Register aad_num `reset()`'s with value 0"] + impl crate::ResetValue for super::AAD_NUM { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Plaintext/ciphertext input data count in bytes, minus one\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pc_num](pc_num) module"] + pub type PC_NUM = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PC_NUM; + #[doc = "`read()` method returns [pc_num::R](pc_num::R) reader structure"] + impl crate::Readable for PC_NUM {} + #[doc = "`write(|w| ..)` method takes [pc_num::W](pc_num::W) writer structure"] + impl crate::Writable for PC_NUM {} + #[doc = "Plaintext/ciphertext input data count in bytes, minus one"] + pub mod pc_num { + #[doc = "Reader of register pc_num"] + pub type R = crate::R; + #[doc = "Writer for register pc_num"] + pub type W = crate::W; + #[doc = "Register pc_num `reset()`'s with value 0"] + impl crate::ResetValue for super::PC_NUM { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Plaintext/ciphertext input data\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [text_data](text_data) module"] + pub type TEXT_DATA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TEXT_DATA; + #[doc = "`read()` method returns [text_data::R](text_data::R) reader structure"] + impl crate::Readable for TEXT_DATA {} + #[doc = "`write(|w| ..)` method takes [text_data::W](text_data::W) writer structure"] + impl crate::Writable for TEXT_DATA {} + #[doc = "Plaintext/ciphertext input data"] + pub mod text_data { + #[doc = "Reader of register text_data"] + pub type R = crate::R; + #[doc = "Writer for register text_data"] + pub type W = crate::W; + #[doc = "Register text_data `reset()`'s with value 0"] + impl crate::ResetValue for super::TEXT_DATA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Additional authenticated data\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [aad_data](aad_data) module"] + pub type AAD_DATA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _AAD_DATA; + #[doc = "`read()` method returns [aad_data::R](aad_data::R) reader structure"] + impl crate::Readable for AAD_DATA {} + #[doc = "`write(|w| ..)` method takes [aad_data::W](aad_data::W) writer structure"] + impl crate::Writable for AAD_DATA {} + #[doc = "Additional authenticated data"] + pub mod aad_data { + #[doc = "Reader of register aad_data"] + pub type R = crate::R; + #[doc = "Writer for register aad_data"] + pub type W = crate::W; + #[doc = "Register aad_data `reset()`'s with value 0"] + impl crate::ResetValue for super::AAD_DATA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Tag check status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tag_chk](tag_chk) module"] + pub type TAG_CHK = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TAG_CHK; + #[doc = "`read()` method returns [tag_chk::R](tag_chk::R) reader structure"] + impl crate::Readable for TAG_CHK {} + #[doc = "`write(|w| ..)` method takes [tag_chk::W](tag_chk::W) writer structure"] + impl crate::Writable for TAG_CHK {} + #[doc = "Tag check status"] + pub mod tag_chk { + #[doc = "Reader of register tag_chk"] + pub type R = crate::R; + #[doc = "Writer for register tag_chk"] + pub type W = crate::W; + #[doc = "Register tag_chk `reset()`'s with value 0"] + impl crate::ResetValue for super::TAG_CHK { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Tag check status\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum TAG_CHK_A { + #[doc = "0: Check not finished"] + BUSY = 0, + #[doc = "1: Check failed"] + FAIL = 1, + #[doc = "2: Check success"] + SUCCESS = 2, + } + impl From for u8 { + #[inline(always)] + fn from(variant: TAG_CHK_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `tag_chk`"] + pub type TAG_CHK_R = crate::R; + impl TAG_CHK_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(TAG_CHK_A::BUSY), + 1 => Val(TAG_CHK_A::FAIL), + 2 => Val(TAG_CHK_A::SUCCESS), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `BUSY`"] + #[inline(always)] + pub fn is_busy(&self) -> bool { + *self == TAG_CHK_A::BUSY + } + #[doc = "Checks if the value of the field is `FAIL`"] + #[inline(always)] + pub fn is_fail(&self) -> bool { + *self == TAG_CHK_A::FAIL + } + #[doc = "Checks if the value of the field is `SUCCESS`"] + #[inline(always)] + pub fn is_success(&self) -> bool { + *self == TAG_CHK_A::SUCCESS + } + } + #[doc = "Write proxy for field `tag_chk`"] + pub struct TAG_CHK_W<'a> { + w: &'a mut W, + } + impl<'a> TAG_CHK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TAG_CHK_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Check not finished"] + #[inline(always)] + pub fn busy(self) -> &'a mut W { + self.variant(TAG_CHK_A::BUSY) + } + #[doc = "Check failed"] + #[inline(always)] + pub fn fail(self) -> &'a mut W { + self.variant(TAG_CHK_A::FAIL) + } + #[doc = "Check success"] + #[inline(always)] + pub fn success(self) -> &'a mut W { + self.variant(TAG_CHK_A::SUCCESS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03); + self.w + } + } + impl R { + #[doc = "Bits 0:1 - Tag check status"] + #[inline(always)] + pub fn tag_chk(&self) -> TAG_CHK_R { + TAG_CHK_R::new((self.bits & 0x03) as u8) + } + } + impl W { + #[doc = "Bits 0:1 - Tag check status"] + #[inline(always)] + pub fn tag_chk(&mut self) -> TAG_CHK_W { + TAG_CHK_W { w: self } + } + } + } + #[doc = "Data can input flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data_in_flag](data_in_flag) module"] + pub type DATA_IN_FLAG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DATA_IN_FLAG; + #[doc = "`read()` method returns [data_in_flag::R](data_in_flag::R) reader structure"] + impl crate::Readable for DATA_IN_FLAG {} + #[doc = "`write(|w| ..)` method takes [data_in_flag::W](data_in_flag::W) writer structure"] + impl crate::Writable for DATA_IN_FLAG {} + #[doc = "Data can input flag"] + pub mod data_in_flag { + #[doc = "Reader of register data_in_flag"] + pub type R = crate::R; + #[doc = "Writer for register data_in_flag"] + pub type W = crate::W; + #[doc = "Register data_in_flag `reset()`'s with value 0"] + impl crate::ResetValue for super::DATA_IN_FLAG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Data can be written to text_data or aad_data when this flag is set\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum DATA_IN_FLAG_A { + #[doc = "0: Cannot input"] + CANNOT_INPUT = 0, + #[doc = "1: Can input"] + CAN_INPUT = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: DATA_IN_FLAG_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `data_in_flag`"] + pub type DATA_IN_FLAG_R = crate::R; + impl DATA_IN_FLAG_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DATA_IN_FLAG_A { + match self.bits { + false => DATA_IN_FLAG_A::CANNOT_INPUT, + true => DATA_IN_FLAG_A::CAN_INPUT, + } + } + #[doc = "Checks if the value of the field is `CANNOT_INPUT`"] + #[inline(always)] + pub fn is_cannot_input(&self) -> bool { + *self == DATA_IN_FLAG_A::CANNOT_INPUT + } + #[doc = "Checks if the value of the field is `CAN_INPUT`"] + #[inline(always)] + pub fn is_can_input(&self) -> bool { + *self == DATA_IN_FLAG_A::CAN_INPUT + } + } + #[doc = "Write proxy for field `data_in_flag`"] + pub struct DATA_IN_FLAG_W<'a> { + w: &'a mut W, + } + impl<'a> DATA_IN_FLAG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DATA_IN_FLAG_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Cannot input"] + #[inline(always)] + pub fn cannot_input(self) -> &'a mut W { + self.variant(DATA_IN_FLAG_A::CANNOT_INPUT) + } + #[doc = "Can input"] + #[inline(always)] + pub fn can_input(self) -> &'a mut W { + self.variant(DATA_IN_FLAG_A::CAN_INPUT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Data can be written to text_data or aad_data when this flag is set"] + #[inline(always)] + pub fn data_in_flag(&self) -> DATA_IN_FLAG_R { + DATA_IN_FLAG_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Data can be written to text_data or aad_data when this flag is set"] + #[inline(always)] + pub fn data_in_flag(&mut self) -> DATA_IN_FLAG_W { + DATA_IN_FLAG_W { w: self } + } + } + } + #[doc = "GCM input tag for comparison with the calculated tag\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gcm_in_tag](gcm_in_tag) module"] + pub type GCM_IN_TAG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _GCM_IN_TAG; + #[doc = "`read()` method returns [gcm_in_tag::R](gcm_in_tag::R) reader structure"] + impl crate::Readable for GCM_IN_TAG {} + #[doc = "`write(|w| ..)` method takes [gcm_in_tag::W](gcm_in_tag::W) writer structure"] + impl crate::Writable for GCM_IN_TAG {} + #[doc = "GCM input tag for comparison with the calculated tag"] + pub mod gcm_in_tag { + #[doc = "Reader of register gcm_in_tag[%s]"] + pub type R = crate::R; + #[doc = "Writer for register gcm_in_tag[%s]"] + pub type W = crate::W; + #[doc = "Register gcm_in_tag[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::GCM_IN_TAG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Plaintext/ciphertext output data\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_data](out_data) module"] + pub type OUT_DATA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _OUT_DATA; + #[doc = "`read()` method returns [out_data::R](out_data::R) reader structure"] + impl crate::Readable for OUT_DATA {} + #[doc = "`write(|w| ..)` method takes [out_data::W](out_data::W) writer structure"] + impl crate::Writable for OUT_DATA {} + #[doc = "Plaintext/ciphertext output data"] + pub mod out_data { + #[doc = "Reader of register out_data"] + pub type R = crate::R; + #[doc = "Writer for register out_data"] + pub type W = crate::W; + #[doc = "Register out_data `reset()`'s with value 0"] + impl crate::ResetValue for super::OUT_DATA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "AES module enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [en](en) module"] + pub type EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _EN; + #[doc = "`read()` method returns [en::R](en::R) reader structure"] + impl crate::Readable for EN {} + #[doc = "`write(|w| ..)` method takes [en::W](en::W) writer structure"] + impl crate::Writable for EN {} + #[doc = "AES module enable"] + pub mod en { + #[doc = "Reader of register en"] + pub type R = crate::R; + #[doc = "Writer for register en"] + pub type W = crate::W; + #[doc = "Register en `reset()`'s with value 0"] + impl crate::ResetValue for super::EN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "AES module enable\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum EN_A { + #[doc = "0: Disable module"] + DISABLE = 0, + #[doc = "1: Enable module"] + ENABLE = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `en`"] + pub type EN_R = crate::R; + impl EN_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLE, + true => EN_A::ENABLE, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == EN_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == EN_A::ENABLE + } + } + #[doc = "Write proxy for field `en`"] + pub struct EN_W<'a> { + w: &'a mut W, + } + impl<'a> EN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EN_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Disable module"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(EN_A::DISABLE) + } + #[doc = "Enable module"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(EN_A::ENABLE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - AES module enable"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - AES module enable"] + #[inline(always)] + pub fn en(&mut self) -> EN_W { + EN_W { w: self } + } + } + } + #[doc = "Data can output flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data_out_flag](data_out_flag) module"] + pub type DATA_OUT_FLAG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DATA_OUT_FLAG; + #[doc = "`read()` method returns [data_out_flag::R](data_out_flag::R) reader structure"] + impl crate::Readable for DATA_OUT_FLAG {} + #[doc = "`write(|w| ..)` method takes [data_out_flag::W](data_out_flag::W) writer structure"] + impl crate::Writable for DATA_OUT_FLAG {} + #[doc = "Data can output flag"] + pub mod data_out_flag { + #[doc = "Reader of register data_out_flag"] + pub type R = crate::R; + #[doc = "Writer for register data_out_flag"] + pub type W = crate::W; + #[doc = "Register data_out_flag `reset()`'s with value 0"] + impl crate::ResetValue for super::DATA_OUT_FLAG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Data can be read from out_data when this flag is set\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum DATA_OUT_FLAG_A { + #[doc = "0: Data cannot output"] + CANNOT_OUTPUT = 0, + #[doc = "1: Data can output"] + CAN_OUTPUT = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: DATA_OUT_FLAG_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `data_out_flag`"] + pub type DATA_OUT_FLAG_R = crate::R; + impl DATA_OUT_FLAG_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DATA_OUT_FLAG_A { + match self.bits { + false => DATA_OUT_FLAG_A::CANNOT_OUTPUT, + true => DATA_OUT_FLAG_A::CAN_OUTPUT, + } + } + #[doc = "Checks if the value of the field is `CANNOT_OUTPUT`"] + #[inline(always)] + pub fn is_cannot_output(&self) -> bool { + *self == DATA_OUT_FLAG_A::CANNOT_OUTPUT + } + #[doc = "Checks if the value of the field is `CAN_OUTPUT`"] + #[inline(always)] + pub fn is_can_output(&self) -> bool { + *self == DATA_OUT_FLAG_A::CAN_OUTPUT + } + } + #[doc = "Write proxy for field `data_out_flag`"] + pub struct DATA_OUT_FLAG_W<'a> { + w: &'a mut W, + } + impl<'a> DATA_OUT_FLAG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DATA_OUT_FLAG_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Data cannot output"] + #[inline(always)] + pub fn cannot_output(self) -> &'a mut W { + self.variant(DATA_OUT_FLAG_A::CANNOT_OUTPUT) + } + #[doc = "Data can output"] + #[inline(always)] + pub fn can_output(self) -> &'a mut W { + self.variant(DATA_OUT_FLAG_A::CAN_OUTPUT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Data can be read from out_data when this flag is set"] + #[inline(always)] + pub fn data_out_flag(&self) -> DATA_OUT_FLAG_R { + DATA_OUT_FLAG_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Data can be read from out_data when this flag is set"] + #[inline(always)] + pub fn data_out_flag(&mut self) -> DATA_OUT_FLAG_W { + DATA_OUT_FLAG_W { w: self } + } + } + } + #[doc = "Can input tag (when using GCM)\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tag_in_flag](tag_in_flag) module"] + pub type TAG_IN_FLAG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TAG_IN_FLAG; + #[doc = "`read()` method returns [tag_in_flag::R](tag_in_flag::R) reader structure"] + impl crate::Readable for TAG_IN_FLAG {} + #[doc = "`write(|w| ..)` method takes [tag_in_flag::W](tag_in_flag::W) writer structure"] + impl crate::Writable for TAG_IN_FLAG {} + #[doc = "Can input tag (when using GCM)"] + pub mod tag_in_flag { + #[doc = "Reader of register tag_in_flag"] + pub type R = crate::R; + #[doc = "Writer for register tag_in_flag"] + pub type W = crate::W; + #[doc = "Register tag_in_flag `reset()`'s with value 0"] + impl crate::ResetValue for super::TAG_IN_FLAG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "GCM tag can be written to gcm_in_tag when this flag is set"] + pub type TAG_IN_FLAG_A = super::data_in_flag::DATA_IN_FLAG_A; + #[doc = "Reader of field `tag_in_flag`"] + pub type TAG_IN_FLAG_R = crate::R; + #[doc = "Write proxy for field `tag_in_flag`"] + pub struct TAG_IN_FLAG_W<'a> { + w: &'a mut W, + } + impl<'a> TAG_IN_FLAG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TAG_IN_FLAG_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Cannot input"] + #[inline(always)] + pub fn cannot_input(self) -> &'a mut W { + self.variant(TAG_IN_FLAG_A::CANNOT_INPUT) + } + #[doc = "Can input"] + #[inline(always)] + pub fn can_input(self) -> &'a mut W { + self.variant(TAG_IN_FLAG_A::CAN_INPUT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - GCM tag can be written to gcm_in_tag when this flag is set"] + #[inline(always)] + pub fn tag_in_flag(&self) -> TAG_IN_FLAG_R { + TAG_IN_FLAG_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - GCM tag can be written to gcm_in_tag when this flag is set"] + #[inline(always)] + pub fn tag_in_flag(&mut self) -> TAG_IN_FLAG_W { + TAG_IN_FLAG_W { w: self } + } + } + } + #[doc = "Tag clear (a write to this register clears the tag_chk status)\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tag_clear](tag_clear) module"] + pub type TAG_CLEAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TAG_CLEAR; + #[doc = "`read()` method returns [tag_clear::R](tag_clear::R) reader structure"] + impl crate::Readable for TAG_CLEAR {} + #[doc = "`write(|w| ..)` method takes [tag_clear::W](tag_clear::W) writer structure"] + impl crate::Writable for TAG_CLEAR {} + #[doc = "Tag clear (a write to this register clears the tag_chk status)"] + pub mod tag_clear { + #[doc = "Reader of register tag_clear"] + pub type R = crate::R; + #[doc = "Writer for register tag_clear"] + pub type W = crate::W; + #[doc = "Register tag_clear `reset()`'s with value 0"] + impl crate::ResetValue for super::TAG_CLEAR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Computed GCM output tag\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gcm_out_tag](gcm_out_tag) module"] + pub type GCM_OUT_TAG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _GCM_OUT_TAG; + #[doc = "`read()` method returns [gcm_out_tag::R](gcm_out_tag::R) reader structure"] + impl crate::Readable for GCM_OUT_TAG {} + #[doc = "`write(|w| ..)` method takes [gcm_out_tag::W](gcm_out_tag::W) writer structure"] + impl crate::Writable for GCM_OUT_TAG {} + #[doc = "Computed GCM output tag"] + pub mod gcm_out_tag { + #[doc = "Reader of register gcm_out_tag[%s]"] + pub type R = crate::R; + #[doc = "Writer for register gcm_out_tag[%s]"] + pub type W = crate::W; + #[doc = "Register gcm_out_tag[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::GCM_OUT_TAG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "5th-8th word of key\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [key_ext](key_ext) module"] + pub type KEY_EXT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _KEY_EXT; + #[doc = "`read()` method returns [key_ext::R](key_ext::R) reader structure"] + impl crate::Readable for KEY_EXT {} + #[doc = "`write(|w| ..)` method takes [key_ext::W](key_ext::W) writer structure"] + impl crate::Writable for KEY_EXT {} + #[doc = "5th-8th word of key"] + pub mod key_ext { + #[doc = "Reader of register key_ext[%s]"] + pub type R = crate::R; + #[doc = "Writer for register key_ext[%s]"] + pub type W = crate::W; + #[doc = "Register key_ext[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::KEY_EXT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Real Time Clock"] +pub struct RTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RTC {} +impl RTC { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rtc::RegisterBlock { + 0x5046_0000 as *const _ + } +} +impl Deref for RTC { + type Target = rtc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*RTC::ptr() } + } +} +#[doc = "Real Time Clock"] +pub mod rtc { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Timer date information"] + pub date: DATE, + #[doc = "0x04 - Timer time information"] + pub time: TIME, + #[doc = "0x08 - Alarm date information"] + pub alarm_date: ALARM_DATE, + #[doc = "0x0c - Alarm time information"] + pub alarm_time: ALARM_TIME, + #[doc = "0x10 - Timer counter initial value"] + pub initial_count: INITIAL_COUNT, + #[doc = "0x14 - Timer counter current value"] + pub current_count: CURRENT_COUNT, + #[doc = "0x18 - RTC interrupt settings"] + pub interrupt_ctrl: INTERRUPT_CTRL, + #[doc = "0x1c - RTC register settings"] + pub register_ctrl: REGISTER_CTRL, + _reserved8: [u8; 8usize], + #[doc = "0x28 - Timer extended information"] + pub extended: EXTENDED, + } + #[doc = "Timer date information\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [date](date) module"] + pub type DATE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DATE; + #[doc = "`read()` method returns [date::R](date::R) reader structure"] + impl crate::Readable for DATE {} + #[doc = "`write(|w| ..)` method takes [date::W](date::W) writer structure"] + impl crate::Writable for DATE {} + #[doc = "Timer date information"] + pub mod date { + #[doc = "Reader of register date"] + pub type R = crate::R; + #[doc = "Writer for register date"] + pub type W = crate::W; + #[doc = "Register date `reset()`'s with value 0"] + impl crate::ResetValue for super::DATE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `week`"] + pub type WEEK_R = crate::R; + #[doc = "Write proxy for field `week`"] + pub struct WEEK_W<'a> { + w: &'a mut W, + } + impl<'a> WEEK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + #[doc = "Reader of field `day`"] + pub type DAY_R = crate::R; + #[doc = "Write proxy for field `day`"] + pub struct DAY_W<'a> { + w: &'a mut W, + } + impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | (((value as u32) & 0x1f) << 8); + self.w + } + } + #[doc = "Reader of field `month`"] + pub type MONTH_R = crate::R; + #[doc = "Write proxy for field `month`"] + pub struct MONTH_W<'a> { + w: &'a mut W, + } + impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16); + self.w + } + } + #[doc = "Reader of field `year`"] + pub type YEAR_R = crate::R; + #[doc = "Write proxy for field `year`"] + pub struct YEAR_W<'a> { + w: &'a mut W, + } + impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0fff << 20)) | (((value as u32) & 0x0fff) << 20); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - Week. Range \\[0,6\\]. 0 is Sunday."] + #[inline(always)] + pub fn week(&self) -> WEEK_R { + WEEK_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:12 - Day. Range \\[1,31\\] +or \\[1,30\\] +or \\[1,29\\] +or \\[1,28\\]"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:19 - Month. Range \\[1,12\\]"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:31 - Year. Range \\[0,99\\]"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 20) & 0x0fff) as u16) + } + } + impl W { + #[doc = "Bits 0:2 - Week. Range \\[0,6\\]. 0 is Sunday."] + #[inline(always)] + pub fn week(&mut self) -> WEEK_W { + WEEK_W { w: self } + } + #[doc = "Bits 8:12 - Day. Range \\[1,31\\] +or \\[1,30\\] +or \\[1,29\\] +or \\[1,28\\]"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 16:19 - Month. Range \\[1,12\\]"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 20:31 - Year. Range \\[0,99\\]"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + } + } + #[doc = "Timer time information\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [time](time) module"] + pub type TIME = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TIME; + #[doc = "`read()` method returns [time::R](time::R) reader structure"] + impl crate::Readable for TIME {} + #[doc = "`write(|w| ..)` method takes [time::W](time::W) writer structure"] + impl crate::Writable for TIME {} + #[doc = "Timer time information"] + pub mod time { + #[doc = "Reader of register time"] + pub type R = crate::R; + #[doc = "Writer for register time"] + pub type W = crate::W; + #[doc = "Register time `reset()`'s with value 0"] + impl crate::ResetValue for super::TIME { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `second`"] + pub type SECOND_R = crate::R; + #[doc = "Write proxy for field `second`"] + pub struct SECOND_W<'a> { + w: &'a mut W, + } + impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 10)) | (((value as u32) & 0x3f) << 10); + self.w + } + } + #[doc = "Reader of field `minute`"] + pub type MINUTE_R = crate::R; + #[doc = "Write proxy for field `minute`"] + pub struct MINUTE_W<'a> { + w: &'a mut W, + } + impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | (((value as u32) & 0x3f) << 16); + self.w + } + } + #[doc = "Reader of field `hour`"] + pub type HOUR_R = crate::R; + #[doc = "Write proxy for field `hour`"] + pub struct HOUR_W<'a> { + w: &'a mut W, + } + impl<'a> HOUR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24); + self.w + } + } + impl R { + #[doc = "Bits 10:15 - Second. Range \\[0,59\\]"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new(((self.bits >> 10) & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Minute. Range \\[0,59\\]"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 24:28 - Hour. Range \\[0,23\\]"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 24) & 0x1f) as u8) + } + } + impl W { + #[doc = "Bits 10:15 - Second. Range \\[0,59\\]"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 16:21 - Minute. Range \\[0,59\\]"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 24:28 - Hour. Range \\[0,23\\]"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + } + } + #[doc = "Alarm date information\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [alarm_date](alarm_date) module"] + pub type ALARM_DATE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ALARM_DATE; + #[doc = "`read()` method returns [alarm_date::R](alarm_date::R) reader structure"] + impl crate::Readable for ALARM_DATE {} + #[doc = "`write(|w| ..)` method takes [alarm_date::W](alarm_date::W) writer structure"] + impl crate::Writable for ALARM_DATE {} + #[doc = "Alarm date information"] + pub mod alarm_date { + #[doc = "Reader of register alarm_date"] + pub type R = crate::R; + #[doc = "Writer for register alarm_date"] + pub type W = crate::W; + #[doc = "Register alarm_date `reset()`'s with value 0"] + impl crate::ResetValue for super::ALARM_DATE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `week`"] + pub type WEEK_R = crate::R; + #[doc = "Write proxy for field `week`"] + pub struct WEEK_W<'a> { + w: &'a mut W, + } + impl<'a> WEEK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + #[doc = "Reader of field `day`"] + pub type DAY_R = crate::R; + #[doc = "Write proxy for field `day`"] + pub struct DAY_W<'a> { + w: &'a mut W, + } + impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | (((value as u32) & 0x1f) << 8); + self.w + } + } + #[doc = "Reader of field `month`"] + pub type MONTH_R = crate::R; + #[doc = "Write proxy for field `month`"] + pub struct MONTH_W<'a> { + w: &'a mut W, + } + impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16); + self.w + } + } + #[doc = "Reader of field `year`"] + pub type YEAR_R = crate::R; + #[doc = "Write proxy for field `year`"] + pub struct YEAR_W<'a> { + w: &'a mut W, + } + impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0fff << 20)) | (((value as u32) & 0x0fff) << 20); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - Week. Range \\[0,6\\]. 0 is Sunday."] + #[inline(always)] + pub fn week(&self) -> WEEK_R { + WEEK_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:12 - Day. Range \\[1,31\\] +or \\[1,30\\] +or \\[1,29\\] +or \\[1,28\\]"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:19 - Month. Range \\[1,12\\]"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:31 - Year. Range \\[0,99\\]"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 20) & 0x0fff) as u16) + } + } + impl W { + #[doc = "Bits 0:2 - Week. Range \\[0,6\\]. 0 is Sunday."] + #[inline(always)] + pub fn week(&mut self) -> WEEK_W { + WEEK_W { w: self } + } + #[doc = "Bits 8:12 - Day. Range \\[1,31\\] +or \\[1,30\\] +or \\[1,29\\] +or \\[1,28\\]"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 16:19 - Month. Range \\[1,12\\]"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 20:31 - Year. Range \\[0,99\\]"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + } + } + #[doc = "Alarm time information\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [alarm_time](alarm_time) module"] + pub type ALARM_TIME = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ALARM_TIME; + #[doc = "`read()` method returns [alarm_time::R](alarm_time::R) reader structure"] + impl crate::Readable for ALARM_TIME {} + #[doc = "`write(|w| ..)` method takes [alarm_time::W](alarm_time::W) writer structure"] + impl crate::Writable for ALARM_TIME {} + #[doc = "Alarm time information"] + pub mod alarm_time { + #[doc = "Reader of register alarm_time"] + pub type R = crate::R; + #[doc = "Writer for register alarm_time"] + pub type W = crate::W; + #[doc = "Register alarm_time `reset()`'s with value 0"] + impl crate::ResetValue for super::ALARM_TIME { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `second`"] + pub type SECOND_R = crate::R; + #[doc = "Write proxy for field `second`"] + pub struct SECOND_W<'a> { + w: &'a mut W, + } + impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 10)) | (((value as u32) & 0x3f) << 10); + self.w + } + } + #[doc = "Reader of field `minute`"] + pub type MINUTE_R = crate::R; + #[doc = "Write proxy for field `minute`"] + pub struct MINUTE_W<'a> { + w: &'a mut W, + } + impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | (((value as u32) & 0x3f) << 16); + self.w + } + } + #[doc = "Reader of field `hour`"] + pub type HOUR_R = crate::R; + #[doc = "Write proxy for field `hour`"] + pub struct HOUR_W<'a> { + w: &'a mut W, + } + impl<'a> HOUR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24); + self.w + } + } + impl R { + #[doc = "Bits 10:15 - Second. Range \\[0,59\\]"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new(((self.bits >> 10) & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Minute. Range \\[0,59\\]"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 24:28 - Hour. Range \\[0,23\\]"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 24) & 0x1f) as u8) + } + } + impl W { + #[doc = "Bits 10:15 - Second. Range \\[0,59\\]"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 16:21 - Minute. Range \\[0,59\\]"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 24:28 - Hour. Range \\[0,23\\]"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + } + } + #[doc = "Timer counter initial value\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [initial_count](initial_count) module"] + pub type INITIAL_COUNT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INITIAL_COUNT; + #[doc = "`read()` method returns [initial_count::R](initial_count::R) reader structure"] + impl crate::Readable for INITIAL_COUNT {} + #[doc = "`write(|w| ..)` method takes [initial_count::W](initial_count::W) writer structure"] + impl crate::Writable for INITIAL_COUNT {} + #[doc = "Timer counter initial value"] + pub mod initial_count { + #[doc = "Reader of register initial_count"] + pub type R = crate::R; + #[doc = "Writer for register initial_count"] + pub type W = crate::W; + #[doc = "Register initial_count `reset()`'s with value 0"] + impl crate::ResetValue for super::INITIAL_COUNT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `count`"] + pub type COUNT_R = crate::R; + #[doc = "Write proxy for field `count`"] + pub struct COUNT_W<'a> { + w: &'a mut W, + } + impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff); + self.w + } + } + impl R { + #[doc = "Bits 0:31 - RTC counter initial value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } + } + impl W { + #[doc = "Bits 0:31 - RTC counter initial value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + } + } + #[doc = "Timer counter current value\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [current_count](current_count) module"] + pub type CURRENT_COUNT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CURRENT_COUNT; + #[doc = "`read()` method returns [current_count::R](current_count::R) reader structure"] + impl crate::Readable for CURRENT_COUNT {} + #[doc = "`write(|w| ..)` method takes [current_count::W](current_count::W) writer structure"] + impl crate::Writable for CURRENT_COUNT {} + #[doc = "Timer counter current value"] + pub mod current_count { + #[doc = "Reader of register current_count"] + pub type R = crate::R; + #[doc = "Writer for register current_count"] + pub type W = crate::W; + #[doc = "Register current_count `reset()`'s with value 0"] + impl crate::ResetValue for super::CURRENT_COUNT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `count`"] + pub type COUNT_R = crate::R; + #[doc = "Write proxy for field `count`"] + pub struct COUNT_W<'a> { + w: &'a mut W, + } + impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff); + self.w + } + } + impl R { + #[doc = "Bits 0:31 - RTC counter current value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } + } + impl W { + #[doc = "Bits 0:31 - RTC counter current value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + } + } + #[doc = "RTC interrupt settings\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_ctrl](interrupt_ctrl) module"] + pub type INTERRUPT_CTRL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_CTRL; + #[doc = "`read()` method returns [interrupt_ctrl::R](interrupt_ctrl::R) reader structure"] + impl crate::Readable for INTERRUPT_CTRL {} + #[doc = "`write(|w| ..)` method takes [interrupt_ctrl::W](interrupt_ctrl::W) writer structure"] + impl crate::Writable for INTERRUPT_CTRL {} + #[doc = "RTC interrupt settings"] + pub mod interrupt_ctrl { + #[doc = "Reader of register interrupt_ctrl"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_ctrl"] + pub type W = crate::W; + #[doc = "Register interrupt_ctrl `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_CTRL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `tick_enable`"] + pub type TICK_ENABLE_R = crate::R; + #[doc = "Write proxy for field `tick_enable`"] + pub struct TICK_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> TICK_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `alarm_enable`"] + pub type ALARM_ENABLE_R = crate::R; + #[doc = "Write proxy for field `alarm_enable`"] + pub struct ALARM_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> ALARM_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `tick_int_mode`"] + pub type TICK_INT_MODE_R = crate::R; + #[doc = "Write proxy for field `tick_int_mode`"] + pub struct TICK_INT_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> TICK_INT_MODE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2); + self.w + } + } + #[doc = "Reader of field `alarm_compare_mask`"] + pub type ALARM_COMPARE_MASK_R = crate::R; + #[doc = "Write proxy for field `alarm_compare_mask`"] + pub struct ALARM_COMPARE_MASK_W<'a> { + w: &'a mut W, + } + impl<'a> ALARM_COMPARE_MASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | (((value as u32) & 0xff) << 24); + self.w + } + } + impl R { + #[doc = "Bit 0 - TICK_ENABLE"] + #[inline(always)] + pub fn tick_enable(&self) -> TICK_ENABLE_R { + TICK_ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Alarm interrupt enable"] + #[inline(always)] + pub fn alarm_enable(&self) -> ALARM_ENABLE_R { + ALARM_ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Tick interrupt enable"] + #[inline(always)] + pub fn tick_int_mode(&self) -> TICK_INT_MODE_R { + TICK_INT_MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 24:31 - Alarm compare mask for interrupt"] + #[inline(always)] + pub fn alarm_compare_mask(&self) -> ALARM_COMPARE_MASK_R { + ALARM_COMPARE_MASK_R::new(((self.bits >> 24) & 0xff) as u8) + } + } + impl W { + #[doc = "Bit 0 - TICK_ENABLE"] + #[inline(always)] + pub fn tick_enable(&mut self) -> TICK_ENABLE_W { + TICK_ENABLE_W { w: self } + } + #[doc = "Bit 1 - Alarm interrupt enable"] + #[inline(always)] + pub fn alarm_enable(&mut self) -> ALARM_ENABLE_W { + ALARM_ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Tick interrupt enable"] + #[inline(always)] + pub fn tick_int_mode(&mut self) -> TICK_INT_MODE_W { + TICK_INT_MODE_W { w: self } + } + #[doc = "Bits 24:31 - Alarm compare mask for interrupt"] + #[inline(always)] + pub fn alarm_compare_mask(&mut self) -> ALARM_COMPARE_MASK_W { + ALARM_COMPARE_MASK_W { w: self } + } + } + } + #[doc = "RTC register settings\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [register_ctrl](register_ctrl) module"] + pub type REGISTER_CTRL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _REGISTER_CTRL; + #[doc = "`read()` method returns [register_ctrl::R](register_ctrl::R) reader structure"] + impl crate::Readable for REGISTER_CTRL {} + #[doc = "`write(|w| ..)` method takes [register_ctrl::W](register_ctrl::W) writer structure"] + impl crate::Writable for REGISTER_CTRL {} + #[doc = "RTC register settings"] + pub mod register_ctrl { + #[doc = "Reader of register register_ctrl"] + pub type R = crate::R; + #[doc = "Writer for register register_ctrl"] + pub type W = crate::W; + #[doc = "Register register_ctrl `reset()`'s with value 0"] + impl crate::ResetValue for super::REGISTER_CTRL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `read_enable`"] + pub type READ_ENABLE_R = crate::R; + #[doc = "Write proxy for field `read_enable`"] + pub struct READ_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> READ_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `write_enable`"] + pub type WRITE_ENABLE_R = crate::R; + #[doc = "Write proxy for field `write_enable`"] + pub struct WRITE_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> WRITE_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `timer_mask`"] + pub type TIMER_MASK_R = crate::R; + #[doc = "Write proxy for field `timer_mask`"] + pub struct TIMER_MASK_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER_MASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 13)) | (((value as u32) & 0xff) << 13); + self.w + } + } + #[doc = "Reader of field `alarm_mask`"] + pub type ALARM_MASK_R = crate::R; + #[doc = "Write proxy for field `alarm_mask`"] + pub struct ALARM_MASK_W<'a> { + w: &'a mut W, + } + impl<'a> ALARM_MASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 21)) | (((value as u32) & 0xff) << 21); + self.w + } + } + #[doc = "Reader of field `initial_count_mask`"] + pub type INITIAL_COUNT_MASK_R = crate::R; + #[doc = "Write proxy for field `initial_count_mask`"] + pub struct INITIAL_COUNT_MASK_W<'a> { + w: &'a mut W, + } + impl<'a> INITIAL_COUNT_MASK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29); + self.w + } + } + #[doc = "Reader of field `interrupt_register_mask`"] + pub type INTERRUPT_REGISTER_MASK_R = crate::R; + #[doc = "Write proxy for field `interrupt_register_mask`"] + pub struct INTERRUPT_REGISTER_MASK_W<'a> { + w: &'a mut W, + } + impl<'a> INTERRUPT_REGISTER_MASK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30); + self.w + } + } + impl R { + #[doc = "Bit 0 - RTC timer read enable"] + #[inline(always)] + pub fn read_enable(&self) -> READ_ENABLE_R { + READ_ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - RTC timer write enable"] + #[inline(always)] + pub fn write_enable(&self) -> WRITE_ENABLE_R { + WRITE_ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 13:20 - RTC timer mask"] + #[inline(always)] + pub fn timer_mask(&self) -> TIMER_MASK_R { + TIMER_MASK_R::new(((self.bits >> 13) & 0xff) as u8) + } + #[doc = "Bits 21:28 - RTC alarm mask"] + #[inline(always)] + pub fn alarm_mask(&self) -> ALARM_MASK_R { + ALARM_MASK_R::new(((self.bits >> 21) & 0xff) as u8) + } + #[doc = "Bit 29 - RTC counter initial count value mask"] + #[inline(always)] + pub fn initial_count_mask(&self) -> INITIAL_COUNT_MASK_R { + INITIAL_COUNT_MASK_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - RTC interrupt register mask"] + #[inline(always)] + pub fn interrupt_register_mask(&self) -> INTERRUPT_REGISTER_MASK_R { + INTERRUPT_REGISTER_MASK_R::new(((self.bits >> 30) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - RTC timer read enable"] + #[inline(always)] + pub fn read_enable(&mut self) -> READ_ENABLE_W { + READ_ENABLE_W { w: self } + } + #[doc = "Bit 1 - RTC timer write enable"] + #[inline(always)] + pub fn write_enable(&mut self) -> WRITE_ENABLE_W { + WRITE_ENABLE_W { w: self } + } + #[doc = "Bits 13:20 - RTC timer mask"] + #[inline(always)] + pub fn timer_mask(&mut self) -> TIMER_MASK_W { + TIMER_MASK_W { w: self } + } + #[doc = "Bits 21:28 - RTC alarm mask"] + #[inline(always)] + pub fn alarm_mask(&mut self) -> ALARM_MASK_W { + ALARM_MASK_W { w: self } + } + #[doc = "Bit 29 - RTC counter initial count value mask"] + #[inline(always)] + pub fn initial_count_mask(&mut self) -> INITIAL_COUNT_MASK_W { + INITIAL_COUNT_MASK_W { w: self } + } + #[doc = "Bit 30 - RTC interrupt register mask"] + #[inline(always)] + pub fn interrupt_register_mask(&mut self) -> INTERRUPT_REGISTER_MASK_W { + INTERRUPT_REGISTER_MASK_W { w: self } + } + } + } + #[doc = "Timer extended information\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [extended](extended) module"] + pub type EXTENDED = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _EXTENDED; + #[doc = "`read()` method returns [extended::R](extended::R) reader structure"] + impl crate::Readable for EXTENDED {} + #[doc = "`write(|w| ..)` method takes [extended::W](extended::W) writer structure"] + impl crate::Writable for EXTENDED {} + #[doc = "Timer extended information"] + pub mod extended { + #[doc = "Reader of register extended"] + pub type R = crate::R; + #[doc = "Writer for register extended"] + pub type W = crate::W; + #[doc = "Register extended `reset()`'s with value 0"] + impl crate::ResetValue for super::EXTENDED { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `century`"] + pub type CENTURY_R = crate::R; + #[doc = "Write proxy for field `century`"] + pub struct CENTURY_W<'a> { + w: &'a mut W, + } + impl<'a> CENTURY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f); + self.w + } + } + #[doc = "Is leap year. 1 is leap year, 0 is not leap year\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum LEAP_YEAR_A { + #[doc = "0: 0 is not leap year"] + NOT_LEAP = 0, + #[doc = "1: 1 is leap year"] + LEAP = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: LEAP_YEAR_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `leap_year`"] + pub type LEAP_YEAR_R = crate::R; + impl LEAP_YEAR_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LEAP_YEAR_A { + match self.bits { + false => LEAP_YEAR_A::NOT_LEAP, + true => LEAP_YEAR_A::LEAP, + } + } + #[doc = "Checks if the value of the field is `NOT_LEAP`"] + #[inline(always)] + pub fn is_not_leap(&self) -> bool { + *self == LEAP_YEAR_A::NOT_LEAP + } + #[doc = "Checks if the value of the field is `LEAP`"] + #[inline(always)] + pub fn is_leap(&self) -> bool { + *self == LEAP_YEAR_A::LEAP + } + } + #[doc = "Write proxy for field `leap_year`"] + pub struct LEAP_YEAR_W<'a> { + w: &'a mut W, + } + impl<'a> LEAP_YEAR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LEAP_YEAR_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "0 is not leap year"] + #[inline(always)] + pub fn not_leap(self) -> &'a mut W { + self.variant(LEAP_YEAR_A::NOT_LEAP) + } + #[doc = "1 is leap year"] + #[inline(always)] + pub fn leap(self) -> &'a mut W { + self.variant(LEAP_YEAR_A::LEAP) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + impl R { + #[doc = "Bits 0:4 - Century. Range \\[0,31\\]"] + #[inline(always)] + pub fn century(&self) -> CENTURY_R { + CENTURY_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 5 - Is leap year. 1 is leap year, 0 is not leap year"] + #[inline(always)] + pub fn leap_year(&self) -> LEAP_YEAR_R { + LEAP_YEAR_R::new(((self.bits >> 5) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:4 - Century. Range \\[0,31\\]"] + #[inline(always)] + pub fn century(&mut self) -> CENTURY_W { + CENTURY_W { w: self } + } + #[doc = "Bit 5 - Is leap year. 1 is leap year, 0 is not leap year"] + #[inline(always)] + pub fn leap_year(&mut self) -> LEAP_YEAR_W { + LEAP_YEAR_W { w: self } + } + } + } +} +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r"All the peripherals"] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "CLINT"] + pub CLINT: CLINT, + #[doc = "PLIC"] + pub PLIC: PLIC, + #[doc = "UARTHS"] + pub UARTHS: UARTHS, + #[doc = "GPIOHS"] + pub GPIOHS: GPIOHS, + #[doc = "KPU"] + pub KPU: KPU, + #[doc = "FFT"] + pub FFT: FFT, + #[doc = "DMAC"] + pub DMAC: DMAC, + #[doc = "GPIO"] + pub GPIO: GPIO, + #[doc = "UART1"] + pub UART1: UART1, + #[doc = "UART2"] + pub UART2: UART2, + #[doc = "UART3"] + pub UART3: UART3, + #[doc = "SPI0"] + pub SPI0: SPI0, + #[doc = "SPI1"] + pub SPI1: SPI1, + #[doc = "SPI2"] + pub SPI2: SPI2, + #[doc = "SPI3"] + pub SPI3: SPI3, + #[doc = "I2S0"] + pub I2S0: I2S0, + #[doc = "APU"] + pub APU: APU, + #[doc = "I2S1"] + pub I2S1: I2S1, + #[doc = "I2S2"] + pub I2S2: I2S2, + #[doc = "I2C0"] + pub I2C0: I2C0, + #[doc = "I2C1"] + pub I2C1: I2C1, + #[doc = "I2C2"] + pub I2C2: I2C2, + #[doc = "FPIOA"] + pub FPIOA: FPIOA, + #[doc = "SHA256"] + pub SHA256: SHA256, + #[doc = "TIMER0"] + pub TIMER0: TIMER0, + #[doc = "TIMER1"] + pub TIMER1: TIMER1, + #[doc = "TIMER2"] + pub TIMER2: TIMER2, + #[doc = "WDT0"] + pub WDT0: WDT0, + #[doc = "WDT1"] + pub WDT1: WDT1, + #[doc = "OTP"] + pub OTP: OTP, + #[doc = "DVP"] + pub DVP: DVP, + #[doc = "SYSCTL"] + pub SYSCTL: SYSCTL, + #[doc = "AES"] + pub AES: AES, + #[doc = "RTC"] + pub RTC: RTC, +} +impl Peripherals { + #[doc = r"Returns all the peripherals *once*"] + #[inline] + pub fn take() -> Option { + /* + riscv::interrupt::free(|_| { + if unsafe { DEVICE_PERIPHERALS } { + None + } else { + Some(unsafe { Peripherals::steal() }) + } + }) + */ + /* + if unsafe { DEVICE_PERIPHERALS } { + None + } else { + Some(unsafe { Peripherals::steal() }) + } + */ + Some(unsafe { Peripherals::steal() }) + } + #[doc = r"Unchecked version of `Peripherals::take`"] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + CLINT: CLINT { + _marker: PhantomData, + }, + PLIC: PLIC { + _marker: PhantomData, + }, + UARTHS: UARTHS { + _marker: PhantomData, + }, + GPIOHS: GPIOHS { + _marker: PhantomData, + }, + KPU: KPU { + _marker: PhantomData, + }, + FFT: FFT { + _marker: PhantomData, + }, + DMAC: DMAC { + _marker: PhantomData, + }, + GPIO: GPIO { + _marker: PhantomData, + }, + UART1: UART1 { + _marker: PhantomData, + }, + UART2: UART2 { + _marker: PhantomData, + }, + UART3: UART3 { + _marker: PhantomData, + }, + SPI0: SPI0 { + _marker: PhantomData, + }, + SPI1: SPI1 { + _marker: PhantomData, + }, + SPI2: SPI2 { + _marker: PhantomData, + }, + SPI3: SPI3 { + _marker: PhantomData, + }, + I2S0: I2S0 { + _marker: PhantomData, + }, + APU: APU { + _marker: PhantomData, + }, + I2S1: I2S1 { + _marker: PhantomData, + }, + I2S2: I2S2 { + _marker: PhantomData, + }, + I2C0: I2C0 { + _marker: PhantomData, + }, + I2C1: I2C1 { + _marker: PhantomData, + }, + I2C2: I2C2 { + _marker: PhantomData, + }, + FPIOA: FPIOA { + _marker: PhantomData, + }, + SHA256: SHA256 { + _marker: PhantomData, + }, + TIMER0: TIMER0 { + _marker: PhantomData, + }, + TIMER1: TIMER1 { + _marker: PhantomData, + }, + TIMER2: TIMER2 { + _marker: PhantomData, + }, + WDT0: WDT0 { + _marker: PhantomData, + }, + WDT1: WDT1 { + _marker: PhantomData, + }, + OTP: OTP { + _marker: PhantomData, + }, + DVP: DVP { + _marker: PhantomData, + }, + SYSCTL: SYSCTL { + _marker: PhantomData, + }, + AES: AES { + _marker: PhantomData, + }, + RTC: RTC { + _marker: PhantomData, + }, + } + } +} diff --git a/tools/k210-pac/update.sh b/tools/k210-pac/update.sh new file mode 100755 index 0000000..c4d3ecc --- /dev/null +++ b/tools/k210-pac/update.sh @@ -0,0 +1,9 @@ +#!/usr/bin/env bash +set -x +set -e + +rm -rf src +mkdir src +svd2rust --target riscv -i k210.svd +mv lib.rs src/ +cargo fmt diff --git a/tools/kflash.py b/tools/kflash.py new file mode 100755 index 0000000..d4cb1da --- /dev/null +++ b/tools/kflash.py @@ -0,0 +1,1452 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- + +from __future__ import (division, print_function) + +import sys +import time +import zlib +import copy +import struct +import binascii +import hashlib +import argparse +import math +import zipfile, tempfile +import json +import re +import os + + +class KFlash: + print_callback = None + + def __init__(self, print_callback = None): + self.killProcess = False + self.loader = None + self.print_callback = print_callback + + @staticmethod + def log(*args, **kwargs): + if KFlash.print_callback: + KFlash.print_callback(*args, **kwargs) + else: + print(*args, **kwargs) + + def process(self, terminal=True, dev="", baudrate=1500000, board=None, sram = False, file="", callback=None, noansi=False, terminal_auto_size=False, terminal_size=(50, 1), slow_mode = False): + self.killProcess = False + BASH_TIPS = dict(NORMAL='\033[0m',BOLD='\033[1m',DIM='\033[2m',UNDERLINE='\033[4m', + DEFAULT='\033[0m', RED='\033[31m', YELLOW='\033[33m', GREEN='\033[32m', + BG_DEFAULT='\033[49m', BG_WHITE='\033[107m') + + ERROR_MSG = BASH_TIPS['RED']+BASH_TIPS['BOLD']+'[ERROR]'+BASH_TIPS['NORMAL'] + WARN_MSG = BASH_TIPS['YELLOW']+BASH_TIPS['BOLD']+'[WARN]'+BASH_TIPS['NORMAL'] + INFO_MSG = BASH_TIPS['GREEN']+BASH_TIPS['BOLD']+'[INFO]'+BASH_TIPS['NORMAL'] + + VID_LIST_FOR_AUTO_LOOKUP = "(1A86)|(0403)|(067B)|(10C4)|(C251)|(0403)" + # WCH FTDI PL CL DAP OPENEC + ISP_RECEIVE_TIMEOUT = 0.5 + + MAX_RETRY_TIMES = 10 + + ISP_FLASH_SECTOR_SIZE = 4096 + ISP_FLASH_DATA_FRAME_SIZE = ISP_FLASH_SECTOR_SIZE * 16 + + def tuple2str(t): + ret = "" + for i in t: + ret += i+" " + return ret + + def raise_exception(exception): + if self.loader: + try: + self.loader._port.close() + except Exception: + pass + raise exception + + try: + from enum import Enum + except ImportError: + err = (ERROR_MSG,'enum34 must be installed, run '+BASH_TIPS['GREEN']+'`' + ('pip', 'pip3')[sys.version_info > (3, 0)] + ' install enum34`',BASH_TIPS['DEFAULT']) + err = tuple2str(err) + raise Exception(err) + try: + import serial + import serial.tools.list_ports + except ImportError: + err = (ERROR_MSG,'PySerial must be installed, run '+BASH_TIPS['GREEN']+'`' + ('pip', 'pip3')[sys.version_info > (3, 0)] + ' install pyserial`',BASH_TIPS['DEFAULT']) + err = tuple2str(err) + raise Exception(err) + + class TimeoutError(Exception): pass + + class ProgramFileFormat(Enum): + FMT_BINARY = 0 + FMT_ELF = 1 + FMT_KFPKG = 2 + + # AES is from: https://github.com/ricmoo/pyaes, Copyright by Richard Moore + class AES: + '''Encapsulates the AES block cipher. + You generally should not need this. Use the AESModeOfOperation classes + below instead.''' + @staticmethod + def _compact_word(word): + return (word[0] << 24) | (word[1] << 16) | (word[2] << 8) | word[3] + + # Number of rounds by keysize + number_of_rounds = {16: 10, 24: 12, 32: 14} + + # Round constant words + rcon = [ 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91 ] + + # S-box and Inverse S-box (S is for Substitution) + S = [ 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb, 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16 ] + Si =[ 0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb, 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb, 0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e, 0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25, 0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92, 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84, 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06, 0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b, 0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73, 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e, 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b, 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4, 0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f, 0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef, 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61, 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d ] + + # Transformations for encryption + T1 = [ 0xc66363a5, 0xf87c7c84, 0xee777799, 0xf67b7b8d, 0xfff2f20d, 0xd66b6bbd, 0xde6f6fb1, 0x91c5c554, 0x60303050, 0x02010103, 0xce6767a9, 0x562b2b7d, 0xe7fefe19, 0xb5d7d762, 0x4dababe6, 0xec76769a, 0x8fcaca45, 0x1f82829d, 0x89c9c940, 0xfa7d7d87, 0xeffafa15, 0xb25959eb, 0x8e4747c9, 0xfbf0f00b, 0x41adadec, 0xb3d4d467, 0x5fa2a2fd, 0x45afafea, 0x239c9cbf, 0x53a4a4f7, 0xe4727296, 0x9bc0c05b, 0x75b7b7c2, 0xe1fdfd1c, 0x3d9393ae, 0x4c26266a, 0x6c36365a, 0x7e3f3f41, 0xf5f7f702, 0x83cccc4f, 0x6834345c, 0x51a5a5f4, 0xd1e5e534, 0xf9f1f108, 0xe2717193, 0xabd8d873, 0x62313153, 0x2a15153f, 0x0804040c, 0x95c7c752, 0x46232365, 0x9dc3c35e, 0x30181828, 0x379696a1, 0x0a05050f, 0x2f9a9ab5, 0x0e070709, 0x24121236, 0x1b80809b, 0xdfe2e23d, 0xcdebeb26, 0x4e272769, 0x7fb2b2cd, 0xea75759f, 0x1209091b, 0x1d83839e, 0x582c2c74, 0x341a1a2e, 0x361b1b2d, 0xdc6e6eb2, 0xb45a5aee, 0x5ba0a0fb, 0xa45252f6, 0x763b3b4d, 0xb7d6d661, 0x7db3b3ce, 0x5229297b, 0xdde3e33e, 0x5e2f2f71, 0x13848497, 0xa65353f5, 0xb9d1d168, 0x00000000, 0xc1eded2c, 0x40202060, 0xe3fcfc1f, 0x79b1b1c8, 0xb65b5bed, 0xd46a6abe, 0x8dcbcb46, 0x67bebed9, 0x7239394b, 0x944a4ade, 0x984c4cd4, 0xb05858e8, 0x85cfcf4a, 0xbbd0d06b, 0xc5efef2a, 0x4faaaae5, 0xedfbfb16, 0x864343c5, 0x9a4d4dd7, 0x66333355, 0x11858594, 0x8a4545cf, 0xe9f9f910, 0x04020206, 0xfe7f7f81, 0xa05050f0, 0x783c3c44, 0x259f9fba, 0x4ba8a8e3, 0xa25151f3, 0x5da3a3fe, 0x804040c0, 0x058f8f8a, 0x3f9292ad, 0x219d9dbc, 0x70383848, 0xf1f5f504, 0x63bcbcdf, 0x77b6b6c1, 0xafdada75, 0x42212163, 0x20101030, 0xe5ffff1a, 0xfdf3f30e, 0xbfd2d26d, 0x81cdcd4c, 0x180c0c14, 0x26131335, 0xc3ecec2f, 0xbe5f5fe1, 0x359797a2, 0x884444cc, 0x2e171739, 0x93c4c457, 0x55a7a7f2, 0xfc7e7e82, 0x7a3d3d47, 0xc86464ac, 0xba5d5de7, 0x3219192b, 0xe6737395, 0xc06060a0, 0x19818198, 0x9e4f4fd1, 0xa3dcdc7f, 0x44222266, 0x542a2a7e, 0x3b9090ab, 0x0b888883, 0x8c4646ca, 0xc7eeee29, 0x6bb8b8d3, 0x2814143c, 0xa7dede79, 0xbc5e5ee2, 0x160b0b1d, 0xaddbdb76, 0xdbe0e03b, 0x64323256, 0x743a3a4e, 0x140a0a1e, 0x924949db, 0x0c06060a, 0x4824246c, 0xb85c5ce4, 0x9fc2c25d, 0xbdd3d36e, 0x43acacef, 0xc46262a6, 0x399191a8, 0x319595a4, 0xd3e4e437, 0xf279798b, 0xd5e7e732, 0x8bc8c843, 0x6e373759, 0xda6d6db7, 0x018d8d8c, 0xb1d5d564, 0x9c4e4ed2, 0x49a9a9e0, 0xd86c6cb4, 0xac5656fa, 0xf3f4f407, 0xcfeaea25, 0xca6565af, 0xf47a7a8e, 0x47aeaee9, 0x10080818, 0x6fbabad5, 0xf0787888, 0x4a25256f, 0x5c2e2e72, 0x381c1c24, 0x57a6a6f1, 0x73b4b4c7, 0x97c6c651, 0xcbe8e823, 0xa1dddd7c, 0xe874749c, 0x3e1f1f21, 0x964b4bdd, 0x61bdbddc, 0x0d8b8b86, 0x0f8a8a85, 0xe0707090, 0x7c3e3e42, 0x71b5b5c4, 0xcc6666aa, 0x904848d8, 0x06030305, 0xf7f6f601, 0x1c0e0e12, 0xc26161a3, 0x6a35355f, 0xae5757f9, 0x69b9b9d0, 0x17868691, 0x99c1c158, 0x3a1d1d27, 0x279e9eb9, 0xd9e1e138, 0xebf8f813, 0x2b9898b3, 0x22111133, 0xd26969bb, 0xa9d9d970, 0x078e8e89, 0x339494a7, 0x2d9b9bb6, 0x3c1e1e22, 0x15878792, 0xc9e9e920, 0x87cece49, 0xaa5555ff, 0x50282878, 0xa5dfdf7a, 0x038c8c8f, 0x59a1a1f8, 0x09898980, 0x1a0d0d17, 0x65bfbfda, 0xd7e6e631, 0x844242c6, 0xd06868b8, 0x824141c3, 0x299999b0, 0x5a2d2d77, 0x1e0f0f11, 0x7bb0b0cb, 0xa85454fc, 0x6dbbbbd6, 0x2c16163a ] + T2 = [ 0xa5c66363, 0x84f87c7c, 0x99ee7777, 0x8df67b7b, 0x0dfff2f2, 0xbdd66b6b, 0xb1de6f6f, 0x5491c5c5, 0x50603030, 0x03020101, 0xa9ce6767, 0x7d562b2b, 0x19e7fefe, 0x62b5d7d7, 0xe64dabab, 0x9aec7676, 0x458fcaca, 0x9d1f8282, 0x4089c9c9, 0x87fa7d7d, 0x15effafa, 0xebb25959, 0xc98e4747, 0x0bfbf0f0, 0xec41adad, 0x67b3d4d4, 0xfd5fa2a2, 0xea45afaf, 0xbf239c9c, 0xf753a4a4, 0x96e47272, 0x5b9bc0c0, 0xc275b7b7, 0x1ce1fdfd, 0xae3d9393, 0x6a4c2626, 0x5a6c3636, 0x417e3f3f, 0x02f5f7f7, 0x4f83cccc, 0x5c683434, 0xf451a5a5, 0x34d1e5e5, 0x08f9f1f1, 0x93e27171, 0x73abd8d8, 0x53623131, 0x3f2a1515, 0x0c080404, 0x5295c7c7, 0x65462323, 0x5e9dc3c3, 0x28301818, 0xa1379696, 0x0f0a0505, 0xb52f9a9a, 0x090e0707, 0x36241212, 0x9b1b8080, 0x3ddfe2e2, 0x26cdebeb, 0x694e2727, 0xcd7fb2b2, 0x9fea7575, 0x1b120909, 0x9e1d8383, 0x74582c2c, 0x2e341a1a, 0x2d361b1b, 0xb2dc6e6e, 0xeeb45a5a, 0xfb5ba0a0, 0xf6a45252, 0x4d763b3b, 0x61b7d6d6, 0xce7db3b3, 0x7b522929, 0x3edde3e3, 0x715e2f2f, 0x97138484, 0xf5a65353, 0x68b9d1d1, 0x00000000, 0x2cc1eded, 0x60402020, 0x1fe3fcfc, 0xc879b1b1, 0xedb65b5b, 0xbed46a6a, 0x468dcbcb, 0xd967bebe, 0x4b723939, 0xde944a4a, 0xd4984c4c, 0xe8b05858, 0x4a85cfcf, 0x6bbbd0d0, 0x2ac5efef, 0xe54faaaa, 0x16edfbfb, 0xc5864343, 0xd79a4d4d, 0x55663333, 0x94118585, 0xcf8a4545, 0x10e9f9f9, 0x06040202, 0x81fe7f7f, 0xf0a05050, 0x44783c3c, 0xba259f9f, 0xe34ba8a8, 0xf3a25151, 0xfe5da3a3, 0xc0804040, 0x8a058f8f, 0xad3f9292, 0xbc219d9d, 0x48703838, 0x04f1f5f5, 0xdf63bcbc, 0xc177b6b6, 0x75afdada, 0x63422121, 0x30201010, 0x1ae5ffff, 0x0efdf3f3, 0x6dbfd2d2, 0x4c81cdcd, 0x14180c0c, 0x35261313, 0x2fc3ecec, 0xe1be5f5f, 0xa2359797, 0xcc884444, 0x392e1717, 0x5793c4c4, 0xf255a7a7, 0x82fc7e7e, 0x477a3d3d, 0xacc86464, 0xe7ba5d5d, 0x2b321919, 0x95e67373, 0xa0c06060, 0x98198181, 0xd19e4f4f, 0x7fa3dcdc, 0x66442222, 0x7e542a2a, 0xab3b9090, 0x830b8888, 0xca8c4646, 0x29c7eeee, 0xd36bb8b8, 0x3c281414, 0x79a7dede, 0xe2bc5e5e, 0x1d160b0b, 0x76addbdb, 0x3bdbe0e0, 0x56643232, 0x4e743a3a, 0x1e140a0a, 0xdb924949, 0x0a0c0606, 0x6c482424, 0xe4b85c5c, 0x5d9fc2c2, 0x6ebdd3d3, 0xef43acac, 0xa6c46262, 0xa8399191, 0xa4319595, 0x37d3e4e4, 0x8bf27979, 0x32d5e7e7, 0x438bc8c8, 0x596e3737, 0xb7da6d6d, 0x8c018d8d, 0x64b1d5d5, 0xd29c4e4e, 0xe049a9a9, 0xb4d86c6c, 0xfaac5656, 0x07f3f4f4, 0x25cfeaea, 0xafca6565, 0x8ef47a7a, 0xe947aeae, 0x18100808, 0xd56fbaba, 0x88f07878, 0x6f4a2525, 0x725c2e2e, 0x24381c1c, 0xf157a6a6, 0xc773b4b4, 0x5197c6c6, 0x23cbe8e8, 0x7ca1dddd, 0x9ce87474, 0x213e1f1f, 0xdd964b4b, 0xdc61bdbd, 0x860d8b8b, 0x850f8a8a, 0x90e07070, 0x427c3e3e, 0xc471b5b5, 0xaacc6666, 0xd8904848, 0x05060303, 0x01f7f6f6, 0x121c0e0e, 0xa3c26161, 0x5f6a3535, 0xf9ae5757, 0xd069b9b9, 0x91178686, 0x5899c1c1, 0x273a1d1d, 0xb9279e9e, 0x38d9e1e1, 0x13ebf8f8, 0xb32b9898, 0x33221111, 0xbbd26969, 0x70a9d9d9, 0x89078e8e, 0xa7339494, 0xb62d9b9b, 0x223c1e1e, 0x92158787, 0x20c9e9e9, 0x4987cece, 0xffaa5555, 0x78502828, 0x7aa5dfdf, 0x8f038c8c, 0xf859a1a1, 0x80098989, 0x171a0d0d, 0xda65bfbf, 0x31d7e6e6, 0xc6844242, 0xb8d06868, 0xc3824141, 0xb0299999, 0x775a2d2d, 0x111e0f0f, 0xcb7bb0b0, 0xfca85454, 0xd66dbbbb, 0x3a2c1616 ] + T3 = [ 0x63a5c663, 0x7c84f87c, 0x7799ee77, 0x7b8df67b, 0xf20dfff2, 0x6bbdd66b, 0x6fb1de6f, 0xc55491c5, 0x30506030, 0x01030201, 0x67a9ce67, 0x2b7d562b, 0xfe19e7fe, 0xd762b5d7, 0xabe64dab, 0x769aec76, 0xca458fca, 0x829d1f82, 0xc94089c9, 0x7d87fa7d, 0xfa15effa, 0x59ebb259, 0x47c98e47, 0xf00bfbf0, 0xadec41ad, 0xd467b3d4, 0xa2fd5fa2, 0xafea45af, 0x9cbf239c, 0xa4f753a4, 0x7296e472, 0xc05b9bc0, 0xb7c275b7, 0xfd1ce1fd, 0x93ae3d93, 0x266a4c26, 0x365a6c36, 0x3f417e3f, 0xf702f5f7, 0xcc4f83cc, 0x345c6834, 0xa5f451a5, 0xe534d1e5, 0xf108f9f1, 0x7193e271, 0xd873abd8, 0x31536231, 0x153f2a15, 0x040c0804, 0xc75295c7, 0x23654623, 0xc35e9dc3, 0x18283018, 0x96a13796, 0x050f0a05, 0x9ab52f9a, 0x07090e07, 0x12362412, 0x809b1b80, 0xe23ddfe2, 0xeb26cdeb, 0x27694e27, 0xb2cd7fb2, 0x759fea75, 0x091b1209, 0x839e1d83, 0x2c74582c, 0x1a2e341a, 0x1b2d361b, 0x6eb2dc6e, 0x5aeeb45a, 0xa0fb5ba0, 0x52f6a452, 0x3b4d763b, 0xd661b7d6, 0xb3ce7db3, 0x297b5229, 0xe33edde3, 0x2f715e2f, 0x84971384, 0x53f5a653, 0xd168b9d1, 0x00000000, 0xed2cc1ed, 0x20604020, 0xfc1fe3fc, 0xb1c879b1, 0x5bedb65b, 0x6abed46a, 0xcb468dcb, 0xbed967be, 0x394b7239, 0x4ade944a, 0x4cd4984c, 0x58e8b058, 0xcf4a85cf, 0xd06bbbd0, 0xef2ac5ef, 0xaae54faa, 0xfb16edfb, 0x43c58643, 0x4dd79a4d, 0x33556633, 0x85941185, 0x45cf8a45, 0xf910e9f9, 0x02060402, 0x7f81fe7f, 0x50f0a050, 0x3c44783c, 0x9fba259f, 0xa8e34ba8, 0x51f3a251, 0xa3fe5da3, 0x40c08040, 0x8f8a058f, 0x92ad3f92, 0x9dbc219d, 0x38487038, 0xf504f1f5, 0xbcdf63bc, 0xb6c177b6, 0xda75afda, 0x21634221, 0x10302010, 0xff1ae5ff, 0xf30efdf3, 0xd26dbfd2, 0xcd4c81cd, 0x0c14180c, 0x13352613, 0xec2fc3ec, 0x5fe1be5f, 0x97a23597, 0x44cc8844, 0x17392e17, 0xc45793c4, 0xa7f255a7, 0x7e82fc7e, 0x3d477a3d, 0x64acc864, 0x5de7ba5d, 0x192b3219, 0x7395e673, 0x60a0c060, 0x81981981, 0x4fd19e4f, 0xdc7fa3dc, 0x22664422, 0x2a7e542a, 0x90ab3b90, 0x88830b88, 0x46ca8c46, 0xee29c7ee, 0xb8d36bb8, 0x143c2814, 0xde79a7de, 0x5ee2bc5e, 0x0b1d160b, 0xdb76addb, 0xe03bdbe0, 0x32566432, 0x3a4e743a, 0x0a1e140a, 0x49db9249, 0x060a0c06, 0x246c4824, 0x5ce4b85c, 0xc25d9fc2, 0xd36ebdd3, 0xacef43ac, 0x62a6c462, 0x91a83991, 0x95a43195, 0xe437d3e4, 0x798bf279, 0xe732d5e7, 0xc8438bc8, 0x37596e37, 0x6db7da6d, 0x8d8c018d, 0xd564b1d5, 0x4ed29c4e, 0xa9e049a9, 0x6cb4d86c, 0x56faac56, 0xf407f3f4, 0xea25cfea, 0x65afca65, 0x7a8ef47a, 0xaee947ae, 0x08181008, 0xbad56fba, 0x7888f078, 0x256f4a25, 0x2e725c2e, 0x1c24381c, 0xa6f157a6, 0xb4c773b4, 0xc65197c6, 0xe823cbe8, 0xdd7ca1dd, 0x749ce874, 0x1f213e1f, 0x4bdd964b, 0xbddc61bd, 0x8b860d8b, 0x8a850f8a, 0x7090e070, 0x3e427c3e, 0xb5c471b5, 0x66aacc66, 0x48d89048, 0x03050603, 0xf601f7f6, 0x0e121c0e, 0x61a3c261, 0x355f6a35, 0x57f9ae57, 0xb9d069b9, 0x86911786, 0xc15899c1, 0x1d273a1d, 0x9eb9279e, 0xe138d9e1, 0xf813ebf8, 0x98b32b98, 0x11332211, 0x69bbd269, 0xd970a9d9, 0x8e89078e, 0x94a73394, 0x9bb62d9b, 0x1e223c1e, 0x87921587, 0xe920c9e9, 0xce4987ce, 0x55ffaa55, 0x28785028, 0xdf7aa5df, 0x8c8f038c, 0xa1f859a1, 0x89800989, 0x0d171a0d, 0xbfda65bf, 0xe631d7e6, 0x42c68442, 0x68b8d068, 0x41c38241, 0x99b02999, 0x2d775a2d, 0x0f111e0f, 0xb0cb7bb0, 0x54fca854, 0xbbd66dbb, 0x163a2c16 ] + T4 = [ 0x6363a5c6, 0x7c7c84f8, 0x777799ee, 0x7b7b8df6, 0xf2f20dff, 0x6b6bbdd6, 0x6f6fb1de, 0xc5c55491, 0x30305060, 0x01010302, 0x6767a9ce, 0x2b2b7d56, 0xfefe19e7, 0xd7d762b5, 0xababe64d, 0x76769aec, 0xcaca458f, 0x82829d1f, 0xc9c94089, 0x7d7d87fa, 0xfafa15ef, 0x5959ebb2, 0x4747c98e, 0xf0f00bfb, 0xadadec41, 0xd4d467b3, 0xa2a2fd5f, 0xafafea45, 0x9c9cbf23, 0xa4a4f753, 0x727296e4, 0xc0c05b9b, 0xb7b7c275, 0xfdfd1ce1, 0x9393ae3d, 0x26266a4c, 0x36365a6c, 0x3f3f417e, 0xf7f702f5, 0xcccc4f83, 0x34345c68, 0xa5a5f451, 0xe5e534d1, 0xf1f108f9, 0x717193e2, 0xd8d873ab, 0x31315362, 0x15153f2a, 0x04040c08, 0xc7c75295, 0x23236546, 0xc3c35e9d, 0x18182830, 0x9696a137, 0x05050f0a, 0x9a9ab52f, 0x0707090e, 0x12123624, 0x80809b1b, 0xe2e23ddf, 0xebeb26cd, 0x2727694e, 0xb2b2cd7f, 0x75759fea, 0x09091b12, 0x83839e1d, 0x2c2c7458, 0x1a1a2e34, 0x1b1b2d36, 0x6e6eb2dc, 0x5a5aeeb4, 0xa0a0fb5b, 0x5252f6a4, 0x3b3b4d76, 0xd6d661b7, 0xb3b3ce7d, 0x29297b52, 0xe3e33edd, 0x2f2f715e, 0x84849713, 0x5353f5a6, 0xd1d168b9, 0x00000000, 0xeded2cc1, 0x20206040, 0xfcfc1fe3, 0xb1b1c879, 0x5b5bedb6, 0x6a6abed4, 0xcbcb468d, 0xbebed967, 0x39394b72, 0x4a4ade94, 0x4c4cd498, 0x5858e8b0, 0xcfcf4a85, 0xd0d06bbb, 0xefef2ac5, 0xaaaae54f, 0xfbfb16ed, 0x4343c586, 0x4d4dd79a, 0x33335566, 0x85859411, 0x4545cf8a, 0xf9f910e9, 0x02020604, 0x7f7f81fe, 0x5050f0a0, 0x3c3c4478, 0x9f9fba25, 0xa8a8e34b, 0x5151f3a2, 0xa3a3fe5d, 0x4040c080, 0x8f8f8a05, 0x9292ad3f, 0x9d9dbc21, 0x38384870, 0xf5f504f1, 0xbcbcdf63, 0xb6b6c177, 0xdada75af, 0x21216342, 0x10103020, 0xffff1ae5, 0xf3f30efd, 0xd2d26dbf, 0xcdcd4c81, 0x0c0c1418, 0x13133526, 0xecec2fc3, 0x5f5fe1be, 0x9797a235, 0x4444cc88, 0x1717392e, 0xc4c45793, 0xa7a7f255, 0x7e7e82fc, 0x3d3d477a, 0x6464acc8, 0x5d5de7ba, 0x19192b32, 0x737395e6, 0x6060a0c0, 0x81819819, 0x4f4fd19e, 0xdcdc7fa3, 0x22226644, 0x2a2a7e54, 0x9090ab3b, 0x8888830b, 0x4646ca8c, 0xeeee29c7, 0xb8b8d36b, 0x14143c28, 0xdede79a7, 0x5e5ee2bc, 0x0b0b1d16, 0xdbdb76ad, 0xe0e03bdb, 0x32325664, 0x3a3a4e74, 0x0a0a1e14, 0x4949db92, 0x06060a0c, 0x24246c48, 0x5c5ce4b8, 0xc2c25d9f, 0xd3d36ebd, 0xacacef43, 0x6262a6c4, 0x9191a839, 0x9595a431, 0xe4e437d3, 0x79798bf2, 0xe7e732d5, 0xc8c8438b, 0x3737596e, 0x6d6db7da, 0x8d8d8c01, 0xd5d564b1, 0x4e4ed29c, 0xa9a9e049, 0x6c6cb4d8, 0x5656faac, 0xf4f407f3, 0xeaea25cf, 0x6565afca, 0x7a7a8ef4, 0xaeaee947, 0x08081810, 0xbabad56f, 0x787888f0, 0x25256f4a, 0x2e2e725c, 0x1c1c2438, 0xa6a6f157, 0xb4b4c773, 0xc6c65197, 0xe8e823cb, 0xdddd7ca1, 0x74749ce8, 0x1f1f213e, 0x4b4bdd96, 0xbdbddc61, 0x8b8b860d, 0x8a8a850f, 0x707090e0, 0x3e3e427c, 0xb5b5c471, 0x6666aacc, 0x4848d890, 0x03030506, 0xf6f601f7, 0x0e0e121c, 0x6161a3c2, 0x35355f6a, 0x5757f9ae, 0xb9b9d069, 0x86869117, 0xc1c15899, 0x1d1d273a, 0x9e9eb927, 0xe1e138d9, 0xf8f813eb, 0x9898b32b, 0x11113322, 0x6969bbd2, 0xd9d970a9, 0x8e8e8907, 0x9494a733, 0x9b9bb62d, 0x1e1e223c, 0x87879215, 0xe9e920c9, 0xcece4987, 0x5555ffaa, 0x28287850, 0xdfdf7aa5, 0x8c8c8f03, 0xa1a1f859, 0x89898009, 0x0d0d171a, 0xbfbfda65, 0xe6e631d7, 0x4242c684, 0x6868b8d0, 0x4141c382, 0x9999b029, 0x2d2d775a, 0x0f0f111e, 0xb0b0cb7b, 0x5454fca8, 0xbbbbd66d, 0x16163a2c ] + + # Transformations for decryption + T5 = [ 0x51f4a750, 0x7e416553, 0x1a17a4c3, 0x3a275e96, 0x3bab6bcb, 0x1f9d45f1, 0xacfa58ab, 0x4be30393, 0x2030fa55, 0xad766df6, 0x88cc7691, 0xf5024c25, 0x4fe5d7fc, 0xc52acbd7, 0x26354480, 0xb562a38f, 0xdeb15a49, 0x25ba1b67, 0x45ea0e98, 0x5dfec0e1, 0xc32f7502, 0x814cf012, 0x8d4697a3, 0x6bd3f9c6, 0x038f5fe7, 0x15929c95, 0xbf6d7aeb, 0x955259da, 0xd4be832d, 0x587421d3, 0x49e06929, 0x8ec9c844, 0x75c2896a, 0xf48e7978, 0x99583e6b, 0x27b971dd, 0xbee14fb6, 0xf088ad17, 0xc920ac66, 0x7dce3ab4, 0x63df4a18, 0xe51a3182, 0x97513360, 0x62537f45, 0xb16477e0, 0xbb6bae84, 0xfe81a01c, 0xf9082b94, 0x70486858, 0x8f45fd19, 0x94de6c87, 0x527bf8b7, 0xab73d323, 0x724b02e2, 0xe31f8f57, 0x6655ab2a, 0xb2eb2807, 0x2fb5c203, 0x86c57b9a, 0xd33708a5, 0x302887f2, 0x23bfa5b2, 0x02036aba, 0xed16825c, 0x8acf1c2b, 0xa779b492, 0xf307f2f0, 0x4e69e2a1, 0x65daf4cd, 0x0605bed5, 0xd134621f, 0xc4a6fe8a, 0x342e539d, 0xa2f355a0, 0x058ae132, 0xa4f6eb75, 0x0b83ec39, 0x4060efaa, 0x5e719f06, 0xbd6e1051, 0x3e218af9, 0x96dd063d, 0xdd3e05ae, 0x4de6bd46, 0x91548db5, 0x71c45d05, 0x0406d46f, 0x605015ff, 0x1998fb24, 0xd6bde997, 0x894043cc, 0x67d99e77, 0xb0e842bd, 0x07898b88, 0xe7195b38, 0x79c8eedb, 0xa17c0a47, 0x7c420fe9, 0xf8841ec9, 0x00000000, 0x09808683, 0x322bed48, 0x1e1170ac, 0x6c5a724e, 0xfd0efffb, 0x0f853856, 0x3daed51e, 0x362d3927, 0x0a0fd964, 0x685ca621, 0x9b5b54d1, 0x24362e3a, 0x0c0a67b1, 0x9357e70f, 0xb4ee96d2, 0x1b9b919e, 0x80c0c54f, 0x61dc20a2, 0x5a774b69, 0x1c121a16, 0xe293ba0a, 0xc0a02ae5, 0x3c22e043, 0x121b171d, 0x0e090d0b, 0xf28bc7ad, 0x2db6a8b9, 0x141ea9c8, 0x57f11985, 0xaf75074c, 0xee99ddbb, 0xa37f60fd, 0xf701269f, 0x5c72f5bc, 0x44663bc5, 0x5bfb7e34, 0x8b432976, 0xcb23c6dc, 0xb6edfc68, 0xb8e4f163, 0xd731dcca, 0x42638510, 0x13972240, 0x84c61120, 0x854a247d, 0xd2bb3df8, 0xaef93211, 0xc729a16d, 0x1d9e2f4b, 0xdcb230f3, 0x0d8652ec, 0x77c1e3d0, 0x2bb3166c, 0xa970b999, 0x119448fa, 0x47e96422, 0xa8fc8cc4, 0xa0f03f1a, 0x567d2cd8, 0x223390ef, 0x87494ec7, 0xd938d1c1, 0x8ccaa2fe, 0x98d40b36, 0xa6f581cf, 0xa57ade28, 0xdab78e26, 0x3fadbfa4, 0x2c3a9de4, 0x5078920d, 0x6a5fcc9b, 0x547e4662, 0xf68d13c2, 0x90d8b8e8, 0x2e39f75e, 0x82c3aff5, 0x9f5d80be, 0x69d0937c, 0x6fd52da9, 0xcf2512b3, 0xc8ac993b, 0x10187da7, 0xe89c636e, 0xdb3bbb7b, 0xcd267809, 0x6e5918f4, 0xec9ab701, 0x834f9aa8, 0xe6956e65, 0xaaffe67e, 0x21bccf08, 0xef15e8e6, 0xbae79bd9, 0x4a6f36ce, 0xea9f09d4, 0x29b07cd6, 0x31a4b2af, 0x2a3f2331, 0xc6a59430, 0x35a266c0, 0x744ebc37, 0xfc82caa6, 0xe090d0b0, 0x33a7d815, 0xf104984a, 0x41ecdaf7, 0x7fcd500e, 0x1791f62f, 0x764dd68d, 0x43efb04d, 0xccaa4d54, 0xe49604df, 0x9ed1b5e3, 0x4c6a881b, 0xc12c1fb8, 0x4665517f, 0x9d5eea04, 0x018c355d, 0xfa877473, 0xfb0b412e, 0xb3671d5a, 0x92dbd252, 0xe9105633, 0x6dd64713, 0x9ad7618c, 0x37a10c7a, 0x59f8148e, 0xeb133c89, 0xcea927ee, 0xb761c935, 0xe11ce5ed, 0x7a47b13c, 0x9cd2df59, 0x55f2733f, 0x1814ce79, 0x73c737bf, 0x53f7cdea, 0x5ffdaa5b, 0xdf3d6f14, 0x7844db86, 0xcaaff381, 0xb968c43e, 0x3824342c, 0xc2a3405f, 0x161dc372, 0xbce2250c, 0x283c498b, 0xff0d9541, 0x39a80171, 0x080cb3de, 0xd8b4e49c, 0x6456c190, 0x7bcb8461, 0xd532b670, 0x486c5c74, 0xd0b85742 ] + T6 = [ 0x5051f4a7, 0x537e4165, 0xc31a17a4, 0x963a275e, 0xcb3bab6b, 0xf11f9d45, 0xabacfa58, 0x934be303, 0x552030fa, 0xf6ad766d, 0x9188cc76, 0x25f5024c, 0xfc4fe5d7, 0xd7c52acb, 0x80263544, 0x8fb562a3, 0x49deb15a, 0x6725ba1b, 0x9845ea0e, 0xe15dfec0, 0x02c32f75, 0x12814cf0, 0xa38d4697, 0xc66bd3f9, 0xe7038f5f, 0x9515929c, 0xebbf6d7a, 0xda955259, 0x2dd4be83, 0xd3587421, 0x2949e069, 0x448ec9c8, 0x6a75c289, 0x78f48e79, 0x6b99583e, 0xdd27b971, 0xb6bee14f, 0x17f088ad, 0x66c920ac, 0xb47dce3a, 0x1863df4a, 0x82e51a31, 0x60975133, 0x4562537f, 0xe0b16477, 0x84bb6bae, 0x1cfe81a0, 0x94f9082b, 0x58704868, 0x198f45fd, 0x8794de6c, 0xb7527bf8, 0x23ab73d3, 0xe2724b02, 0x57e31f8f, 0x2a6655ab, 0x07b2eb28, 0x032fb5c2, 0x9a86c57b, 0xa5d33708, 0xf2302887, 0xb223bfa5, 0xba02036a, 0x5ced1682, 0x2b8acf1c, 0x92a779b4, 0xf0f307f2, 0xa14e69e2, 0xcd65daf4, 0xd50605be, 0x1fd13462, 0x8ac4a6fe, 0x9d342e53, 0xa0a2f355, 0x32058ae1, 0x75a4f6eb, 0x390b83ec, 0xaa4060ef, 0x065e719f, 0x51bd6e10, 0xf93e218a, 0x3d96dd06, 0xaedd3e05, 0x464de6bd, 0xb591548d, 0x0571c45d, 0x6f0406d4, 0xff605015, 0x241998fb, 0x97d6bde9, 0xcc894043, 0x7767d99e, 0xbdb0e842, 0x8807898b, 0x38e7195b, 0xdb79c8ee, 0x47a17c0a, 0xe97c420f, 0xc9f8841e, 0x00000000, 0x83098086, 0x48322bed, 0xac1e1170, 0x4e6c5a72, 0xfbfd0eff, 0x560f8538, 0x1e3daed5, 0x27362d39, 0x640a0fd9, 0x21685ca6, 0xd19b5b54, 0x3a24362e, 0xb10c0a67, 0x0f9357e7, 0xd2b4ee96, 0x9e1b9b91, 0x4f80c0c5, 0xa261dc20, 0x695a774b, 0x161c121a, 0x0ae293ba, 0xe5c0a02a, 0x433c22e0, 0x1d121b17, 0x0b0e090d, 0xadf28bc7, 0xb92db6a8, 0xc8141ea9, 0x8557f119, 0x4caf7507, 0xbbee99dd, 0xfda37f60, 0x9ff70126, 0xbc5c72f5, 0xc544663b, 0x345bfb7e, 0x768b4329, 0xdccb23c6, 0x68b6edfc, 0x63b8e4f1, 0xcad731dc, 0x10426385, 0x40139722, 0x2084c611, 0x7d854a24, 0xf8d2bb3d, 0x11aef932, 0x6dc729a1, 0x4b1d9e2f, 0xf3dcb230, 0xec0d8652, 0xd077c1e3, 0x6c2bb316, 0x99a970b9, 0xfa119448, 0x2247e964, 0xc4a8fc8c, 0x1aa0f03f, 0xd8567d2c, 0xef223390, 0xc787494e, 0xc1d938d1, 0xfe8ccaa2, 0x3698d40b, 0xcfa6f581, 0x28a57ade, 0x26dab78e, 0xa43fadbf, 0xe42c3a9d, 0x0d507892, 0x9b6a5fcc, 0x62547e46, 0xc2f68d13, 0xe890d8b8, 0x5e2e39f7, 0xf582c3af, 0xbe9f5d80, 0x7c69d093, 0xa96fd52d, 0xb3cf2512, 0x3bc8ac99, 0xa710187d, 0x6ee89c63, 0x7bdb3bbb, 0x09cd2678, 0xf46e5918, 0x01ec9ab7, 0xa8834f9a, 0x65e6956e, 0x7eaaffe6, 0x0821bccf, 0xe6ef15e8, 0xd9bae79b, 0xce4a6f36, 0xd4ea9f09, 0xd629b07c, 0xaf31a4b2, 0x312a3f23, 0x30c6a594, 0xc035a266, 0x37744ebc, 0xa6fc82ca, 0xb0e090d0, 0x1533a7d8, 0x4af10498, 0xf741ecda, 0x0e7fcd50, 0x2f1791f6, 0x8d764dd6, 0x4d43efb0, 0x54ccaa4d, 0xdfe49604, 0xe39ed1b5, 0x1b4c6a88, 0xb8c12c1f, 0x7f466551, 0x049d5eea, 0x5d018c35, 0x73fa8774, 0x2efb0b41, 0x5ab3671d, 0x5292dbd2, 0x33e91056, 0x136dd647, 0x8c9ad761, 0x7a37a10c, 0x8e59f814, 0x89eb133c, 0xeecea927, 0x35b761c9, 0xede11ce5, 0x3c7a47b1, 0x599cd2df, 0x3f55f273, 0x791814ce, 0xbf73c737, 0xea53f7cd, 0x5b5ffdaa, 0x14df3d6f, 0x867844db, 0x81caaff3, 0x3eb968c4, 0x2c382434, 0x5fc2a340, 0x72161dc3, 0x0cbce225, 0x8b283c49, 0x41ff0d95, 0x7139a801, 0xde080cb3, 0x9cd8b4e4, 0x906456c1, 0x617bcb84, 0x70d532b6, 0x74486c5c, 0x42d0b857 ] + T7 = [ 0xa75051f4, 0x65537e41, 0xa4c31a17, 0x5e963a27, 0x6bcb3bab, 0x45f11f9d, 0x58abacfa, 0x03934be3, 0xfa552030, 0x6df6ad76, 0x769188cc, 0x4c25f502, 0xd7fc4fe5, 0xcbd7c52a, 0x44802635, 0xa38fb562, 0x5a49deb1, 0x1b6725ba, 0x0e9845ea, 0xc0e15dfe, 0x7502c32f, 0xf012814c, 0x97a38d46, 0xf9c66bd3, 0x5fe7038f, 0x9c951592, 0x7aebbf6d, 0x59da9552, 0x832dd4be, 0x21d35874, 0x692949e0, 0xc8448ec9, 0x896a75c2, 0x7978f48e, 0x3e6b9958, 0x71dd27b9, 0x4fb6bee1, 0xad17f088, 0xac66c920, 0x3ab47dce, 0x4a1863df, 0x3182e51a, 0x33609751, 0x7f456253, 0x77e0b164, 0xae84bb6b, 0xa01cfe81, 0x2b94f908, 0x68587048, 0xfd198f45, 0x6c8794de, 0xf8b7527b, 0xd323ab73, 0x02e2724b, 0x8f57e31f, 0xab2a6655, 0x2807b2eb, 0xc2032fb5, 0x7b9a86c5, 0x08a5d337, 0x87f23028, 0xa5b223bf, 0x6aba0203, 0x825ced16, 0x1c2b8acf, 0xb492a779, 0xf2f0f307, 0xe2a14e69, 0xf4cd65da, 0xbed50605, 0x621fd134, 0xfe8ac4a6, 0x539d342e, 0x55a0a2f3, 0xe132058a, 0xeb75a4f6, 0xec390b83, 0xefaa4060, 0x9f065e71, 0x1051bd6e, 0x8af93e21, 0x063d96dd, 0x05aedd3e, 0xbd464de6, 0x8db59154, 0x5d0571c4, 0xd46f0406, 0x15ff6050, 0xfb241998, 0xe997d6bd, 0x43cc8940, 0x9e7767d9, 0x42bdb0e8, 0x8b880789, 0x5b38e719, 0xeedb79c8, 0x0a47a17c, 0x0fe97c42, 0x1ec9f884, 0x00000000, 0x86830980, 0xed48322b, 0x70ac1e11, 0x724e6c5a, 0xfffbfd0e, 0x38560f85, 0xd51e3dae, 0x3927362d, 0xd9640a0f, 0xa621685c, 0x54d19b5b, 0x2e3a2436, 0x67b10c0a, 0xe70f9357, 0x96d2b4ee, 0x919e1b9b, 0xc54f80c0, 0x20a261dc, 0x4b695a77, 0x1a161c12, 0xba0ae293, 0x2ae5c0a0, 0xe0433c22, 0x171d121b, 0x0d0b0e09, 0xc7adf28b, 0xa8b92db6, 0xa9c8141e, 0x198557f1, 0x074caf75, 0xddbbee99, 0x60fda37f, 0x269ff701, 0xf5bc5c72, 0x3bc54466, 0x7e345bfb, 0x29768b43, 0xc6dccb23, 0xfc68b6ed, 0xf163b8e4, 0xdccad731, 0x85104263, 0x22401397, 0x112084c6, 0x247d854a, 0x3df8d2bb, 0x3211aef9, 0xa16dc729, 0x2f4b1d9e, 0x30f3dcb2, 0x52ec0d86, 0xe3d077c1, 0x166c2bb3, 0xb999a970, 0x48fa1194, 0x642247e9, 0x8cc4a8fc, 0x3f1aa0f0, 0x2cd8567d, 0x90ef2233, 0x4ec78749, 0xd1c1d938, 0xa2fe8cca, 0x0b3698d4, 0x81cfa6f5, 0xde28a57a, 0x8e26dab7, 0xbfa43fad, 0x9de42c3a, 0x920d5078, 0xcc9b6a5f, 0x4662547e, 0x13c2f68d, 0xb8e890d8, 0xf75e2e39, 0xaff582c3, 0x80be9f5d, 0x937c69d0, 0x2da96fd5, 0x12b3cf25, 0x993bc8ac, 0x7da71018, 0x636ee89c, 0xbb7bdb3b, 0x7809cd26, 0x18f46e59, 0xb701ec9a, 0x9aa8834f, 0x6e65e695, 0xe67eaaff, 0xcf0821bc, 0xe8e6ef15, 0x9bd9bae7, 0x36ce4a6f, 0x09d4ea9f, 0x7cd629b0, 0xb2af31a4, 0x23312a3f, 0x9430c6a5, 0x66c035a2, 0xbc37744e, 0xcaa6fc82, 0xd0b0e090, 0xd81533a7, 0x984af104, 0xdaf741ec, 0x500e7fcd, 0xf62f1791, 0xd68d764d, 0xb04d43ef, 0x4d54ccaa, 0x04dfe496, 0xb5e39ed1, 0x881b4c6a, 0x1fb8c12c, 0x517f4665, 0xea049d5e, 0x355d018c, 0x7473fa87, 0x412efb0b, 0x1d5ab367, 0xd25292db, 0x5633e910, 0x47136dd6, 0x618c9ad7, 0x0c7a37a1, 0x148e59f8, 0x3c89eb13, 0x27eecea9, 0xc935b761, 0xe5ede11c, 0xb13c7a47, 0xdf599cd2, 0x733f55f2, 0xce791814, 0x37bf73c7, 0xcdea53f7, 0xaa5b5ffd, 0x6f14df3d, 0xdb867844, 0xf381caaf, 0xc43eb968, 0x342c3824, 0x405fc2a3, 0xc372161d, 0x250cbce2, 0x498b283c, 0x9541ff0d, 0x017139a8, 0xb3de080c, 0xe49cd8b4, 0xc1906456, 0x84617bcb, 0xb670d532, 0x5c74486c, 0x5742d0b8 ] + T8 = [ 0xf4a75051, 0x4165537e, 0x17a4c31a, 0x275e963a, 0xab6bcb3b, 0x9d45f11f, 0xfa58abac, 0xe303934b, 0x30fa5520, 0x766df6ad, 0xcc769188, 0x024c25f5, 0xe5d7fc4f, 0x2acbd7c5, 0x35448026, 0x62a38fb5, 0xb15a49de, 0xba1b6725, 0xea0e9845, 0xfec0e15d, 0x2f7502c3, 0x4cf01281, 0x4697a38d, 0xd3f9c66b, 0x8f5fe703, 0x929c9515, 0x6d7aebbf, 0x5259da95, 0xbe832dd4, 0x7421d358, 0xe0692949, 0xc9c8448e, 0xc2896a75, 0x8e7978f4, 0x583e6b99, 0xb971dd27, 0xe14fb6be, 0x88ad17f0, 0x20ac66c9, 0xce3ab47d, 0xdf4a1863, 0x1a3182e5, 0x51336097, 0x537f4562, 0x6477e0b1, 0x6bae84bb, 0x81a01cfe, 0x082b94f9, 0x48685870, 0x45fd198f, 0xde6c8794, 0x7bf8b752, 0x73d323ab, 0x4b02e272, 0x1f8f57e3, 0x55ab2a66, 0xeb2807b2, 0xb5c2032f, 0xc57b9a86, 0x3708a5d3, 0x2887f230, 0xbfa5b223, 0x036aba02, 0x16825ced, 0xcf1c2b8a, 0x79b492a7, 0x07f2f0f3, 0x69e2a14e, 0xdaf4cd65, 0x05bed506, 0x34621fd1, 0xa6fe8ac4, 0x2e539d34, 0xf355a0a2, 0x8ae13205, 0xf6eb75a4, 0x83ec390b, 0x60efaa40, 0x719f065e, 0x6e1051bd, 0x218af93e, 0xdd063d96, 0x3e05aedd, 0xe6bd464d, 0x548db591, 0xc45d0571, 0x06d46f04, 0x5015ff60, 0x98fb2419, 0xbde997d6, 0x4043cc89, 0xd99e7767, 0xe842bdb0, 0x898b8807, 0x195b38e7, 0xc8eedb79, 0x7c0a47a1, 0x420fe97c, 0x841ec9f8, 0x00000000, 0x80868309, 0x2bed4832, 0x1170ac1e, 0x5a724e6c, 0x0efffbfd, 0x8538560f, 0xaed51e3d, 0x2d392736, 0x0fd9640a, 0x5ca62168, 0x5b54d19b, 0x362e3a24, 0x0a67b10c, 0x57e70f93, 0xee96d2b4, 0x9b919e1b, 0xc0c54f80, 0xdc20a261, 0x774b695a, 0x121a161c, 0x93ba0ae2, 0xa02ae5c0, 0x22e0433c, 0x1b171d12, 0x090d0b0e, 0x8bc7adf2, 0xb6a8b92d, 0x1ea9c814, 0xf1198557, 0x75074caf, 0x99ddbbee, 0x7f60fda3, 0x01269ff7, 0x72f5bc5c, 0x663bc544, 0xfb7e345b, 0x4329768b, 0x23c6dccb, 0xedfc68b6, 0xe4f163b8, 0x31dccad7, 0x63851042, 0x97224013, 0xc6112084, 0x4a247d85, 0xbb3df8d2, 0xf93211ae, 0x29a16dc7, 0x9e2f4b1d, 0xb230f3dc, 0x8652ec0d, 0xc1e3d077, 0xb3166c2b, 0x70b999a9, 0x9448fa11, 0xe9642247, 0xfc8cc4a8, 0xf03f1aa0, 0x7d2cd856, 0x3390ef22, 0x494ec787, 0x38d1c1d9, 0xcaa2fe8c, 0xd40b3698, 0xf581cfa6, 0x7ade28a5, 0xb78e26da, 0xadbfa43f, 0x3a9de42c, 0x78920d50, 0x5fcc9b6a, 0x7e466254, 0x8d13c2f6, 0xd8b8e890, 0x39f75e2e, 0xc3aff582, 0x5d80be9f, 0xd0937c69, 0xd52da96f, 0x2512b3cf, 0xac993bc8, 0x187da710, 0x9c636ee8, 0x3bbb7bdb, 0x267809cd, 0x5918f46e, 0x9ab701ec, 0x4f9aa883, 0x956e65e6, 0xffe67eaa, 0xbccf0821, 0x15e8e6ef, 0xe79bd9ba, 0x6f36ce4a, 0x9f09d4ea, 0xb07cd629, 0xa4b2af31, 0x3f23312a, 0xa59430c6, 0xa266c035, 0x4ebc3774, 0x82caa6fc, 0x90d0b0e0, 0xa7d81533, 0x04984af1, 0xecdaf741, 0xcd500e7f, 0x91f62f17, 0x4dd68d76, 0xefb04d43, 0xaa4d54cc, 0x9604dfe4, 0xd1b5e39e, 0x6a881b4c, 0x2c1fb8c1, 0x65517f46, 0x5eea049d, 0x8c355d01, 0x877473fa, 0x0b412efb, 0x671d5ab3, 0xdbd25292, 0x105633e9, 0xd647136d, 0xd7618c9a, 0xa10c7a37, 0xf8148e59, 0x133c89eb, 0xa927eece, 0x61c935b7, 0x1ce5ede1, 0x47b13c7a, 0xd2df599c, 0xf2733f55, 0x14ce7918, 0xc737bf73, 0xf7cdea53, 0xfdaa5b5f, 0x3d6f14df, 0x44db8678, 0xaff381ca, 0x68c43eb9, 0x24342c38, 0xa3405fc2, 0x1dc37216, 0xe2250cbc, 0x3c498b28, 0x0d9541ff, 0xa8017139, 0x0cb3de08, 0xb4e49cd8, 0x56c19064, 0xcb84617b, 0x32b670d5, 0x6c5c7448, 0xb85742d0 ] + + # Transformations for decryption key expansion + U1 = [ 0x00000000, 0x0e090d0b, 0x1c121a16, 0x121b171d, 0x3824342c, 0x362d3927, 0x24362e3a, 0x2a3f2331, 0x70486858, 0x7e416553, 0x6c5a724e, 0x62537f45, 0x486c5c74, 0x4665517f, 0x547e4662, 0x5a774b69, 0xe090d0b0, 0xee99ddbb, 0xfc82caa6, 0xf28bc7ad, 0xd8b4e49c, 0xd6bde997, 0xc4a6fe8a, 0xcaaff381, 0x90d8b8e8, 0x9ed1b5e3, 0x8ccaa2fe, 0x82c3aff5, 0xa8fc8cc4, 0xa6f581cf, 0xb4ee96d2, 0xbae79bd9, 0xdb3bbb7b, 0xd532b670, 0xc729a16d, 0xc920ac66, 0xe31f8f57, 0xed16825c, 0xff0d9541, 0xf104984a, 0xab73d323, 0xa57ade28, 0xb761c935, 0xb968c43e, 0x9357e70f, 0x9d5eea04, 0x8f45fd19, 0x814cf012, 0x3bab6bcb, 0x35a266c0, 0x27b971dd, 0x29b07cd6, 0x038f5fe7, 0x0d8652ec, 0x1f9d45f1, 0x119448fa, 0x4be30393, 0x45ea0e98, 0x57f11985, 0x59f8148e, 0x73c737bf, 0x7dce3ab4, 0x6fd52da9, 0x61dc20a2, 0xad766df6, 0xa37f60fd, 0xb16477e0, 0xbf6d7aeb, 0x955259da, 0x9b5b54d1, 0x894043cc, 0x87494ec7, 0xdd3e05ae, 0xd33708a5, 0xc12c1fb8, 0xcf2512b3, 0xe51a3182, 0xeb133c89, 0xf9082b94, 0xf701269f, 0x4de6bd46, 0x43efb04d, 0x51f4a750, 0x5ffdaa5b, 0x75c2896a, 0x7bcb8461, 0x69d0937c, 0x67d99e77, 0x3daed51e, 0x33a7d815, 0x21bccf08, 0x2fb5c203, 0x058ae132, 0x0b83ec39, 0x1998fb24, 0x1791f62f, 0x764dd68d, 0x7844db86, 0x6a5fcc9b, 0x6456c190, 0x4e69e2a1, 0x4060efaa, 0x527bf8b7, 0x5c72f5bc, 0x0605bed5, 0x080cb3de, 0x1a17a4c3, 0x141ea9c8, 0x3e218af9, 0x302887f2, 0x223390ef, 0x2c3a9de4, 0x96dd063d, 0x98d40b36, 0x8acf1c2b, 0x84c61120, 0xaef93211, 0xa0f03f1a, 0xb2eb2807, 0xbce2250c, 0xe6956e65, 0xe89c636e, 0xfa877473, 0xf48e7978, 0xdeb15a49, 0xd0b85742, 0xc2a3405f, 0xccaa4d54, 0x41ecdaf7, 0x4fe5d7fc, 0x5dfec0e1, 0x53f7cdea, 0x79c8eedb, 0x77c1e3d0, 0x65daf4cd, 0x6bd3f9c6, 0x31a4b2af, 0x3fadbfa4, 0x2db6a8b9, 0x23bfa5b2, 0x09808683, 0x07898b88, 0x15929c95, 0x1b9b919e, 0xa17c0a47, 0xaf75074c, 0xbd6e1051, 0xb3671d5a, 0x99583e6b, 0x97513360, 0x854a247d, 0x8b432976, 0xd134621f, 0xdf3d6f14, 0xcd267809, 0xc32f7502, 0xe9105633, 0xe7195b38, 0xf5024c25, 0xfb0b412e, 0x9ad7618c, 0x94de6c87, 0x86c57b9a, 0x88cc7691, 0xa2f355a0, 0xacfa58ab, 0xbee14fb6, 0xb0e842bd, 0xea9f09d4, 0xe49604df, 0xf68d13c2, 0xf8841ec9, 0xd2bb3df8, 0xdcb230f3, 0xcea927ee, 0xc0a02ae5, 0x7a47b13c, 0x744ebc37, 0x6655ab2a, 0x685ca621, 0x42638510, 0x4c6a881b, 0x5e719f06, 0x5078920d, 0x0a0fd964, 0x0406d46f, 0x161dc372, 0x1814ce79, 0x322bed48, 0x3c22e043, 0x2e39f75e, 0x2030fa55, 0xec9ab701, 0xe293ba0a, 0xf088ad17, 0xfe81a01c, 0xd4be832d, 0xdab78e26, 0xc8ac993b, 0xc6a59430, 0x9cd2df59, 0x92dbd252, 0x80c0c54f, 0x8ec9c844, 0xa4f6eb75, 0xaaffe67e, 0xb8e4f163, 0xb6edfc68, 0x0c0a67b1, 0x02036aba, 0x10187da7, 0x1e1170ac, 0x342e539d, 0x3a275e96, 0x283c498b, 0x26354480, 0x7c420fe9, 0x724b02e2, 0x605015ff, 0x6e5918f4, 0x44663bc5, 0x4a6f36ce, 0x587421d3, 0x567d2cd8, 0x37a10c7a, 0x39a80171, 0x2bb3166c, 0x25ba1b67, 0x0f853856, 0x018c355d, 0x13972240, 0x1d9e2f4b, 0x47e96422, 0x49e06929, 0x5bfb7e34, 0x55f2733f, 0x7fcd500e, 0x71c45d05, 0x63df4a18, 0x6dd64713, 0xd731dcca, 0xd938d1c1, 0xcb23c6dc, 0xc52acbd7, 0xef15e8e6, 0xe11ce5ed, 0xf307f2f0, 0xfd0efffb, 0xa779b492, 0xa970b999, 0xbb6bae84, 0xb562a38f, 0x9f5d80be, 0x91548db5, 0x834f9aa8, 0x8d4697a3 ] + U2 = [ 0x00000000, 0x0b0e090d, 0x161c121a, 0x1d121b17, 0x2c382434, 0x27362d39, 0x3a24362e, 0x312a3f23, 0x58704868, 0x537e4165, 0x4e6c5a72, 0x4562537f, 0x74486c5c, 0x7f466551, 0x62547e46, 0x695a774b, 0xb0e090d0, 0xbbee99dd, 0xa6fc82ca, 0xadf28bc7, 0x9cd8b4e4, 0x97d6bde9, 0x8ac4a6fe, 0x81caaff3, 0xe890d8b8, 0xe39ed1b5, 0xfe8ccaa2, 0xf582c3af, 0xc4a8fc8c, 0xcfa6f581, 0xd2b4ee96, 0xd9bae79b, 0x7bdb3bbb, 0x70d532b6, 0x6dc729a1, 0x66c920ac, 0x57e31f8f, 0x5ced1682, 0x41ff0d95, 0x4af10498, 0x23ab73d3, 0x28a57ade, 0x35b761c9, 0x3eb968c4, 0x0f9357e7, 0x049d5eea, 0x198f45fd, 0x12814cf0, 0xcb3bab6b, 0xc035a266, 0xdd27b971, 0xd629b07c, 0xe7038f5f, 0xec0d8652, 0xf11f9d45, 0xfa119448, 0x934be303, 0x9845ea0e, 0x8557f119, 0x8e59f814, 0xbf73c737, 0xb47dce3a, 0xa96fd52d, 0xa261dc20, 0xf6ad766d, 0xfda37f60, 0xe0b16477, 0xebbf6d7a, 0xda955259, 0xd19b5b54, 0xcc894043, 0xc787494e, 0xaedd3e05, 0xa5d33708, 0xb8c12c1f, 0xb3cf2512, 0x82e51a31, 0x89eb133c, 0x94f9082b, 0x9ff70126, 0x464de6bd, 0x4d43efb0, 0x5051f4a7, 0x5b5ffdaa, 0x6a75c289, 0x617bcb84, 0x7c69d093, 0x7767d99e, 0x1e3daed5, 0x1533a7d8, 0x0821bccf, 0x032fb5c2, 0x32058ae1, 0x390b83ec, 0x241998fb, 0x2f1791f6, 0x8d764dd6, 0x867844db, 0x9b6a5fcc, 0x906456c1, 0xa14e69e2, 0xaa4060ef, 0xb7527bf8, 0xbc5c72f5, 0xd50605be, 0xde080cb3, 0xc31a17a4, 0xc8141ea9, 0xf93e218a, 0xf2302887, 0xef223390, 0xe42c3a9d, 0x3d96dd06, 0x3698d40b, 0x2b8acf1c, 0x2084c611, 0x11aef932, 0x1aa0f03f, 0x07b2eb28, 0x0cbce225, 0x65e6956e, 0x6ee89c63, 0x73fa8774, 0x78f48e79, 0x49deb15a, 0x42d0b857, 0x5fc2a340, 0x54ccaa4d, 0xf741ecda, 0xfc4fe5d7, 0xe15dfec0, 0xea53f7cd, 0xdb79c8ee, 0xd077c1e3, 0xcd65daf4, 0xc66bd3f9, 0xaf31a4b2, 0xa43fadbf, 0xb92db6a8, 0xb223bfa5, 0x83098086, 0x8807898b, 0x9515929c, 0x9e1b9b91, 0x47a17c0a, 0x4caf7507, 0x51bd6e10, 0x5ab3671d, 0x6b99583e, 0x60975133, 0x7d854a24, 0x768b4329, 0x1fd13462, 0x14df3d6f, 0x09cd2678, 0x02c32f75, 0x33e91056, 0x38e7195b, 0x25f5024c, 0x2efb0b41, 0x8c9ad761, 0x8794de6c, 0x9a86c57b, 0x9188cc76, 0xa0a2f355, 0xabacfa58, 0xb6bee14f, 0xbdb0e842, 0xd4ea9f09, 0xdfe49604, 0xc2f68d13, 0xc9f8841e, 0xf8d2bb3d, 0xf3dcb230, 0xeecea927, 0xe5c0a02a, 0x3c7a47b1, 0x37744ebc, 0x2a6655ab, 0x21685ca6, 0x10426385, 0x1b4c6a88, 0x065e719f, 0x0d507892, 0x640a0fd9, 0x6f0406d4, 0x72161dc3, 0x791814ce, 0x48322bed, 0x433c22e0, 0x5e2e39f7, 0x552030fa, 0x01ec9ab7, 0x0ae293ba, 0x17f088ad, 0x1cfe81a0, 0x2dd4be83, 0x26dab78e, 0x3bc8ac99, 0x30c6a594, 0x599cd2df, 0x5292dbd2, 0x4f80c0c5, 0x448ec9c8, 0x75a4f6eb, 0x7eaaffe6, 0x63b8e4f1, 0x68b6edfc, 0xb10c0a67, 0xba02036a, 0xa710187d, 0xac1e1170, 0x9d342e53, 0x963a275e, 0x8b283c49, 0x80263544, 0xe97c420f, 0xe2724b02, 0xff605015, 0xf46e5918, 0xc544663b, 0xce4a6f36, 0xd3587421, 0xd8567d2c, 0x7a37a10c, 0x7139a801, 0x6c2bb316, 0x6725ba1b, 0x560f8538, 0x5d018c35, 0x40139722, 0x4b1d9e2f, 0x2247e964, 0x2949e069, 0x345bfb7e, 0x3f55f273, 0x0e7fcd50, 0x0571c45d, 0x1863df4a, 0x136dd647, 0xcad731dc, 0xc1d938d1, 0xdccb23c6, 0xd7c52acb, 0xe6ef15e8, 0xede11ce5, 0xf0f307f2, 0xfbfd0eff, 0x92a779b4, 0x99a970b9, 0x84bb6bae, 0x8fb562a3, 0xbe9f5d80, 0xb591548d, 0xa8834f9a, 0xa38d4697 ] + U3 = [ 0x00000000, 0x0d0b0e09, 0x1a161c12, 0x171d121b, 0x342c3824, 0x3927362d, 0x2e3a2436, 0x23312a3f, 0x68587048, 0x65537e41, 0x724e6c5a, 0x7f456253, 0x5c74486c, 0x517f4665, 0x4662547e, 0x4b695a77, 0xd0b0e090, 0xddbbee99, 0xcaa6fc82, 0xc7adf28b, 0xe49cd8b4, 0xe997d6bd, 0xfe8ac4a6, 0xf381caaf, 0xb8e890d8, 0xb5e39ed1, 0xa2fe8cca, 0xaff582c3, 0x8cc4a8fc, 0x81cfa6f5, 0x96d2b4ee, 0x9bd9bae7, 0xbb7bdb3b, 0xb670d532, 0xa16dc729, 0xac66c920, 0x8f57e31f, 0x825ced16, 0x9541ff0d, 0x984af104, 0xd323ab73, 0xde28a57a, 0xc935b761, 0xc43eb968, 0xe70f9357, 0xea049d5e, 0xfd198f45, 0xf012814c, 0x6bcb3bab, 0x66c035a2, 0x71dd27b9, 0x7cd629b0, 0x5fe7038f, 0x52ec0d86, 0x45f11f9d, 0x48fa1194, 0x03934be3, 0x0e9845ea, 0x198557f1, 0x148e59f8, 0x37bf73c7, 0x3ab47dce, 0x2da96fd5, 0x20a261dc, 0x6df6ad76, 0x60fda37f, 0x77e0b164, 0x7aebbf6d, 0x59da9552, 0x54d19b5b, 0x43cc8940, 0x4ec78749, 0x05aedd3e, 0x08a5d337, 0x1fb8c12c, 0x12b3cf25, 0x3182e51a, 0x3c89eb13, 0x2b94f908, 0x269ff701, 0xbd464de6, 0xb04d43ef, 0xa75051f4, 0xaa5b5ffd, 0x896a75c2, 0x84617bcb, 0x937c69d0, 0x9e7767d9, 0xd51e3dae, 0xd81533a7, 0xcf0821bc, 0xc2032fb5, 0xe132058a, 0xec390b83, 0xfb241998, 0xf62f1791, 0xd68d764d, 0xdb867844, 0xcc9b6a5f, 0xc1906456, 0xe2a14e69, 0xefaa4060, 0xf8b7527b, 0xf5bc5c72, 0xbed50605, 0xb3de080c, 0xa4c31a17, 0xa9c8141e, 0x8af93e21, 0x87f23028, 0x90ef2233, 0x9de42c3a, 0x063d96dd, 0x0b3698d4, 0x1c2b8acf, 0x112084c6, 0x3211aef9, 0x3f1aa0f0, 0x2807b2eb, 0x250cbce2, 0x6e65e695, 0x636ee89c, 0x7473fa87, 0x7978f48e, 0x5a49deb1, 0x5742d0b8, 0x405fc2a3, 0x4d54ccaa, 0xdaf741ec, 0xd7fc4fe5, 0xc0e15dfe, 0xcdea53f7, 0xeedb79c8, 0xe3d077c1, 0xf4cd65da, 0xf9c66bd3, 0xb2af31a4, 0xbfa43fad, 0xa8b92db6, 0xa5b223bf, 0x86830980, 0x8b880789, 0x9c951592, 0x919e1b9b, 0x0a47a17c, 0x074caf75, 0x1051bd6e, 0x1d5ab367, 0x3e6b9958, 0x33609751, 0x247d854a, 0x29768b43, 0x621fd134, 0x6f14df3d, 0x7809cd26, 0x7502c32f, 0x5633e910, 0x5b38e719, 0x4c25f502, 0x412efb0b, 0x618c9ad7, 0x6c8794de, 0x7b9a86c5, 0x769188cc, 0x55a0a2f3, 0x58abacfa, 0x4fb6bee1, 0x42bdb0e8, 0x09d4ea9f, 0x04dfe496, 0x13c2f68d, 0x1ec9f884, 0x3df8d2bb, 0x30f3dcb2, 0x27eecea9, 0x2ae5c0a0, 0xb13c7a47, 0xbc37744e, 0xab2a6655, 0xa621685c, 0x85104263, 0x881b4c6a, 0x9f065e71, 0x920d5078, 0xd9640a0f, 0xd46f0406, 0xc372161d, 0xce791814, 0xed48322b, 0xe0433c22, 0xf75e2e39, 0xfa552030, 0xb701ec9a, 0xba0ae293, 0xad17f088, 0xa01cfe81, 0x832dd4be, 0x8e26dab7, 0x993bc8ac, 0x9430c6a5, 0xdf599cd2, 0xd25292db, 0xc54f80c0, 0xc8448ec9, 0xeb75a4f6, 0xe67eaaff, 0xf163b8e4, 0xfc68b6ed, 0x67b10c0a, 0x6aba0203, 0x7da71018, 0x70ac1e11, 0x539d342e, 0x5e963a27, 0x498b283c, 0x44802635, 0x0fe97c42, 0x02e2724b, 0x15ff6050, 0x18f46e59, 0x3bc54466, 0x36ce4a6f, 0x21d35874, 0x2cd8567d, 0x0c7a37a1, 0x017139a8, 0x166c2bb3, 0x1b6725ba, 0x38560f85, 0x355d018c, 0x22401397, 0x2f4b1d9e, 0x642247e9, 0x692949e0, 0x7e345bfb, 0x733f55f2, 0x500e7fcd, 0x5d0571c4, 0x4a1863df, 0x47136dd6, 0xdccad731, 0xd1c1d938, 0xc6dccb23, 0xcbd7c52a, 0xe8e6ef15, 0xe5ede11c, 0xf2f0f307, 0xfffbfd0e, 0xb492a779, 0xb999a970, 0xae84bb6b, 0xa38fb562, 0x80be9f5d, 0x8db59154, 0x9aa8834f, 0x97a38d46 ] + U4 = [ 0x00000000, 0x090d0b0e, 0x121a161c, 0x1b171d12, 0x24342c38, 0x2d392736, 0x362e3a24, 0x3f23312a, 0x48685870, 0x4165537e, 0x5a724e6c, 0x537f4562, 0x6c5c7448, 0x65517f46, 0x7e466254, 0x774b695a, 0x90d0b0e0, 0x99ddbbee, 0x82caa6fc, 0x8bc7adf2, 0xb4e49cd8, 0xbde997d6, 0xa6fe8ac4, 0xaff381ca, 0xd8b8e890, 0xd1b5e39e, 0xcaa2fe8c, 0xc3aff582, 0xfc8cc4a8, 0xf581cfa6, 0xee96d2b4, 0xe79bd9ba, 0x3bbb7bdb, 0x32b670d5, 0x29a16dc7, 0x20ac66c9, 0x1f8f57e3, 0x16825ced, 0x0d9541ff, 0x04984af1, 0x73d323ab, 0x7ade28a5, 0x61c935b7, 0x68c43eb9, 0x57e70f93, 0x5eea049d, 0x45fd198f, 0x4cf01281, 0xab6bcb3b, 0xa266c035, 0xb971dd27, 0xb07cd629, 0x8f5fe703, 0x8652ec0d, 0x9d45f11f, 0x9448fa11, 0xe303934b, 0xea0e9845, 0xf1198557, 0xf8148e59, 0xc737bf73, 0xce3ab47d, 0xd52da96f, 0xdc20a261, 0x766df6ad, 0x7f60fda3, 0x6477e0b1, 0x6d7aebbf, 0x5259da95, 0x5b54d19b, 0x4043cc89, 0x494ec787, 0x3e05aedd, 0x3708a5d3, 0x2c1fb8c1, 0x2512b3cf, 0x1a3182e5, 0x133c89eb, 0x082b94f9, 0x01269ff7, 0xe6bd464d, 0xefb04d43, 0xf4a75051, 0xfdaa5b5f, 0xc2896a75, 0xcb84617b, 0xd0937c69, 0xd99e7767, 0xaed51e3d, 0xa7d81533, 0xbccf0821, 0xb5c2032f, 0x8ae13205, 0x83ec390b, 0x98fb2419, 0x91f62f17, 0x4dd68d76, 0x44db8678, 0x5fcc9b6a, 0x56c19064, 0x69e2a14e, 0x60efaa40, 0x7bf8b752, 0x72f5bc5c, 0x05bed506, 0x0cb3de08, 0x17a4c31a, 0x1ea9c814, 0x218af93e, 0x2887f230, 0x3390ef22, 0x3a9de42c, 0xdd063d96, 0xd40b3698, 0xcf1c2b8a, 0xc6112084, 0xf93211ae, 0xf03f1aa0, 0xeb2807b2, 0xe2250cbc, 0x956e65e6, 0x9c636ee8, 0x877473fa, 0x8e7978f4, 0xb15a49de, 0xb85742d0, 0xa3405fc2, 0xaa4d54cc, 0xecdaf741, 0xe5d7fc4f, 0xfec0e15d, 0xf7cdea53, 0xc8eedb79, 0xc1e3d077, 0xdaf4cd65, 0xd3f9c66b, 0xa4b2af31, 0xadbfa43f, 0xb6a8b92d, 0xbfa5b223, 0x80868309, 0x898b8807, 0x929c9515, 0x9b919e1b, 0x7c0a47a1, 0x75074caf, 0x6e1051bd, 0x671d5ab3, 0x583e6b99, 0x51336097, 0x4a247d85, 0x4329768b, 0x34621fd1, 0x3d6f14df, 0x267809cd, 0x2f7502c3, 0x105633e9, 0x195b38e7, 0x024c25f5, 0x0b412efb, 0xd7618c9a, 0xde6c8794, 0xc57b9a86, 0xcc769188, 0xf355a0a2, 0xfa58abac, 0xe14fb6be, 0xe842bdb0, 0x9f09d4ea, 0x9604dfe4, 0x8d13c2f6, 0x841ec9f8, 0xbb3df8d2, 0xb230f3dc, 0xa927eece, 0xa02ae5c0, 0x47b13c7a, 0x4ebc3774, 0x55ab2a66, 0x5ca62168, 0x63851042, 0x6a881b4c, 0x719f065e, 0x78920d50, 0x0fd9640a, 0x06d46f04, 0x1dc37216, 0x14ce7918, 0x2bed4832, 0x22e0433c, 0x39f75e2e, 0x30fa5520, 0x9ab701ec, 0x93ba0ae2, 0x88ad17f0, 0x81a01cfe, 0xbe832dd4, 0xb78e26da, 0xac993bc8, 0xa59430c6, 0xd2df599c, 0xdbd25292, 0xc0c54f80, 0xc9c8448e, 0xf6eb75a4, 0xffe67eaa, 0xe4f163b8, 0xedfc68b6, 0x0a67b10c, 0x036aba02, 0x187da710, 0x1170ac1e, 0x2e539d34, 0x275e963a, 0x3c498b28, 0x35448026, 0x420fe97c, 0x4b02e272, 0x5015ff60, 0x5918f46e, 0x663bc544, 0x6f36ce4a, 0x7421d358, 0x7d2cd856, 0xa10c7a37, 0xa8017139, 0xb3166c2b, 0xba1b6725, 0x8538560f, 0x8c355d01, 0x97224013, 0x9e2f4b1d, 0xe9642247, 0xe0692949, 0xfb7e345b, 0xf2733f55, 0xcd500e7f, 0xc45d0571, 0xdf4a1863, 0xd647136d, 0x31dccad7, 0x38d1c1d9, 0x23c6dccb, 0x2acbd7c5, 0x15e8e6ef, 0x1ce5ede1, 0x07f2f0f3, 0x0efffbfd, 0x79b492a7, 0x70b999a9, 0x6bae84bb, 0x62a38fb5, 0x5d80be9f, 0x548db591, 0x4f9aa883, 0x4697a38d ] + + def __init__(self, key): + + if len(key) not in (16, 24, 32): + raise_exception( ValueError('Invalid key size') ) + + rounds = self.number_of_rounds[len(key)] + + # Encryption round keys + self._Ke = [[0] * 4 for i in range(rounds + 1)] + + # Decryption round keys + self._Kd = [[0] * 4 for i in range(rounds + 1)] + + round_key_count = (rounds + 1) * 4 + KC = len(key) // 4 + + # Convert the key into ints + tk = [ struct.unpack('>i', key[i:i + 4])[0] for i in range(0, len(key), 4) ] + + # Copy values into round key arrays + for i in range(0, KC): + self._Ke[i // 4][i % 4] = tk[i] + self._Kd[rounds - (i // 4)][i % 4] = tk[i] + + # Key expansion (fips-197 section 5.2) + rconpointer = 0 + t = KC + while t < round_key_count: + + tt = tk[KC - 1] + tk[0] ^= ((self.S[(tt >> 16) & 0xFF] << 24) ^ + (self.S[(tt >> 8) & 0xFF] << 16) ^ + (self.S[ tt & 0xFF] << 8) ^ + self.S[(tt >> 24) & 0xFF] ^ + (self.rcon[rconpointer] << 24)) + rconpointer += 1 + + if KC != 8: + for i in range(1, KC): + tk[i] ^= tk[i - 1] + + # Key expansion for 256-bit keys is "slightly different" (fips-197) + else: + for i in range(1, KC // 2): + tk[i] ^= tk[i - 1] + tt = tk[KC // 2 - 1] + + tk[KC // 2] ^= (self.S[ tt & 0xFF] ^ + (self.S[(tt >> 8) & 0xFF] << 8) ^ + (self.S[(tt >> 16) & 0xFF] << 16) ^ + (self.S[(tt >> 24) & 0xFF] << 24)) + + for i in range(KC // 2 + 1, KC): + tk[i] ^= tk[i - 1] + + # Copy values into round key arrays + j = 0 + while j < KC and t < round_key_count: + self._Ke[t // 4][t % 4] = tk[j] + self._Kd[rounds - (t // 4)][t % 4] = tk[j] + j += 1 + t += 1 + + # Inverse-Cipher-ify the decryption round key (fips-197 section 5.3) + for r in range(1, rounds): + for j in range(0, 4): + tt = self._Kd[r][j] + self._Kd[r][j] = (self.U1[(tt >> 24) & 0xFF] ^ + self.U2[(tt >> 16) & 0xFF] ^ + self.U3[(tt >> 8) & 0xFF] ^ + self.U4[ tt & 0xFF]) + + def encrypt(self, plaintext): + 'Encrypt a block of plain text using the AES block cipher.' + + if len(plaintext) != 16: + raise_exception( ValueError('wrong block length') ) + + rounds = len(self._Ke) - 1 + (s1, s2, s3) = [1, 2, 3] + a = [0, 0, 0, 0] + + # Convert plaintext to (ints ^ key) + t = [(AES._compact_word(plaintext[4 * i:4 * i + 4]) ^ self._Ke[0][i]) for i in range(0, 4)] + + # Apply round transforms + for r in range(1, rounds): + for i in range(0, 4): + a[i] = (self.T1[(t[ i ] >> 24) & 0xFF] ^ + self.T2[(t[(i + s1) % 4] >> 16) & 0xFF] ^ + self.T3[(t[(i + s2) % 4] >> 8) & 0xFF] ^ + self.T4[ t[(i + s3) % 4] & 0xFF] ^ + self._Ke[r][i]) + t = copy.copy(a) + + # The last round is special + result = [ ] + for i in range(0, 4): + tt = self._Ke[rounds][i] + result.append((self.S[(t[ i ] >> 24) & 0xFF] ^ (tt >> 24)) & 0xFF) + result.append((self.S[(t[(i + s1) % 4] >> 16) & 0xFF] ^ (tt >> 16)) & 0xFF) + result.append((self.S[(t[(i + s2) % 4] >> 8) & 0xFF] ^ (tt >> 8)) & 0xFF) + result.append((self.S[ t[(i + s3) % 4] & 0xFF] ^ tt ) & 0xFF) + + return result + + def decrypt(self, ciphertext): + 'Decrypt a block of cipher text using the AES block cipher.' + + if len(ciphertext) != 16: + raise_exception( ValueError('wrong block length') ) + + rounds = len(self._Kd) - 1 + (s1, s2, s3) = [3, 2, 1] + a = [0, 0, 0, 0] + + # Convert ciphertext to (ints ^ key) + t = [(AES._compact_word(ciphertext[4 * i:4 * i + 4]) ^ self._Kd[0][i]) for i in range(0, 4)] + + # Apply round transforms + for r in range(1, rounds): + for i in range(0, 4): + a[i] = (self.T5[(t[ i ] >> 24) & 0xFF] ^ + self.T6[(t[(i + s1) % 4] >> 16) & 0xFF] ^ + self.T7[(t[(i + s2) % 4] >> 8) & 0xFF] ^ + self.T8[ t[(i + s3) % 4] & 0xFF] ^ + self._Kd[r][i]) + t = copy.copy(a) + + # The last round is special + result = [ ] + for i in range(0, 4): + tt = self._Kd[rounds][i] + result.append((self.Si[(t[ i ] >> 24) & 0xFF] ^ (tt >> 24)) & 0xFF) + result.append((self.Si[(t[(i + s1) % 4] >> 16) & 0xFF] ^ (tt >> 16)) & 0xFF) + result.append((self.Si[(t[(i + s2) % 4] >> 8) & 0xFF] ^ (tt >> 8)) & 0xFF) + result.append((self.Si[ t[(i + s3) % 4] & 0xFF] ^ tt ) & 0xFF) + + return result + + class AES_128_CBC: + + def __init__(self, key, iv = None): + self._aes = AES(key) + if iv is None: + self._last_cipherblock = [ 0 ] * 16 + elif len(iv) != 16: + raise_exception( ValueError('initialization vector must be 16 bytes') ) + else: + self._last_cipherblock = iv + + + def encrypt(self, plaintext): + if len(plaintext) != 16: + raise_exception( ValueError('plaintext block must be 16 bytes') ) + + precipherblock = [ (p ^ l) for (p, l) in zip(plaintext, self._last_cipherblock) ] + self._last_cipherblock = self._aes.encrypt(precipherblock) + + return b''.join(map(lambda x: x.to_bytes(1, 'little'), self._last_cipherblock)) + + def decrypt(self, ciphertext): + if len(ciphertext) != 16: + raise_exception( ValueError('ciphertext block must be 16 bytes') ) + + cipherblock = ciphertext + plaintext = [ (p ^ l) for (p, l) in zip(self._aes.decrypt(cipherblock), self._last_cipherblock) ] + self._last_cipherblock = cipherblock + + return b''.join(map(lambda x: x.to_bytes(1, 'little'), plaintext)) + + ISP_PROG = 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+ ISP_PROG = binascii.unhexlify(ISP_PROG) + ISP_PROG = zlib.decompress(ISP_PROG) + + def printProgressBar (iteration, total, prefix = '', suffix = '', filename = '', decimals = 1, length = 100, fill = '='): + """ + Call in a loop to create terminal progress bar + @params: + iteration - Required : current iteration (Int) + total - Required : total iterations (Int) + prefix - Optional : prefix string (Str) + suffix - Optional : suffix string (Str) + decimals - Optional : positive number of decimals in percent complete (Int) + length - Optional : character length of bar (Int) + fill - Optional : bar fill character (Str) + """ + percent = ("{0:." + str(decimals) + "f}").format(100 * (iteration / float(total))) + filledLength = int(length * iteration // total) + bar = fill * filledLength + '-' * (length - filledLength) + KFlash.log('\r%s |%s| %s%% %s' % (prefix, bar, percent, suffix), end = '\r') + # Print New Line on Complete + if iteration == total: + KFlash.log() + if callback: + fileTypeStr = filename + if prefix == "Downloading ISP:": + fileTypeStr = "ISP" + elif prefix == "Programming BIN:" and fileTypeStr == "": + fileTypeStr = "BIN" + callback(fileTypeStr, iteration, total, suffix) + + def slip_reader(port): + partial_packet = None + in_escape = False + + while True: + waiting = port.inWaiting() + read_bytes = port.read(1 if waiting == 0 else waiting) + if read_bytes == b'': + raise_exception( Exception("Timed out waiting for packet %s" % ("header" if partial_packet is None else "content")) ) + for b in read_bytes: + + if type(b) is int: + b = bytes([b]) # python 2/3 compat + + if partial_packet is None: # waiting for packet header + if b == b'\xc0': + partial_packet = b"" + else: + raise_exception( Exception('Invalid head of packet (%r)' % b) ) + elif in_escape: # part-way through escape sequence + in_escape = False + if b == b'\xdc': + partial_packet += b'\xc0' + elif b == b'\xdd': + partial_packet += b'\xdb' + else: + raise_exception( Exception('Invalid SLIP escape (%r%r)' % (b'\xdb', b)) ) + elif b == b'\xdb': # start of escape sequence + in_escape = True + elif b == b'\xc0': # end of packet + yield partial_packet + partial_packet = None + else: # normal byte in packet + partial_packet += b + + + class ISPResponse: + class ISPOperation(Enum): + ISP_ECHO = 0xC1 + ISP_NOP = 0xC2 + ISP_MEMORY_WRITE = 0xC3 + ISP_MEMORY_READ = 0xC4 + ISP_MEMORY_BOOT = 0xC5 + ISP_DEBUG_INFO = 0xD1 + ISP_CHANGE_BAUDRATE = 0xc6 + + class ErrorCode(Enum): + ISP_RET_DEFAULT = 0 + ISP_RET_OK = 0xE0 + ISP_RET_BAD_DATA_LEN = 0xE1 + ISP_RET_BAD_DATA_CHECKSUM = 0xE2 + ISP_RET_INVALID_COMMAND = 0xE3 + + @staticmethod + def parse(data): + # type: (bytes) -> (int, int, str) + op = 0 + reason = 0 + text = '' + + if (sys.version_info > (3, 0)): + op = int(data[0]) + reason = int(data[1]) + else: + op = ord(data[0]) + reason = ord(data[1]) + + try: + if ISPResponse.ISPOperation(op) == ISPResponse.ISPOperation.ISP_DEBUG_INFO: + text = data[2:].decode() + except ValueError: + KFlash.log('Warning: recv unknown op', op) + + return (op, reason, text) + + + class FlashModeResponse: + class Operation(Enum): + ISP_DEBUG_INFO = 0xD1 + ISP_NOP = 0xD2 + ISP_FLASH_ERASE = 0xD3 + ISP_FLASH_WRITE = 0xD4 + ISP_REBOOT = 0xD5 + ISP_UARTHS_BAUDRATE_SET = 0xD6 + FLASHMODE_FLASH_INIT = 0xD7 + + class ErrorCode(Enum): + ISP_RET_DEFAULT = 0 + ISP_RET_OK = 0xE0 + ISP_RET_BAD_DATA_LEN = 0xE1 + ISP_RET_BAD_DATA_CHECKSUM = 0xE2 + ISP_RET_INVALID_COMMAND = 0xE3 + ISP_RET_BAD_INITIALIZATION = 0xE4 + + @staticmethod + def parse(data): + # type: (bytes) -> (int, int, str) + op = 0 + reason = 0 + text = '' + + if (sys.version_info > (3, 0)): + op = int(data[0]) + reason = int(data[1]) + else: + op = ord(data[0]) + reason = ord(data[1]) + + if FlashModeResponse.Operation(op) == FlashModeResponse.Operation.ISP_DEBUG_INFO: + text = data[2:].decode() + + return (op, reason, text) + + + def chunks(l, n): + """Yield successive n-sized chunks from l.""" + for i in range(0, len(l), n): + yield l[i:i + n] + + class TerminalSize: + @staticmethod + def getTerminalSize(): + import platform + current_os = platform.system() + tuple_xy=None + if current_os == 'Windows': + tuple_xy = TerminalSize._getTerminalSize_windows() + if tuple_xy is None: + tuple_xy = TerminalSize._getTerminalSize_tput() + # needed for window's python in cygwin's xterm! + if current_os == 'Linux' or current_os == 'Darwin' or current_os.startswith('CYGWIN'): + tuple_xy = TerminalSize._getTerminalSize_linux() + if tuple_xy is None: + # Use default value + tuple_xy = (80, 25) # default value + return tuple_xy + + @staticmethod + def _getTerminalSize_windows(): + res=None + try: + from ctypes import windll, create_string_buffer + + # stdin handle is -10 + # stdout handle is -11 + # stderr handle is -12 + + h = windll.kernel32.GetStdHandle(-12) + csbi = create_string_buffer(22) + res = windll.kernel32.GetConsoleScreenBufferInfo(h, csbi) + except: + return None + if res: + import struct + (bufx, bufy, curx, cury, wattr, + left, top, right, bottom, maxx, maxy) = struct.unpack("hhhhHhhhhhh", csbi.raw) + sizex = right - left + 1 + sizey = bottom - top + 1 + return sizex, sizey + else: + return None + + @staticmethod + def _getTerminalSize_tput(): + # get terminal width + # src: http://stackoverflow.com/questions/263890/how-do-i-find-the-width-height-of-a-terminal-window + try: + import subprocess + proc=subprocess.Popen(["tput", "cols"],stdin=subprocess.PIPE,stdout=subprocess.PIPE) + output=proc.communicate(input=None) + cols=int(output[0]) + proc=subprocess.Popen(["tput", "lines"],stdin=subprocess.PIPE,stdout=subprocess.PIPE) + output=proc.communicate(input=None) + rows=int(output[0]) + return (cols,rows) + except: + return None + + @staticmethod + def _getTerminalSize_linux(): + def ioctl_GWINSZ(fd): + try: + import fcntl, termios, struct, os + cr = struct.unpack('hh', fcntl.ioctl(fd, termios.TIOCGWINSZ,'1234')) + except: + return None + return cr + cr = ioctl_GWINSZ(0) or ioctl_GWINSZ(1) or ioctl_GWINSZ(2) + if not cr: + try: + fd = os.open(os.ctermid(), os.O_RDONLY) + cr = ioctl_GWINSZ(fd) + os.close(fd) + except: + pass + if not cr: + try: + cr = (os.env['LINES'], os.env['COLUMNS']) + except: + return None + return int(cr[1]), int(cr[0]) + + @staticmethod + def get_terminal_size(fallback=(100, 24), terminal = False): + try: + columns, rows = TerminalSize.getTerminalSize() + if not terminal: + if not terminal_auto_size: + columns, rows = terminal_size + except: + columns, rows = fallback + + return columns, rows + + class MAIXLoader: + def change_baudrate(self, baudrate): + KFlash.log(INFO_MSG,"Selected Baudrate: ", baudrate, BASH_TIPS['DEFAULT']) + out = struct.pack('III', 0, 4, baudrate) + crc32_checksum = struct.pack('I', binascii.crc32(out) & 0xFFFFFFFF) + out = struct.pack('HH', 0xd6, 0x00) + crc32_checksum + out + self.write(out) + time.sleep(0.05) + self._port.baudrate = baudrate + if args.Board == "goE": + if baudrate >= 4500000: + # OPENEC super baudrate + KFlash.log(INFO_MSG, "Enable OPENEC super baudrate!!!", BASH_TIPS['DEFAULT']) + if baudrate == 4500000: + self._port.baudrate = 300 + if baudrate == 6000000: + self._port.baudrate = 250 + if baudrate == 7500000: + self._port.baudrate = 350 + + def change_baudrate_stage0(self, baudrate): + # Dangerous, here are dinosaur infested!!!!! + # Don't touch this code unless you know what you are doing + # Stage0 baudrate is fixed + # Contributor: [@rgwan](https://github.com/rgwan) + # rgwan + baudrate = 1500000 + if args.Board == "goE" or args.Board == "trainer": + KFlash.log(INFO_MSG,"Selected Stage0 Baudrate: ", baudrate, BASH_TIPS['DEFAULT']) + # This is for openec, contained ft2232, goE and trainer + KFlash.log(INFO_MSG,"FT2232 mode", BASH_TIPS['DEFAULT']) + baudrate_stage0 = int(baudrate * 38.6 / 38) + out = struct.pack('III', 0, 4, baudrate_stage0) + crc32_checksum = struct.pack('I', binascii.crc32(out) & 0xFFFFFFFF) + out = struct.pack('HH', 0xc6, 0x00) + crc32_checksum + out + self.write(out) + time.sleep(0.05) + self._port.baudrate = baudrate + + retry_count = 0 + while 1: + self.checkKillExit() + retry_count = retry_count + 1 + if retry_count > 3: + err = (ERROR_MSG,'Fast mode failed, please use slow mode by add parameter ' + BASH_TIPS['GREEN'] + '--Slow', BASH_TIPS['DEFAULT']) + err = tuple2str(err) + self.raise_exception( Exception(err) ) + try: + self.greeting() + break + except TimeoutError: + pass + elif args.Board == "dan" or args.Board == "bit" or args.Board == "kd233": + KFlash.log(INFO_MSG,"CH340 mode", BASH_TIPS['DEFAULT']) + # This is for CH340, contained dan, bit and kd233 + baudrate_stage0 = int(baudrate * 38.4 / 38) + # CH340 can not use this method, test failed, take risks at your own risk + else: + # This is for unknown board + KFlash.log(WARN_MSG,"Unknown mode", BASH_TIPS['DEFAULT']) + + def __init__(self, port='/dev/ttyUSB1', baudrate=115200): + # configure the serial connections (the parameters differs on the device you are connecting to) + self._port = serial.Serial( + port=port, + baudrate=baudrate, + parity=serial.PARITY_NONE, + stopbits=serial.STOPBITS_ONE, + bytesize=serial.EIGHTBITS, + timeout=0.1 + ) + KFlash.log(INFO_MSG, "Default baudrate is", baudrate, ", later it may be changed to the value you set.", BASH_TIPS['DEFAULT']) + + self._port.isOpen() + self._slip_reader = slip_reader(self._port) + self._kill_process = False + + """ Read a SLIP packet from the serial port """ + + def read(self): + return next(self._slip_reader) + + """ Write bytes to the serial port while performing SLIP escaping """ + + def write(self, packet): + buf = b'\xc0' \ + + (packet.replace(b'\xdb', b'\xdb\xdd').replace(b'\xc0', b'\xdb\xdc')) \ + + b'\xc0' + #KFlash.log('[WRITE]', binascii.hexlify(buf)) + return self._port.write(buf) + + def read_loop(self): + #out = b'' + # while self._port.inWaiting() > 0: + # out += self._port.read(1) + + # KFlash.log(out) + while 1: + sys.stdout.write('[RECV] raw data: ') + sys.stdout.write(binascii.hexlify(self._port.read(1)).decode()) + sys.stdout.flush() + + def recv_one_return(self): + timeout_init = time.time() + data = b'' + # find start boarder + #sys.stdout.write('[RECV one return] raw data: ') + while 1: + if time.time() - timeout_init > ISP_RECEIVE_TIMEOUT: + raise TimeoutError + c = self._port.read(1) + #sys.stdout.write(binascii.hexlify(c).decode()) + sys.stdout.flush() + if c == b'\xc0': + break + + in_escape = False + while 1: + if time.time() - timeout_init > ISP_RECEIVE_TIMEOUT: + self.raise_exception( TimeoutError ) + c = self._port.read(1) + #sys.stdout.write(binascii.hexlify(c).decode()) + sys.stdout.flush() + if c == b'\xc0': + break + + elif in_escape: # part-way through escape sequence + in_escape = False + if c == b'\xdc': + data += b'\xc0' + elif c == b'\xdd': + data += b'\xdb' + else: + self.raise_exception( Exception('Invalid SLIP escape (%r%r)' % (b'\xdb', c)) ) + elif c == b'\xdb': # start of escape sequence + in_escape = True + + data += c + + #sys.stdout.write('\n') + return data + + # kd233 or open-ec or new cmsis-dap + def reset_to_isp_kd233(self): + self._port.setDTR (False) + self._port.setRTS (False) + time.sleep(0.1) + #KFlash.log('-- RESET to LOW, IO16 to HIGH --') + # Pull reset down and keep 10ms + self._port.setDTR (True) + self._port.setRTS (False) + time.sleep(0.1) + #KFlash.log('-- IO16 to LOW, RESET to HIGH --') + # Pull IO16 to low and release reset + self._port.setRTS (True) + self._port.setDTR (False) + time.sleep(0.1) + def reset_to_boot_kd233(self): + self._port.setDTR (False) + self._port.setRTS (False) + time.sleep(0.1) + #KFlash.log('-- RESET to LOW --') + # Pull reset down and keep 10ms + self._port.setDTR (True) + self._port.setRTS (False) + time.sleep(0.1) + #KFlash.log('-- RESET to HIGH, BOOT --') + # Pull IO16 to low and release reset + self._port.setRTS (False) + self._port.setDTR (False) + time.sleep(0.1) + + #dan dock + def reset_to_isp_dan(self): + self._port.setDTR (False) + self._port.setRTS (False) + time.sleep(0.1) + #KFlash.log('-- RESET to LOW, IO16 to HIGH --') + # Pull reset down and keep 10ms + self._port.setDTR (False) + self._port.setRTS (True) + time.sleep(0.1) + #KFlash.log('-- IO16 to LOW, RESET to HIGH --') + # Pull IO16 to low and release reset + self._port.setRTS (False) + self._port.setDTR (True) + time.sleep(0.1) + def reset_to_boot_dan(self): + self._port.setDTR (False) + self._port.setRTS (False) + time.sleep(0.1) + #KFlash.log('-- RESET to LOW --') + # Pull reset down and keep 10ms + self._port.setDTR (False) + self._port.setRTS (True) + time.sleep(0.1) + #KFlash.log('-- RESET to HIGH, BOOT --') + # Pull IO16 to low and release reset + self._port.setRTS (False) + self._port.setDTR (False) + time.sleep(0.1) + + # maix goD for old cmsis-dap firmware + def reset_to_isp_goD(self): + self._port.setDTR (True) ## output 0 + self._port.setRTS (True) + time.sleep(0.1) + #KFlash.log('-- RESET to LOW --') + # Pull reset down and keep 10ms + self._port.setRTS (False) + self._port.setDTR (True) + time.sleep(0.1) + #KFlash.log('-- RESET to HIGH, BOOT --') + # Pull IO16 to low and release reset + self._port.setRTS (False) + self._port.setDTR (True) + time.sleep(0.1) + def reset_to_boot_goD(self): + self._port.setDTR (False) + self._port.setRTS (False) + time.sleep(0.1) + #KFlash.log('-- RESET to LOW --') + # Pull reset down and keep 10ms + self._port.setRTS (False) + self._port.setDTR (True) + time.sleep(0.1) + #KFlash.log('-- RESET to HIGH, BOOT --') + # Pull IO16 to low and release reset + self._port.setRTS (True) + self._port.setDTR (True) + time.sleep(0.1) + + # maix goE for openec or new cmsis-dap firmware + def reset_to_boot_maixgo(self): + self._port.setDTR (False) + self._port.setRTS (False) + time.sleep(0.1) + #KFlash.log('-- RESET to LOW --') + # Pull reset down and keep 10ms + self._port.setRTS (False) + self._port.setDTR (True) + time.sleep(0.1) + #KFlash.log('-- RESET to HIGH, BOOT --') + # Pull IO16 to low and release reset + self._port.setRTS (False) + self._port.setDTR (False) + time.sleep(0.1) + + def greeting(self): + self._port.write(b'\xc0\xc2\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc0') + op, reason, text = ISPResponse.parse(self.recv_one_return()) + + #KFlash.log('MAIX return op:', ISPResponse.ISPOperation(op).name, 'reason:', ISPResponse.ErrorCode(reason).name) + + + def flash_greeting(self): + retry_count = 0 + while 1: + self.checkKillExit() + self._port.write(b'\xc0\xd2\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc0') + retry_count = retry_count + 1 + try: + op, reason, text = FlashModeResponse.parse(self.recv_one_return()) + except IndexError: + if retry_count > MAX_RETRY_TIMES: + err = (ERROR_MSG,"Failed to Connect to K210's Stub",BASH_TIPS['DEFAULT']) + err = tuple2str(err) + self.raise_exception( Exception(err) ) + KFlash.log(WARN_MSG,"Index Error, retrying...",BASH_TIPS['DEFAULT']) + time.sleep(0.1) + continue + except TimeoutError: + if retry_count > MAX_RETRY_TIMES: + err = (ERROR_MSG,"Failed to Connect to K210's Stub",BASH_TIPS['DEFAULT']) + err = tuple2str(err) + self.raise_exception( Exception(err) ) + KFlash.log(WARN_MSG,"Timeout Error, retrying...",BASH_TIPS['DEFAULT']) + time.sleep(0.1) + continue + except: + if retry_count > MAX_RETRY_TIMES: + err = (ERROR_MSG,"Failed to Connect to K210's Stub",BASH_TIPS['DEFAULT']) + err = tuple2str(err) + self.raise_exception( Exception(err) ) + KFlash.log(WARN_MSG,"Unexcepted Error, retrying...",BASH_TIPS['DEFAULT']) + time.sleep(0.1) + continue + # KFlash.log('MAIX return op:', FlashModeResponse.Operation(op).name, 'reason:', + # FlashModeResponse.ErrorCode(reason).name) + if FlashModeResponse.Operation(op) == FlashModeResponse.Operation.ISP_NOP and FlashModeResponse.ErrorCode(reason) == FlashModeResponse.ErrorCode.ISP_RET_OK: + KFlash.log(INFO_MSG,"Boot to Flashmode Successfully",BASH_TIPS['DEFAULT']) + self._port.flushInput() + self._port.flushOutput() + break + else: + if retry_count > MAX_RETRY_TIMES: + err = (ERROR_MSG,"Failed to Connect to K210's Stub",BASH_TIPS['DEFAULT']) + err = tuple2str(err) + self.raise_exception( Exception(err) ) + KFlash.log(WARN_MSG,"Unexcepted Return recevied, retrying...",BASH_TIPS['DEFAULT']) + time.sleep(0.1) + continue + + def boot(self, address=0x80000000): + KFlash.log(INFO_MSG,"Booting From " + hex(address),BASH_TIPS['DEFAULT']) + + out = struct.pack('II', address, 0) + + crc32_checksum = struct.pack('I', binascii.crc32(out) & 0xFFFFFFFF) + + out = struct.pack('HH', 0xc5, 0x00) + crc32_checksum + out # op: ISP_MEMORY_WRITE: 0xc3 + self.write(out) + + def recv_debug(self): + op, reason, text = ISPResponse.parse(self.recv_one_return()) + #KFlash.log('[RECV] op:', ISPResponse.ISPOperation(op).name, 'reason:', ISPResponse.ErrorCode(reason).name) + if text: + KFlash.log('-' * 30) + KFlash.log(text) + KFlash.log('-' * 30) + if ISPResponse.ErrorCode(reason) not in (ISPResponse.ErrorCode.ISP_RET_DEFAULT, ISPResponse.ErrorCode.ISP_RET_OK): + KFlash.log('Failed, retry, errcode=', hex(reason)) + return False + return True + + def flash_recv_debug(self): + op, reason, text = FlashModeResponse.parse(self.recv_one_return()) + #KFlash.log('[Flash-RECV] op:', FlashModeResponse.Operation(op).name, 'reason:', + # FlashModeResponse.ErrorCode(reason).name) + if text: + KFlash.log('-' * 30) + KFlash.log(text) + KFlash.log('-' * 30) + + if FlashModeResponse.ErrorCode(reason) not in (FlashModeResponse.ErrorCode.ISP_RET_OK, FlashModeResponse.ErrorCode.ISP_RET_OK): + KFlash.log('Failed, retry') + return False + return True + + def init_flash(self, chip_type): + chip_type = int(chip_type) + KFlash.log(INFO_MSG,"Selected Flash: ",("In-Chip", "On-Board")[chip_type],BASH_TIPS['DEFAULT']) + out = struct.pack('II', chip_type, 0) + crc32_checksum = struct.pack('I', binascii.crc32(out) & 0xFFFFFFFF) + out = struct.pack('HH', 0xd7, 0x00) + crc32_checksum + out + '''Retry when it have error''' + retry_count = 0 + while 1: + self.checkKillExit() + sent = self.write(out) + retry_count = retry_count + 1 + try: + op, reason, text = FlashModeResponse.parse(self.recv_one_return()) + except IndexError: + if retry_count > MAX_RETRY_TIMES: + err = (ERROR_MSG,"Failed to initialize flash",BASH_TIPS['DEFAULT']) + err = tuple2str(err) + self.raise_exception( Exception(err) ) + KFlash.log(WARN_MSG,"Index Error, retrying...",BASH_TIPS['DEFAULT']) + time.sleep(0.1) + continue + except TimeoutError: + if retry_count > MAX_RETRY_TIMES: + err = (ERROR_MSG,"Failed to initialize flash",BASH_TIPS['DEFAULT']) + err = tuple2str(err) + self.raise_exception( Exception(err) ) + KFlash.log(WARN_MSG,"Timeout Error, retrying...",BASH_TIPS['DEFAULT']) + time.sleep(0.1) + continue + except: + if retry_count > MAX_RETRY_TIMES: + err = (ERROR_MSG,"Failed to initialize flash",BASH_TIPS['DEFAULT']) + err = tuple2str(err) + self.raise_exception( Exception(err) ) + KFlash.log(WARN_MSG,"Unexcepted Error, retrying...",BASH_TIPS['DEFAULT']) + time.sleep(0.1) + continue + # KFlash.log('MAIX return op:', FlashModeResponse.Operation(op).name, 'reason:', + # FlashModeResponse.ErrorCode(reason).name) + if FlashModeResponse.Operation(op) == FlashModeResponse.Operation.FLASHMODE_FLASH_INIT and FlashModeResponse.ErrorCode(reason) == FlashModeResponse.ErrorCode.ISP_RET_OK: + KFlash.log(INFO_MSG,"Initialization flash Successfully",BASH_TIPS['DEFAULT']) + break + else: + if retry_count > MAX_RETRY_TIMES: + err = (ERROR_MSG,"Failed to initialize flash",BASH_TIPS['DEFAULT']) + err = tuple2str(err) + self.raise_exception( Exception(err) ) + KFlash.log(WARN_MSG,"Unexcepted Return recevied, retrying...",BASH_TIPS['DEFAULT']) + time.sleep(0.1) + continue + + def flash_dataframe(self, data, address=0x80000000): + DATAFRAME_SIZE = 1024 + data_chunks = chunks(data, DATAFRAME_SIZE) + #KFlash.log('[DEBUG] flash dataframe | data length:', len(data)) + total_chunk = math.ceil(len(data)/DATAFRAME_SIZE) + + time_start = time.time() + for n, chunk in enumerate(data_chunks): + self.checkKillExit() + while 1: + self.checkKillExit() + #KFlash.log('[INFO] sending chunk', i, '@address', hex(address), 'chunklen', len(chunk)) + out = struct.pack('II', address, len(chunk)) + + crc32_checksum = struct.pack('I', binascii.crc32(out + chunk) & 0xFFFFFFFF) + + out = struct.pack('HH', 0xc3, 0x00) + crc32_checksum + out + chunk # op: ISP_MEMORY_WRITE: 0xc3 + sent = self.write(out) + #KFlash.log('[INFO]', 'sent', sent, 'bytes', 'checksum', binascii.hexlify(crc32_checksum).decode()) + + address += len(chunk) + + if self.recv_debug(): + break + + columns, lines = TerminalSize.get_terminal_size((100, 24), terminal) + time_delta = time.time() - time_start + speed = '' + if (time_delta > 1): + speed = str(int((n + 1) * DATAFRAME_SIZE / 1024.0 / time_delta)) + 'kiB/s' + printProgressBar(n+1, total_chunk, prefix = 'Downloading ISP:', suffix = speed, length = columns - 35) + + def dump_to_flash(self, data, address=0): + ''' + typedef struct __attribute__((packed)) { + uint8_t op; + int32_t checksum; /* All the fields below are involved in the calculation of checksum */ + uint32_t address; + uint32_t data_len; + uint8_t data_buf[1024]; + } isp_request_t; + ''' + + DATAFRAME_SIZE = ISP_FLASH_DATA_FRAME_SIZE + data_chunks = chunks(data, DATAFRAME_SIZE) + #KFlash.log('[DEBUG] flash dataframe | data length:', len(data)) + + + + for n, chunk in enumerate(data_chunks): + #KFlash.log('[INFO] sending chunk', i, '@address', hex(address)) + out = struct.pack('II', address, len(chunk)) + + crc32_checksum = struct.pack('I', binascii.crc32(out + chunk) & 0xFFFFFFFF) + + out = struct.pack('HH', 0xd4, 0x00) + crc32_checksum + out + chunk + #KFlash.log("[$$$$]", binascii.hexlify(out[:32]).decode()) + retry_count = 0 + while True: + try: + sent = self.write(out) + #KFlash.log('[INFO]', 'sent', sent, 'bytes', 'checksum', crc32_checksum) + self.flash_recv_debug() + except: + retry_count = retry_count + 1 + if retry_count > MAX_RETRY_TIMES: + err = (ERROR_MSG,"Error Count Exceeded, Stop Trying",BASH_TIPS['DEFAULT']) + err = tuple2str(err) + self.raise_exception( Exception(err) ) + continue + break + address += len(chunk) + + + + def flash_erase(self): + #KFlash.log('[DEBUG] erasing spi flash.') + self._port.write(b'\xc0\xd3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc0') + op, reason, text = FlashModeResponse.parse(self.recv_one_return()) + #KFlash.log('MAIX return op:', FlashModeResponse.Operation(op).name, 'reason:', + # FlashModeResponse.ErrorCode(reason).name) + + def install_flash_bootloader(self, data): + # Download flash bootloader + self.flash_dataframe(data, address=0x80000000) + + def load_elf_to_sram(self, f): + try: + from elftools.elf.elffile import ELFFile + from elftools.elf.descriptions import describe_p_type + except ImportError: + err = (ERROR_MSG,'pyelftools must be installed, run '+BASH_TIPS['GREEN']+'`' + ('pip', 'pip3')[sys.version_info > (3, 0)] + ' install pyelftools`',BASH_TIPS['DEFAULT']) + err = tuple2str(err) + self.raise_exception( Exception(err) ) + + elffile = ELFFile(f) + if elffile['e_entry'] != 0x80000000: + KFlash.log(WARN_MSG,"ELF entry is 0x%x instead of 0x80000000" % (elffile['e_entry']), BASH_TIPS['DEFAULT']) + + for segment in elffile.iter_segments(): + t = describe_p_type(segment['p_type']) + KFlash.log(INFO_MSG, ("Program Header: Size: %d, Virtual Address: 0x%x, Type: %s" % (segment['p_filesz'], segment['p_vaddr'], t)), BASH_TIPS['DEFAULT']) + if not (segment['p_vaddr'] & 0x80000000): + continue + if segment['p_filesz']==0 or segment['p_vaddr']==0: + KFlash.log("Skipped") + continue + self.flash_dataframe(segment.data(), segment['p_vaddr']) + + def flash_firmware(self, firmware_bin, aes_key = None, address_offset = 0, sha256Prefix = True, filename = ""): + # type: (bytes, bytes, int, bool) -> None + # Don't remove above code! + + #KFlash.log('[DEBUG] flash_firmware DEBUG: aeskey=', aes_key) + + if sha256Prefix == True: + # Add header to the firmware + # Format: SHA256(after)(32bytes) + AES_CIPHER_FLAG (1byte) + firmware_size(4bytes) + firmware_data + aes_cipher_flag = b'\x01' if aes_key else b'\x00' + + # Encryption + if aes_key: + enc = AES_128_CBC(aes_key, iv=b'\x00'*16).encrypt + padded = firmware_bin + b'\x00'*15 # zero pad + firmware_bin = b''.join([enc(padded[i*16:i*16+16]) for i in range(len(padded)//16)]) + + firmware_len = len(firmware_bin) + + data = aes_cipher_flag + struct.pack('I', firmware_len) + firmware_bin + + sha256_hash = hashlib.sha256(data).digest() + + firmware_with_header = data + sha256_hash + + total_chunk = math.ceil(len(firmware_with_header)/ISP_FLASH_DATA_FRAME_SIZE) + # Slice download firmware + data_chunks = chunks(firmware_with_header, ISP_FLASH_DATA_FRAME_SIZE) # 4kiB for a sector, 16kiB for dataframe + else: + total_chunk = math.ceil(len(firmware_bin)/ISP_FLASH_DATA_FRAME_SIZE) + data_chunks = chunks(firmware_bin, ISP_FLASH_DATA_FRAME_SIZE) + + time_start = time.time() + for n, chunk in enumerate(data_chunks): + self.checkKillExit() + chunk = chunk.ljust(ISP_FLASH_DATA_FRAME_SIZE, b'\x00') # align by size of dataframe + + # Download a dataframe + #KFlash.log('[INFO]', 'Write firmware data piece') + self.dump_to_flash(chunk, address= n * ISP_FLASH_DATA_FRAME_SIZE + address_offset) + columns, lines = TerminalSize.get_terminal_size((100, 24), terminal) + time_delta = time.time() - time_start + speed = '' + if (time_delta > 1): + speed = str(int((n + 1) * ISP_FLASH_DATA_FRAME_SIZE / 1024.0 / time_delta)) + 'kiB/s' + printProgressBar(n+1, total_chunk, prefix = 'Programming BIN:', filename=filename, suffix = speed, length = columns - 35) + + def kill(self): + self._kill_process = True + + def checkKillExit(self): + if self._kill_process: + self._port.close() + self._kill_process = False + raise Exception("Cancel") + + def open_terminal(reset): + control_signal = '0' if reset else '1' + control_signal_b = not reset + import serial.tools.miniterm + # For using the terminal with MaixPy the 'filter' option must be set to 'direct' + # because some control characters are emited + sys.argv = [sys.argv[0], _port, '115200', '--dtr='+control_signal, '--rts='+control_signal, '--filter=direct'] + serial.tools.miniterm.main(default_port=_port, default_baudrate=115200, default_dtr=control_signal_b, default_rts=control_signal_b) + sys.exit(0) + + boards_choices = ["kd233", "dan", "bit", "bit_mic", "goE", "goD", "maixduino", "trainer"] + if terminal: + parser = argparse.ArgumentParser() + parser.add_argument("-p", "--port", help="COM Port", default="DEFAULT") + parser.add_argument("-f", "--flash", help="SPI Flash type, 0 for SPI3, 1 for SPI0", default=1) + parser.add_argument("-b", "--baudrate", type=int, help="UART baudrate for uploading firmware", default=115200) + parser.add_argument("-l", "--bootloader", help="Bootloader bin path", required=False, default=None) + parser.add_argument("-k", "--key", help="AES key in hex, if you need encrypt your firmware.", required=False, default=None) + parser.add_argument("-v", "--version", help="Print version.", action='version', version='0.8.3') + parser.add_argument("--verbose", help="Increase output verbosity", default=False, action="store_true") + parser.add_argument("-t", "--terminal", help="Start a terminal after finish (Python miniterm)", default=False, action="store_true") + parser.add_argument("-n", "--noansi", help="Do not use ANSI colors, recommended in Windows CMD", default=False, action="store_true") + parser.add_argument("-s", "--sram", help="Download firmware to SRAM and boot", default=False, action="store_true") + parser.add_argument("-B", "--Board",required=False, type=str, help="Select dev board", choices=boards_choices) + parser.add_argument("-S", "--Slow",required=False, help="Slow download mode", default=False) + parser.add_argument("firmware", help="firmware bin path") + args = parser.parse_args() + else: + args = argparse.Namespace() + setattr(args, "port", "DEFAULT") + setattr(args, "flash", 1) + setattr(args, "baudrate", 115200) + setattr(args, "bootloader", None) + setattr(args, "key", None) + setattr(args, "verbose", False) + setattr(args, "terminal", False) + setattr(args, "noansi", False) + setattr(args, "sram", False) + setattr(args, "Board", None) + setattr(args, "Slow", False) + + # udpate args for none terminal call + if not terminal: + args.port = dev + args.baudrate = baudrate + args.noansi = noansi + args.sram = sram + args.Board = board + args.firmware = file + + if args.Board == "maixduino" or args.Board == "bit_mic": + args.Board = "goE" + + if (args.noansi == True): + BASH_TIPS = dict(NORMAL='',BOLD='',DIM='',UNDERLINE='', + DEFAULT='', RED='', YELLOW='', GREEN='', + BG_DEFAULT='', BG_WHITE='') + ERROR_MSG = BASH_TIPS['RED']+BASH_TIPS['BOLD']+'[ERROR]'+BASH_TIPS['NORMAL'] + WARN_MSG = BASH_TIPS['YELLOW']+BASH_TIPS['BOLD']+'[WARN]'+BASH_TIPS['NORMAL'] + INFO_MSG = BASH_TIPS['GREEN']+BASH_TIPS['BOLD']+'[INFO]'+BASH_TIPS['NORMAL'] + KFlash.log(INFO_MSG,'ANSI colors not used',BASH_TIPS['DEFAULT']) + + manually_set_the_board = False + if args.Board: + manually_set_the_board = True + + if args.port == "DEFAULT": + if args.Board == "goE": + list_port_info = list(serial.tools.list_ports.grep("0403")) #Take the second one + if len(list_port_info) == 0: + err = (ERROR_MSG,"No vaild COM Port found in Auto Detect, Check Your Connection or Specify One by"+BASH_TIPS['GREEN']+'`--port/-p`',BASH_TIPS['DEFAULT']) + err = tuple2str(err) + raise_exception( Exception(err) ) + list_port_info.sort() + if len(list_port_info) == 1: + _port = list_port_info[0].device + elif len(list_port_info) > 1: + _port = list_port_info[1].device + KFlash.log(INFO_MSG,"COM Port Auto Detected, Selected ", _port, BASH_TIPS['DEFAULT']) + elif args.Board == "trainer": + list_port_info = list(serial.tools.list_ports.grep("0403")) #Take the first one + if(len(list_port_info)==0): + err = (ERROR_MSG,"No vaild COM Port found in Auto Detect, Check Your Connection or Specify One by"+BASH_TIPS['GREEN']+'`--port/-p`',BASH_TIPS['DEFAULT']) + err = tuple2str(err) + raise_exception( Exception(err) ) + list_port_info.sort() + _port = list_port_info[0].device + KFlash.log(INFO_MSG,"COM Port Auto Detected, Selected ", _port, BASH_TIPS['DEFAULT']) + else: + try: + list_port_info = next(serial.tools.list_ports.grep(VID_LIST_FOR_AUTO_LOOKUP)) #Take the first one within the list + _port = list_port_info.device + KFlash.log(INFO_MSG,"COM Port Auto Detected, Selected ", _port, BASH_TIPS['DEFAULT']) + except StopIteration: + err = (ERROR_MSG,"No vaild COM Port found in Auto Detect, Check Your Connection or Specify One by"+BASH_TIPS['GREEN']+'`--port/-p`',BASH_TIPS['DEFAULT']) + err = tuple2str(err) + raise_exception( Exception(err) ) + else: + _port = args.port + KFlash.log(INFO_MSG,"COM Port Selected Manually: ", _port, BASH_TIPS['DEFAULT']) + + self.loader = MAIXLoader(port=_port, baudrate=115200) + file_format = ProgramFileFormat.FMT_BINARY + + # 0. Check firmware + try: + firmware_bin = open(args.firmware, 'rb') + except FileNotFoundError: + err = (ERROR_MSG,'Unable to find the firmware at ', args.firmware, BASH_TIPS['DEFAULT']) + err = tuple2str(err) + raise_exception( Exception(err) ) + + with open(args.firmware, 'rb') as f: + file_header = f.read(4) + #if file_header.startswith(bytes([0x50, 0x4B])): + if file_header.startswith(b'\x50\x4B'): + if ".kfpkg" != os.path.splitext(args.firmware)[1]: + KFlash.log(INFO_MSG, 'Find a zip file, but not with ext .kfpkg:', args.firmware, BASH_TIPS['DEFAULT']) + else: + file_format = ProgramFileFormat.FMT_KFPKG + + #if file_header.startswith(bytes([0x7F, 0x45, 0x4C, 0x46])): + if file_header.startswith(b'\x7f\x45\x4c\x46'): + file_format = ProgramFileFormat.FMT_ELF + if args.sram: + KFlash.log(INFO_MSG, 'Find an ELF file:', args.firmware, BASH_TIPS['DEFAULT']) + else: + err = (ERROR_MSG, 'This is an ELF file and cannot be programmed to flash directly:', args.firmware, BASH_TIPS['DEFAULT'] , '\r\nPlease retry:', args.firmware + '.bin', BASH_TIPS['DEFAULT']) + err = tuple2str(err) + raise_exception( Exception(err) ) + + # 1. Greeting. + KFlash.log(INFO_MSG,"Trying to Enter the ISP Mode...",BASH_TIPS['DEFAULT']) + + retry_count = 0 + + while 1: + self.checkKillExit() + try: + retry_count = retry_count + 1 + if retry_count > 15: + err = (ERROR_MSG,"No vaild Kendryte K210 found in Auto Detect, Check Your Connection or Specify One by"+BASH_TIPS['GREEN']+'`-p '+('/dev/ttyUSB0', 'COM3')[sys.platform == 'win32']+'`',BASH_TIPS['DEFAULT']) + err = tuple2str(err) + raise_exception( Exception(err) ) + if args.Board == "dan" or args.Board == "bit" or args.Board == "trainer": + try: + KFlash.log('.', end='') + self.loader.reset_to_isp_dan() + self.loader.greeting() + break + except TimeoutError: + pass + elif args.Board == "kd233": + try: + KFlash.log('_', end='') + self.loader.reset_to_isp_kd233() + self.loader.greeting() + break + except TimeoutError: + pass + elif args.Board == "goE": + try: + KFlash.log('*', end='') + self.loader.reset_to_isp_kd233() + self.loader.greeting() + break + except TimeoutError: + pass + elif args.Board == "goD": + try: + KFlash.log('#', end='') + self.loader.reset_to_isp_goD() + self.loader.greeting() + break + except TimeoutError: + pass + else: + try: + KFlash.log('.', end='') + self.loader.reset_to_isp_dan() + self.loader.greeting() + args.Board = "dan" + KFlash.log() + KFlash.log(INFO_MSG,"Automatically detected dan/bit/trainer",BASH_TIPS['DEFAULT']) + break + except TimeoutError: + pass + try: + KFlash.log('_', end='') + self.loader.reset_to_isp_kd233() + self.loader.greeting() + args.Board = "kd233" + KFlash.log() + KFlash.log(INFO_MSG,"Automatically detected goE/kd233",BASH_TIPS['DEFAULT']) + break + except TimeoutError: + pass + try: + KFlash.log('.', end='') + self.loader.reset_to_isp_goD() + self.loader.greeting() + args.Board = "goD" + KFlash.log() + KFlash.log(INFO_MSG,"Automatically detected goD",BASH_TIPS['DEFAULT']) + break + except TimeoutError: + pass + try: + # Magic, just repeat, don't remove, it may unstable, don't know why. + KFlash.log('_', end='') + self.loader.reset_to_isp_kd233() + self.loader.greeting() + args.Board = "kd233" + KFlash.log() + KFlash.log(INFO_MSG,"Automatically detected goE/kd233",BASH_TIPS['DEFAULT']) + break + except TimeoutError: + pass + except Exception as e: + KFlash.log() + raise_exception( Exception("Greeting fail, check serial port ("+str(e)+")" ) ) + + # Don't remove this line + # Dangerous, here are dinosaur infested!!!!! + ISP_RECEIVE_TIMEOUT = 3 + + KFlash.log() + KFlash.log(INFO_MSG,"Greeting Message Detected, Start Downloading ISP",BASH_TIPS['DEFAULT']) + + if manually_set_the_board and (not args.Slow): + if (args.baudrate >= 1500000) or args.sram: + self.loader.change_baudrate_stage0(args.baudrate) + + # 2. download bootloader and firmware + if args.sram: + if file_format == ProgramFileFormat.FMT_KFPKG: + err = (ERROR_MSG, "Unable to load kfpkg to SRAM") + err = tuple2str(err) + raise_exception( Exception(err) ) + elif file_format == ProgramFileFormat.FMT_ELF: + self.loader.load_elf_to_sram(firmware_bin) + else: + self.loader.install_flash_bootloader(firmware_bin.read()) + else: + # install bootloader at 0x80000000 + isp_loader = open(args.bootloader, 'rb').read() if args.bootloader else ISP_PROG + self.loader.install_flash_bootloader(isp_loader) + + # Boot the code from SRAM + self.loader.boot() + + if args.sram: + # Dangerous, here are dinosaur infested!!!!! + # Don't touch this code unless you know what you are doing + self.loader._port.baudrate = args.baudrate + KFlash.log(INFO_MSG,"Boot user code from SRAM", BASH_TIPS['DEFAULT']) + if(args.terminal == True): + open_terminal(False) + msg = "Burn SRAM OK" + raise_exception( Exception(msg) ) + + # Dangerous, here are dinosaur infested!!!!! + # Don't touch this code unless you know what you are doing + self.loader._port.baudrate = 115200 + + KFlash.log(INFO_MSG,"Wait For 0.1 second for ISP to Boot", BASH_TIPS['DEFAULT']) + + time.sleep(0.1) + + self.loader.flash_greeting() + + if args.baudrate != 115200: + self.loader.change_baudrate(args.baudrate) + KFlash.log(INFO_MSG,"Baudrate changed, greeting with ISP again ... ", BASH_TIPS['DEFAULT']) + self.loader.flash_greeting() + + self.loader.init_flash(args.flash) + + if file_format == ProgramFileFormat.FMT_KFPKG: + KFlash.log(INFO_MSG,"Extracting KFPKG ... ", BASH_TIPS['DEFAULT']) + firmware_bin.close() + with tempfile.TemporaryDirectory() as tmpdir: + try: + with zipfile.ZipFile(args.firmware) as zf: + zf.extractall(tmpdir) + except zipfile.BadZipFile: + err = (ERROR_MSG,'Unable to Decompress the kfpkg, your file might be corrupted.',BASH_TIPS['DEFAULT']) + err = tuple2str(err) + raise_exception( Exception(err) ) + + fFlashList = open(os.path.join(tmpdir, 'flash-list.json'), "r") + sFlashList = re.sub(r'"address": (.*),', r'"address": "\1",', fFlashList.read()) #Pack the Hex Number in json into str + fFlashList.close() + jsonFlashList = json.loads(sFlashList) + for lBinFiles in jsonFlashList['files']: + self.checkKillExit() + KFlash.log(INFO_MSG,"Writing",lBinFiles['bin'],"into","0x%08x"%int(lBinFiles['address'], 0),BASH_TIPS['DEFAULT']) + with open(os.path.join(tmpdir, lBinFiles["bin"]), "rb") as firmware_bin: + self.loader.flash_firmware(firmware_bin.read(), None, int(lBinFiles['address'], 0), lBinFiles['sha256Prefix'], filename=lBinFiles['bin']) + else: + if args.key: + aes_key = binascii.a2b_hex(args.key) + if len(aes_key) != 16: + raise_exception( ValueError('AES key must by 16 bytes') ) + + self.loader.flash_firmware(firmware_bin.read(), aes_key=aes_key) + else: + self.loader.flash_firmware(firmware_bin.read()) + + # 3. boot + if args.Board == "dan" or args.Board == "bit" or args.Board == "trainer": + self.loader.reset_to_boot_dan() + elif args.Board == "kd233": + self.loader.reset_to_boot_kd233() + elif args.Board == "goE": + self.loader.reset_to_boot_maixgo() + elif args.Board == "goD": + self.loader.reset_to_boot_goD() + else: + KFlash.log(WARN_MSG,"Board unknown !! please press reset to boot!!") + + KFlash.log(INFO_MSG,"Rebooting...", BASH_TIPS['DEFAULT']) + try: + self.loader._port.close() + except Exception: + pass + + if(args.terminal == True): + open_terminal(True) + + def kill(self): + if self.loader: + self.loader.kill() + self.killProcess = True + + def checkKillExit(self): + if self.killProcess: + if self.loader: + self.loader._port.close() + raise Exception("Cancel") + + +def main(): + kflash = KFlash() + try: + kflash.process() + except Exception as e: + if str(e) == "Burn SRAM OK": + sys.exit(0) + kflash.log(str(e)) + sys.exit(1) + +if __name__ == '__main__': + main() diff --git a/user/Makefile b/user/Makefile index a7ea1fb..ab21f83 100644 --- a/user/Makefile +++ b/user/Makefile @@ -1,7 +1,7 @@ .PHONY: build TARGET := riscv64imac-unknown-none-elf -MODE := debug +MODE := release # 用户程序目录 SRC_DIR := src/bin @@ -16,6 +16,8 @@ OUT_DIR := build/disk IMG_FILE := build/raw.img QCOW_FILE := build/disk.img +SDCARD ?= /dev/sdb + # 安装 rcore-fs-fuse 工具 dependency: ifeq ($(shell which rcore-fs-fuse),) @@ -25,15 +27,25 @@ endif # 编译、打包、格式转换、预留空间 build: dependency +ifeq ($(MODE),release) + @cargo build --release +else @cargo build +endif + $(foreach bin_file,$(BIN_FILES),riscv64-unknown-elf-objcopy --strip-debug $(bin_file) $(bin_file);) @echo Targets: $(patsubst $(SRC_DIR)/%.rs, %, $(SRC_FILES)) @rm -rf $(OUT_DIR) @mkdir -p $(OUT_DIR) @cp $(BIN_FILES) $(OUT_DIR) + @dd if=/dev/zero of=$(OUT_DIR)/SWAP_FILE bs=1M count=16 @rcore-fs-fuse --fs sfs $(IMG_FILE) $(OUT_DIR) zip @qemu-img convert -f raw $(IMG_FILE) -O qcow2 $(QCOW_FILE) @qemu-img resize $(QCOW_FILE) +1G +sdcard: build + @sudo dd if=/dev/zero of=$(SDCARD) bs=1M count=50 + @sudo dd if=$(IMG_FILE) of=$(SDCARD) + clean: @cargo clean - @rm -rf $(OUT_DIR) $(IMG_FILE) $(QCOW_FILE) \ No newline at end of file + @rm -rf $(OUT_DIR) $(IMG_FILE) $(QCOW_FILE) diff --git a/user/src/bin/fantastic_text.rs b/user/src/bin/fantastic_text.rs new file mode 100644 index 0000000..cd3f563 --- /dev/null +++ b/user/src/bin/fantastic_text.rs @@ -0,0 +1,44 @@ +#![no_std] +#![no_main] + +#[macro_use] +extern crate user_lib; + +macro_rules! color_text { + ($text:expr, $color:expr) => {{ + format_args!("\x1b[{}m{}\x1b[0m", $color, $text) + }}; +} + +// IMPORTANT: Must define main() like this +#[no_mangle] +pub fn main() { + println!( + "{}{}{}{}{} {}{}{}{} {}{}{}{}{}{}", + color_text!("H", 31), + color_text!("e", 32), + color_text!("l", 33), + color_text!("l", 34), + color_text!("o", 35), + color_text!("R", 36), + color_text!("u", 37), + color_text!("s", 90), + color_text!("t", 91), + color_text!("u", 92), + color_text!("C", 93), + color_text!("o", 94), + color_text!("r", 95), + color_text!("e", 96), + color_text!("!", 97), + ); + + let text = + "reguler \x1b[4munderline\x1b[24m \x1b[7mreverse\x1b[27m \x1b[9mstrikethrough\x1b[29m"; + println!("\x1b[47m{}\x1b[0m", color_text!(text, 30)); + for i in 31..38 { + println!("{}", color_text!(text, i)); + } + for i in 90..98 { + println!("{}", color_text!(text, i)); + } +} diff --git a/user/src/bin/notebook.rs b/user/src/bin/notebook.rs index 42c02da..53d42be 100644 --- a/user/src/bin/notebook.rs +++ b/user/src/bin/notebook.rs @@ -7,10 +7,19 @@ extern crate user_lib; use user_lib::console::*; #[no_mangle] -pub fn main() -> ! { +pub fn main() -> isize { println!("\x1b[2J"); loop { + /* let string = getchars(); print!("{}", string); + */ + let ch = getchar(); + if ch == 29 { + // Ctrl + ] + return 0; + } + print!("{}", ch as char); } + 0 } diff --git a/user/src/bin/swap_test.rs b/user/src/bin/swap_test.rs new file mode 100644 index 0000000..797e324 --- /dev/null +++ b/user/src/bin/swap_test.rs @@ -0,0 +1,17 @@ +#![no_std] +#![no_main] +#[macro_use] +extern crate user_lib; + +static mut array: [usize; 256 * 1024] = [0usize; 256 * 1024]; +#[no_mangle] +pub unsafe fn main()->usize{ + for i in 0..array.len() { + array[i] = i; + } + for i in 0..array.len() { + assert_eq!(i, array[i]); + } + println!("\x1b[32mtest passed\x1b[0m"); + 0 +} \ No newline at end of file diff --git a/user/src/bin/user_shell.rs b/user/src/bin/user_shell.rs new file mode 100644 index 0000000..fc7836c --- /dev/null +++ b/user/src/bin/user_shell.rs @@ -0,0 +1,51 @@ +#![no_std] +#![no_main] + +extern crate alloc; + +#[macro_use] +extern crate user_lib; + +const LF: u8 = 0x0au8; +const CR: u8 = 0x0du8; +const DL: u8 = 0x7fu8; +const BS: u8 = 0x08u8; + +use alloc::string::String; +use user_lib::syscall::sys_exec; +use user_lib::console::getchar; + +#[no_mangle] +pub fn main(){ + println!("Rust user shell"); + let mut line: String = String::new(); + print!(">> "); + loop { + let c = getchar(); + match c { + LF | CR => { + println!(""); + if !line.is_empty() { + println!("searching for program {}", line); + line.push('\0'); + sys_exec(line.as_ptr()); + line.clear(); + } + print!(">> "); + } + DL => { + if !line.is_empty() { + print!("{}", BS as char); + print!(" "); + print!("{}", BS as char); + line.pop(); + } + } + _ => { + print!("{}", c as char); + line.push(c as char); + } + } + } +} + diff --git a/user/src/config.rs b/user/src/config.rs index e99f189..b73c427 100644 --- a/user/src/config.rs +++ b/user/src/config.rs @@ -1,2 +1,2 @@ /// 每个用户进程所用的堆大小（1M） -pub const USER_HEAP_SIZE: usize = 0x10_0000; +pub const USER_HEAP_SIZE: usize = 0x1_0000; diff --git a/user/src/syscall.rs b/user/src/syscall.rs index bd719ad..b7ef0e7 100644 --- a/user/src/syscall.rs +++ b/user/src/syscall.rs @@ -6,6 +6,7 @@ pub const STDOUT: usize = 1; const SYSCALL_READ: usize = 63; const SYSCALL_WRITE: usize = 64; const SYSCALL_EXIT: usize = 93; +const SYSCALL_EXEC: usize = 221; /// 将参数放在对应寄存器中，并执行 `ecall` fn syscall(id: usize, arg0: usize, arg1: usize, arg2: usize) -> isize { @@ -51,3 +52,7 @@ pub fn sys_exit(code: isize) -> ! { syscall(SYSCALL_EXIT, code as usize, 0, 0); unreachable!() } + +pub fn sys_exec(path:*const u8)->isize{ + syscall(SYSCALL_EXEC,path as usize,0,0) +} \ No newline at end of file