ruby
diff --git a/‎zjit/src/asm/x86_64/mod.rs‎
Lines changed: 2 additions & 2 deletions b/‎zjit/src/asm/x86_64/mod.rs‎
Lines changed: 2 additions & 2 deletions
diff --git a/‎zjit/src/backend/arm64/mod.rs‎
Lines changed: 2 additions & 2 deletions b/‎zjit/src/backend/arm64/mod.rs‎
Lines changed: 2 additions & 2 deletions
@@ -921,7 +921,7 @@ pub fn lea(cb: &mut CodeBlock, dst: X86Opnd, src: X86Opnd) {
         assert!(matches!(src, X86Opnd::Mem(_) | X86Opnd::IPRel(_)));
         write_rm(cb, false, true, dst, src, None, &[0x8d]);
     } else {
-        unreachable!();
+        unreachable!("expected dst to be Reg, but got: {dst:?}");
     }
 }
 
@@ -1334,7 +1334,7 @@ pub fn test(cb: &mut CodeBlock, rm_opnd: X86Opnd, test_opnd: X86Opnd) {
                 write_rm(cb, rm_num_bits == 16, rm_num_bits == 64, test_opnd, rm_opnd, None, &[0x85]);
             }
         },
-        _ => unreachable!()
+        _ => unreachable!("expected test_opnd to be Reg, UImm, or Imm, but got: {rm_opnd:?}, {test_opnd:?}")
     };
 }
 
 
@@ -184,14 +184,13 @@ fn emit_load_value(cb: &mut CodeBlock, rd: A64Opnd, value: u64) -> usize {
 /// This has the same number of registers for x86_64 and arm64.
 /// SCRATCH0 and SCRATCH1 are excluded.
 pub const ALLOC_REGS: &[Reg] = &[
-    X0_REG,
     X1_REG,
     X2_REG,
     X3_REG,
     X4_REG,
     X5_REG,
     X11_REG,
-    X12_REG,
+    X0_REG,
 ];
 
 impl Assembler
@@ -205,6 +204,7 @@ impl Assembler
     const SCRATCH1_REG: Reg = X17_REG;
     const SCRATCH0: A64Opnd = A64Opnd::Reg(Self::SCRATCH0_REG);
     const SCRATCH1: A64Opnd = A64Opnd::Reg(Self::SCRATCH1_REG);
+    pub const SPILL_BASE_REG: Reg = X12_REG;
 
     /// Get the list of registers from which we will allocate on this platform
     pub fn get_alloc_regs() -> Vec<Reg> {
Original file line number	Diff line number	Diff line change
`@@ -921,7 +921,7 @@ pub fn lea(cb: &mut CodeBlock, dst: X86Opnd, src: X86Opnd) {`
`921`	`921`	`assert!(matches!(src, X86Opnd::Mem(_) \| X86Opnd::IPRel(_)));`
`922`	`922`	`write_rm(cb, false, true, dst, src, None, &[0x8d]);`
`923`	`923`	`} else {`
`924`		`- unreachable!();`
	`924`	`+ unreachable!("expected dst to be Reg, but got: {dst:?}");`
`925`	`925`	`}`
`926`	`926`	`}`
`927`	`927`
`@@ -1334,7 +1334,7 @@ pub fn test(cb: &mut CodeBlock, rm_opnd: X86Opnd, test_opnd: X86Opnd) {`
`1334`	`1334`	`write_rm(cb, rm_num_bits == 16, rm_num_bits == 64, test_opnd, rm_opnd, None, &[0x85]);`
`1335`	`1335`	`}`
`1336`	`1336`	`},`
`1337`		`- _ => unreachable!()`
	`1337`	`+ _ => unreachable!("expected test_opnd to be Reg, UImm, or Imm, but got: {rm_opnd:?}, {test_opnd:?}")`
`1338`	`1338`	`};`
`1339`	`1339`	`}`
`1340`	`1340`