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Commits on May 29, 2026

• [CUDA] Support preferred copy instruction lowering (#2303)

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  LeiWang1999

  authored
  d093756

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• [Transform] Reduce ragged SIMT copy padding (#2302)

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  LeiWang1999

  authored
  44df176

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• [Transform] Preserve ragged parallel padding guards (#2299)

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  LeiWang1999

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  b175da0

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Commits on May 28, 2026

• [BugFix][Transform] Deduplicate DeclBuffer names after loop unrolling (#2290)

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  zhouyangye1076

  and

  LeiWang1999

  authored
  ac2e1d7

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• [BugFix][CuTeDSL] Support TileKernels backend cases (#2289)

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  JayceSu98

  and

  dingsg

  authored
  6520965

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• [Feature] Add stochastic rounding cast for f32 -> fp8/fp4 on CUDA (#2260)

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  3 peopleauthored
  ec3be54

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• [Reduce][Codegen] Guard packed local reduce ramp loads (#2298)

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  LeiWang1999

  authored
  4e9b054

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• [TIR][Transform] Fix ragged SIMT loop partitioning (#2296)

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  LeiWang1999

  authored
  b9c87cd

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• [Backend] Promote PassPipeline to backend sub-folder and cleanup Metal Leftover (#2291)

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  SiriusNEO

  authored
  4f0e127

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• [TIR][Transform] Fix shared.dyn alias sync analysis (#2293)

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  LeiWang1999

  authored
  b0b945b

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• [Transform] Prefer full-thread loop partitioning (#2288)

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  LeiWang1999

  authored
  0d689e7

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• [FIX] pass enable_2cta to ptx_tcgen05_mma_ts in tcgen05 macro generator (#2287)

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  ighoshsubho

  and

  Rachmanino

  authored
  21fbbf9

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Commits on May 27, 2026

• [Backend] Refactor Transform Pipeline to support different backends (#2189)

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  SiriusNEO

  authored
  0a9b651

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• [Feature] Add float4_e2m1_unpacked dtype (#2271)

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  Rachmanino

  authored
  362d9e0

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• [TIR][Transform] Handle ragged SIMT copy partitioning (#2285)

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  LeiWang1999

  authored
  693f5e1

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• Fix HIP intrinsic rules registered on tir.* instead of tirx.* (#2282)

  kashif

  authored
  93f6863

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• [Fix] Remove "stop on other gen" heuristic in kill-point reorder (#2204)

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  Rachmanino

  and

  claude

  authored
  0779910

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Commits on May 26, 2026

• [BugFix][CUDA] Lower FP32 MMA operands as TF32 (#2280)

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  JayceSu98

  authored
  23d91c5

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• [Transform][Pipeline] Keep pointer binds out of replayable scalar inlining (#2278)

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  LeiWang1999

  authored
  1d3bb9f

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• [TIR][Transform] Revert per-epoch shared memory liveness (#2281)

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  LeiWang1999

  authored
  e0c3265

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• [Windows] Gate libtvm compatibility symlinks to Unix (#2273)

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  LeiWang1999

  authored
  928c942

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• [Transform] Rewrite MergeSharedMemoryAllocations with per-epoch liveness (#2185)

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  TensorGlue-IEIT

  authored
  e84a0ee

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• [Pipeline] Refactor software pipeline transforms (#2245)

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  LeiWang1999

  authored
  3bf3d00

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• [CUDA][Reduce] Fix packed mixed-dtype reduce casts (#2276)

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  LeiWang1999

  authored
  124ba6a

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• [BugFix][Examples] Align grouped GEMM backward runner arguments (#2275)

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  JayceSu98

  authored
  fb4f473

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• [Feature] Support named barrier arrive (#2194)

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  3 peopleauthored
  c66cadf

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• [CuTeDSL] Represent tfloat32 storage as Float32 (#2268)

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  JayceSu98

  authored
  16589d8

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Commits on May 25, 2026

• [Bugfix] Fix cached source restore and Metal codegen fallback (#2266)

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  LeiWang1999

  authored
  7f359ea

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• [Feature] Add CUDA __ffs intrinsic for bit manipulation (#2264)

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  Rachmanino

  authored
  4ad6e3e

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• [TileOP] Add scan operators (#2262)

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  LeiWang1999

  authored
  146a1d3

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• [FFI][Host] Refactor packed API binder to use FFI asserts (#2263)

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  LeiWang1999

  authored
  6554543

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• [CuTeDSL] Lower handle_add_byte_offset in Python codegen (#2261)

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  JayceSu98

  authored
  91305a5

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• Optimize disk cache source loading (#2176)

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  sepcnt

  and

  LeiWang1999

  authored
  e20e74f

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• [Feature] Add thread_extent parameter to `T.tma_copy` for flexible TMA copy (#2205)

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  3 peopleauthored
  6928c82

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• [Example] Add CLC-pipelined 2-CTA GEMM example for sm100 (#2169)

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  ighoshsubho

  authored
  b04555b

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