In SiliconCompiler, I am trying to illustrate the full digital flow from RTL to signoff using a minimal design. May I know how to generate a padring and assign IO/VDD/GND pads using any of the supported open-source PDKs (e.g., IHP130 or Sky130)?
For illustration, my goal is to attach:

1. 3 IO pads (for in, out, and clock)
2. The necessary VDD and GND pads

Here's the minimal Verilog and Python script I’m using:

module find_verilog(in, out, clock);
input in;
input clock;
output reg out;

always @ (posedge clock) begin
out <= in;
end
endmodule

#!/usr/bin/env python3

from siliconcompiler import Chip
from siliconcompiler.targets import freepdk45_demo

if name == "main":
chip = Chip('find_verilog')
chip.input('find_verilog.v')
chip.set('design', 'find_verilog')
chip.use(freepdk45_demo)
chip.clock('clock', period=1)
chip.set('option', 'remote', False)
chip.set('option', 'nodisplay', True)
chip.set('option', 'loglevel', 'warning')
chip.set('option', 'clean', True)
chip.set('constraint', 'outline', [(0, 0), (4, 4)])
chip.set('constraint', 'density', 8)
chip.run()
chip.summary()
chip.snapshot()

What steps need to be added or modified in this script to:

1. Generate a padframe (padring)?
2. Assign specific IO pads for in, out, and clock?
3. Include the required power/ground pads?
4. Complete DRC for signoff?

If this is only partially supported via SiliconCompiler's high-level Python API, are there low-level overrides or integration points (e.g., using OpenRoad/OpenLane's padframe support or external GDS stitching) that you would recommend?

Any specific example or guidance would be highly appreciated - thank you!