diff --git a/devices/common_patches/fdcan/fdcan_g4.yaml b/devices/common_patches/fdcan/fdcan_g4.yaml index ad00d8500..5f25bb618 100644 --- a/devices/common_patches/fdcan/fdcan_g4.yaml +++ b/devices/common_patches/fdcan/fdcan_g4.yaml @@ -4,6 +4,14 @@ _include: - ./fdcan_common.yaml "FDCAN,FDCAN?": + _modify: + CREL: + resetValue: 0x32141218 + PSR: + access: read-only + RXF0S: + access: read-only + RXGFC: _add: LSE: @@ -22,6 +30,32 @@ _include: description: FIFO 1 operation mode bitOffset: 8 bitWidth: 1 + _modify: + ANFS: + description: Accept Non-matching frames standard + ANFE: + description: Accept Non-matching frames extended + RRFS: + description: Reject remote frames standard + RRFE: + description: Reject remote frames extended + + ANFS: + accept_rx_fifo0: [0b00, "Accept non-matching standard frames in Rx FIFO 0"] + accept_rx_fifo1: [0b01, "Accept non-matching standard frames in Rx FIFO 1"] + reject: [0b10, "Reject non-matching standard frames"] + reject_: [0b11, "Reject non-matching standard frames"] + ANFE: + accept_rx_fifo0: [0b00, "Accept non-matching extended frames in Rx FIFO 0"] + accept_rx_fifo1: [0b01, "Accept non-matching extended frames in Rx FIFO 1"] + reject: [0b10, "Reject non-matching extended frames"] + reject_: [0b11, "Reject non-matching extended frames"] + RRFS: + filter: [0b0, "Filter remote frames with 11-bit standard IDs"] + reject: [0b1, "Reject all remote frames with 11-bit standard IDs"] + RRFE: + filter: [0b0, "Filter remote frames with 29-bit standard IDs"] + reject: [0b1, "Reject remote frames with 29-bit standard IDs"] # Interrupt registers are a disaster, start over IR: @@ -260,8 +294,10 @@ _include: TXFQS: _modify: TFQPI: + bitOffset: 16 bitWidth: 2 TFGI: + bitOffset: 8 bitWidth: 2 TFFL: bitWidth: 3 @@ -301,3 +337,76 @@ _include: _modify: CFIE: bitWidth: 3 + + ECR: + _modify: + TREC: + name: REC + + HPMS: + _modify: + FIDX: + bitOffset: 8 + bitWidth: 5 + MSI: + bitOffset: 6 + bitWidth: 2 + BIDX: + bitOffset: 0 + bitWidth: 3 + + RXF0S: + _modify: + F0PI: + bitOffset: 16 + bitWidth: 2 + F0GI: + bitOffset: 8 + bitWidth: 2 + F0FL: + bitOffset: 0 + bitWidth: 4 + + RXF0A: + _modify: + F0AI: + bitOffset: 0 + bitWidth: 3 + + RXF1S: + _delete: + DMS: + _modify: + F1PI: + bitOffset: 16 + bitWidth: 2 + F1GI: + bitOffset: 8 + bitWidth: 2 + F1FL: + bitOffset: 0 + bitWidth: 4 + + RXF1A: + _modify: + F1AI: + bitOffset: 0 + bitWidth: 4 + + TXBC: + _delete: + TFQS: + NDTB: + TBSA: + _modify: + TFQM: + bitOffset: 24 + bitWidth: 1 + TFQM: + fifo: [0b0, "Tx FIFO operation"] + queue: [0b1, "Tx queue operation"] + + TXEFA: + _modify: + EFAI: + bitWidth: 2 diff --git a/devices/common_patches/tim/v2/g4.yaml b/devices/common_patches/tim/v2/g4.yaml index f37cf2b58..6f7ead883 100644 --- a/devices/common_patches/tim/v2/g4.yaml +++ b/devices/common_patches/tim/v2/g4.yaml @@ -14,6 +14,76 @@ _derive: OC6M_bit3: name: OC6M_3 + CR1: + CKD: + Div1: [0, "t_DTS = t_CK_INT"] + Div2: [1, "t_DTS = 2 × t_CK_INT"] + Div4: [2, "t_DTS = 4 × t_CK_INT"] + CMS: + EdgeAligned: [0, "The counter counts up or down depending on the direction bit"] + CenterAligned1: [1, "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."] + CenterAligned2: [2, "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."] + CenterAligned3: [3, "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."] + DIR: + Up: [0, "Counter used as upcounter"] + Down: [1, "Counter used as downcounter"] + CEN: + Disabled: [0, "Counter disabled"] + Enabled: [1, "Counter enabled"] + + CCMR1_Output: + OC2PE: + Disabled: [0, "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"] + Enabled: [1, "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"] + CC2S: + Output: [0, "CC2 channel is configured as output"] + OC1PE: + Disabled: [0, "Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately"] + Enabled: [1, "Preload register on CCR1 enabled. Preload value is loaded into active register on each update event"] + CC1S: + Output: [0, "CC1 channel is configured as output"] + + CCMR2_Output: + OC4PE: + Disabled: [0, "Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately"] + Enabled: [1, "Preload register on CCR4 enabled. Preload value is loaded into active register on each update event"] + CC4S: + Output: [0, "CC4 channel is configured as output"] + OC3PE: + Disabled: [0, "Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately"] + Enabled: [1, "Preload register on CCR3 enabled. Preload value is loaded into active register on each update event"] + CC3S: + Output: [0, "CC3 channel is configured as output"] + + DIER: + TDE: + Disabled: [0, "Trigger DMA request disabled"] + Enabled: [1, "Trigger DMA request enabled"] + "CC?DE": + Disabled: [0, "CCx DMA request disabled"] + Enabled: [1, "CCx DMA request enabled"] + UDE: + Disabled: [0, "Update DMA request disabled"] + Enabled: [1, "Update DMA request enabled"] + TIE: + Disabled: [0, "Trigger interrupt disabled"] + Enabled: [1, "Trigger interrupt enabled"] + "CC?IE": + Disabled: [0, "CCx interrupt disabled"] + Enabled: [1, "CCx interrupt enabled"] + UIE: + Disabled: [0, "Update interrupt disabled"] + Enabled: [1, "Update interrupt enabled"] + + PSC: + _modify: + PSC: + bitOffset: 0 + bitWidth: 16 + _write_constraint: [0, 65535] + + + TIM2: CNT: _modify: @@ -33,15 +103,26 @@ TIM2: CNT: _modify: CNT: + bitOffset: 0 bitWidth: 16 + _write_constraint: [0, 65535] ARR: _modify: ARR: - bitWidth: 20 + bitOffset: 0 + bitWidth: 16 + _write_constraint: [0, 65535] CCR?: _modify: CCR?: - bitWidth: 20 + bitOffset: 0 + bitWidth: 16 + _write_constraint: [0, 65535] + CCR: + bitOffset: 0 + bitWidth: 16 + _write_constraint: [0, 65535] + _include: - ../tim_ccr.yaml diff --git a/devices/stm32g431.yaml b/devices/stm32g431.yaml index 5d79b4698..c6ff256f2 100644 --- a/devices/stm32g431.yaml +++ b/devices/stm32g431.yaml @@ -31,3 +31,5 @@ _include: - ../peripherals/rcc/rcc_g4.yaml - common_patches/tim/v2/g4.yaml - ../peripherals/tim/v2/ccm.yaml + - ../peripherals/can/fdcan.yaml + - ./common_patches/fdcan/fdcan_g4.yaml diff --git a/devices/stm32g441.yaml b/devices/stm32g441.yaml index b4eb769ae..2ffda05df 100644 --- a/devices/stm32g441.yaml +++ b/devices/stm32g441.yaml @@ -23,7 +23,7 @@ _include: - ../peripherals/cordic/cordic_g4.yaml - ./common_patches/sai/sai_v1.yaml - ./common_patches/rtc/rtc_cr.yaml - - ../peripherals/opamp/opamp_g4_common.yaml + - ../peripherals/opamp/opamp_g4_common.yaml - ../peripherals/i2c/i2c_v2.yaml - ../peripherals/gpio/gpio_v2.yaml - ./common_patches/rename_USB_FS_peripheral_to_USB.yaml @@ -31,3 +31,5 @@ _include: - ../peripherals/rcc/rcc_g4.yaml - common_patches/tim/v2/g4.yaml - ../peripherals/tim/v2/ccm.yaml + - ../peripherals/can/fdcan.yaml + - ./common_patches/fdcan/fdcan_g4.yaml diff --git a/devices/stm32g471.yaml b/devices/stm32g471.yaml index db81b894e..fadab54b3 100644 --- a/devices/stm32g471.yaml +++ b/devices/stm32g471.yaml @@ -23,7 +23,7 @@ _include: - ../peripherals/cordic/cordic_g4.yaml - ./common_patches/sai/sai_v1.yaml - ./common_patches/rtc/rtc_cr.yaml - - ../peripherals/opamp/opamp_g4_common.yaml + - ../peripherals/opamp/opamp_g4_common.yaml - ../peripherals/i2c/i2c_v2.yaml - ../peripherals/gpio/gpio_v2.yaml - ./common_patches/rename_USB_FS_peripheral_to_USB.yaml @@ -31,3 +31,5 @@ _include: - ../peripherals/rcc/rcc_g4.yaml - common_patches/tim/v2/g4.yaml - ../peripherals/tim/v2/ccm.yaml + - ../peripherals/can/fdcan.yaml + - ./common_patches/fdcan/fdcan_g4.yaml diff --git a/devices/stm32g473.yaml b/devices/stm32g473.yaml index d4165f850..28b787623 100644 --- a/devices/stm32g473.yaml +++ b/devices/stm32g473.yaml @@ -20,12 +20,12 @@ _include: - ../peripherals/iwdg/iwdg_with_WINR.yaml - ../peripherals/wwdg/wwdg_v2.yaml - ./common_patches/g4_cordic.yaml - - ../peripherals/cordic/cordic_g4.yaml + - ../peripherals/cordic/cordic_g4.yaml - ./common_patches/sai/sai_v1.yaml - ./common_patches/rtc/rtc_cr.yaml - - ../peripherals/opamp/opamp_g4_common.yaml - - ../peripherals/opamp/opamp_g4_opamp4_5.yaml - - ../peripherals/opamp/opamp_g4_opamp6.yaml + - ../peripherals/opamp/opamp_g4_common.yaml + - ../peripherals/opamp/opamp_g4_opamp4_5.yaml + - ../peripherals/opamp/opamp_g4_opamp6.yaml - ../peripherals/i2c/i2c_v2.yaml - ../peripherals/gpio/gpio_v2.yaml - ./common_patches/rename_USB_FS_peripheral_to_USB.yaml @@ -33,3 +33,5 @@ _include: - ../peripherals/rcc/rcc_g4.yaml - common_patches/tim/v2/g4.yaml - ../peripherals/tim/v2/ccm.yaml + - ../peripherals/can/fdcan.yaml + - ./common_patches/fdcan/fdcan_g4.yaml diff --git a/devices/stm32g474.yaml b/devices/stm32g474.yaml index 259984e29..aebbbf7d2 100644 --- a/devices/stm32g474.yaml +++ b/devices/stm32g474.yaml @@ -11,7 +11,6 @@ VREFBUF: _include: - ./common_patches/g4_rcc.yaml - ./common_patches/g4_exti.yaml - - ./common_patches/fdcan/fdcan_g4.yaml - ../peripherals/exti/exti.yaml - ../peripherals/adc/adc_v3_g4.yaml - ../peripherals/adc/adc_v3_common_g4.yaml @@ -23,9 +22,9 @@ _include: - ../peripherals/cordic/cordic_g4.yaml - ./common_patches/sai/sai_v1.yaml - ./common_patches/rtc/rtc_cr.yaml - - ../peripherals/opamp/opamp_g4_common.yaml - - ../peripherals/opamp/opamp_g4_opamp4_5.yaml - - ../peripherals/opamp/opamp_g4_opamp6.yaml + - ../peripherals/opamp/opamp_g4_common.yaml + - ../peripherals/opamp/opamp_g4_opamp4_5.yaml + - ../peripherals/opamp/opamp_g4_opamp6.yaml - ../peripherals/i2c/i2c_v2.yaml - ../peripherals/gpio/gpio_v2.yaml - ./common_patches/rename_USB_FS_peripheral_to_USB.yaml @@ -33,3 +32,8 @@ _include: - ../peripherals/rcc/rcc_g4.yaml - common_patches/tim/v2/g4.yaml - ../peripherals/tim/v2/ccm.yaml + - ../peripherals/flash/flash_g4.yaml + - ./common_patches/rename_f0_SPI_registers.yaml + - ../peripherals/spi/spi_v2_without_UDR_CHSIDE.yaml + - ../peripherals/can/fdcan.yaml + - ./common_patches/fdcan/fdcan_g4.yaml diff --git a/devices/stm32g483.yaml b/devices/stm32g483.yaml index e6e37ee3e..21c13ca0c 100644 --- a/devices/stm32g483.yaml +++ b/devices/stm32g483.yaml @@ -23,10 +23,10 @@ _include: - ../peripherals/cordic/cordic_g4.yaml - ./common_patches/sai/sai_v1.yaml - ./common_patches/rtc/rtc_cr.yaml - - ../peripherals/cordic/cordic_g4.yaml - - ../peripherals/opamp/opamp_g4_common.yaml - - ../peripherals/opamp/opamp_g4_opamp4_5.yaml - - ../peripherals/opamp/opamp_g4_opamp6.yaml + - ../peripherals/cordic/cordic_g4.yaml + - ../peripherals/opamp/opamp_g4_common.yaml + - ../peripherals/opamp/opamp_g4_opamp4_5.yaml + - ../peripherals/opamp/opamp_g4_opamp6.yaml - ../peripherals/i2c/i2c_v2.yaml - ../peripherals/gpio/gpio_v2.yaml - ./common_patches/rename_USB_FS_peripheral_to_USB.yaml @@ -34,3 +34,5 @@ _include: - ../peripherals/rcc/rcc_g4.yaml - common_patches/tim/v2/g4.yaml - ../peripherals/tim/v2/ccm.yaml + - ../peripherals/can/fdcan.yaml + - ./common_patches/fdcan/fdcan_g4.yaml diff --git a/devices/stm32g484.yaml b/devices/stm32g484.yaml index 4c0284601..44f0f3843 100644 --- a/devices/stm32g484.yaml +++ b/devices/stm32g484.yaml @@ -23,8 +23,8 @@ _include: - ../peripherals/cordic/cordic_g4.yaml - ./common_patches/sai/sai_v1.yaml - ./common_patches/rtc/rtc_cr.yaml - - ../peripherals/opamp/opamp_g4_common.yaml - - ../peripherals/opamp/opamp_g4_opamp4_5.yaml + - ../peripherals/opamp/opamp_g4_common.yaml + - ../peripherals/opamp/opamp_g4_opamp4_5.yaml - ../peripherals/opamp/opamp_g4_opamp6.yaml - ../peripherals/i2c/i2c_v2.yaml - ../peripherals/gpio/gpio_v2.yaml @@ -33,3 +33,5 @@ _include: - ../peripherals/rcc/rcc_g4.yaml - common_patches/tim/v2/g4.yaml - ../peripherals/tim/v2/ccm.yaml + - ../peripherals/can/fdcan.yaml + - ./common_patches/fdcan/fdcan_g4.yaml diff --git a/devices/stm32g491.yaml b/devices/stm32g491.yaml index 3a2ff6ac7..0cea4d912 100644 --- a/devices/stm32g491.yaml +++ b/devices/stm32g491.yaml @@ -33,8 +33,8 @@ _include: - ./common_patches/g4_cordic.yaml - ../peripherals/cordic/cordic_g4.yaml - ./common_patches/rtc/rtc_cr.yaml - - ../peripherals/opamp/opamp_g4_common.yaml - - ../peripherals/opamp/opamp_g4_opamp6.yaml + - ../peripherals/opamp/opamp_g4_common.yaml + - ../peripherals/opamp/opamp_g4_opamp6.yaml - ../peripherals/i2c/i2c_v2.yaml - ../peripherals/gpio/gpio_v2.yaml - ./common_patches/rename_USB_FS_peripheral_to_USB.yaml @@ -42,3 +42,5 @@ _include: - ../peripherals/rcc/rcc_g4.yaml - common_patches/tim/v2/g4.yaml - ../peripherals/tim/v2/ccm.yaml + - ../peripherals/can/fdcan.yaml + - ./common_patches/fdcan/fdcan_g4.yaml diff --git a/peripherals/can/fdcan.yaml b/peripherals/can/fdcan.yaml new file mode 100644 index 000000000..5e4378af0 --- /dev/null +++ b/peripherals/can/fdcan.yaml @@ -0,0 +1,95 @@ +"FDCAN,FDCAN?": + TEST: + RX: + dominant: [0b0, "CAN bus is dominant"] + recessive: [0b1, "Can bus is recessive"] + TX: + can_core: [0b00, "TX controlled by the CAN core, updated at the end of the CAN bit time"] + sample_point: [0b01, "Sample point can be monitored at pin FDCANx_TX"] + dominant: [0b10, "Dominant (0) level at pin FDCANx_TX"] + recessive: [0b11, "Recessive (1) at pin FDCANx_TX"] + + CCCR: + TEST: + normal: [0b0, "Normal operation, register TEST holds reset values"] + test: [0b1, "Test Mode, write access to register TEST enabled"] + DAR: + retransmit: [0b0, "Automatric retransmission of messages not transmitted successfully enabled"] + noretransmit: [0b1, "Automatic retransmission disabled"] + ASM: + normal: [0b0, "Normal CAN operation"] + restricted: [0b1, "Restricted operation Mode active"] + CCE: + readonly: [0b0, "The CPU has no write access to the protected configuration registers"] + readwrite: [0b1, "The CPU has write access to the protected configuration registers (while CCCR.INIT = 1)"] + INIT: + run: [0b0, "Normal operation"] + init: [0b1, "Initialization started"] + + TSCC: + TSS: + zero: [0b00, "Timestamp counter value always 0x000"] + increment_by_tcp: [0b01, "Timestamp counter value incremented according to TCP"] + tim3_cnt: [0b10, "External timestamp counter from TIM3 value (tim3_cnt[0:15])"] + zero_: [0b11, "Same as 00 (zero)"] + + TOCC: + TOS: + continuous: [0b00, "Continuous operation"] + tx_event_fifo: [0b01, "Timeout controlled by Tx event FIFO"] + rx_fifo0: [0b10, "Timeout controlled by Rx FIFO 0"] + rx_fifo1: [0b11, "Timeout controlled by Rx FIFO 1"] + + PSR: + DLEC: + none: [0b000, "No error"] + stuff: [0b001, "Stuff error"] + form: [0b010, "Form error"] + ack: [0b11, "Ack error"] + bit1: [0b100, "Bit1 error"] + bit0: [0b101, "Bit0 error"] + crc: [0b110, "Crc error"] + no_change: [0b111, "No change: any read access to the Protocol status register re-initializes DLEC to '7'. When DLEC shows the value '7', no CAN bus event was detected since the last CPU read"] + ACT: + synchronizing: [0b00, "Node is synchronizing on CAN communication"] + idle: [0b01, "Node is neither receiver nor transmitter"] + receiver: [0b10, "Node is operating as receiver"] + transmitter: [0b11, "Node is operating as transmitter"] + LEC: + none: [0b000, "No error"] + stuff: [0b001, "Stuff error"] + form: [0b010, "Form error"] + ack: [0b11, "Ack error"] + bit1: [0b100, "Bit1 error"] + bit0: [0b101, "Bit0 error"] + crc: [0b110, "Crc error"] + no_change: [0b111, "No change: any read access to the Protocol status register re-initializes LEC to '7'. When LEC shows the value '7', no CAN bus event was detected since the last CPU read"] + + HPMS: + FLST: + standard: [0b0, "Standard filter list"] + extended: [0b1, "Extended filter list"] + MSI: + no_fifo: [0b00, "No FIFO selected"] + fifo_overrun: [0b01, "FIFO overrun"] + store_fifo0: [0b10, "Message stored in FIFO 0"] + store_fifo1: [0b11, "Message stored in FIFO 1"] + + CKDIV: + PDIV: + div1: [0b0000, "APB clock divided by 1"] + div2: [0b0001, "APB clock divided by 2"] + div4: [0b0010, "APB clock divided by 4"] + div6: [0b0011, "APB clock divided by 6"] + div8: [0b0100, "APB clock divided by 8"] + div10: [0b0101, "APB clock divided by 10"] + div12: [0b0110, "APB clock divided by 12"] + div14: [0b0111, "APB clock divided by 14"] + div16: [0b1000, "APB clock divided by 16"] + div18: [0b1001, "APB clock divided by 18"] + div20: [0b1010, "APB clock divided by 20"] + div22: [0b1011, "APB clock divided by 22"] + div24: [0b1100, "APB clock divided by 24"] + div26: [0b1101, "APB clock divided by 26"] + div28: [0b1110, "APB clock divided by 28"] + div30: [0b1111, "APB clock divided by 30"] diff --git a/peripherals/flash/flash_g4.yaml b/peripherals/flash/flash_g4.yaml new file mode 100644 index 000000000..843dda526 --- /dev/null +++ b/peripherals/flash/flash_g4.yaml @@ -0,0 +1,131 @@ +FLASH: + # Device-specific, based on amount of flash available. + # _add: + # PCROP2SR: + # description: Proprietary code readout protection 2 start + # addressOffset: 0x0044 + # access: read-write + # size: 32 + # resetValue: 0xFFFFxxxx + # fields: + # PCROP2_STRT: + # description: PCROP area start offset + # msb: 14 + # lsb: 0 + # PCROP2ER: + # description: Proprietary code readout protection 2 end + # addressOffset: 0x0048 + # access: read-write + # size: 32 + # resetValue: 0x0000xxxx + # fields: + # PCROP2_END: + # description: PCROP area end offset + # msb: 14 + # lsb: 0 + # WRP2AR: + # description: Bank 2 WRP area A address + # addressOffset: 0x004C + # access: read-write + # size: 32 + # resetValue: 0x00xx00xx + # fields: + # WRP2A_END: + # description: WRP first area A end offset + # msb: 22 + # lsb: 16 + # WRP2A_STRT: + # description: WRP first area A start offset + # msb: 6 + # lsb: 0 + # WRP2BR: + # description: Bank 2 WRP area B address + # addressOffset: 0x0050 + # access: read-write + # size: 32 + # resetValue: 0x00xx00xx + # fields: + # WRP2B_END: + # description: WRP first area B end offset + # msb: 22 + # lsb: 16 + # WRP2B_STRT: + # description: WRP first area B start offset + # msb: 6 + # lsb: 0 + # SEC2R: + # description: Flash securable area bank2 + # addressOffset: 0x0074 + # access: read-write + # size: 32 + # resetValue: 0xFFFFFFXX + # fields: + # SEC_SIZE2: + # description: number of pages in secure bank 2 + # msb: 7 + # lsb: 0 + + ACR: + DCRST: + NotReset: [0, "Data cache is not reset"] + Reset: [1, "Data cache is reset"] + ICRST: + NotReset: [0, "Instruction cache is not reset"] + Reset: [1, "Instruction cache is reset"] + DCEN: + Disabled: [0, "Data cache is disabled"] + Enabled: [1, "Data cache is enabled"] + ICEN: + Disabled: [0, "Instruction cache is disabled"] + Enabled: [1, "Instruction cache is enabled"] + PRFTEN: + Disabled: [0, "Prefetch is disabled"] + Enabled: [1, "Prefetch is enabled"] + LATENCY: + Zero: [0, "Zero wait state"] + One: [1, "One wait state"] + Two: [2, "Two wait states"] + Three: [3, "Three wait states"] + Four: [4, "Four wait states"] + Five: [5, "Five wait states"] + Six: [6, "Six wait states"] + Seven: [7, "Seven wait states"] + Eight: [8, "Eight wait states"] + Nine: [9, "Nine wait states"] + Ten: [10, "Ten wait states"] + Eleven: [11, "Eleven wait states"] + Twelve: [12, "Twelve wait states"] + Thirteen: [13, "Thirteen wait states"] + Fourteen: [14, "Fourteen wait states"] + Fifteen: [15, "Fifteen wait states"] + + CR: + _add: + SEC_PROT2: + description: Securable memory area protection bank 2 + bitOffset: 29 + bitWidth: 1 + MER2: + description: Bank 2 mass erase + bitOffset: 15 + bitWidth: 1 + BKER: + description: Bank erase + bitOffset: 11 + bitWidth: 1 + OPTR: + _modify: + SRAM2_RST: + name: CCMSRAM_RST + description: CCM SRAM Erase when system reset + SRAM2_PE: + name: SRAM_PE + _add: + DBANK: + description: Single or dual bank mode + bitOffset: 22 + bitWidth: 1 + BFB2: + description: Dual-bank boot + bitOffset: 20 + bitWidth: 1