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toddstradertoddstrader
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Intermediate variables for system calls during expression coverage
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9 files changed

+539
-4
lines changed

9 files changed

+539
-4
lines changed

‎src/V3Ast.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -901,6 +901,8 @@ class AstNode VL_NOT_FINAL {
901901
// isUnlikely handles $stop or similar statement which means an above IF
902902
// statement is unlikely to be taken
903903
virtual bool isUnlikely() const { return false; }
904+
// Is an IEEE system function (versus internally-generated)
905+
virtual bool isSystemFunc() const { return false; }
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virtual int instrCount() const { return 0; }
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// Iff node is identical to another node
906908
virtual bool isSame(const AstNode* samep) const {

‎src/V3AstNodeExpr.h‎

Lines changed: 53 additions & 0 deletions
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‎src/V3Coverage.cpp‎

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -141,7 +141,7 @@ class CoverageVisitor final : public VNVisitor {
141141
const VNUser2InUse m_inuser2;
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V3UniqueNames m_exprTempNames; // For generating unique temporary variable names used by
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// expression coverage
144-
std::unordered_map<VNRef<AstFuncRef>, AstVar*> m_funcTemps;
144+
std::unordered_map<AstNodeExpr*, AstVar*> m_funcTemps;
145145

146146
// STATE - across all visitors
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int m_nextHandle = 0;
@@ -277,6 +277,7 @@ class CoverageVisitor final : public VNVisitor {
277277
VL_RESTORER(m_modp);
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VL_RESTORER(m_state);
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VL_RESTORER(m_exprTempNames);
280+
VL_RESTORER(m_funcTemps);
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createHandle(nodep);
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m_modp = nodep;
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m_state.m_inModOff
@@ -333,6 +334,7 @@ class CoverageVisitor final : public VNVisitor {
333334
void visit(AstNodeFTask* nodep) override {
334335
VL_RESTORER(m_ftaskp);
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VL_RESTORER(m_exprTempNames);
337+
VL_RESTORER(m_funcTemps);
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m_ftaskp = nodep;
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if (!nodep->dpiImport()) iterateProcedure(nodep);
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}
@@ -784,9 +786,10 @@ class CoverageVisitor final : public VNVisitor {
784786
comment += (first ? "" : " && ") + term.m_emitV
785787
+ "==" + (term.m_objective ? "1" : "0");
786788
AstNodeExpr* covExprp = nullptr;
787-
if (AstFuncRef* const frefp = VN_CAST(term.m_exprp, FuncRef)) {
788-
AstNodeDType* const dtypep = frefp->taskp()->fvarp()->dtypep();
789-
const auto pair = m_funcTemps.emplace(*frefp, nullptr);
789+
if (VN_IS(term.m_exprp, FuncRef) || term.m_exprp->isSystemFunc()) {
790+
AstNodeExpr* const frefp = term.m_exprp;
791+
AstNodeDType* const dtypep = frefp->dtypep();
792+
const auto pair = m_funcTemps.emplace(frefp, nullptr);
790793
AstVar* varp = pair.first->second;
791794
if (pair.second) {
792795
varp = new AstVar{fl, VVarType::MODULETEMP, m_exprTempNames.get(frefp),

‎src/V3EmitV.cpp‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -699,6 +699,10 @@ class EmitVBaseVisitorConst VL_NOT_FINAL : public VNVisitorConst {
699699
emitVerilogFormat(nodep, nodep->emitVerilog(), nodep->lhsp(), nodep->rhsp(),
700700
nodep->thsp());
701701
}
702+
void visit(AstNodeQuadop* nodep) override {
703+
emitVerilogFormat(nodep, nodep->emitVerilog(), nodep->lhsp(), nodep->rhsp(), nodep->thsp(),
704+
nodep->fhsp());
705+
}
702706
void visit(AstMemberSel* nodep) override {
703707
iterateConst(nodep->fromp());
704708
puts(".");

‎test_regress/t/t_cover_sys_line_expr.out‎

Lines changed: 339 additions & 0 deletions
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‎test_regress/t/t_cover_sys_line_expr.py‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
5+
# can redistribute it and/or modify it under the terms of either the GNU
6+
# Lesser General Public License Version 3 or the Perl Artistic License
7+
# Version 2.0.
8+
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
9+
10+
import vltest_bootstrap
11+
12+
test.scenarios("simulator")
13+
14+
test.compile(verilator_flags2=["--cc --coverage-line --coverage-expr"])
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16+
test.execute()
17+
18+
test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage",
19+
"--annotate-points",
20+
"--annotate", test.obj_dir + "/annotated",
21+
test.obj_dir + "/coverage.dat"],
22+
verilator_run=True) # yapf:disable
23+
24+
test.files_identical(test.obj_dir + "/annotated/t_cover_sys_line_expr.v", test.golden_filename)
25+
26+
test.passes()

‎test_regress/t/t_cover_sys_line_expr.v‎

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@@ -0,0 +1,81 @@
1+
// DESCRIPTION: Verilator: Verilog Test module
2+
//
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// This file ONLY is placed under the Creative Commons Public Domain, for
4+
// any use, without warranty, 2024 by Wilson Snyder.
5+
// SPDX-License-Identifier: CC0-1.0
6+
7+
module t (/*AUTOARG*/
8+
// Inputs
9+
clk
10+
);
11+
12+
input clk;
13+
14+
int cyc, bump, result;
15+
logic foo;
16+
initial begin
17+
cyc = 0;
18+
foo = '1;
19+
end
20+
21+
22+
always @(posedge clk) begin
23+
if (($time != 0) && foo) bump <= bump + 1;
24+
if (($realtime != 0) && foo) bump <= bump + 1;
25+
if (($stime != 0) && foo) bump <= bump + 1;
26+
if (($bitstoreal(123) != 0) && foo) bump <= bump + 1;
27+
if (($itor(123) != 0) && foo) bump <= bump + 1;
28+
if (($signed(3) != 0) && foo) bump <= bump + 1;
29+
if (($realtobits(1.23) != 0) && foo) bump <= bump + 1;
30+
if (($rtoi(1.23) != 0) && foo) bump <= bump + 1;
31+
if (($unsigned(-3) != 0) && foo) bump <= bump + 1;
32+
if (($clog2(123) != 0) && foo) bump <= bump + 1;
33+
if (($ln(123) != 0) && foo) bump <= bump + 1;
34+
if (($log10(123) != 0) && foo) bump <= bump + 1;
35+
if (($exp(123) != 0) && foo) bump <= bump + 1;
36+
if (($sqrt(123) != 0) && foo) bump <= bump + 1;
37+
if (($pow(123, 2) != 0) && foo) bump <= bump + 1;
38+
if (($floor(1.23) != 0) && foo) bump <= bump + 1;
39+
if (($ceil(1.23) != 0) && foo) bump <= bump + 1;
40+
if (($sin(123) != 0) && foo) bump <= bump + 1;
41+
if (($cos(123) != 0) && foo) bump <= bump + 1;
42+
if (($tan(123) != 0) && foo) bump <= bump + 1;
43+
if (($asin(123) != 0) && foo) bump <= bump + 1;
44+
if (($acos(123) != 0) && foo) bump <= bump + 1;
45+
if (($atan(123) != 0) && foo) bump <= bump + 1;
46+
if (($atan2(123, 2) != 0) && foo) bump <= bump + 1;
47+
if (($hypot(123, 2) != 0) && foo) bump <= bump + 1;
48+
if (($sinh(123) != 0) && foo) bump <= bump + 1;
49+
if (($cosh(123) != 0) && foo) bump <= bump + 1;
50+
if (($tanh(123) != 0) && foo) bump <= bump + 1;
51+
if (($asinh(123) != 0) && foo) bump <= bump + 1;
52+
if (($acosh(123) != 0) && foo) bump <= bump + 1;
53+
if (($atanh(123) != 0) && foo) bump <= bump + 1;
54+
if (($countbits(123, 2) != 0) && foo) bump <= bump + 1;
55+
if (($onehot(123) != 0) && foo) bump <= bump + 1;
56+
if ($isunknown(foo) && foo) bump <= bump + 1;
57+
if (($countones(123) != 0) && foo) bump <= bump + 1;
58+
if (($onehot0(123) != 0) && foo) bump <= bump + 1;
59+
if (($sampled(foo) != 0) && foo) bump <= bump + 1;
60+
if (($fell(foo) != 0) && foo) bump <= bump + 1;
61+
if (($changed(foo) != 0) && foo) bump <= bump + 1;
62+
if (($rose(foo) != 0) && foo) bump <= bump + 1;
63+
if (($stable(foo) != 0) && foo) bump <= bump + 1;
64+
if (($past(foo) != 0) && foo) bump <= bump + 1;
65+
if (($random != 0) && foo) bump <= bump + 1;
66+
if (($dist_erlang(result, 2, 3) != 0) && foo) bump <= bump + 1;
67+
if (($dist_normal(result, 2, 3) != 0) && foo) bump <= bump + 1;
68+
if (($dist_t(result, 2) != 0) && foo) bump <= bump + 1;
69+
if (($dist_chi_square(result, 2) != 0) && foo) bump <= bump + 1;
70+
if (($dist_exponential(result, 2) != 0) && foo) bump <= bump + 1;
71+
if (($dist_poisson(result, 2) != 0) && foo) bump <= bump + 1;
72+
if (($dist_uniform(result, 2, 3) != 0) && foo) bump <= bump + 1;
73+
if (($sformatf("abc") != "abc") && foo) bump <= bump + 1;
74+
if (foo && foo) bump <= bump + 1;
75+
cyc <= cyc + 1;
76+
if (cyc==9) begin
77+
$write("*-* All Finished *-*\n");
78+
$finish;
79+
end
80+
end
81+
endmodule

‎test_regress/t/t_sys_file_basic_cover_expr.out‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
t_sys_file_basic.out

‎test_regress/t/t_sys_file_basic_cover_expr.py‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
#!/usr/bin/env python3
2+
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
3+
#
4+
# Copyright 2024 by Wilson Snyder. This program is free software; you
5+
# can redistribute it and/or modify it under the terms of either the GNU
6+
# Lesser General Public License Version 3 or the Perl Artistic License
7+
# Version 2.0.
8+
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
9+
10+
import vltest_bootstrap
11+
12+
test.scenarios("simulator")
13+
test.top_filename = "t/t_sys_file_basic.v"
14+
15+
test.unlink_ok(test.obj_dir + "/t_sys_file_basic_test.log")
16+
17+
test.compile(
18+
verilator_flags2=["--coverage-expr"],
19+
# Build without cached objects, see bug363
20+
make_flags=["VM_PARALLEL_BUILDS=0"],
21+
)
22+
23+
test.execute()
24+
test.files_identical(test.obj_dir + "/t_sys_file_basic_test.log", test.golden_filename)
25+
26+
test.passes()

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