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[CH 3_4] Handle return register $lr
1 parent cf68d5b commit ed4d5c6

12 files changed

Lines changed: 443 additions & 130 deletions

‎llvm/lib/Target/Cpu0/Cpu0CallingConv.td‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,19 @@
1313
class CCIfSubtarget<string F, CCAction A>:
1414
CCIf<!strconcat("State.getTarget().getSubtarget<Cpu0Subtarget>().", F), A>;
1515

16+
/* NOTE(fh):
17+
? Why are they inheriting the same base class?
18+
*/
19+
20+
def RetCC_Cpu0EABI : CallingConv<[
21+
// i32 are returned in registers V0, V1, A0, A1
22+
CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>
23+
]>;
24+
25+
def RetCC_Cpu0 : CallingConv<[
26+
CCDelegateTo<RetCC_Cpu0EABI>
27+
]>;
28+
1629
def CSR_O32 : CalleeSavedRegs<(add LR, FP,
1730
(sequence "S%u", 1, 0))>;
1831

‎llvm/lib/Target/Cpu0/Cpu0ISelDAGToDAG.cpp‎

Lines changed: 11 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -53,42 +53,18 @@ bool Cpu0DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
5353
return Ret;
5454
}
5555

56-
/* NOTE(fh):
57-
* In .td:
58-
* def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex],
59-
* [SDNPWantParent]>;
60-
* - Address operands in LD/ST patterns use addr
61-
* - addr expands into two operands (base, offset)
62-
* - The C++ "SelectAddr" must fill thouse outputs
63-
*
64-
* This is for the selection of "DATA DAG node with addr type"
65-
* This choose the addressing operands (operand decomposition)
66-
* The address expression in the DAG can be many shapes:
67-
* add(base, imm), add(reg, reg), Wrapper(GlobalAddress)
68-
* But Cpu0 LD/ST instr would only want operands in the form:
69-
* LD Base, Offset
70-
* llvm need a way to take an arbitrary DAG address expression and decompose it
71-
* into the operands which instruction would expect.
72-
*
73-
* PatFrag vs ComplexPattern
74-
* - PatFrag: helps match the operation node (e.g. aligned store with certain
75-
* contraints)
76-
* -> a named DAG-op matcher (with optional predicate)
77-
* - ComplexPattern: helps match/decompose an operand (addr -> base + offset)
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* -> a named operand matcher/decomposer implemented in C++
79-
*/
8056
//@SelectAddr {
8157
/// ComplexPattern used on Cpu0InstrInfo
8258
/// Used on Cpu0 Load/Store instructions
83-
bool Cpu0DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base,
84-
SDValue &Offset) {
85-
//@SelectAddr }
59+
bool Cpu0DAGToDAGISel::
60+
SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) {
61+
//@SelectAddr }
8662
EVT ValTy = Addr.getValueType();
8763
SDLoc DL(Addr);
8864

8965
// If Parent is an unaligned f32 load or store, select a (base + index)
9066
// floating point load/store instruction (luxc1 or suxc1).
91-
const LSBaseSDNode *LS = 0;
67+
const LSBaseSDNode* LS = 0;
9268

9369
if (Parent && (LS = dyn_cast<LSBaseSDNode>(Parent))) {
9470
EVT VT = LS->getMemoryVT();
@@ -102,26 +78,21 @@ bool Cpu0DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base,
10278

10379
// if Address is FI, get the TargetFrameIndex.
10480
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
105-
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
81+
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
10682
Offset = CurDAG->getTargetConstant(0, DL, ValTy);
10783
return true;
10884
}
10985

110-
Base = Addr;
86+
Base = Addr;
11187
Offset = CurDAG->getTargetConstant(0, DL, ValTy);
11288
return true;
11389
}
11490

115-
/* NOTE(fh):
116-
! This is for the selection of "OP code DAG Node"
117-
* This choose the instruction (opcode-level)
118-
* Called for every node in SelectionDAG (ISD::ADD, Cpu0ISD::Ret)
119-
*/
12091
//@Select {
12192
/// Select instructions not customized! Used for
12293
/// expanded, promoted and normal instructions
12394
void Cpu0DAGToDAGISel::Select(SDNode *Node) {
124-
//@Select }
95+
//@Select }
12596
unsigned Opcode = Node->getOpcode();
12697

12798
// If we have a custom node, we already have selected!
@@ -132,23 +103,15 @@ void Cpu0DAGToDAGISel::Select(SDNode *Node) {
132103
}
133104

134105
// See if subclasses can handle this node.
135-
/* NOTE(fh):
136-
* trySelect is a pure virtual function, and is overridden by the derived
137-
* class that handles target specific cases -> subtarget custom hook
138-
*/
139106
if (trySelect(Node))
140107
return;
141108

142-
switch (Opcode) {
143-
default:
144-
break;
109+
switch(Opcode) {
110+
default: break;
111+
145112
}
146113

147-
/* NOTE(fh):
148-
* SelectCode is the TableGen-generated matcher
149-
* - It tries patterns from .td
150-
* - If none match, it will throw an error
151-
*/
152114
// Select the default instruction
153115
SelectCode(Node);
154116
}
117+

‎llvm/lib/Target/Cpu0/Cpu0ISelDAGToDAG.h‎

Lines changed: 6 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -8,32 +8,12 @@
88
//===----------------------------------------------------------------------===//
99
//
1010
// This file defines an instruction selector for the CPU0 target.
11-
/* NOTE(fh):
12-
* Cpu0ISelLowering vs. Cpu0ISelDAGtoDAG:
13-
* - They are two consecutive stages of the same SelectionDAG
14-
* instruction-selection pipeline:
15-
* - ISelLowering:
16-
* - decide what DAG nodes exist for Cpu0
17-
* - introduces Cpu0-specific nodes like CpuISD::Ret
18-
* - ISelDAGtoDAG:
19-
* - decide how to turn those DAG nodes into Cpu0 machine instructions
20-
* - e.g. Cpu0ISD::Ret -> RET machine opcode
21-
*/
2211
//
2312
//===----------------------------------------------------------------------===//
2413

2514
#ifndef LLVM_LIB_TARGET_CPU0_CPU0ISELDAGTODAG_H
2615
#define LLVM_LIB_TARGET_CPU0_CPU0ISELDAGTODAG_H
2716

28-
/* NOTE(fh):
29-
* This class includes the generic case
30-
* - The standard SelectionDAGISel behavior
31-
* - Shared helpers like SelectAddr
32-
* - a hook "trySelect()" for subtargets
33-
* - * most matching is auto-generated by TabelGen
34-
* - * only write C++ for the werid parts (address modes, special cases)
35-
*/
36-
3717
#include "Cpu0Config.h"
3818

3919
#include "Cpu0.h"
@@ -66,17 +46,14 @@ class Cpu0DAGToDAGISel : public SelectionDAGISel {
6646
bool runOnMachineFunction(MachineFunction &MF) override;
6747

6848
protected:
49+
6950
/// Keep a pointer to the Cpu0Subtarget around so that we can make the right
7051
/// decision when generating code for different targets.
7152
const Cpu0Subtarget *Subtarget;
7253

7354
private:
74-
/* NOTE(fh):
75-
* This file is auto-generated at build time from the patterns in .td
76-
* It contains the huge pattern-matching decision tree used by SelectCode(Node)
77-
*/
78-
// Include the pieces autogenerated from the target description.
79-
#include "Cpu0GenDAGISel.inc"
55+
// Include the pieces autogenerated from the target description.
56+
#include "Cpu0GenDAGISel.inc"
8057

8158
/// getTargetMachine - Return a reference to the TargetMachine, casted
8259
/// to the target-specific type.
@@ -97,8 +74,10 @@ class Cpu0DAGToDAGISel : public SelectionDAGISel {
9774
}
9875

9976
virtual void processFunctionAfterISel(MachineFunction &MF) = 0;
77+
10078
};
10179

102-
} // namespace llvm
80+
}
10381

10482
#endif
83+

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