Home on Awesome resources for Hardware Description

pyVHDLParser

Sat, 28 Dec 2019 00:00:00 +0000

Main Goals Parsing Slice an input document into tokens and text blocks which are categorized in groups for fast indexing. reserve case, whitespace and comments. Recover on parsing errors Good error reporting / throw exceptions Fast Processing Multi-pass parsing and analysis Delay analysis if not needed for current pass Link tokens and blocks for fast-forward scanning (triple helix) Generic VHDL Language Model Assemble a sourcecode document-object-model (Code-DOM) Provide an API for code introspection Provide an API for code modification / transformation Use Cases Generate documentation by using the fast-forward scanner Generate a document/language model by using the grouped text-block scanner Extract compile orders and other dependency graphs Generate highlighted syntax

Mon, 01 Jan 0001 00:00:00 +0000

The Artix®-7 FPGA AC701 Evaluation Kit features the leading system performance per watt Artix-7 family to get you quickly prototyping for your cost sensitive applications. This includes all the basic components of hardware, design tools, IP, and pre-verified reference designs. This also features a targeted reference design enabling high-performance serial connectivity and advanced memory interfacing equipped with a full license for the Northwest Logic DMA engine.

Mon, 01 Jan 0001 00:00:00 +0000

The ML506 platform corresponds to the ML505 platform for all but the FPGA device. Refer to ML505 for pinout information.

Mon, 01 Jan 0001 00:00:00 +0000

The XUPV5 platform corresponds to the ML505 platform for all but the FPGA device. Refer to ML505 for pinout information.

Mon, 01 Jan 0001 00:00:00 +0000

About

Mon, 01 Jan 0001 00:00:00 +0000

Note: This site was uploaded for gathering feedback from the community. We encourage users/contributors/collegues to open issues for bringing up the matters for discussion before contributing modifications. Disclaimer: All third party trademarks (including logos and icons) and images referenced by hdl/awesome remain the property of their respective owners. Unless specifically identified as such, hdl/awesome’s use of third party trademarks and/or images does not indicate any relationship, sponsorship, or endorsement between the hdl organisation and the owners of these trademarks.

Adafruit Feather Board Specification

Mon, 01 Jan 0001 00:00:00 +0000

The Adafruit Feather are a line of development boards from Adafruit that are standalone and stackable. Typically powered by lipo batteries or through USB, feathers are flexible, portable and light. Daughter boards or peripheral boards for feathers are named wings. Apart from Adafruit’s feather and wing ecosystem, there are several open source FPGA development boards which are designed with the same form factor and pin specification. See, for instance, OrangeCrab, QuickFeather or iCE40-feather.

Amaranth HDL (previously known as nMigen)

Mon, 01 Jan 0001 00:00:00 +0000

“The Amaranth project provides an open-source toolchain for developing hardware based on synchronous digital logic using the Python programming language, as well as evaluation board definitions, a System on Chip toolkit, and more. It aims to be easy to learn and use, reduce or eliminate common coding mistakes, and simplify the design of complex hardware with reusable components. The Amaranth toolchain consists of the Amaranth hardware definition language, the standard library, the simulator, and the build system, covering all steps of a typical FPGA development workflow.

Arachne-pnr

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

ARMmbed DAPLink

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Axion-HDL

Mon, 01 Jan 0001 00:00:00 +0000

Axion-HDL generates AXI4-Lite register interfaces from inline HDL annotations or standalone data files (YAML, TOML, XML, JSON). Registers are described directly inside VHDL or SystemVerilog source files using @axion comments, removing the need for a separate register description language. Axion-HDL can: Read register definitions from inline @axion comments in VHDL or SystemVerilog source files Read standalone register map files in YAML, TOML, XML, or JSON format Generate synthesizable VHDL and SystemVerilog AXI4-Lite register block modules Generate C headers with access macros for software integration Generate HTML register map documentation Export register maps back to YAML, TOML, XML, or JSON Insert built-in clock domain crossing (CDC) synchronizers, configurable per module Pack multiple fields into a single address (subregisters) and auto-split wide signals across addresses

Boolector

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Calyx

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Cascade

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

CHIPS (Common Hardware for Interfaces, Processors and Systems) Alliance

Mon, 01 Jan 0001 00:00:00 +0000

“The CHIPS Alliance develops high-quality, open source hardware designs relevant to silicon devices and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks. CHIPS Alliance is open to all organizations who are interested in collaborating on open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.”

CHIPS Alliance Workshops and Meetings

Mon, 01 Jan 0001 00:00:00 +0000

Chisel/FIRRTL Hardware Compiler Framework

Mon, 01 Jan 0001 00:00:00 +0000

“Chisel adds hardware construction primitives to the Scala programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog. This generator methodology enables the creation of re-usable components and libraries, such as the FIFO queue and arbiters in the Chisel Standard Library, raising the level of abstraction in design while retaining fine-grained control." Currently, Chisel (Constructing Hardware in a Scala Embedded Language) is in its version 3 (first commit in 2015).

Circt

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

CircuitGraph

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Clash

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Cooperating Validity Checker (CVC)

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Coriolis

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Coroutine Co-simulation Test Bench (cocotb)

Mon, 01 Jan 0001 00:00:00 +0000

“cocotb is a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python."

Device Firmware Upgrade Utilities (dfu-util)

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Digilent PMOD Interface Specification

Mon, 01 Jan 0001 00:00:00 +0000

PMOD is an interface specification for low frequency and low I/O pin count peripherals, based on standard 100 mil spaced, 25 mil square, pin-header style connectors. Connectors can have one or two rows, each of them with 6 pins, 2 of which correspond to Vcc and GND. Additionally, the Digilent Pmod Standard lays out guidelines for form factor and communication protocols.

Version 1.0.0 of the specification defined 2x4 connectors too, for I2C interfaces. However, those were removed in later versions. The latest version is Digilent Pmod™ Interface Specification v1.3.0.

ecpprog

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

eda-twiki

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

edalize

Mon, 01 Jan 0001 00:00:00 +0000

“Edalize is a Python Library for interacting with EDA tools. It can create project files for supported tools and run them in batch or GUI mode (where supported)." “All EDA tools such as Icarus, Yosys, ModelSim, Vivado, Verilator, GHDL, Quartus etc get input HDL files (Verilog and VHDL) and some tool-specific files (constraint files, memory initialization files, IP description files etc). Together with the files, perhaps a couple of Verilog defines, some top-level parameters/generics or some tool-specific options are set.

Electronic Design Automation Abstraction (EDA²)

Mon, 01 Jan 0001 00:00:00 +0000

“Electronic Design Automation Abstraction (EDA²) is a conceptual model for characterising the abstraction layers in Electronic Design Automation (EDA) projects based on Hardware Description Languages (HDLs). Its goal is the interoperability of diverse tools and languages, through documented interfaces.

EDA² aims to provide reference Python implementations and schemas of commonly needed software layers for (open source) EDA tooling/frameworks to reduce code duplication and reinventions of existing algorithms and data structures. Each layer solves the problems at a different abstraction level, hence, they are organised as an stack."

Embench

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

EPFL Logic Synthesis Libraries

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

F4PGA

Mon, 01 Jan 0001 00:00:00 +0000

“F4PGA is a fully open source toolchain for the development of FPGAs of multiple vendors. Currently, it targets the Xilinx 7-Series, Lattice iCE40, Lattice ECP5 FPGAs, QuickLogic EOS S3 and is gradually being expanded to provide a comprehensive end-to-end FPGA synthesis flow.”

FASM

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

FPGACPU.CA

Mon, 01 Jan 0001 00:00:00 +0000

“Charles Eric LaForest, PhD operates fpgacpu.ca as a resource about FPGAs, computer history, and computer architecture."

fphdl

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

fritzing

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

fujprog

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

fusesoc

Mon, 01 Jan 0001 00:00:00 +0000

FuseSoC is a package manager and a set of build tools for HDL code. Its main purpose is to increase reuse of IP cores and be an aid for creating, building and simulating SoC solutions. FuseSoC provides utilities for: reusing existing cores creating compile-time or run-time configurations running regression tests against multiple simulators porting designs to new targets leting other projects use your code References: fusesoc-cores: FuseSoC standard core library tiny-cores: Collection of assorted small cores edalize was part of FuseSoC FuseSoc is the continuation of ORPSoC

GDS3D

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

gdsfactory

Mon, 01 Jan 0001 00:00:00 +0000

“gdsfactory is a python library to design chips (Photonics, Analog, Quantum, MEMs, …), objects for 3D printing or PCBs. You can describe your hardware in code (python or YAML), verify it (DRC, simulation, extraction) and validate it (to make sure it meets your specifications after fabrication).."

GHDL

Mon, 01 Jan 0001 00:00:00 +0000

Open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL). GHDL is not an interpreter: it allows you to analyse and elaborate sources to generate machine code from your design. Native program execution is the only way for high speed simulation. Full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the latest 2008 revision. Partial support of PSL. Can write waveforms to a GHW, VCD or FST file.

ghdl-yosys-plugin

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Graphviz

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

GTKWave

Mon, 01 Jan 0001 00:00:00 +0000

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

HDL Checker

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

hdlConvertor

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

HDLmake

Mon, 01 Jan 0001 00:00:00 +0000

“A tool designed to help FPGA designers to manage and share their HDL code by automatically finding file dependencies, writing synthesis & simulation Makefiles, and fetching IP-Core libraries from remote repositories Synthesis Makefile generation Simulation Makefile generation HDL parser and dependency solver GIT/SVN Support Multiple HDL Languages Multiple Tools Multiple Operating Systems”

Hierarchical Asynchronous Circuit Kompiler Toolkit (HACKT)

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Highly Agile Masks Made Effortlessly from RTL (HAMMER)

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

HWToolkit (hwt)

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Icarus Verilog (iverilog)

Mon, 01 Jan 0001 00:00:00 +0000

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the vvp command. For synthesis, the compiler generates netlists in the desired format.

icesprog

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

icestorm

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

IRSIM

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

JSON-for-VHDL

Mon, 01 Jan 0001 00:00:00 +0000

JSON-for-VHDL is a library to parse and query JSON data structures in VHDL. The complete functionality is included in a single synthesizable VHDL package, without special dependencies. It allows reading JSON from files and/or from (optionally encoded) stringified JSON generics. It is included in VUnit, for passing generics for arbitrary complexity from Python to the testbeches.

Kactus2

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

KiCad

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

KLayout

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

LATTE: Languages, Tools, and Techniques for Accelerator Design

Mon, 01 Jan 0001 00:00:00 +0000

"LATTE is an ASPLOS workshop on applying programming languages and compilers techniques to generate hardware accelerators." There is a GitHub repository with discussion threads for each paper.

legoHDL

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

LibreCores

Mon, 01 Jan 0001 00:00:00 +0000

" Digital devices are the basic building blocks of electronic systems. Such devices are for application-specific devices like a USB controller. But also programmable System-on-Chip are found in embedded systems. Both tastes of a chip are composed of basic building blocks, so called IP (Intellectual Property) cores. A “LibreCore” is such an IP core that is created and distributed in the open source spirit. And LibreCores.org is like a good neighborhood pub, a place to meet the community and —most importantly— find such cores.

LibreCores CI

Mon, 01 Jan 0001 00:00:00 +0000

“LibreCores CI is a service, which provides Continuous Integration of projects being hosted on LibreCores. The objective of the service is to improve the contributor experience and to increase trust to projects by providing automated testing and health metrics of the projects.”

LiteX

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

LiveHD

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Low Level Hardware Description (LLHD)

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Magic

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

migen

Mon, 01 Jan 0001 00:00:00 +0000

“Despite being faster than schematics entry, hardware design with Verilog and VHDL remains tedious and inefficient for several reasons. The event-driven model introduces issues and manual coding that are unnecessary for synchronous circuits […]. To address those issues, we have developed the Migen FHDL, a library that replaces the event-driven paradigm with the notions of combinatorial and synchronous statements, has arithmetic rules that make integers always behave like mathematical integers, and most importantly allows the design’s logic to be constructed by a Python program.

mistral

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

MyHDL

Mon, 01 Jan 0001 00:00:00 +0000

“MyHDL turns Python into a hardware description and verification language, providing hardware engineers with the power of the Python ecosystem."

Netgen

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

netlistsvg

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

nextpnr

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

ngspice

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

nMigen

Mon, 01 Jan 0001 00:00:00 +0000

See Amaranth HDL. There is/was a dispute between M-Labs and whitequark about the ownership of the brand nMigen. Most of the codebase of nMigen was written by whitequark and the upstream was nmigen/nmigen. However, there is a fork in m-labs/nmigen and M-Labs claims the brand as being based on Migen (see nmigen.org).

NVC

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Opal Kelly SYZYGY Interface Specification

Mon, 01 Jan 0001 00:00:00 +0000

SYZYGY is a free to license interface specification for low cost, compact and high-performance connectors that economize the pin count available in FPGAs. See section Interface comparison in syzygyfpga.io for a reference of where does SYZYGY fit, between PMOD and FMC. There are few development boards (carriers) and peripherals with SYZYGY connectors yet. An open source carrier design is ButterStick. However, there are PCB templates for KiCAD and Altium available for anyone to use (see SYZYGYfpga/pcb-templates).

Open Source Design Automation (OSDA)

Mon, 01 Jan 0001 00:00:00 +0000

“This one-day workshop aims to bring together industrial, academic, and hobbyist actors to explore, disseminate, and network over ongoing efforts for open design automation, with a view to enabling unfettered research and development, improving EDA quality, and lowering the barriers and risks to entry for industry. These aims are particularly poignant due to the recent efforts across the European Union (and beyond) that mandate ‘open access’ for publicly funded research to both published manuscripts as well as any code necessary for reproducing its conclusions."

Open Source VHDL Verification Methodology (OSVVM)

Mon, 01 Jan 0001 00:00:00 +0000

“OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your FPGA or ASIC verification project from start to finish. Using these libraries you can create a simple, readable, and powerful testbench that is suitable for either a simple FPGA block or a complex ASIC."

OpenCores

Mon, 01 Jan 0001 00:00:00 +0000

“OpenCores is the most prominent online community for the development of gateware IP (Intellectual Properties) Cores. It is the place where such cores are shared and promoted in the spirit of Free and Open Source collaboration." “The OpenCores portal hosts the source code for different digital gateware projects and supports the users’ community providing a platform for listing, presenting, and managing such projects; together with version control systems for sources management.

openFPGALoader

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

OpenOCD

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

OpenROAD

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

OpenSTA

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

ORConf

Mon, 01 Jan 0001 00:00:00 +0000

“ORConf is an annual conference for open source digital, semiconductor and embedded systems designers and users. Each year attendees are treated to an ever-impressive array of presentations from all corners of the open source hardware space."

Parallel Programming for FPGAs

Mon, 01 Jan 0001 00:00:00 +0000

“Parallel Programming for FPGAs is an open-source book aimed at teaching hardware and software developers how to efficiently program FPGAs using high-level synthesis (HLS). The authors developed the book as we noticed a lack of material aimed at teaching people to effectively use HLS tools."

PCBFlow

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

PeakRDL

Mon, 01 Jan 0001 00:00:00 +0000

PeakRDL is a free and open-source control & status register (CSR) automation toolchain. This project provides a command-line tool that unifies many aspects of register automation centered around the SystemRDL register description language. This tool can: Process SystemRDL 2.0 register descriptions. Import & export IP-XACT XML. Generate synthesizable SystemVerilog RTL register blocks using APB, AXI4-Lite, Avalon, and other interfaces. Create rich and dynamic HTML documentation. Build a UVM register model abstraction layer.

Pile of Cores Library (PoC)

Mon, 01 Jan 0001 00:00:00 +0000

PoC - “Pile of Cores” provides implementations for often required hardware functions such as Arithmetic Units, Caches, Clock-Domain-Crossing Circuits, FIFOs, RAM wrappers, and I/O Controllers. The hardware modules are typically provided as VHDL or Verilog source code, so it can be easily re-used in a variety of hardware designs. All hardware modules use a common set of VHDL packages to share new VHDL types, sub-programs and constants. Additionally, a set of simulation helper packages eases the writing of testbenches.

Pinout

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

PipelineC

Mon, 01 Jan 0001 00:00:00 +0000

“Fundamental design elements are state machines/stateful elements(registers, rams, etc), auto-pipelined stateless pure functions, and interconnects (wires, cdc, async fifos, etc). By isolating complex logic into autopipelineable functions, and only writing literal clock by clock hardware description when absolutely necessary, PipelineC designs do not need to be rewritten for each new target device / operating frequency. The hope is to build shared, high performance, device agnostic, hardware designs described in a familiar and powerfully composable C language look.

Pono

Mon, 01 Jan 0001 00:00:00 +0000

“Pono is a performant, adaptable, and extensible SMT-based model checker implemented in C++. It was developed as the next generation of CoSA and thus was originally named cosa2."

Princeton Reconfigurable Gate Array (PRGA)

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Project Apicula

Mon, 01 Jan 0001 00:00:00 +0000

Project Apicula uses a combination of fuzzing and parsing of the vendor data files to find the meaning of all the bits in the bitstream.

Project Bureau

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Project Oxide

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Project Trellis

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Project U-Ray

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Project X-Ray

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

pyFPGA

Mon, 01 Jan 0001 00:00:00 +0000

PyFPGA is a Python Class for vendor-independent FPGA development. It allows using a single project file and programmatically executing synthesis, implementation, generation of bitstream and/or transference to supported boards. The workflow is command-line centric. It’s friendly with Version Control Systems and Continuous Integration (CI). Allows reproducibility and repeatability. Consumes fewer system resources than GUI based workflows. Also, some command-line helpers are provided, for quick tests or small projects.

PyHDI

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

pyIPCMI

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

pyVHDLModel

Mon, 01 Jan 0001 00:00:00 +0000

Main Goals This Python package provides a unified abstract language model for VHDL. Projects reading from source files can derive own classes and implement additional logic to create a concrete language model for their tools. Projects consuming pre-processed VHDL data (parsed, analyzed or elaborated) can build higher level features and services on such a model, while supporting multiple frontends. Use Cases High-level API for GHDL’s libghdl offered as Python package pyGHDL.

PyXHDL - Python Frontend For VHDL And Verilog

Mon, 01 Jan 0001 00:00:00 +0000

PyXHDL allows to write HDL code in Python, generating VHDL (>= 2008) and Verilog (SystemVerilog >= 2012) code to be used for synthesis and simulation. PyXHDL does not try to create an IR to be lowered, but instead interprets Python AST code and maps that directly into the selected HDL backend code. The optimizations are left to the OEM HDL compiler used to syntesize the design. The main advantage of PyXHDL is that you can write functions and modules/entities wihtout explicit parametrization.

RapidWright

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

renode

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

RgGen

Mon, 01 Jan 0001 00:00:00 +0000

RgGen is a code generator tool to generate source files for configuration and status registers (CSR) from human readable register map specifications. RgGen has following features: Generate following source files for CSR automatically from register map specifications SystemVerilog/Verilog RTL Veryl RTL VHDL RTL UVM register model (RAL) Markdown documents C header file Register map specifications can be written in following format YAML JSON TOML Spreadsheet (xlsx/xls/ods/csv/tsv) SiFive DUH Ruby SystemRDL Now planning Support standard bus protocols AMBA APB AMBA AXI4-Lite Wishbone Plugin feature Add your own bit field types Add your own bus protocol

rust_hdl

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

scopehal

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Serial-Studio

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

sigrok-cli

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Silice

Mon, 01 Jan 0001 00:00:00 +0000

“Silice makes it possible to write algorithms for FPGAs in the same way we write them for processors: defining sequences of operations, subroutines that can be called, and using control flow statements such as while and break. At the same time, Silice lets you fully exploit the parallelism and niceties of FPGA architectures, describing operations and algorithms that run in parallel and are always active, as well as pipelines. Silice remains close to the hardware: nothing gets obfuscated away.

SiliconCompiler

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

SKiDL

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

SLAC Ultimate RTL Framework (SURF)

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

SpinalHDL

Mon, 01 Jan 0001 00:00:00 +0000

“SpinalHDL is an open source high-level hardware description language. It can be used as an alternative to VHDL or Verilog and has several advantages over them."

SpyDrNet

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Super Prove

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Surelog

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

SVUnit

Mon, 01 Jan 0001 00:00:00 +0000

“SVUnit is an open-source test framework for ASIC and FPGA developers writing Verilog/SystemVerilog code. SVUnit is automated, fast, lightweight and easy to use making it the only SystemVerilog test framework in existence suited to both design and verification engineers that aspire to high quality code and low bug rates."

SymbiFlow

Mon, 01 Jan 0001 00:00:00 +0000

“SymbiFlow is now F4PGA!” See F4PGA.

SymbiYosys (sby)

Mon, 01 Jan 0001 00:00:00 +0000

“SymbiYosis a front-end driver program for Yosys-based formal hardware verification flows. SymbiYosys provides flows for the following formal tasks: Bounded verification of safety properties (assertions), Unbounded verification of safety properties, Generation of test benches from cover statements, Verification of liveness properties”

Synthesijer

Mon, 01 Jan 0001 00:00:00 +0000

Synthesijer is a high-level synthesis tool, which generates VHDL and Verilog HDL code from Java code. Synthesijer also provides a backend to generate VHDL/Verilog HDL, which helps to develop high-level synthesis tools and DSLs. For example, prepare the following Java program, /* Test.java */ public class Test{ public boolean flag; private int count = 0; public void run(){ while(true){ count++; if(count == 5000000){ count = 0; flag = !flag; } } } } and compile it with Synthesijer.

SystemRDL Compiler

Mon, 01 Jan 0001 00:00:00 +0000

SystemRDL is a domain specific language used to describe control/status registers (CSR) that define a hardware/software boundary for hardware peripherals. By describing the structure of a CSR in SystemRDL, one can create a single source of truth specification for CSR automation and code generation. The systemrdl-compiler project implements a generic compiler front-end for Accellera’s SystemRDL 2.0 register description language. The goal of this project is to provide a free and open compiler that lowers the barrier to entry to using an industry standard register description language.

Tim’s Open FPGA Expansion (TOFE)

Mon, 01 Jan 0001 00:00:00 +0000

“The TOFE interface dramatically reduces the cost of high-speed I/O functionality by taking inspiration from the PCI-Express standard and re-purposing its connectors and mechanical specifications."

Torc

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

tsfpga

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Universal Hardware Data Model (UHDM)

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Universal VHDL Verification Methodology (UVVM)

Mon, 01 Jan 0001 00:00:00 +0000

“Open Source VHDL Verification Library and Methodology - for very efficient VHDL verification of FPGA and ASIC - resulting also in a significant quality improvement”

VASG Packages

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Verible

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

verilator

Mon, 01 Jan 0001 00:00:00 +0000

Verilator is “the fastest free Verilog HDL simulator”. From a verification perspective it supports line coverage, signal toggle coverage and limited specification of functional coverage using SystemVerilog Assertions. It also allows one to write testbenches in C++ or SystemC.

Verilog to Routing (VTR)

Mon, 01 Jan 0001 00:00:00 +0000

“The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture." It performs: Elaboration & Synthesis (ODIN II) Logic Optimization & Technology Mapping (ABC) Packing, Placement, Routing & Timing Analysis (VPR) “to generate FPGA speed and area results.

Versatile Place and Route (VPR)

Mon, 01 Jan 0001 00:00:00 +0000

“VPR (Versatile Place and Route) is an open source academic CAD tool designed for the exploration of new FPGA architectures and CAD algorithms, at the packing, placement and routing phases of the CAD flow […]. Since its public introduction, VPR has been used extensively in many academic projects partly because it is robust, well documented, easy-to-use, and can flexibly target a range of architectures." “VPR takes, as input, a description of an FPGA architecture along with a technology-mapped user circuit.

VHDL-extras

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

VUnit

Mon, 01 Jan 0001 00:00:00 +0000

“VUnit is an open source unit testing framework for VHDL/SystemVerilog […] It features the functionality needed to realize continuous and automated testing of your HDL code. VUnit doesn’t replace but rather complements traditional testing methodologies by supporting a “test early and often” approach through automation."

wavedrom

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Xeda

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

XLS

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

XSCHEM

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Xyce

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Yices 2

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Yosys Open SYnthesis Suite (Yosys)

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…

Z3

Mon, 01 Jan 0001 00:00:00 +0000

This is a long description…