Thanks to visit codestin.com
Credit goes to llvm.org

LLVM 22.0.0git
AMDGPUMCTargetDesc.h
Go to the documentation of this file.
1//===-- AMDGPUMCTargetDesc.h - AMDGPU Target Descriptions -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Provides AMDGPU specific target descriptions.
11//
12//===----------------------------------------------------------------------===//
13//
14
15#ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H
16#define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H
17
19#include <cstdint>
20#include <memory>
21
22namespace llvm {
23class Target;
24class MCAsmBackend;
25class MCCodeEmitter;
26class MCContext;
27class MCInstrInfo;
29class MCRegisterInfo;
30class MCSubtargetInfo;
31class MCTargetOptions;
32
33enum AMDGPUDwarfFlavour : unsigned { Wave64 = 0, Wave32 = 1 };
34
35MCRegisterInfo *createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour);
36
37MCCodeEmitter *createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII,
38 MCContext &Ctx);
39
40MCAsmBackend *createAMDGPUAsmBackend(const Target &T,
41 const MCSubtargetInfo &STI,
42 const MCRegisterInfo &MRI,
43 const MCTargetOptions &Options);
44
45std::unique_ptr<MCObjectTargetWriter>
46createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI,
47 bool HasRelocationAddend);
48
49namespace AMDGPU {
51private:
52 unsigned VgprMSBs = 0;
53
54public:
57
58 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
59 uint64_t &Target) const override;
60
61 void resetState() override { VgprMSBs = 0; }
62
63 void updateState(const MCInst &Inst, uint64_t Addr) override;
64
65 unsigned getVgprMSBs() const { return VgprMSBs; }
66};
67
68} // namespace AMDGPU
69
70} // namespace llvm
71
72#define GET_REGINFO_ENUM
73#include "AMDGPUGenRegisterInfo.inc"
74
75#define GET_INSTRINFO_ENUM
76#define GET_INSTRINFO_MC_HELPER_DECLS
77#include "AMDGPUGenInstrInfo.inc"
78
79#define GET_SUBTARGETINFO_ENUM
80#include "AMDGPUGenSubtargetInfo.inc"
81
82#endif
unsigned const MachineRegisterInfo * MRI
static LVOptions Options
Definition LVOptions.cpp:25
#define T
void resetState() override
Clear the internal state. See updateState for more information.
bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const override
Given a branch instruction try to get the address the branch targets.
void updateState(const MCInst &Inst, uint64_t Addr) override
Update internal state with Inst at Addr.
AMDGPUMCInstrAnalysis(const MCInstrInfo *Info)
Generic interface to target specific assembler backends.
MCCodeEmitter - Generic instruction encoding interface.
Context object for machine code objects.
Definition MCContext.h:83
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
const MCInstrInfo * Info
MCInstrAnalysis(const MCInstrInfo *Info)
Interface to description of machine instruction set.
Definition MCInstrInfo.h:27
Base class for classes that define behaviour that is specific to both the target and the object forma...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
This is an optimization pass for GlobalISel generic memory operations.
MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend)
MCRegisterInfo * createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour)
MCCodeEmitter * createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)