概述
数据手册AD7948BRS-REEL 概述
最高分辨率:12;元器件封装:20-SSOP; DA转换器
AD7948BRS-REEL 数据手册
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PDF下载+3.3 V/+5 V Multiplying
12-Bit DACs
a
AD7943/AD7945/AD7948
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
12-Bit Multiplying DACs
V
R
FB
DD
Guaranteed Specifications with +3.3 V/+5 V Supply
0.5 LSBs INL and DNL
Low Power: 5 W typ
AD7943
I
I
OUT1
12-BIT DAC
V
REF
OUT2
Fast Interface
CLR
LD1
LD2
AGND
SRO
40 ns Strobe Pulsewidth (AD7943)
40 ns Write Pulsewidth (AD7945, AD7948)
Low Glitch: 60 nV-s with Amplifier Connected
Fast Settling: 600 ns to 0.01% with AD843
DAC REGISTER
INPUT SHIFT REGISTER
SRI
APPLICATIONS
Battery-Powered Instrumentation
Laptop Computers
Upgrades for All 754x Series DACs (5 V Designs)
STB1 STB2
STB4 DGND
STB3
V
R
DD
FB
GENERAL DESCRIPTION
AD7945
I
OUT1
The AD7943, AD7945 and AD7948 are fast 12-bit multiplying
DACs that operate from a single +5 V supply (Normal Mode)
and a single +3.3 V to +5 V supply (Biased Mode). The
AD7943 has a serial interface, the AD7945 has a 12-bit parallel
interface, and the AD7948 has an 8-bit byte interface. They will
replace the industry-standard AD7543, AD7545 and AD7548
in many applications, and they offer superior speed and power
consumption performance.
12-BIT DAC
12
V
REF
AGND
CS
WR
INPUT LATCH
12
DB11–DB0
DGND
R
V
FB
DD
The AD7943 is available in 16-lead DIP, 16-lead SOP (Small
Outline Package) and 20-lead SSOP (Shrink Small Outline
Package).
I
OUT1
V
12-BIT DAC
12
REF
AGND
AD7948
The AD7945 is available in 20-lead DIP, 20-lead SOP and 20-
lead SSOP.
DF/DOR
DATA OVERRIDE LOGIC
12
CTRL
The AD7948 is available in 20-lead DIP, 20-lead SOP and 20-
lead SSOP.
DAC REGISTER
LDAC
WR
12
CONTROL
LOGIC
INPUT REGISTERS
CSLSB
CSMSB
12
DATA STEERING LOGIC
8
DB7–DB0
DGND
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1998
AD7943/AD7945/AD7948–SPECIFICATIONS1
(AD7943: VDD = +4.5 V to +5.5 V; VIOUT1 = VIOUT2 = AGND = 0 V; VREF = +10 V; TA = TMIN to TMAX, unless otherwise noted.
AD7945, AD7948: VDD = +4.5 V to +5.5 V; VIOUT1 = AGND = 0 V; VREF = +10 V; TA = TMIN to TMAX, unless otherwise noted.)
NORMAL MODE
Parameter
B Grades2 T Grade2, 3 Units
Test Conditions/Comments
ACCURACY
Resolution
12
12
Bits
1 LSB = VREF/212 = 2.44 mV when VREF = 10 V
Relative Accuracy
Differential Nonlinearity
±0.5
±0.5
±0.5
±0.5
LSB max
LSB max
All Grades Guaranteed Monotonic over
Temperature
Gain Error
T
MIN to TMAX
±2
2
5
±2
2
5
LSB max
ppm FSR/°C typ
ppm FSR/°C max
Gain Temperature Coefficient4
Output Leakage Current
IOUT1
@ +25°C
TMIN to TMAX
10
100
10
100
nA max
nA max
See Terminology Section
Typically 20 nA over Temperature
REFERENCE INPUT
Input Resistance
6
12
6
12
kΩ min
kΩ max
Typical Input Resistance = 9 kΩ
DIGITAL INPUTS
V
V
INH, Input High Voltage
INL, Input Low Voltage
2.4
0.8
±1
10
2.4
0.8
±1
10
V min
V max
µA max
pF max
IINH, Input Current
CIN, Input Capacitance4
DIGITAL OUTPUT (AD7943 SRO)
For 1 CMOS Load
Output Low Voltage (VOL
Output High Voltage (VOH
)
0.2
VDD – 0.2
0.2
VDD – 0.2
V max
V min
)
POWER REQUIREMENTS
V
DD Range
4.5/5.5
4.5/5.5
V min/V max
Power Supply Sensitivity4
∆Gain/∆VDD
DD (AD7943)
–75
5
–75
5
dB typ
µA max
I
VINH = VDD – 0.1 V min, VINL = 0.1 V max.
SRO Open Circuit. No STB Signal. Typically
1 µA. Typically 100 µA with a 1 MHz STB
Frequency. At Input Levels of 0.8 V and 2.4 V,
IDD Is Typically 2.5 mA.
IDD (AD7945, AD7948)
5
5
µA max
VINH = VDD – 0.1 V min, VINL = 0.1 V max.
Typically 1 µA. At Input Levels of 0.8 V and
2.4 V, IDD Is Typically 2.5 mA.
NOTES
1The AD7943, AD7945 and AD7948 are specified in the normal current mode configuration and in the biased current mode for single-supply applications.
Figures 14 and 15 are examples of normal mode operation.
2Temperature ranges as follows: B Grades: –40°C to +85°C; T Grade: –55°C to +125°C.
3The T Grade applies to the AD7945 only.
4Guaranteed by design.
Specifications subject to change without notice.
–2–
REV. B
AD7943/AD7945/AD7948
SPECIFICATIONS1
(AD7943: VDD = +3 V to +5.5 V; VIOUT1 = VIOUT2 = AGND = 1.23 V; VREF = +0 V to 2.45 V; TA = TMIN to TMAX, unless other-
wise noted. AD7945, AD7948: VDD = +3 V to +5.5 V; VIOUT1 = AGND = 1.23 V; VREF = +0 V to 2.45 V; TA = TMIN to TMAX, unless otherwise noted.)
BIASED MODE
Parameter
A Grades2 Units
Test Conditions/Comments
ACCURACY
Resolution
12
Bits
1 LSB = (VIOUT1 – VREF)/212 = 300 µV When
VIOUT1 = 1.23 V and VREF = 0 V
Relative Accuracy
Differential Nonlinearity
±1
±0.9
LSB max
LSB max
All Grades Guaranteed Monotonic
over Temperature
Gain Error @ +25°C
TMIN to TMAX
±3
±4
2
LSB max
LSB max
ppm FSR/°C typ
ppm FSR/°C max
Gain Temperature Coefficient3
5
Output Leakage Current
IOUT1
@ +25°C
TMIN to TMAX
Input Resistance
See Terminology Section
10
100
nA max
nA max
Typically 20 nA over Temperature
This Varies with DAC Input Code
@ IOUT2 Pin (AD7943)
@ AGND Pin (AD7945, AD7948)
6
6
kΩ min
kΩ min
DIGITAL INPUTS
V
INH, Input High Voltage @ VDD = +5 V
2.4
V min
V min
V max
V max
µA max
pF max
VINH, Input High Voltage @ VDD = +3.3 V 2.1
VINL, Input Low Voltage @ VDD = +5 V
VINL, Input Low Voltage @ VDD = +3.3 V
IINH, Input Current
0.8
0.6
±1
10
CIN, Input Capacitance3
DIGITAL OUTPUT (SRO)
For 1 CMOS Load
Output Low Voltage (VOL
)
0.2
V max
Output High Voltage (VOH
)
VDD – 0.2 V min
POWER REQUIREMENTS
VDD Range
3.0/5.5
V min/V max
Power Supply Sensitivity3
∆Gain/∆VDD
–75
5
dB typ
µA max
IDD (AD7943)
VINH = VDD – 0.1 V min, VINL = 0.1 V max.
SRO Open Circuit; No STB Signal; Typically
1 µA. Typically 100 µA with 1 MHz STB
Frequency.
VINH = VDD – 0.1 V min, VINL = 0.1 V max.
Typically 1 µA.
IDD (AD7945, AD7948)
5
µA max
NOTES
1These specifications apply with the devices biased up at 1.23 V for single supply applications. The model numbering reflects this by means of a “–B” suffix
(for example: AD7943AN-B). Figure 16 is an example of Biased Mode Operation.
2Temperature ranges as follows: A Versions: –40°C to +85°C.
3Guaranteed by design.
Specifications subject to change without notice.
REV. B
–3–
AD7943/AD7945/AD7948
AC PERFORMANCE CHARACTERISTICS
(AD7943: VDD = +4.5 V to +5.5 V; VIOUT1 = VIOUT2 = AGND = 0 V. AD7945, AD7948: VDD = +4.5 V to +5.5 V; VIOUT1 =AGND =
0 V. VREF = 6 V rms, 1 kHz sine wave; TA = TMIN to TMAX; DAC output op amp is AD843; unless otherwise noted.) These characteristics are in-
cluded for Design Guidance and are not subject to test.
NORMAL MODE
Parameter
B Grades
T Grade
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time
600
700
ns typ
To 0.01% of Full-Scale Range. VREF =
+10 V; DAC Latch Alternately Loaded with
All 0s and All 1s
Digital to Analog Glitch Impulse
60
60
nV-s typ
Measured with VREF = 0 V. DAC Latch
Alternately Loaded with All 0s and All 1s
DAC Latch Loaded with All 0s
All 1s Loaded to DAC
All 0s Loaded to DAC
Feedthrough to the DAC Output with LD1,
LD2 High and Alternate Loading of All 0s
and All 1s into the Input Shift Register
Feedthrough to the DAC Output with CS
High and Alternate Loading of All 0s and
All 1s to the DAC Bus
Multiplying Feedthrough Error
Output Capacitance
–75
60
30
5
–75
60
30
5
dB max
pF max
pF max
nV-s typ
Digital Feedthrough (AD7943)
Digital Feedthrough (AD7945, AD7948) 5
5
nV-s typ
Total Harmonic Distortion
Output Noise Spectral Density
@ 1 kHz
–83
35
–83
35
dB typ
nV/√Hz typ All 1s Loaded to DAC. VREF = 0 V. Output
Op Amp Is OP07
Specifications subject to change without notice.
AC PERFORMANCE CHARACTERISTICS
(AD7943: VDD = +3 V to +5.5 V; VIOUT1 = VIOUT2 = AGND = 1.23 V. AD7945, AD7948: VDD = +3 V to +5.5 V; VIOUT1 = AGND =
1.23 V. VREF = 1 kHz, 2.45 V p-p, sine wave biased at 1.23 V; DAC output op amp is AD820; TA = TMIN to TMAX; unless otherwise noted.) These
characteristics are included for Design Guidance and are not subject to test.
BIASED MODE
Parameter
A Grades
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time
5
µs typ
To 0.01% of Full-Scale Range. VREF = 0 V
DAC Latch Alternately Loaded with All 0s and All 1s
VREF = 1.23 V. DAC Register Alternately Loaded
with All 0s and All 1s
Digital to Analog Glitch Impulse
60
nV-s typ
Multiplying Feedthrough Error
Output Capacitance
–75
60
30
5
dB max
pF max
pF max
nV-s typ
DAC Latch Loaded with All 0s
All 1s Loaded to DAC
All 0s Loaded to DAC
Feedthrough to the DAC Output with LD1, LD2
High and Alternate Loading of All 0s and All 1s
into the Input Shift Register
Digital Feedthrough
Digital Feedthrough (AD7945, AD7948)
5
nV-s typ
Feedthrough to the DAC Output with CS High
and Alternate Loading of All 0s and All 1s to the
DAC Bus
Total Harmonic Distortion
Output Noise Spectral Density
@ 1 kHz
–83
25
dB typ
nV/√Hz typ
All 1s Loaded to DAC. VREF = 1.23 V
Specifications subject to change without notice.
–4–
REV. B
AD7943/AD7945/AD7948
AD7943 TIMING SPECIFICATIONS1
(TA = TMIN to TMAX, unless otherwise noted)
Limit @
Limit @
Parameter
VDD = +3 V to +3.6 V
VDD = +4.5 V to +5.5 V
Units
Description
2
tSTB
tDS
tDH
tSRI
tLD
60
15
35
55
55
55
0
40
10
25
35
35
35
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
STB Pulsewidth
Data Setup Time
Data Hold Time
SRI Data Pulsewidth
Load Pulsewidth
CLR Pulsewidth
Min Time Between Strobing Input Shift
Register and Loading DAC Register
STB Clocking Edge to SRO Data Valid Delay
tCLR
tASB
3
tSV
60
35
ns max
NOTES
1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. tr and tf should not exceed 1 µs on any digital input.
2STB mark/space ratio range is 60/40 to 40/60.
3tSV is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
Specifications subject to change without notice.
tSTB
STB1,
STB2,
STB4
STB3
tDH
tDS
tSRI
DB11(N)
(MSB)
DB10(N)
SRI
DB0(N)
tLD, tCLR
tASB
LD1,
LD2,
CLR
tSV
DB0(N–1)
DB10(N–1)
SRO
Figure 1. AD7943 Timing Diagram
I
1.6mA
OL
TO OUTPUT
PIN
+2.1V
C
L
50pF
200A
I
OH
Figure 2. Load Circuit for Digital Output Timing Specifications
REV. B
–5–
AD7943/AD7945/AD7948
AD7945 TIMING SPECIFICATIONS1
(TA = TMIN to TMAX, unless otherwise noted)
Limit @
Limit @
Parameter
VDD = +3 V to +3.6 V
VDD = +4.5 V to +5.5 V
Units
Description
tDS
tDH
tCS
tCH
tWR
35
10
60
0
20
10
40
0
ns min
ns min
ns min
ns min
ns min
Data Setup Time
Data Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Pulsewidth
60
40
NOTES
1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.
tCS
tCH
CS
tWR
WR
tDS
tDH
DB11–DB0
DATA VALID
Figure 3. AD7945 Timing Diagram
AD7948 TIMING SPECIFICATIONS1
(TA = TMIN to TMAX, unless otherwise noted)
Limit @
Limit @
Parameter
VDD = +3 V to +3.6 V
VDD = +4.5 V to +5.5 V
Units
Description
tDS
tDH
tCWS
tCWH
tLWS
tLWH
tWR
45
10
0
0
0
0
60
30
10
0
0
0
0
40
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Data Setup Time
Data Hold Time
CSMSB or CSLSB to WR Setup Time
CSMSB or CSLSB to WR Hold Time
LDAC to WR Setup Time
LDAC to WR Hold Time
Write Pulsewidth
NOTES
1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.
tCWH
tCWS
CSMSB
tCWH
tCWS
CSLSB
tLWH
tLWS
LDAC
tWR
tWR
WR
tDH
tDH
tDS
tDS
DATA
VALID
DATA
VALID
DB7–DB0
Figure 4. AD7948 Timing Diagram
–6–
REV. B
AD7943/AD7945/AD7948
SOP Package, Power Dissipation . . . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
SSOP Package, Power Dissipation . . . . . . . . . . . . . . . . 875 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 132°C/W
Lead Temperature, Soldering
I
OUT1 to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
IOUT2 to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND . . . . . . –0.3 V to VDD + 0.3 V
VRFB, VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . ±15 V
Input Current to Any Pin Except Supplies2 . . . . . . . . ±10 mA
Operating Temperature Range
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
DIP Package, Power Dissipation . . . . . . . . . . . . . . . . 670 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 116°C/W
Lead Temperature, Soldering, (10 sec) . . . . . . . . . . +260°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7943/AD7945/AD7948 feature proprietary ESD protection circuitry, perma-
nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Temperature
Range
Linearity
Error (LSBs)
Nominal
Supply Voltage
Package
Option1
Model
AD7943BN
AD7943BR
AD7943BRS
AD7943AN-B
AD7943ARS-B
AD7945BN
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
±0.5
±0.5
±0.5
±1
+5 V
+5 V
+5 V
+3.3 V to +5 V
+3.3 V to +5 V
+5 V
+5 V
+5 V
+3.3 V to +5 V
+3.3 V to +5 V
+5 V
+5 V
+5 V
+5 V
+3.3 V to +5 V
+3.3 V to +5 V
N-16
R-16
RS-20
N-16
RS-20
N-20
R-20
RS-20
N-20
RS-20
Q-20
N-20
R-20
±1
±0.5
±0.5
±0.5
±1
±1
±1
±0.5
±0.5
±0.5
±1
AD7945BR
AD7945BRS
AD7945AN-B
AD7945ARS-B
AD7945TQ
AD7948BN
AD7948BR
AD7948BRS
AD7948AN-B
AD7948ARS-B
RS-20
N-20
RS-20
±1
NOTE
1N = Plastic DIP; R = SOP (Small Outline Package); RS = SSOP (Shrink Small Outline Package); Q = Cerdip.
REV. B
–7–
AD7943/AD7945/AD7948
TERMINOLOGY
Output Capacitance
Relative Accuracy
This is the capacitance from the IOUT1 pin to AGND.
Relative Accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error and is normally
expressed in Least Significant Bits or as a percentage of full-
scale reading.
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change. For these devices, it
is specified both with the AD843 as the output op amp in the
normal current mode and with the AD820 in the biased current
mode.
Differential Nonlinearity
Digital to Analog Glitch Impulse
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
This is the amount of charge injected into the analog output
when the inputs change state. It is specified as the area of the
glitch in nV-s. It is measured with the reference input connected
to AGND and the digital inputs toggled between all 1s and all
0s. As with Settling Time, it is specified with both the AD817
and the AD820.
Gain Error
Gain Error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s
in the DAC after offset error has been adjusted out and is ex-
pressed in Least Significant Bits. Gain error is adjustable to
zero with an external potentiometer.
AC Feedthrough Error
This is the error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal, when all 0s are
loaded in the DAC.
Output Leakage Current
Digital Feedthrough
Output leakage current is current which flows in the DAC lad-
der switches when these are turned off. For the IOUT1 terminal,
it can be measured by loading all 0s to the DAC and measuring
the IOUT1 current. Minimum current will flow in the IOUT2 line
when the DAC is loaded with all 1s.
When the device is not selected, high frequency logic activity on
the device digital inputs is capacitively coupled through the
device to show up as noise on the IOUT1 pin and subsequently on
the op amp output. This noise is digital feedthrough.
PIN CONFIGURATIONS
DIP/SOP/SSOP
DIP/SOP
SSOP
DIP/SOP/SSOP
1
2
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
1
2
20
19
18
17
16
15
R
V
R
V
R
V
I
I
I
R
V
I
I
OUT1
FB
FB
FB
OUT1
OUT1
FB
OUT1
I
AGND
DGND
DB11
DB10
DB9
AGND
DGND
OUT2
REF
DD
REF
DD
REF
DD
REF
DD
OUT2
3
3
V
V
V
V
AGND
STB1
LD1
AGND
AD7943
TOP VIEW
(Not to Scale)
AD7945
TOP VIEW
(Not to Scale)
AD7948
TOP VIEW
(Not to Scale)
AD7943
TOP VIEW
(Not to Scale)
4
4
STB1
NC
CLR
NC
WR
WR
CS
CSMSB
CLR
5
5
CSLSB
LDAC
DGND
STB4
DF/DOR
NC
6
CTRL
6
SRO
SRI
NC
DB0
DB1
DB2
DB3
DB4
LD1
14 DGND
DB8
7
DB7 (MSB)
DB6
7
14 DB0 (LSB)
STB3
LD2
DB7
8
13
8
13
12
11
DB1
DB2
DB3
SRO
SRI
STB4
STB2
DB6
9
12
DB5
9
STB3
DB5
10
DB4
STB2 10
11
10
LD2
NC = NO CONNECT
–8–
REV. B
AD7943/AD7945/AD7948
AD7943 PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Description
IOUT1
DAC current output terminal 1.
IOUT2
DAC current output terminal 2. This should be connected to the AGND pin.
AGND
This pin connects to the back gates of the current steering switches. In normal operation, it should be connected
to the signal ground of the system. In biased single-supply operation it may be biased to some voltage between
0 V and the 1.23 V. See Figure 11 for more details.
STB1
This is the Strobe 1 input. Data is clocked into the input shift register on the rising edge of this signal. STB3
must be high. STB2, STB4 must be low.
LD1, LD2
SRI
Active low inputs. When both of these are low, the DAC register is updated and the output will change to
reflect this.
Serial Data Input. Data on this line will be clocked into the input shift register on one of the Strobe inputs,
when they are enabled.
STB2
This is the Strobe 2 input. Data is clocked into the input shift register on the rising edge of this signal.
STB3 must be high. STB1, STB4 must be low.
STB3
This is the Strobe 3 input. Data is clocked into the input shift register on the falling edge of this signal. STB1,
STB2, STB4, must be low.
STB4
This is the Strobe 4 input. Data is clocked into the input shift register on the rising edge of this signal. STB3
must be high. STB1, STB2 must be low.
DGND
CLR
Digital Ground.
Asynchronous CLR input. When this input is taken low, all 0s are loaded to the DAC latch.
VDD
Power supply input. This is nominally +5 V for Normal Mode Operation and +3.3 V to +5 V for Biased
Mode Operation.
VREF
RFB
DAC reference input.
DAC feedback resistor pin.
AD7945 PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Description
IOUT1
DAC current output terminal 1.
AGND
This pin connects to the back gates of the current steering switches. The DAC IOUT2 terminal is also connected
internally to this point.
DGND
DB11–DB0
CS
Digital Ground.
Digital Data Inputs.
Active Low, Chip Select Input.
Active Low, Write Input.
WR
VDD
Power supply input. This is nominally +5 V for Normal Mode Operation and +3.3 V to +5 V for Biased Mode
Operation.
VREF
RFB
DAC reference input.
DAC feedback resistor pin.
REV. B
–9–
AD7943/AD7945/AD7948
AD7948 PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Description
IOUT1
AGND
DAC current output terminal 1. Normally terminated at the virtual ground of output amplifier.
Analog Ground Pin. This pin connects to the back gates of the current steering switches. The DAC IOUT2
terminal is also connected internally to this point.
DGND
Digital Ground Pin.
CSMSB
Chip Select Most Significant Byte. Active Low Input. Used in combination with WR to load external data into
the input register or in combination with LDAC and WR to load external data into both input and DAC registers.
DF/DOR
Data Format/Data Override. When this input is low, data in the DAC register is forced to one of two override
codes selected by CTRL. When the override signal is removed, the DAC output returns to reflect the value in
the DAC register. With DF/DOR high, CTRL selects either a left or right justified input data format. For normal
operation, DF/DOR is held high. See Table I.
Table I. Truth Table for DF/DOR CTRL
DF/DOR
CTRL
Function
0
0
1
1
0
1
0
1
DAC Register Contents Overridden by All 0s
DAC Register Contents Overridden by All 1s
Left-Justified Input Data Selected
Right-Justified Input Data Selected
CTRL
Control Input. See DF/DOR description.
DB7–DB0
LDAC
Digital Data Inputs.
Load DAC input, active low. This signal, in combination with others, is used to load the DAC register from
either the input register or the external data bus.
CSLSB
Chip Select Least Significant (LS) Byte. Active Low Input. Used in combination with WR to load external data
into the input register or in combination with WR and LDAC to load external data into both input and DAC
registers.
Table II. Truth Table for AD7948 Write Operation
WR
CSMSB
CSLSB
LDAC
Function
0
0
0
0
0
1
1
1
0
0
1
X
0
0
1
1
1
X
1
0
1
0
0
X
Load LS Byte to Input Register
Load LS Byte to Input Register and DAC Register
Load MS Byte to Input Register
Load MS Byte to Input Register and DAC Register
Load Input Register to DAC Register
No Data Transfer
WR
Write input, active low. This active low signal, in combination with others is used in loading external data into
the AD7948 input register and in transferring data from the input register to the DAC register.
VDD
Power supply input. This is nominally +5 V for Normal Mode Operation and +3.3 V to +5 V for Biased Mode
Operation.
VREF
RFB
DAC reference input.
DAC feedback resistor pin.
–10–
REV. B
AD7943/AD7945/AD7948
Typical Performance Curves
0.5
0.50
0.25
V
V
= +5V
DD
V
T
= +5V
DD
= +10V
REF
= +25؇C
OP AMP = AD843
= +25؇C
A
0.4
0.3
0.2
OP AMP = AD843
T
A
0.00
–0.25
–0.50
0.1
0
2
4
6
8
10
1024
3072
4095
2048
0
V
– Volts
INPUT CODE
REF
Figure 5. Differential Nonlinearity Error vs.
REF (Normal Mode)
Figure 7. All Codes Linearity In Normal Mode (VDD = +5 V)
V
1.0
0.9
6
V
= +5V
DD
V
T
= +3.3V
DD
T
= +25؇C
A
= +25؇C
OP AMP = AD843
A
5
4
3
2
0.8
0.7
0.6
0.5
0.4
0.3
0.2
OP AMP = AD820
1
0
0.1
0
2
4
6
8
10
0.2
0.4
0.6
|V
0.8
1.0
| – Volts
1.2
1.4
V
– Volts
– V
REF
REF
BIAS
Figure 6. Integral Nonlinearity Error vs.
VREF (Normal Mode)
Figure 8. Linearity Error vs. VREF (Biased Mode)
REV. B
–11–
AD7943/AD7945/AD7948
1.00
V
V
V
= +3.3V
DD
= 0V
REF
= 1.23V
BIAS
5V
200ns
OP AMP = AD820
= +25؇C
0.50
0.00
T
A
100
90
V
T
= +5V
DD
= +25؇C
A
V
= 0V
REF
OP AMP = AD711
AD711 OUTPUT
10
–0.50
–1.00
0%
50mV
200ns
0
2048
3072
4095
1024
INPUT CODE
Figure 9. All Codes Linearity in Biased Mode
(VDD = +3.3 V)
Figure 11. Digital-to-Analog Glitch Impulse
–50
–55
–60
0
V = +5V
DD
V
= +5V
DD
–10
–20
–30
–40
–50
–60
–70
T = +25؇C
T
= +25؇C
= 6V rms
A
A
V = 20V p-p
IN
OP AMP = AD711
V
IN
DAC LOADED WITH ALL 1S
OP AMP = AD711
–65
–70
–75
–80
–85
–90
DAC LOADED WITH ALL 0S
–80
–90
–95
–100
–100
100
1k
10k
FREQUERCY – Hz
100k
1k
10k
100k
FREQUENCY – Hz
1M
10M
Figure 10. Total Harmonic Distortion vs. Frequency
Figure 12. Multiplying Frequency Response vs.
Digital Code
–12–
REV. B
AD7943/AD7945/AD7948
GENERAL DESCRIPTION
UNIPOLAR BINARY OPERATION
D/A Section
(Two-Quadrant Multiplication)
The AD7943, AD7945 and AD7948 are 12-bit current-output
D/A converters. A simplified circuit diagram is shown in Fig-
ure 13. The DAC architecture is segmented. This means that
the 2 MSBs of the 12-bit data word are decoded to drive the
three switches A, B and C. The remaining 10 bits of the data
word drive the switches S0 to S9 in a standard inverting R-2R
ladder configuration.
Figure 14 shows the standard unipolar binary connection dia-
gram for the AD7943, AD7945 and AD7948. When VIN is an
ac signal, the circuit performs two-quadrant multiplication.
Resistors R1 and R2 allow the user to adjust the DAC gain
error. With a specified gain error of 2 LSBs over temperature,
these are not necessary in many applications. Circuit offset is
due completely to the output amplifier offset. It can be re-
moved by adjusting the amplifier offset voltage. Alternatively,
choosing a low offset amplifier makes this unnecessary.
Each of the switches A to C steers 1/4 of the total reference
current into either IOUT1 or IOUT2 with the remaining 1/4 of the
total current passing through the R-2R section. Switches S9 to
S0 steer binarily weighted currents into either IOUT1 or IOUT2. If
IOUT1 and IOUT2 are kept at the same potential, a constant cur-
rent flows in each ladder leg, regardless of digital input code.
Thus, the input resistance seen at VREF is always constant. It is
equal to R/2. The VREF input may be driven by any reference
voltage or current, ac or dc that is within the Absolute Maxi-
mum Ratings.
A1 should be chosen to suit the application. For example, the
OP07 is ideal for very low bandwidth applications (10 kHz or
R2 10⍀
RFB
C1
I
I
OUT1
OUT2
V
REF
A1
V
DAC
V
OUT
IN
R1 20⍀
A1: OP07
AD711
AD843
AD845
AD7943/45/48
The device provides access to the VREF, RFB, and IOUT1 termi-
nals of the DAC. This makes the device extremely versatile and
allows it to be configured in several different operating modes.
Examples of these are shown in the following sections. The
AD7943 also has a separate IOUT2 pin. In the AD7945 and
AD7948 this is internally tied to AGND.
AGND
SIGNAL GROUND
NOTES
1. ONLY ONE DAC IS SHOWN FOR CLAIRITY.
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C1 PHASE COMPENSATION (5 – 15pF) MAY BE REQUIRED
WHEN USING HIGH SPEED AMPLIFIER.
When an output amplifier is connected in the standard configu-
ration of Figure 14, the output voltage is given by:
Figure 14. Unipolar Binary Operation
lower) while the AD711 is suitable for medium bandwidth ap-
plications (200 kHz or lower). For high bandwidth applications
of greater than 200 kHz, the AD843 and AD847 offer very fast
settling times.
VOUT = –D × VREF
where D is the fractional representation of the digital word
loaded to the DAC. D can be set from 0 to 4095/4096, since it
has 12-bit resolution.
The code table for Figure 14 is shown in Table III.
V
REF
Table III. Unipolar Binary Code
R
R
R
Digital Input
Analog Output
(VOUT as Shown in Figure 14)
2R
2R
2R
2R
2R
2R
2R
MSB
LSB
C
B
A
S9
S8
S0
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
–VREF (4095/4096)
–VREF (2049/4096)
–VREF (2048/4096)
–VREF (2047/4096)
–VREF (1/4096)
R/2
R
FB
I
OUT1
I
OUT2
SHOWN FOR ALL 1S ON DAC
Figure 13. Simplified D/A Circuit Diagram
–VREF (0/4096) = 0
NOTE
Nominal LSB size for the circuit of Figure 14 is given by: VREF (1/4096).
REV. B
–13–
AD7943/AD7945/AD7948
BIPOLAR OPERATION
SINGLE SUPPLY APPLICATIONS
(Four-Quadrant Multiplication)
The “-B” versions of the devices are specified and tested for
single supply applications. Figure 16 shows the recommended
circuit for operation with a single +5 V to +3.3 V supply. The
IOUT2 and AGND terminals are biased to 1.23 V. Thus, with 0 V
applied to the VREF terminal, the output will go from 1.23 V (all
0s loaded to the DAC) to 2.46 V (all 1s loaded). With 2.45 V
applied to the VREF terminal, the output will go from 1.23 V (all
0s loaded) to 0.01 V (all 1s loaded). It is important when con-
sidering INL in a single-supply system to realize that most
single-supply amplifiers cannot sink current and maintain zero
volts at the output. In Figure 16, with VREF = 2.45 V the re-
quired sink current is 200 µA. The minimum output voltage
level is 10 mV. Op amps like the OP295 are capable of main-
taining this level while sinking 200 µA.
Figure 15 shows the standard connection diagram for bipolar
operation of the AD7943, AD7945 and AD7948. The coding is
offset binary as shown in Table IV. When VIN is an ac signal,
the circuit performs four-quadrant multiplication. Resistors R1
and R2 are for gain error adjustment and are not needed in
many applications where the device gain error specifications are
adequate. To maintain the gain error specifications, resistors
R3, R4 and R5 should be ratio matched to 0.01%.
R4 20k⍀
R2 10⍀
R5
20k⍀
RFB
C1
I
I
OUT1
OUT2
V
V
IN
REF
R3
A1
DAC
Figure 16 shows the IOUT2 and AGND terminals being driven
by an amplifier. This is to maintain the bias voltage at 1.23 V
as the impedance seen looking into the IOUT2 terminal changes.
This impedance is code dependent and varies from infinity (all
0s loaded in the DAC) to about 6 kΩ minimum. The AD589
has a typical output resistance of 0.6 Ω and it can be used to
drive the terminals directly. However, this will cause a typical
linearity degradation of 0.2 LSBs. If this is unacceptable then
the buffer amplifier is necessary. Figure 9 shows the typical
linearity performance of the AD7943/AD7945/AD7948 when
used as in Figure 16 with VDD set at +3.3 V and VREF = 0 V.
10k⍀
R1 20⍀
A2
V
OUT
AD7943/45/48
AGND
SIGNAL GROUND
NOTES
1. ONLY ONE DAC IS SHOWN FOR CLAIRITY.
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C1 PHASE COMPENSATION (5 – 15pF) MAY BE REQUIRED
WHEN USING HIGH SPEED AMPLIFIER, A1.
Figure 15. Bipolar Operation (Four-Quadrant
Multiplication)
Suitable dual amplifiers for use with Figure 15 are the OP270
(low noise, low bandwidth, 15 kHz), the AD712 (medium
bandwidth, 200 kHz) or the AD827 (wide bandwidth, 1 MHz).
+3.3V
V
RFB
DAC
DD
C1
Table IV. Bipolar (Offset Binary) Code
I
I
OUT1
OUT2
V
REF
V
A1
V
IN
OUT
Table Digital Input
MSB LSB
Analog Output
(VOUT as Shown in Figure 15)
A1: OP295
AD822
AD7943/45/48
DGND
OP283
AGND
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
NOTE
+VREF (2047/2048)
+VREF (1/2048)
+5V
+VREF (0/2048) = 0
–VREF (1/2048)
5.6k⍀
A1
AD589
–VREF (2047/2048)
–VREF (2048/2048) = –VREF
SIGNAL GROUND
Figure 16. Single Supply System
Nominal LSB size for the circuit of Figure 15 is given by: VREF (1/2048).
–14–
REV. B
AD7943/AD7945/AD7948
MICROPROCESSOR INTERFACING
AD7945 to MC68000 Interface
AD7943 to ADSP-2101 Interface
Figure 19 shows the MC68000 interface to the AD7945. The
appropriate data is written into the DAC in one MOVE instruc-
tion to the appropriate memory location.
Figure 17 shows the AD7943 to ADSP-2101 interface diagram.
The DSP is set up for alternate inverted framing with an inter-
nally generated SCLK. TFS from the ADSP-2101 drives the
STB1 input on the AD7943. The serial word length should be
set at 12. This is done by making SLEN = 11 (1011 binary).
The SLEN field is Bits 3–0 in the SPORT control register
(0x3FF6 for SPORT0 and 0x3FF2 for SPORT1).
A1 – A23
MC68000
ADDRESS
DECODE
AS
CS
With the 16 MHz version of the ADSP-2101, the maximum
output SCLK is 8 MHz. The AD7943 setup and hold time of
10 ns and 25 ns mean that it is compatible with the DSP when
running at this speed.
AD7945
DTACK
WR
R/W
The OUTPUT FLAG drives both LD1 and LD2 and is brought
low to update the DAC register and change the analog output.
DB11 – DB0
D15 – D0
+5V
AD7943
ADSP-2101
CLR
Figure 19. AD7945 to MC68000 Interface
AD7948 to Z80 Interface
Figure 20 is the interface between the AD7948 and the 8-bit
bus of the Z80 processor. Three write operations are needed to
load the DAC. The first two load the MS byte and the LS byte
and the third brings the LDAC low to update the output.
TFS
STB1
STB3
SRI
SCLK
DT
OUTPUT FLAG
LD1
LD2
STB2
STB4
A0 – A15
ADDRESS BUS
Figure 17. AD7943 to ADSP-2101 Interface
AD7943 to DSP56001 Interface
Z80
CSMSB
ADDRESS
DECODE
CSLSB
LDAC
MREQ
WR
Figure 18 shows the interface diagram for the AD7943 to the
DSP56001. The DSP56001 is configured for normal mode
synchronous operation with gated clock. The serial clock, SCK,
is set up as an output from the DSP and the serial word length
is set for 12 bits (WL0 = 1, WL1 = 0, in Control Register A).
SCK from the DSP56001 is applied to the AD7943 STB3 in-
put. Data from the DSP56000 is valid on the falling edge of
SCK and this is the edge which clocks the data into the AD7943
shift register. STB1, STB2 and STB4 are tied low on the
AD7943 to permanently enable the STB3 input.
AD7948
WR
DB7 – DB0
D7 – D0
DATA BUS
Figure 20. AD7948 to Z80 Interface
When the 12-bit serial word has been written to the AD7943,
the LD1, LD2 inputs are brought low to update the DAC
register.
+5V
AD7943
DSP56001
CLR
STB3
SCK
STD
SRI
OUTPUT FLAG
LD1
LD2
STB1
STB2
STB4
Figure 18. AD7943 to DSP56001 Interface
REV. B
–15–
AD7943/AD7945/AD7948
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Plastic DIP (N-16)
16-Lead SOP (R-16)
0.4133 (10.50)
0.3977 (10.00)
0.840 (21.34)
0.745 (18.92)
16
9
16
1
9
8
0.280 (7.11)
0.240 (6.10)
0.325 (8.26)
0.195 (4.95)
0.115 (2.93)
0.300 (7.62)
1
8
PIN 1
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
PIN 1
0.160 (4.06)
0.115 (2.93)
x 45°
0.0118 (0.30)
0.0040 (0.10)
0.015 (0.381)
0.008 (0.204)
0.100
(2.54)
BSC
0.070 (1.77) SEATING
0.022 (0.558)
0.014 (0.356)
PLANE
0.045 (1.15)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
0.0138 (0.35)
20-Lead Plastic DIP (N-20)
20-Lead Cerdip (Q-20)
0.005 (0.13) MIN
20
0.098 (2.49) MAX
1.060 (26.90)
0.925 (23.50)
11
20
1
11
0.310 (7.87)
0.280 (7.11)
0.220 (5.59)
10
0.240 (6.10)
10
1
0.325 (8.25)
0.195 (4.95)
0.115 (2.93)
0.320 (8.13)
0.290 (7.37)
0.300 (7.62)
PIN 1
1.060 (26.92) MAX
PIN 1
0.060 (1.52)
0.015 (0.38)
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.200 (5.08)
0.130
(3.30)
MIN
MAX
0.150
(3.81)
MIN
0.160 (4.06)
0.115 (2.93)
0.200 (5.08)
0.125 (3.18)
0.015 (0.381)
0.008 (0.204)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.100
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
SEATING
PLANE
0.070 (1.78)
0.030 (0.76)
15°
0°
20-Lead SOP (R-20)
20-Lead SSOP (RS-20)
0.295 (7.50)
0.5118 (13.00)
0.4961 (12.60)
0.271 (6.90)
20
11
20
11
10
1
10
1
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
x 45°
0.0098 (0.25)
0.07 (1.78)
0.078 (1.98)
0.068 (1.73)
PIN 1
0.066 (1.67)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.037 (0.94)
0.022 (0.559)
0.0500 0.0192 (0.49)
8°
0°
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
0.0256
(0.65)
BSC
(1.27)
0.0138 (0.35)
0.008 (0.203)
0.002 (0.050)
SEATING
PLANE
0.009 (0.229)
BSC
0.005 (0.127)
–16–
REV. B
AD7948BRS-REEL 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| AD7948BRSZ | ADI | +3.3 V/+5 V Multiplying 12-Bit DAC With an 8-Bit Byte Interface | 获取价格 |
|
| AD7948BRSZ-REEL | ADI | +3.3 V/+5 V Multiplying 12-Bit DAC With an 8-Bit Byte Interface | 获取价格 |
|
| AD7948BRZ | ADI | +3.3 V/+5 V Multiplying 12-Bit DAC With an 8-Bit Byte Interface | 获取价格 |
|
| AD7948BRZ-REEL | ADI | +3.3 V/+5 V Multiplying 12-Bit DAC With an 8-Bit Byte Interface | 获取价格 |
|
| AD7948_15 | ADI | 3.3 V/5 V Multiplying 12-Bit DACs | 获取价格 |
|
| AD7949 | ADI | 16-Bit, 8-Channel, 250 kSPS PulSAR㈢ ADC. | 获取价格 |
|
| AD7949BCPZ | ADI | 14-Bit, 8-Channel, 250 kSPS PulSAR ADC | 获取价格 |
|
| AD7949BCPZRL7 | ADI | 14-Bit, 8-Channel, 250 kSPS PulSAR ADC | 获取价格 |
|
| AD7949_09 | ADI | 14-Bit, 8-Channel, 250 kSPS PulSAR ADC | 获取价格 |
|
| AD795 | ADI | Low Power, Low Noise Precision FET Op Amp | 获取价格 |
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