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5962-0051801QQX

更新时间：2025-05-02 13:03:32

品牌：ATMEL

描述：Microcontroller, 8-Bit, 30MHz, CMOS, CDIP40, 0.600 INCH, SIDE BRAZED, DIP-40

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概述
规格参数
数据手册

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5962-0051801QQX 概述

Microcontroller, 8-Bit, 30MHz, CMOS, CDIP40, 0.600 INCH, SIDE BRAZED, DIP-40 微控制器

5962-0051801QQX 规格参数

生命周期：	Transferred	零件包装代码：	DIP
包装说明：	DIP,	针数：	40
Reach Compliance Code：	unknown	ECCN代码：	3A001.A.2.C
HTS代码：	8542.31.00.01	风险等级：	5.2
Is Samacsys：	N	具有ADC：	NO
地址总线宽度：	16	位大小：	8
最大时钟频率：	30 MHz	DAC 通道：	NO
DMA 通道：	NO	外部数据总线宽度：	8
JESD-30 代码：	R-CDIP-T40	长度：	50.93 mm
I/O 线路数量：	32	端子数量：	40
最高工作温度：	125 °C	最低工作温度：	-55 °C
PWM 通道：	NO	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	认证状态：	Qualified
筛选级别：	MIL-PRF-38535 Class Q	座面最大高度：	4.83 mm
速度：	30 MHz	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	MILITARY	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
宽度：	15.24 mm	uPs/uCs/外围集成电路类型：	MICROCONTROLLER
Base Number Matches：	1

5962-0051801QQX 数据手册

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Features

•

8032 Pin and Instruction Compatible

Four 8-bit I/O Ports

Three 16-bit Timer/Counters

256 bytes RAM

Full-duplex UART

Asynchronous Port Reset

6 Sources, 2 Level Interrupt Structure

64 Kbytes Program Memory Space

64 Kbytes Data Memory Space

Power Control Modes

Rad. Tolerant

8-bit ROMless

Microcontroller

Idle Mode

Power-down Mode

On-chip Oscillator

Operating Frequency: 30 MHz

Power Supply: 4.5V to 5.5V

Temperature Range: Military (-55^oC to 125^oC)

No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm²

Tested up to a Total Dose of 30 krads (Si) according to MIL STD 883 Method 1019

Packages: Side Brazed 40-pin, MQFPJ 44-pin

Quality grades: QML Q and V with SMD 5962-00518 and ESCC with Specification

9521002

80C32E

Description

The 80C32E is a radiation tolerant ROMless version of the 80C52 single chip 8-bit

microcontroller.

The 80C32E retains all the features of the 80C32 with 256 bytes of internal RAM, a 6-

source, 2-level interrupt system, an on-chip oscillator and three 16-bit timer/counters.

The fully static design of the 80C32E reduces system power consumption by bringing

the clock frequency down to any value, even DC, without loss of data.

The 80C32E has 2 software-selectable modes of reduced activity for further reduction

in power consumption. In the idle mode the CPU is frozen while the timers, the serial

port and the interrupt system are still operating. In the power-down mode the RAM is

saved and all other functions are inoperative.

Rev. 4149N–AERO–04/07

Block Diagram

XTAL1

XTAL2

RAM

256x8

Parallel I/O Ports & Ext. Bus

UART

Port 0Port 1

Port 3

Port 2

ALE

C51

CORE

IB-bus

PSEN

CPU

Timer 0

Timer 1 Timer 2

INT

Ctrl

Pin Configuration

P1.0/T2

VCC

P0.0/A0

P0.1/A1

P1.1/T2EX

P1.2

P1.3

37 P0.2/A2

P0.3/A3

P0.4/A4

P1.4

P1.5

P1.6

5 4 3 2 1

44 43 42 41 40

P0.5/A5

P1.5

P1.6

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

P0.6/A6

P0.7/A7

P1.7

RST

P1.7

EA/VPP

ALE

P3.0/RxD 10

RST

SB40

P3.1/TxD

P3.0/RxD

NIC*

PSEN

P3.2/INT0

NIC*

MQFPJ44

P2.7/A15

P2.6/A14

P3.3/INT1 13

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

ALE

P3.4/T0

P3.5/T1

P3.6/WR

PSEN

P2.5/A13

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

P3.7/RD

XTAL2

P2.2/A10

P2.1/A9

P2.0/A8

18 19 20 21 22 23 24 25 26 27 28

XTAL1

VSS

Note:

NIC: No Internal Connection

80C32E

4149N–AERO–04/07

80C32E

Pin Description

Mnemonic

Type Name and Function

V_SS

Ground: 0V reference

Power Supply: This is the power supply voltage for normal, idle and

power-down operation

V_CC

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that

have 1s written to them float and can be used as high impedance inputs.

Port 0 pins must be polarized to Vcc or Vss in order to prevent any

parasitic current consumption. Port 0 is also the multiplexed low-order

address and data bus during access to external program and data

memory. In this application, it uses strong internal pull-up when emitting

1s.

P0.0-P0.7

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1

pins that have 1s written to them are pulled high by the internal pull-ups

and can be used as inputs. As inputs, Port 1 pins that are externally

pulled low will source current because of the internal pull-ups.

P1.0-P1.7

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2

pins that have 1s written to them are pulled high by the internal pull-ups

and can be used as inputs. As inputs, Port 2 pins that are externally

pulled low will source current because of the internal pull-ups. Port 2

emits the high-order address byte during fetches from external program

memory and during accesses to external data memory that use 16-bit

addresses (MOVX @DPTR).In this application, it uses strong internal

pull-ups emitting 1s. During accesses to external data memory that use

8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.

P2.0-P2.7

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3

pins that have 1s written to them are pulled high by the internal pull-ups

and can be used as inputs. As inputs, Port 3 pins that are externally

pulled low will source current because of the internal pull-ups. Port 3 also

serves the special features of the 80C51 family, as listed below.

RXD (P3.0): Serial input port

TXD (P3.1): Serial output port

P3.0-P3.7

INT0 (P3.2): External interrupt 0

INT1 (P3.3): External interrupt 1

T0 (P3.4): Timer 0 external input

T1 (P3.5): Timer 1 external input

WR (P3.6): External data memory write strobe

RD (P3.7): External data memory read strobe

Reset: A high on this pin for two machine cycles while the oscillator is

running, resets the device. An internal diffused resistor to V_SSpermits a

power-on reset using only an external capacitor to V_CC.

RST

4149N–AERO–04/07

Mnemonic

Type Name and Function

Address Latch Enable: Output pulse for latching the low byte of the

address during an access to external memory. In normal operation, ALE

O (I) is emitted at a constant rate of 1/6 the oscillator frequency, and can be

used for external timing or clocking. Note that one ALE pulse is skipped

during each access to external data memory.

ALE

Program Store ENable: The read strobe to external program memory.

When executing code from the external program memory, PSEN is

PSEN

activated twice each machine cycle, except that two PSEN activations

are skipped during each access to external data memory. PSEN is not

activated during fetches from internal program memory.

External Access Enable: EA must be externally held low to enable the

device to fetch code from external program memory locations.

Crystal 1: Input to the inverting oscillator amplifier and input to the

internal clock generator circuits.

XTAL1

XTAL2

Crystal 2: Output from the inverting oscillator amplifier

80C32E

4149N–AERO–04/07

80C32E

Idle and Power-down Idle mode allows the interrupt, serial port and timer blocks to continue to operate while

the clock of the CPU is gated off.

Operation

Power-down mode stops the oscillator.

Table 1. PCON Register

PCON – Power Control Register

SMOD

GF1

GF0

IDL

Bit

Mnemonic Description

Number

Double Baud Rate bit

Set to select double baud rate in mode 1, 2 or 3.

SMOD

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

General-purpose Flag

Cleared by user for General-purpose usage.

Set by user for General-purpose usage.

GF1

GF0

General-purpose Flag

Cleared by user for General-purpose usage.

Set by user for General-purpose usage.

Power-down mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

Idle mode bit

Clear by hardware when interrupt or reset occurs.

Set to enter idle mode.

IDL

Reset Value = 000X 0000

Not bit addressable

4149N–AERO–04/07

Idle Mode

An instruction that sets PCON.0 causes that to be the last instruction executed before

going into Idle mode. In Idle mode, the internal clock signal is gated off to the CPU, but

not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its

entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator, RAM

and all other registers maintain their data during Idle. The port pins hold the logical

states they had at the time Idle was activated. ALE and PSEN hold at logic high levels.

There are two ways to terminate the Idle. Activation of any enabled interrupt will cause

PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be ser-

viced, and following RETI the next instruction to be executed will be the one following

the instruction that put the device into idle.

The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred dur-

ing normal operation or during an Idle. For example, an instruction that activates Idle

can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt

service routine can examine the flag bits.

The other way of terminating the Idle mode is with a hardware reset. Since the clock

oscillator is still running, the hardware reset needs to be held active for only two

machine cycles (24 oscillator periods) to complete the reset.

Power-down Mode

To save maximum power, a power-down mode can be invoked by software.

In power-down mode, the oscillator is stopped and the instruction that invoked power-

down mode is the last instruction executed. The internal RAM and SFRs retain their

value until the power-down mode is terminated. V_CCcan be lowered to save further

power. Either a hardware reset or an external interrupt can cause an exit from power-

down. To properly terminate power-down, the reset or external interrupt should not be

executed before V_CCis restored to its normal operating level and must be held active

long enough for the oscillator to restart and stabilize.

Only external interrupts INT0 and INT1 are useful to exit from power-down. For that,

interrupt must be enabled and configured as level or edge sensitive interrupt input.

Holding the pin low restarts the oscillator but bringing the pin high completes the exit as

detailed in Figure 1. When both interrupts are enabled, the oscillator restarts as soon as

one of the two inputs is held low and Power-down exit will be completed when the first

input will be released. In this case the higher priority interrupt service routine is executed

Once the interrupt is serviced, the next instruction to be executed after RETI will be the

one following the instruction that put 80C32E into power-down mode.

Figure 1. Power-down Exit Waveform

INT0

INT1

XTAL1

Active phase

Power-down phase Oscillator restart phase

Active phase

Exit from power-down by reset redefines all the SFRs, exit from power-down by external

interrupt does no affect the SFRs.

80C32E

4149N–AERO–04/07

80C32E

Exit from power-down by either reset or external interrupt does not affect the internal

RAM content.

Note:

If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence

is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and

idle mode is not entered.

Table 2. State of Ports During Idle and Power-down Modes

Program

Memory

Mode

ALE

PSEN

PORT0

PORT1

PORT2

PORT3

Idle

External

Floating

Port Data

Address

Port Data

Power-

down

External

Floating

Port Data

4149N–AERO–04/07

Hardware

Description

Refer to the C51 8-bit Microcontroller Hardware description manual for details on

80C32E functionality.

Electrical Characteristics

Absolute Maximum Ratings⁽²⁾

Notes: 1. Stresses at or above those listed under “ Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions above those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions may affect device reliability.

Ambient Temperature Under Bias. M = Military-55°C to 125°C

Storage Temperature.................................... -65°C to + 150°C

Voltage on V_CCto V_SS..........................................-0.5V to + 7V

Voltage on Any Pin to V_SS..........................-0.5V to V_CC+ 0.5V

2. This value is based on the maximum allowable

die temperature and the thermal resistance of the

package.

Power Dissipation........................................................... 1 W⁽²⁾

80C32E

4149N–AERO–04/07

80C32E

DC Parameters

Table 3. DC Parameters in Standard VoltageTA = -55°C to +125°C; V_SS= 0V; V_CC= 5V 10%; F = 0 to 30 MHz.

Symbol

V_IL

Parameter

Min.

-0.5

Max

0.2 V_CC- 0.1

V_CC+ 0.5

0.45

Unit Test Conditions

Input Low Voltage

V_IH

Input High Voltage except XTAL1, RST

Input High Voltage, XTAL1, RST

0.2 V_CC+ 1.4

0.7 V_CC

V_IH1

V_OL

Output Low Voltage, ports 1, 2, 3⁽⁵⁾

Output Low Voltage, port 0, ALE, PSEN⁽⁵⁾

I_OL= 1.6 mA⁽⁴⁾

I_OL= 3.2 mA⁽⁴⁾

V_OL1

0.45

2.4

I_OH= -60 µA

I_OH= -25 µA

V_OH

Output High Voltage, ports 1, 2, 3

0.75 V_CC

0.9 V_CC

_OH= -10 µA

I_OH= -400 µA

I_OH= -150 µA

2.4

V_OH1

Output High Voltage, port 0, ALE, PSEN

0.75 V_CC

0.9 V_CC

I_OH= -40 µA

R_RST

I_IL

RST Pull-down Resistor

200

-75

kΩ

µA

Logical 0 Input Current ports 1, 2 and 3

Input Leakage Current

Vin = 0.45V

I_LI

0.45 V < Vin < V_CC

Vin = 2.0V

I_TL

Logical 1 to 0 Transition Current, ports 1, 2, 3

-750

Fc = 1 MHz

= 25°C

C_IO

I_PD

Capacitance of I/O Buffer

Power-down Current ⁽³⁾

µA

2.0V < V_{CC <}5.5V

Power Supply Current ^(1)(2)(6)

Freq = 1 MHz Icc Op

Freq = 1 MHz Icc Idle

Freq = 6 MHz Icc Op

Freq = 6 MHz Icc Idle

Freq >12 MHz Icc Op

Freq >12 MHz Icc Idle

_CC= 5.5V

1.8

I_CC

1.25F + 5

0.36F + 2.7

F in MHz

Notes: 1. I_CCunder reset is measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns (see Figure 6), V_IL

V_SS+ 0.5V,

V_IH= V_CC- 0.5V; XTAL2 N.C.; EA = RST = Port 0 = V_CC. I_CCwould be slightly higher if a crystal oscillator is used.

2. Idle I_CCis measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns, V_IL= V_SS+ 0.5V, V_IH= V_CC

0.5V; XTAL2 N.C; Port 0 = V_CC; EA = RST = V_SS(see Figure 4).

3. Power-down I_CCis measured with all output pins disconnected; EA = V_SS, PORT 0 = V_CC; XTAL2 NC.; RST = V_SS(see Fig-

ure 5).

4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V_OLs of ALE and Ports 1

and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0

transitions during bus operation. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed

0.45V with maxi V_OLpeak 0.6V. The use of a Schmitt Trigger is not necessary.

5. Under steady state (non-transient) conditions, I_OLmust be externally limited as follows:

Maximum I_OLper port pin: 10 mA

Maximum I_OLper 8-bit port:

Port 0: 26 mA

Ports 1, 2 and 3: 15 mA

Maximum total I_OLfor all output pins: 71 mA

4149N–AERO–04/07

If I_OLexceeds the test condition, V_OLmay exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test conditions.

6. Operating I_CCis measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns, V_IL= V_SS+ 0.5V,

V_IH= V_CC- 0.5V; XTAL2 N.C.; EA = Port 0 = V_CC; RST = V_SS. The internal ROM runs the code 80 FE (label: SJMP label). I_CC

would be slightly higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is

the worst case.

Figure 2. I_CCTest Condition, Under Reset

V_CC

I_CC

V_CC

RST

XTAL2

XTAL1

(NC)

CLOCK

SIGNAL

V_SS

All other pins are disconnected.

Figure 3. Operating I_CCTest Condition

V_CC

I_CC

V_CC

Reset = Vss after a high pulse

during at least 24 clock cycles

RST

(NC)

CLOCK

XTAL2

XTAL1

SIGNAL

All other pins are disconnected.

V_SS

Figure 4. I_CCTest Condition, Idle Mode

V_CC

I_CC

V_CC

Reset = Vss after a high pulse

during at least 24 clock cycles

V_CC

RST

(NC)

CLOCK

SIGNAL

XTAL2

XTAL1

V_SS

All other pins are disconnected.

80C32E

4149N–AERO–04/07

80C32E

Figure 5. I_CCTest Condition, Power-down Mode

V_CC

I_CC

V_CC

Reset = Vss after a high pulse

during at least 24 clock cycles

RST

(NC)

XTAL2

XTAL1

V_SS

All other pins are disconnected.

Figure 6. Clock Signal Waveform for I_CCTests in Active and Idle Modes

V_CC-0.5V

0.7V_CC

0.2V_CC-0.1

0.45V

T_CLCH

T_CHCL

T_CLCH= T_CHCL= 5ns.

4149N–AERO–04/07

AC Parameters

Each timing symbol has 5 characters. The first character is always a “T” (stands for

time). The other characters, depending on their positions, stand for the name of a signal

or the logical status of that signal. The following is a list of all the characters and what

they stand for.

Example:

T_AVLL= Time for Address Valid to ALE Low.

T_LLPL= Time for ALE Low to PSEN Low.

TA = -55°C to +125°C (Military temperature range); V_SS= 0V; V_CC= 5V 10%;

Load capacitance for Port 0, ALE and PSEN = 100 pF; Load capacitance for all other

outputs = 80 pF.

Table 4. External Program Memory Characteristics (ns)

30 MHz

Symbol

T_LHLL

T_AVLL

T_LLAX

T_LLIV

Parameter

Min Max

ALE Pulse Width

100

Address Valid to ALE

Address Hold After ALE

ALE to Valid Instruction In

ALE to PSEN

T_LLPL

T_PLPH

T_PLIV

PSEN Pulse Width

PSEN to Valid Instruction In

Input Instruction Hold After PSEN

Input Instruction Float After PSEN

PSEN to Address Valid

Address to Valid Instruction In

PSEN Low to Address Float

T_PXIX

T_PXIZ

T_PXAV

T_AVIV

130

T_PLAZ

Figure 7. External Program Memory Read Cycle

12 T_CLCL

T_LHLL

T_LLIV

T_LLPL

ALE

PSEN

T_PLPH

T_PXAV

T_PXIZ

T_LLAX

T_AVLL

T_PLIV

TPLAZ

T_PXIX

INSTR IN

PORT 0

PORT 2

INSTR IN

A0-A7

INSTR IN

T_AVIV

ADDRESS A8-A15

ADDRESS

OR SFR-P2

ADDRESS A8-A15

80C32E

4149N–AERO–04/07

80C32E

Table 5. External Data Memory Characteristics (ns)

30 MHz

min max

180

Symbol

T_RLRH

T_WLWH

T_RLDV

T_RHDX

T_RHDZ

T_LLDV

Parameter

RD Pulse Width

WR Pulse Width

180

RD to Valid Data In

Data Hold After RD

Data Float After RD

ALE to Valid Data In

Address to Valid Data In

ALE to WR or RD

135

235

T_AVDV

T_LLWL

260

115

T_AVWL

T_QVWX

T_QVWH

T_WHQX

T_RLAZ

Address to WR or RD

Data Valid to WR Transition

Data set-up to WR High

Data Hold After WR

RD Low to Address Float

RD or WR High to ALE high

215

T_WHLH

Figure 8. External Data Memory Write Cycle

T_WHLH

T_LLDV

ALE

PSEN

T_LLWL

T_RLRH

T_RLDV

T_RHDZ

T_AVDV

T_LLAX

T_RHDX

DATA IN

PORT 0

A0-A7

T_RLAZ

T_AVWL

ADDRESS

OR SFR-P2

PORT 2

ADDRESS A8-A15 OR SFR P2

4149N–AERO–04/07

Figure 9. External Data Memory Read Cycle

T_WHLH

ALE

PSEN

T_LLWL

T_WLWH

T_QVWX

T_WHQX

T_LLAX

A0-A7

T_QVWH

DATA OUT

PORT 0

T_AVWL

ADDRESS

OR SFR-P2

PORT 2

ADDRESS A8-A15 OR SFR P2

Table 6. Serial Port Timing – Shift Register Mode (ns)

30 MHz

Symbol

T_XLXL

Parameter

Min Max

Serial port clock cycle time

400

300

T_QVHX

T_XHQX

T_XHDX

T_XHDV

Output data set-up to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

300

Figure 10. Shift Register Timing Waveforms

INSTRUCTION

ALE

T_XLXL

CLOCK

T_XHQX

T_QVXH

OUTPUT DATA

T_XHDX

SET TI

VALID

SET RI

T_XHDV

WRITE to SBUF

INPUT DATA

VALID

CLEAR RI

80C32E

4149N–AERO–04/07

80C32E

Table 7. External Clock Drive Characteristics (XTAL1)

Symbol

T_CLCL

Parameter

Oscillator Period

High Time

Low Time

Min

33.33

Max

Unit

T_CHCX

T_CLCX

T_CLCH

T_CHCL

Rise Time

Fall Time

Figure 11. External Clock Drive Waveforms

V_CC-0.5V

0.45 V

0.7V_CC

0.2V_CC-0.1V

T_CHCL

T_CHCX

T_CLCH

T_CLCX

T_CLCL

Figure 12. AC Testing Input/Output Waveforms

V_CC-0.5V

0.45V

0.2V_CC+0.9

0.2V_CC-0.1

INPUT/OUTPUT

AC inputs during testing are driven at V_CC- 0.5 for a logic “1” and 0.45V for a logic “0”.

Timing measurement are made at V_IHmin for a logic “1” and V_ILmax for a logic “0”.

Figure 13. Float Waveforms

FLOAT

V_OH-0.1V

V_LOAD

V_LOAD+0.1V

V_LOAD-0.1V

V_OL+0.1V

For timing purposes a port pin is no longer floating when a 100 mV change from load

voltage occurs and begins to float when a 100 mV change from the loaded V_OH/V_OLlevel

occurs. I_OL/I_OH

≥

20 mA.

4149N–AERO–04/07

Figure 14. Clock Waveforms

STATE1

P1P2

STATE2

P1P2

STATE3

P1P2

STATE4

P1P2

STATE4

STATE5

P1P2

STATE6

P1P2

STATE5

P1P2

INTERNAL

CLOCK

P1P2

XTAL2

ALE

THESE SIGNALS ARE NOT ACTIVATED DURING THE

EXECUTION OF A MOVX INSTRUCTION

EXTERNAL PROGRAM MEMORY FETCH

PSEN

PCL OUT

DATA

SAMPLED

FLOAT

DATA

SAMPLED

FLOAT

SAMPLED

FLOAT

INDICATES ADDRESS

P2 (EXT)

TRANSITIONS

READ CYCLE

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

DPL OR Rt OUT

FLOAT

INDICATES DPH OR P2 SFR TO PCH TRANSITION

WRITE CYCLE

PCL OUT (EVEN IF

MEMORY IS INTERNAL)

DPL OR Rt OUT

DATA OUT

INDICATES DPH OR P2 SFR TO PCH TRANSITION

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

PORT OPERATION

OLD DATA

P0 PINS SAMPLED

NEW DATA

P0 PINS SAMPLED

MOV DEST P0

P1, P2, P3 PINS SAMPLED

RXD SAMPLED

P1, P2, P3 PINS SAMPLED

MOV DEST PORT (P1, P2,

(INCLUDES INT0, INT1, TO, T1)

RXD SAMPLED

SERIAL PORT SHIFT CLOCK

TXD (MODE 0)

This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however,

ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propaga-

tion also varies from output to output and component. Typically though (T_A=25°C fully loaded) RD and WR propagation

delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC

specifications.

80C32E

4149N–AERO–04/07

80C32E

Ordering Information

Table 8. Possible Order Entries

Temperature

Range

Part Number

Speed (MHz)

Package

Quality Flow

MC-80C32E-30-E

MJ-80C32E-30-E

5962-0051801QQC

5962-0051801QXC

5962-0051801VQC

5962-0051801VXC

952100201

25°C

Side Brazed 40-pin (.6)

MQFPJ 44-pin

Engineering samples

QML-Q

-55°C to +125°C Side Brazed 40 pin (.6)

-55°C to +125°C MQFPJ 44-pin

-55°C to +125°C Side Brazed 40 pin (.6)

-55°C to +125°C MQFPJ 44-pin

-55°C to +125°C Side Brazed 40 pin (.6)

-55°C to +125°C MQFPJ 44-pin

-55°C to +125°C Die

QML-Q

QML-V

ESCC

952100202

ESCC

MM0-80C32E-30-E⁽¹⁾

MM0-80C32E-30-SV

Engineering samples

QML-V

-55°C to +125°C Die

Note:

1. Please contact Atmel for availability.

4149N–AERO–04/07

Package Drawings

40-pin Side Braze (600 mils)

80C32E

4149N–AERO–04/07

80C32E

44-pin Multilayer Quad Flat Pack

4149N–AERO–04/07

Atmel Headquarters

Atmel Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 487-2600

Memory

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

TEL (49) 71-31-67-0

FAX (49) 71-31-67-2340

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 436-4314

Europe

Atmel Sarl

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 436-4314

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL 1(719) 576-3300

FAX 1(719) 540-1759

TEL (41) 26-426-5555

FAX (41) 26-426-5500

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

TEL (33) 2-40-18-18-18

FAX (33) 2-40-18-19-60

Biometrics/Imaging/Hi-Rel MPU/

High Speed Converters/RF Data-

com

Avenue de Rochepleine

BP 123

38521 Saint-Egreve Cedex, France

TEL (33) 4-76-58-30-00

FAX (33) 4-76-58-34-80

Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimhatsui

East Kowloon

Hong Kong

TEL (852) 2721-9778

FAX (852) 2722-1369

ASIC/ASSP/Smart Cards

Zone Industrielle

13106 Rousset Cedex, France

TEL (33) 4-42-53-60-00

FAX (33) 4-42-53-60-01

Japan

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL 1(719) 576-3300

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

FAX 1(719) 540-1759

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

TEL (44) 1355-803-000

FAX (44) 1355-242-743

e-mail

[email protected]

Web Site

http://www.atmel.com

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise,to anyintellectu-

alproperty right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-TIONS OF

SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORYWAR-

RANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICU-

LARPURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL

OR INCIDEN-TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMA-

TION) ARISING OUTOF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAM-

AGES. Atmel makes norepresentationsor warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make

changes to specificationsand product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein.

Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended,

authorized, or warranted for useas components in applications intended to support or sustainlife.

tered trademarks, of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

4149N–AERO–04/07

/xM

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