100324 概述
Low Power Hex TTL-to-ECL Translator 低功耗六角TTL至ECL转换器
100324 数据手册
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PDF下载July 1988
Revised August 2000
100324
Low Power Hex TTL-to-ECL Translator
General Description
Features
The 100324 is a hex translator, designed to convert TTL
logic levels to 100K ECL logic levels. The inputs are com-
patible with standard or Schottky TTL. A common Enable
(E), when LOW, holds all inverting outputs HIGH and holds
all true outputs LOW. The differential outputs allow each
circuit to be used as an inverting/non-inverting translator, or
as a differential line driver. The output levels are voltage
compensated over the full −4.2V to −5.7V range.
■ Pin/function compatible with 100124
■ Meets 100124 AC specifications
■ 50% power reduction of the 100124
■ Differential outputs
■ 2000V ESD protection
■ −4.2V to −5.7V operating range
■ Available to MIL-STD-883
When the circuit is used in the differential mode, the
100324, due to its high common mode rejection, over-
comes voltage gradients between the TTL and ECL ground
systems. The VEE and VTTL power may be applied in either
■ Available to industrial grade temperature range
(PLCC package only)
order.
The 100324 is pin and function compatible with the 100124
with similar AC performance, but features power dissipa-
tion roughly half of the 100124 to ease system cooling
requirements.
Ordering Code:
Order Number Package Number
Package Description
100324SC
100324PC
100324QC
100324QI
M24B
N24E
V28A
V28A
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
24-Pin DIP/SOIC
28-Pin PLCC
© 2000 Fairchild Semiconductor Corporation
DS009878
www.fairchildsemi.com
Pin Descriptions
Truth Table
Pin Names
Description
Data Inputs
Enable Input
Inputs
Outputs
D0–D5
E
Dn
Qn
Qn
E
L
X
L
L
L
H
H
L
Q0–Q5
Q0–Q5
Data Outputs
Complementary
Data Outputs
H
H
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
Logic Diagram
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature (TSTG
Maximum Junction Temperature (TJ)
EE Pin Potential to Ground Pin
)
−65°C to +150°C
+150°C
Case Temperature (TC)
Commercial
V
−7.0V to +0.5V
−0.5V to +6.0V
−0.5V to +6.0V
−50 mA
0°C to +85°C
−40°C to +85°C
−5.7V to −4.2V
VTTL Pin Potential to Ground Pin
Input Voltage (DC)
Industrial
Supply Voltage (VEE
)
Output Current (DC Output HIGH)
ESD (Note 2)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
≥2000V
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
DC Electrical Characteristics (Note 3)
VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C, VTTL = +4.5V to +5.5V
Symbol
Parameter
Output HIGH Voltage
Min
Typ
−955
−1705
Max
−870
Units
Conditions
Loading with
VOH
VOL
−1025
−1830
−1035
V
IN =VIH (Max)
or VIL (Min)
IN = VIH(Min)
mV
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
−1620
50Ω to −2.0V
Loading with
50Ω to −2.0V
VOHC
VOLC
VIH
V
mV
V
−1610
or VIL (Max)
2.0
0
5.0
Guaranteed HIGH
Signal for All Inputs
Guaranteed LOW
Signal for All Inputs
VIL
Input LOW Voltage
0.8
V
V
VCD
IIH
Input Clamp Diode Voltage
Input HIGH Current
Data
−1.2
I
IN = −18 mA
IN = +2.4V,
All Other Inputs VIN = GND
V
20
µA
Enable
120
Input HIGH Current
Breakdown Test, All Inputs
Input LOW Current
Data
V
IN = +5.5V,
All Other Inputs = GND
VIN = +0.4V,
1.0
mA
mA
IIL
−0.9
−5.4
−70
All Other Inputs VIN = VIH
Enable
IEE
VEE Power Supply Current
VTTL Power Supply Current
−45
−22
mA
mA
All Inputs VIN = +4.0V
All Inputs VIN = GND
ITTL
25
38
Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under “worst case” conditions.
DIP AC Electric Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND, VTTL = +4.5V to +5.5V
T
C = 0°C
T
C = +25°C
TC = +85°C
Symbol
Parameter
Units
ns
Conditions
Min
Max
Min
Max
Min
Max
tPLH
tPHL
tTLH
tTHL
Propagation Delay
0.50
0.45
3.00
1.80
0.50
2.90
0.50
3.00
Data and Enable to Output
Transition Time
Figures 2, 1
0.45
1.80
0.45
1.80
ns
20% to 80%, 80% to 20%
3
www.fairchildsemi.com
Commercial Version (Continued)
SOIC and PLCC AC Electrical Characteristics
V
EE = −4.2V to −5.7V, VCC = VCCA = GND, VTTL = +4.5V to +5.5V
T
C = 0°C
T
C = +25°C
TC = +85°C
Symbol
Parameter
Units
ns
Conditions
Min
Max
Min
Max
Min
Max
tPLH
tPHL
tTLH
tTHL
tOSHL
Propagation Delay
0.50
0.45
2.80
1.70
0.50
2.70
0.50
2.80
Data and Enable to Output
Transition Time
Figures 2, 1
0.45
1.70
0.95
0.45
1.70
0.95
ns
20% to 80%, 80% to 20%
Maximum Skew Common Edge
Output-to-Output Variation
Data to Output Path
PLCC Only
(Note 4)
0.95
0.70
1.60
1.20
ns
ns
ns
ns
tOSLH
tOST
tPS
Maximum Skew Common Edge
Output-to-Output Variation
Data to Output Path
PLCC Only
(Note 4)
0.70
1.60
1.20
0.70
1.60
1.20
Maximum Skew Opposite Edge
Output-to-Output Variation
Data to Output Path
PLCC Only
(Note 4)
Maximum Skew
PLCC Only
(Note 4)
Pin (Signal) Transition Variation
Data to Output Path
Note 4: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-
aged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite
directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design.
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4
Industrial Version
DC Electrical Characteristics (Note 5)
V
EE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C, VTTL = +4.5V to +5.5V
T
C = −40°C
TC = 0°C to +85°C
Symbol
Parameter
Units
Conditions
Loading with
Min
Max
−870
Min
Max
−870
VOH
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
−1085
−1830
−1095
−1025
−1830
−1035
V
IN =VIH (Max)
or VIL (Min)
VIN = VIH(Min)
mV
VOL
−1575
−1620
50Ω to −2.0V
Loading with
50Ω to −2.0V
VOHC
VOLC
VIH
mV
V
−1565
−1610
or VIL (Max)
2.0
0
5.0
2.0
0
5.0
Guaranteed HIGH
Signal for All Inputs
Guaranteed LOW
Signal for All Inputs
VIL
Input LOW Voltage
0.8
0.8
V
V
VCD
IIH
Input Clamp Diode Voltage
Input HIGH Current
Data
−1.2
−1.2
I
IN = −18 mA
IN = +2.4V,
All Other Inputs VIN = GND
V
20
20
µA
Enable
120
120
Input HIGH Current
Breakdown Test, All Inputs
Input LOW Current
Data
V
IN = +5.5V,
All Other Inputs = GND
IN = +0.4V,
1.0
1.0
mA
mA
IIL
V
−0.9
−5.4
−70
−0.9
−5.4
−70
All Other Inputs VIN = VIH
Enable
IEE
VEE Power Supply Current
VTTL Power Supply Current
−22
−22
mA
mA
All Inputs VIN = +4.0V
All Inputs VIN = GND
ITTL
38
38
Note 5: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under “worst case” conditions.
AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND, VTTL = +4.5V to +5.5V
T
C = −40°C
T
C = +25°C
TC = +85°C
Symbol
Parameter
Propagation Delay
Units
ns
Conditions
Figures 2, 1
Figures 2, 1
Min
Max
Min
Max
Min
Max
tPLH
tPHL
tTLH
tTHL
0.50
2.80
0.50
2.70
0.50
2.80
Data and Enable to Output
Transition Times
0.35
1.80
0.45
1.70
0.45
1.70
ns
20% to 80%, 80% to 20%
5
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Test Circuit
Note:
•
VCC, VCCA = 0V, VEE = −4.5V, VTTL = +5.0V, VIH = +3.0V
L1, L2 and L3 = equal length 50Ω impedance lines
•
•
R
T = 50Ω terminator internal to scope
•
Decoupling 0.1 µF from GND to VCC, VEE and VTTL
•
•
All unused outputs are loaded with 50Ω to −2V or with equivalent ECL terminator network
C
L = Fixture and stray capacitance ≤ 3 pF
FIGURE 1. AC Test Circuit
Switching Waveform
FIGURE 2. Propagation Delay and Transition Times
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6
Physical Dimensions inches (millimeters) unless otherwise noted
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
Package Number N24E
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square)
Package Number V28A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
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8
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