MAX517BCSA+T
更新时间：2025-05-02 13:07:59
品牌：MAXIM
描述：D/A Converter, 1 Func, Serial Input Loading, 6us Settling Time, PDSO8, 0.150 INCH, SO-8
概述
规格参数
数据手册
替代型号MAX517BCSA+T 概述
D/A Converter, 1 Func, Serial Input Loading, 6us Settling Time, PDSO8, 0.150 INCH, SO-8 DA转换器 数模转换器
MAX517BCSA+T 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 零件包装代码： | SOIC |
| 包装说明： | SOP, SOP8,.25 | 针数： | 8 |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | Factory Lead Time： | 6 weeks |
| 风险等级： | 5.06 | Is Samacsys： | N |
| 最大模拟输出电压： | 5 V | 最小模拟输出电压： | |
| 转换器类型： | D/A CONVERTER | 输入位码： | BINARY |
| 输入格式： | SERIAL | JESD-30 代码： | R-PDSO-G8 |
| JESD-609代码： | e3 | 长度： | 4.9 mm |
| 湿度敏感等级： | 1 | 位数： | 8 |
| 功能数量： | 1 | 端子数量： | 8 |
| 最高工作温度： | 70 °C | 最低工作温度： | |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | SOP |
| 封装等效代码： | SOP8,.25 | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE | 峰值回流温度（摄氏度）： | 260 |
| 电源： | 5 V | 认证状态： | Not Qualified |
| 座面最大高度： | 1.75 mm | 标称安定时间 (tstl)： | 6 µs |
| 子类别： | Other Converters | 最大压摆率： | 3 mA |
| 标称供电电压： | 5 V | 表面贴装： | YES |
| 技术： | BICMOS | 温度等级： | COMMERCIAL |
| 端子面层： | Matte Tin (Sn) | 端子形式： | GULL WING |
| 端子节距： | 1.27 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 宽度： | 3.9 mm |
| Base Number Matches： | 1 |
MAX517BCSA+T 数据手册
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PDF下载19-0393; Rev 0; 5/95
2 -Wire S e ria l 8 -Bit DACs w it h
Ra il-t o -Ra il Ou t p u t s
78/MAX519
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ Single +5V Supply
♦ Simple 2-Wire Serial Interface
♦ I2C Compatible
♦ Output Buffer Amplifiers Swing Rail-to-Rail
♦ Space-Saving 8-pin DIP/SO Packages
(MAX517/MAX518)
The MAX517/MAX518/MAX519 are 8-bit voltage output
digital-to-analog converters (DACs) with a simple 2-wire
serial interface that allows communication between
multiple devices. They operate from a single 5V supply
and their internal precision buffers allow the DAC out-
puts to swing rail-to-rail.
The MAX517 is a single DAC and the MAX518/MAX519
are dual DACs. The MAX518 uses the supply voltage
as the reference for both DACs. The MAX517 has a ref-
e re nc e inp ut for its s ing le DAC a nd e a c h of the
MAX519’s two DACs has its own reference input.
♦ Reference Input Range Includes Both Supply Rails
(MAX517/MAX519)
♦ Power-On Reset Clears All Latches
♦ 4µA Power-Down Mode
The MAX517/MAX518/MAX519 feature a serial interface
and internal software protocol, allowing communication
at data rates up to 400kbps. The interface, combined
with the double-buffered input configuration, allows the
DAC registers of the dual devices to be updated indi-
vidually or simultaneously. In addition, the devices can
be put into a low-power shutdown mode that reduces
supply current to 4µA. Power-on reset ensures the DAC
outputs are at 0V when power is initially applied.
______________Ord e rin g In fo rm a t io n
TUE
(LSB)
PART
TEMP. RANGE PIN-PACKAGE
MAX517ACPA
MAX517BCPA
MAX517ACSA
MAX517BCSA
MAX517BC/D
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
8 Plastic DIP
8 Plastic DIP
8 SO
1
1.5
1
8 SO
1.5
1.5
Dice*
The MAX517/MAX518 are available in space-saving 8-
pin DIP and SO packages. The MAX519 comes in 16-
pin DIP and SO packages.
Ordering Information continued at end of data sheet.
*Dice are specified at T = +25°C, DC parameters only.
A
**Contact factory for availability and processing to MIL-STD-883.
________________________Ap p lic a t io n s
Minimum Component Analog Systems
Digital Offset/Gain Adjustment
________________Fu n c t io n a l Dia g ra m
V
DD
7
Industrial Process Control
Automatic Test Equipment
REF
1
Programmable Attenuators
INPUT
LATCH 0
OUTPUT
LATCH 0
DAC0
OUT0
_________________P in Co n fig u ra t io n s
REF
8
INPUT
LATCH 1
OUTPUT
LATCH 1
DAC1
OUT1
TOP VIEW
1
2
3
4
8
7
6
5
OUT0
GND
SCL
8-BIT
SHIFT
REGISTER
OUT1 (REF0)
MAX518
ADDRESS
COMPARATOR
V
DD
MAX517
MAX518
3
4
AD0
AD1
SCL
SDA
SDA
START/STOP
DETECTOR
DECODE
DIP/SO
( ) ARE FOR MAX517
Pin Configurations continued at end of data sheet.
6
5
2
GND
AD0 AD1
________________________________________________________________ Maxim Integrated Products
1
Ca ll t o ll fre e 1 -8 0 0 -9 9 8 -8 8 0 0 fo r fre e s a m p le s o r lit e ra t u re .
2 -Wire S e ria l 8 -Bit DACs w it h
Ra il-t o -Ra il Ou t p u t s
ABSOLUTE MAXIMUM RATINGS
DD
OUT_ ..........................................................-0.3V to (V + 0.3V)
REF_ (MAX517, MAX519)...........................-0.3V to (V + 0.3V)
V
to GND..............................................................-0.3V to +6V
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)..842mW
16-Pin Narrow SO (derate 8.70mW/°C above +70°C) ...696mW
16-Pin CERDIP (derate 10.00mW/°C above +70°C)......800mW
Operating Temperature Ranges
DD
DD
DD
AD_.............................................................-0.3V to (V + 0.3V)
SCL, SDA to GND.....................................................-0.3V to +6V
Maximum Current into Any Pin............................................50mA
MAX51_C_ _ .......................................................0°C to +70°C
MAX51_E_ _.....................................................-40°C to +85°C
MAX51_MJB ..................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Continuous Power Dissipation (T = +70°C)
A
8-Pin Plastic DIP (derate 9.09mW/°C above +70°C) ...727mW
8-Pin SO (derate 5.88mW/°C above +70°C)................471mW
8-Pin CERDIP (derate 8.00mW/°C above +70°C)........640mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = 5V ±10%, V
= 4V (MAX517, MAX519), R = 10kΩ, C = 100pF, T = T
to T , unless otherwise noted.
MAX
DD
REF_
L
L
A
MIN
Typical values are T = +25°C.)
A
PARAMETER
STATIC ACCURACY
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
8
Bits
LSB
LSB
MAX51 _A
MAX51 _B
±1
Total Unadjusted Error (Note 1)
Differential Nonlinearity (Note 1)
TUE
DNL
±1.5
±1
18
Guaranteed monotonic
MAX51 _C
MAX51 _E
78/MAX519
Zero-Code Error
ZCE
Code = 00 hex
20
mV
MAX51 _BM
MAX51 _C
MAX51 _E
20
±1
±1
Zero-Code-Error Supply Rejection
Code = 00 hex
Code = 00 hex
mV
MAX51 _BM
±1
Zero-Code-Error Temperature Coefficient
±10
µV/°C
MAX51 _C
MAX51 _E
MAX51 _BM
±18
±20
±20
Code = FF hex,
MAX518 unloaded
Full-Scale Error
mV
MAX51 _C
MAX51 _E
MAX51 _BM
±1
±1
MAX517, MAX519
Code = FF hex
Full-Scale-Error Supply Rejection
mV
V
= +5V ±10%
DD
±1
Full-Scale-Error Temperature Coefficient
Code = FF hex
±10
µV/°C
2
_______________________________________________________________________________________
2 -Wire S e ria l 8 -Bit DACs w it h
Ra il-t o -Ra il Ou t p u t s
78/MAX519
ELECTRICAL CHARACTERISTICS (continued)
(V = 5V ±10%, V
= 4V (MAX517, MAX519), R = 10kΩ, C = 100pF, T = T
to T , unless otherwise noted.
MAX
DD
REF_
L
L
A
MIN
Typical values are T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
REFERENCE INPUTS (MAX517, MAX519)
Input Voltage Range
0
V
DD
V
Input Resistance
Input Current
R
Code = 55 hex (Note 2)
Power-down mode
16
24
kΩ
µA
pF
IN
±10
Input Capacitance
Code = FF hex (Note 3)
30
-60
-70
Channel-to-Channel Isolation
(MAX519)
(Note 4)
(Note 5)
dB
dB
AC Feedthrough
DAC OUTPUTS
Full-Scale Output Voltage
0
V
DD
V
OUT_ = 4V, 0mA to 2.5mA
0.25
1.5
MAX51 _C/E, REF_ = V
DD
(MAX517, MAX519), code = FF hex,
0µA to 500µA
Output Load Regulation
LSB
µA
MAX51 _M, REF_ = V
(MAX517, MAX519), code = FF hex,
0µA to 500µA
DD
2.0
Output Leakage Current
DIGITAL INPUTS SCL, SDA
Input High Voltage
OUT_ = 0V to V , power-down mode
±10
DD
V
0.7V
V
V
IH
DD
Input Low Voltage
V
IL
0.3V
DD
Input Leakage Current
Input Hysteresis
I
0V ≤ V ≤ V
±10
µA
V
IN
IN
DD
V
0.05V
DD
HYST
Input Capacitance
C
(Note 6)
10
pF
IN
DIGITAL INPUTS AD0, AD1, AD2, AD3
Input High Voltage
V
2.4
V
V
IH
Input Low Voltage
V
IL
0.8
Input Leakage Current
DIGITAL OUTPUT SDA (Note 7)
I
IN
V
IN
= 0V to V
DD
±10
µA
I
= 3mA
= 6mA
0.4
0.6
±10
10
SINK
Output Low Voltage
V
V
OL
I
SINK
Three-State Leakage Current
Three-State Output Capacitance
DYNAMIC PERFORMANCE
I
V
= 0V to V
DD
µA
pF
L
IN
C
(Note 6)
OUT
MAX51 _C
MAX51 _E
MAX51 _M
2.0
1.4
1.0
Voltage Output Slew Rate
Positive and negative
V/µs
Output Settling Time
Digital Feedthrough
To 1/2 LSB, 10kΩ and 100pF load (Note 8)
Code = 00 hex, all digital inputs from 0V to V
6
5
µs
nV-s
DD
_______________________________________________________________________________________
3
2 -Wire S e ria l 8 -Bit DACs w it h
Ra il-t o -Ra il Ou t p u t s
ELECTRICAL CHARACTERISTICS (continued)
(V = 5V ±10%, V
= 4V (MAX517, MAX519), R = 10kΩ, C = 100pF, T = T
to T , unless otherwise noted.
MAX
DD
REF_
L
L
A
MIN
Typical values are T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Digital-Analog Glitch Impulse
Code 128 to 127
12
nV-s
Signal to Noise + Distortion
Ratio (MAX517, MAX519)
V
= 4Vp-p at 1kHz, V = 5V,
REF_ DD
SINAD
87
dB
Code = FF hex
Multiplying Bandwidth
(MAX517, MAX519)
V
REF_
= 4Vp-p, 3dB bandwidth
1
MHz
Wideband Amplifier Noise
POWER REQUIREMENTS
Supply Voltage
60
µV
RMS
V
4.5
5.5
3.0
3.5
5
V
DD
MAX517C
1.5
1.5
2.5
2.5
4
Normal mode, output(s)
unloaded, all digital inputs
MAX517E/M
mA
µA
Supply Current
I
DD
MAX518C, MAX519C
at 0V or V
DD
MAX518E/M, MAX519E/M
6
Power-down mode
20
TIMING CHARACTERISTICS
(V = 5V ±10%, T = T
to T
, unless otherwise noted. Typical values are T = +25°C.)
DD
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
400
UNITS
Serial Clock Frequency
f
0
kHz
SCL
78/MAX519
Bus Free Time Between a STOP and a
START Condition
t
1.3
µs
BUF
Hold Time, (Repeated) Start Condition
Low Period of the SCL Clock
t
t
0.6
1.3
0.6
0.6
0
µs
µs
µs
µs
µs
ns
ns
ns
ns
µs
pF
ns
HD, STA
t
LOW
High Period of the SCL Clock
t
HIGH
Setup Time for a Repeated START Condition
Data Hold Time
SU, STA
HD, DAT
t
(Note 9)
0.9
Data Setup Time
t
100
SU, DAT
Rise Time of Both SDA and SCL Signals, Receiving
Fall Time of Both SDA and SCL Signals, Receiving
Fall Time of SDA Transmitting (Note 7)
Setup Time for STOP Condition
t
(Note 10)
(Note 10)
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
0.6
300
300
250
R
t
t
F
F
I
≤ 6mA (Note 10)
SINK
t
SU, STO
Cb
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
400
50
t
SP
(Notes 6, 11)
0
Note 1: For the MAX518 (full-scale = V ) the last three codes are excluded from the TUE and DNL specifications, due to the limited
DD
output swing when loaded with 10kΩ to GND.
Note 2: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex.
Note 3: Input capacitance is code dependent. The highest input capacitance occurs at code FF hex.
Note 4:
V
= 4Vp-p, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the
REF_
code of all other DACs to 00 hex.
= 4Vp-p, 10kHz, DAC code = 00 hex.
Note 5:
V
REF_
Note 6: Guaranteed by design.
Note 7: I2C compatible mode.
Note 8: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.
Note 9: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V of the SCL signal) in order to
IL
bridge the undefined region of SCL’s falling edge.
Note 10: Cb = total capacitance of one bus line in pF. t and t measured between 0.3V and 0.7V
.
R
F
DD DD
Note 11: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
4
_______________________________________________________________________________________
2 -Wire S e ria l 8 -Bit DACs w it h
Ra il-t o -Ra il Ou t p u t s
78/MAX519
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(T = +25°C, unless otherwise noted.)
A
FULL-SCALE ERROR vs. SOURCE CURRENT
MAX517/MAX519 SUPPLY CURRENT
vs. TEMPERATURE
ZERO-CODE ERROR
vs. SINK CURRENT
(V = V
)
REF DD
10
3.0
2.5
2.0
1.5
1.0
0.5
0
10
V
= V = 5V
REF
DD
V
= 5.5V
V
= V = 5V
REF
DD
DD
DAC CODE = FF HEX
LOAD TO AGND
REF_ INPUTS = 0.6V
ALL DIGITAL INPUTS to V
DAC CODE = 00 HEX
LOAD to V
DD
DD
8
6
4
2
0
8
6
4
2
0
MAX519, DAC CODE = FF HEX
MAX517, DAC CODE = FF HEX
MAX517, MAX519
DAC CODE = 00 HEX
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OUTPUT SOURCE CURRENT (mA)
-55 -35 -15
5
25 45 65 85 105 125
0
0.5
1.0
1.5
2.0
TEMPERATURE (°C)
OUTPUT SINK CURRENT (mA)
MAX518 SUPPLY CURRENT
vs. DAC CODE
MAX518 SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
3.0
3.5
3.0
6
V
= 5.5V
V
= 5.5V
V
= 5.5V
DD
BOTH DACS SET
DD
ALL DIGITAL INPUTS to V
DD
AD0, AD1 = V
DD
DD
2.5
2.0
1.5
1.0
5
4
3
2
1
0
2.5
2.0
1.5
1.0
DAC CODE = 1B HEX
DAC CODE = FF HEX
DAC CODE = 00 HEX
0.5
0
0.5
0
-55 -35
5
45 65 85 105 125
0
32 64 96 128 160 192 224 256
DAC CODE (DECIMAL)
-15
25
-55 -35 -15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
MAX517/MAX519 SUPPLY CURRENT
vs. REFERENCE VOLTAGE
MAX517/MAX519 REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
POSITIVE FULL-SCALE STEP RESPONSE
2.5
2.0
1.5
1.0
0.5
0
V
= 5V
DD
DAC CODE(S) FF HEX
0
-4
MAX519
OUT0
1V/div
4V SINE
P-P
-8
-12
-16
2V SINE
P-P
1V SINE
P-P
0.5V SINE
P-P
MAX517
V
V
REF
= 5V
= SINE WAVE
CENTERED AT 2.5V
1k 10k 100k
FREQUENCY (Hz)
DD
1µs/div
1M
10M
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
OUT0 LOADED WITH 10kΩ II 100pF
REF0 = 4V (MAX517/MAX519)
DAC CODE = 00 HEX to FF HEX
REFERENCE VOLTAGE (V)
_______________________________________________________________________________________
5
2 -Wire S e ria l 8 -Bit DACs w it h
Ra il-t o -Ra il Ou t p u t s
______________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(T = +25°C, unless otherwise noted.)
A
WORST-CASE 1LSB STEP CHANGE
NEGATIVE FULL-SCALE STEP RESPONSE
OUT0
20mV/div
AC COUPLED
OUT0
1V/div
1µs/div
OUT0 LOADED WITH 10kΩ II 100pF
REF0 = 4V (MAX517/MAX519)
500ns/div
REF0 = 5V (MAX517/MAX519)
DAC CODE = 80 HEX to 7F HEX
MAX517/MAX519
REFERENCE FEEDTHROUGH AT 1kHz
DAC CODE = FF HEX to 00 HEX
CLOCK FEEDTHROUGH
A
A
B
78/MAX519
B
A = SCL, 400kHz, 5V/div
B = OUT0, 5mV/div
DAC CODE = 7F HEX
A = REF0, 1V/div (4V
)
P-P
B = OUT0, 50µV/div, UNLOADED
FILTER PASSBAND = 100Hz to 10kHz
DAC CODE = 00 HEX
REF0 = 5V (MAX517/MAX519)
MAX517/MAX519
REFERENCE FEEDTHROUGH AT 10kHz
MAX517/MAX519
REFERENCE FEEDTHROUGH AT 100kHz
A
B
A
B
A = REF0, 1V/div (4V
)
P-P
A = REF0, 1V/div (4V )
P-P
B = OUT0, 50µV/div, UNLOADED
FILTER PASSBAND = 1kHz to 100kHz
DAC CODE = 00 HEX
B = OUT0, 50µV/div, UNLOADED
FILTER PASSBAND = 10kHz to 1MHz
DAC CODE = 00 HEX
6
_______________________________________________________________________________________
2 -Wire S e ria l 8 -Bit DACs w it h
Ra il-t o -Ra il Ou t p u t s
78/MAX519
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
MAX517
MAX518
MAX519
1
2
1
2
1
OUT0
GND
AD3
DAC0 Voltage Output
Ground
4
—
3
—
3
5
Address Input 3; sets IC’s slave address
Serial Clock Input
6
SCL
SDA
AD2
4
4
8
Serial Data Input
—
5
—
5
9
Address Input 2; sets IC’s slave address
Address Input 1; sets IC’s slave address
Address Input 0; sets IC’s slave address
Power Supply, +5V; used as reference for MAX518
Reference Voltage Input for DAC1
Reference Voltage Input for DAC0
DAC1 Voltage Output
10
AD1
6
6
11
AD0
7
7
12
13
VDD
REF1
REF0
OUT1
N.C.
—
8
—
—
8
15
—
—
16
—
2, 3, 7, 14
No Connect—not internally connected.
_______________De t a ile d De s c rip t io n
V
DD
REF0
(REF1)
S e ria l In t e rfa c e
The MAX517/MAX518/MAX519 us e a s imp le 2-wire
serial interface requiring only two I/O lines (2-wire bus)
of a standard microprocessor (µP) port. Figure 2 shows
the timing d ia g ra m for s ig na ls on the 2-wire b us .
Figure 3 shows a typical application. The 2-wire bus can
ha ve s e ve ra l d e vic e s (in a d d ition to the MAX517/
MAX518/MAX519) attached. The two bus lines (SDA and
SCL) must be high when the bus is not in use. When in
use, the port bits are toggled to generate the appropriate
signals for SDA and SCL. External pull-up resistors are
not re q uire d on the s e line s . The MAX517/MAX518/
MAX519 can be used in applications where pull-up resis-
INPUT
OUTPUT
LATCH 0
DAC0
OUT0
LATCH 0
INPUT
LATCH 1
OUTPUT
LATCH 1
DAC1
(OUT1)
MAX519 ONLY
2
tors are required (such as in I C systems) to maintain
compatibility with existing circuitry.
8-BIT
SHIFT
REGISTER
ADDRESS
COMPARATOR
The MAX517/MAX518/MAX519 are receive-only devices
and must be controlled by a bus master device. They
operate at SCL rates up to 400kHz. A master device
sends information to the devices by transmitting their
address over the bus and then transmitting the desired
information. Each transmission consists of a START
condition, the MAX517/MAX518/MAX519’s programm-
able slave-address, one or more command-byte/out-
put-byte pairs (or a command byte alone, if it is the last
byte in the transmission), and finally, a STOP condition
(Figure 4).
MAX517/MAX519
SCL
SDA
START/STOP
DETECTOR
DECODE
AD0 (AD2)
AD1 (AD3)
GND
( ) ARE FOR MAX519
Figure 1. MAX517/MAX519 Functional Diagram
_______________________________________________________________________________________
7
2 -Wire S e ria l 8 -Bit DACs w it h
Ra il-t o -Ra il Ou t p u t s
SDA
t
BUF
t
,
t ,
SU STA
SU DAT
t
,
HD STA
t
,
SU STO
t
t ,
HD DAT
LOW
SCL
t
HIGH
t
,
HD STA
t
R
t
F
START CONDITION
REPEATED START CONDITION
STOP CONDITION START CONDITION
Figure 2. Two-Wire Serial Interface Timing Diagram
The address byte and pairs of command and output
bytes are transmitted between the START and STOP con-
ditions. The SDA state is allowed to change only while
SCL is low, with the exception of START and STOP condi-
tions. SDA’s state is sampled, and therefore must remain
stable while SCL is high. Data is transmitted in 8-bit
bytes. Nine clock cycles are required to transfer the data
bits to the MAX517/MAX518/MAX519. Set SDA low dur-
ing the 9th clock cycle as the MAX517/MAX518/MAX519
+1V
+4V
REF0
REF1
µC
DUAL
DAC
SDA
SCL
78/MAX519
R
C
1k
MAX519
SCL
SDA
AD0
AD1
AD2
AD3
OFFSET ADJUSTMENT
GAIN ADJUSTMENT
OUT0
OUT1
pull SDA low during this time. R (see Figure 3) limits the
C
current that flows during this time if SDA stays high for
short periods of time.
The START and STOP Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a transmis-
sion with a START condition by transitioning SDA from
high to low while SCL is high (Figure 5). When the mas-
ter has finished communicating with the slave, it issues
a STOP condition by transitioning SDA from low to high
while SCL is high. The bus is then free for another
transmission.
DUAL
DAC
MAX518
SCL
SDA
AD0
AD1
BRIGHTNESS ADJUSTMENT
CONTRAST ADJUSTMENT
OUT0
OUT1
The Slave Address
The MAX517/MAX518/MAX519 each have a 7-bit long
slave address (Figure 6). The first three bits (MSBs) of
the slave address have been factory programmed and
are always 010. In addition, the MAX517 and MAX518
have the next two bits factory programmed to 1s. The
logic state of the address inputs (AD0 and AD1 on the
MAX517/MAX518; AD0, AD1, AD2, and AD3 on the
MAX519) de te rmine the LSB b its of the 7-bit sla ve
address. These input pins may be connected to VDD or
DGND, or they may be actively driven by TTL or CMOS
logic levels. The MAX517/MAX518 have four possible
slave addresses and therefore a maximum of four of
+2.5V
REF0
OUT0
SINGLE
DAC
MAX517
SCL
SDA
AD0
AD1
THRESHOLD ADJUSTMENT
+5V
Figure 3. MAX517/MAX518/MAX519 Application Circuit
_______________________________________________________________________________________
8
2 -Wire S e ria l 8 -Bit DACs w it h
Ra il-t o -Ra il Ou t p u t s
78/MAX519
SLAVE ADDRESS BYTE
COMMAND BYTE
OUTPUT BYTE
SDA
SCL
MSB
LSB
ACK
MSB
LSB ACK
MSB
LSB
ACK
STOP CONDITION
START CONDITION
Figure 4. A Complete Serial Transmission
R2
R1
R0 RST
PD
A0/0 ACK
LSB
X
X
SDA
SDA
MSB
SCL
SCL
START CONDITION
STOP CONDITION
R2, R1, R0: RESERVED BITS. SET TO 0.
RST: RESET BIT, SET TO 1 TO RESET ALL DAC REGISTERS.
Figure 5. All communications begin with a START condition and
end with a STOP condition, both generated by a bus master.
PD: POWER-DOWN BIT. SET TO 1 TO PLACE THE DEVICE IN THE 4µA SHUTDOWN
MODE. SET TO 0 TO RETURN TO THE NORMAL OPERATIONAL STATE.
A0: ADDRESS BIT. DETERMINES WHICH DAC'S INPUT LATCH RECEIVES THE 8 BITS
OF DATA IN THE NEXT BYTE. SET TO 0 FOR MAX517.
SLAVE ADDRESS
ACK: ACKNOWLEDGE BIT. THE MAX517/MAX518/MAX519 PULLS SDA LOW DURING
THE 9TH CLOCK PULSE.
0
1
0
1 or
AD3 AD2
1 or AD1
AD0
0
ACK
X: DON’T CARE.
SDA
SCL
LSB
Figure 7. Command Byte
SLAVE ADDRESS BITS AD0, AD1, AD2, AND AD3 CORRESPOND TO THE LOGIC
STATE OF THE ADDRESS INPUT PINS.
Figure 6. Address Byte
these devices may share the bus. The MAX519 has 16
possible slave addresses. The eighth bit (LSB) in the
slave address byte should be low when writing to the
MAX517/MAX518/MAX519.
ignored. If an output byte follows the command byte,
A0 of the command byte indicates the digital address
of the DAC whose input data latch receives the digital
outp ut d a ta . Se t this b it to 0 whe n writing to the
MAX517. The data is transferred to the DAC’s output
latch during the STOP condition following the transmis-
sion. This allows both DACs of the MAX518/MAX519 to
be updated simultaneously (Figure 8).
The MAX517/MAX518/MAX519 monitor the bus continu-
ously, waiting for a START condition followed by their
slave address. When a device recognizes its slave
address, it is ready to accept data.
Se tting the PD b it hig h p owe rs d own the MAX517/
MAX518/MAX519 following a STOP condition (Figure
9a). If a command byte with PD set high is followed by
an output byte, the addressed DAC’s input latch will be
updated and the data will be transferred to the DAC’s
output latch following the STOP condition (Figure 9b).
The Command Byte and Output Byte
A command byte follows the slave address. Figure 7
shows the format for the command byte. A command
byte is usually followed by an output byte unless it is
the last byte in the transmission. If it is the last byte, all
b its e xc e p t PD (p owe r-d own) a nd RST (re s e t) a re
_______________________________________________________________________________________
9
2 -Wire S e ria l 8 -Bit DACs w it h
Ra il-t o -Ra il Ou t p u t s
1
1
or or
0
1
0
AD0 0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
AD3 AD2AD1
1
1
1
1
0
SDA
ACK
ADDRESS BYTE
ACK
COMMAND BYTE
(ADDRESSING DAC0)
OUTPUT BYTE
(FULL SCALE)
ACK
START
STOP
CONDITION
CONDITION
DAC0 INPUT LATCH
(
)
SET TO FULL SCALE
DAC OUTPUT CHANGES HERE:
(
DAC0 GOES TO FULL SCALE.
)
Figure 8a. Setting One DAC Output (MAX517/MAX518/MAX519)
1
1
or or
0
1
0 AD3 AD2AD1 AD0 0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0 0
0
0
SDA
SDA
ACK
ADDRESS BYTE
ACK
COMMAND BYTE
(ADDRESSING DAC0)
OUTPUT BYTE
(FULL SCALE)
COMMAND BYTE
(ADDRESSING DAC1)
DAC0 INPUT LATCH
ACK
ACK
START
CONDITION
(
)
SET TO FULL SCALE
78/MAX519
1
1
1
1
1
1
1
1
0
OUTPUT BYTE
(FULL SCALE)
ACK
STOP
CONDITION
DAC1 INPUT LATCH
(
)
SET TO FULL SCALE
DAC OUTPUTS CHANGE HERE:
DAC0 AND DAC1 GO TO FULL SCALE.
(
)
Figure 8b. Setting Both DAC Outputs (MAX518/MAX519)
1
1
or or
0 AD3 AD2AD1AD0 0
(a)
SDA
(PD)
1
0
1
0
0
0
0
0
0
X
X
X
X
ADDRESS BYTE
ACK
COMMAND BYTE
ACK
STOP
START
CONDITION
DEVICE ENTERS
CONDITION POWER-DOWN STATE
(
)
1
1
or or
0 AD3 AD2AD1AD0 0
(b)
SDA
(PD)
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
1
1
X
ACK
ADDRESS BYTE
ACK
COMMAND BYTE
(ADDRESSING DAC0)
OUTPUT BYTE
(FULL SCALE)
ACK
STOP
START
CONDITION
CONDITION
DAC0 INPUT LATCH
SET TO FULL SCALE.
(
)
DEVICE ENTERS POWER-DOWN STATE.
DAC0 OUTPUT LATCH SET TO FULL SCALE.
NOTE: X = DON'T CARE
(
)
Figure 9. Entering the Power-Down State
10 ______________________________________________________________________________________
2 -Wire S e ria l 8 -Bit DACs w it h
Ra il-t o -Ra il Ou t p u t s
78/MAX519
Furthermore if the transmission’s last command byte
following output byte is ignored. Subsequent pairs of
c omma nd /outp ut b yte s ove rwrite the inp ut la tc he s
(Figure 11b).
has PD high, the output latches are updated, but volt-
age outputs will not reflect the newly entered data
because the DAC enters power-down mode when the
STOP condition is detected. When in power-down, the
DAC outputs float. In this mode, the supply current is a
maximum of 20µA. A command byte with the PD bit low
returns the MAX517/MAX518/MAX519 to normal opera-
tion following a STOP condition, with the voltage out-
puts reflecting the output-latch contents (Figures 10a
and 10b). Because each subsequent command byte
overwrites the previous PD bit, only the last command
byte of a transmission affects the power-down state.
All c ha ng e s ma d e d uring a tra nsmission a ffe c t the
MAX517/MAX518/MAX519’s outp uts only whe n the
transmission ends and a STOP has been recognized.
The R0, R1, and R2 bits are reserved and must be set
to zero.
2
I C Co m p a t ib ilit y
The MAX517/MAX518/MAX519 are fully compatible
with e xis ting I2C s ys te ms . SCL a nd SDA a re hig h-
impedance inputs; SDA has an open drain that pulls
the data line low during the 9th clock pulse. Figure 12
shows a typical I2C application.
Setting the RST bit high clears the DAC input latches.
The DAC outputs remain unchanged until a STOP con-
dition is detected (Figure 11a). If a reset is issued, the
1
or
1
or
(PD)
0
(a)
SDA
0
1
0
AD2 AD1AD0 0
0
0
0
0
0
0
AD3
X
X
X
0
ADDRESS BYTE
ACK
COMMAND BYTE
ACK
STOP
START
CONDITION
DEVICE RETURNS TO
CONDITION NORMAL OPERATION
(
)
1
1
(b)
SDA
or or
(PD)
0
0
1
0
AD1AD0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AD3 AD2
X
X
ACK
ADDRESS BYTE
ACK
COMMAND BYTE
(ADDRESSING DAC0)
OUTPUT BYTE
(SET TO 0)
ACK
STOP
CONDITION
START
CONDITION
DAC0 INPUT
LATCH SET TO 0.
(
)
NOTE: X = DON'T CARE
DEVICE RETURNS TO NORMAL OPERATION.
(
)
DAC0 SET TO 0.
Figure 10. Returning to Normal Operation from Power-Down
1
1
or or
AD3 AD2
(a)
SDA
(RST)
1
0
1
0
AD1AD0 0
0
0
0
0
0
0
X
X X
ADDRESS BYTE
ACK
COMMAND BYTE
ACK
STOP
CONDITION
START
CONDITION
ALL INPUT LATCHES
(
)
SET TO 0.
ALL OUTPUTS
SET TO 0.
1
1
(
)
(b)
SDA
or or
(RST)
1
0
1
0
AD1AD0 0
0
0
0
0
0
0
0
AD3 AD2
X
X
X
X X X X X X X X
ACK ADDITIONAL
COMMAND BYTE/
OUTPUT BYTE PAIRS
"DUMMY"
OUTPUT BYTE
ADDRESS BYTE
ACK
COMMAND BYTE
ACK
STOP
CONDITION
START
CONDITION
ALL INPUT LATCHES
SET TO 0.
DAC OUTPUTS SET TO 0 UNLESS
CHANGED BY ADDITIONAL COMMAND
BYTE/OUTPUT BYTE PAIRS.
(
)
NOTE: X = DON'T CARE
(
)
Figure 11. Resetting DAC Outputs
______________________________________________________________________________________ 11
2 -Wire S e ria l 8 -Bit DACs w it h
Ra il-t o -Ra il Ou t p u t s
latches with data that has not been transferred to the
output latches (Figure 13). Only the currently addressed
device will recognize a STOP condition and transfer
data to its output latches. If the device is left with data in
its input latches, the data can be transferred to the out-
put latches the next time the device is addressed, as
long as it receives at least one command byte and a
STOP condition.
2
µC
E PROM
XICOR
X24C04
SDA SCL
SCL
SDA
Early STOP Conditions
The addressed device recognizes a STOP condition at
any point in a transmission. If the STOP occurs during a
command byte, all previous uninterrupted command
and output byte pairs are accepted, the interrupted
command byte is ignored, and the transmission ends
(Figure 14a). If the STOP occurs during an output byte,
all previous uninterrupted command and output byte
DUAL
DAC
OUT0
OUT1
MAX518
SCL
SDA
AD0
AD1
pairs are accepted, the final command byte’s PD and
RST bits are accepted, the interrupted output byte is
ignored, and the transmission ends (Figure 14b).
SINGLE
DAC
OUT0
+5V
An a lo g S e c t io n
MAX517
SCL
SDA
AD0
AD1
DAC Operation
The MAX518 and MAX519 contain two matched volt-
age-output DACs. The MAX517 contains a single DAC.
The DACs are inverted R-2R ladder networks that con-
vert 8-bit digital words into equivalent analog output
voltages in proportion to the applied reference volt-
ages. The MAX518 has both DAC’s reference inputs
78/MAX519
Figure 12. MAX517/MAX518/MAX519 Used in a Typical I2C
Application Circuit
connected to V . Figure 15 shows a simplified dia-
DD
gram of one DAC.
Additional START Conditions
It is possible to interrupt a transmission to a device with
a ne w START (re p e a te d s ta rt) c ond ition (p e rha p s
addressing another device), which leaves the input
MAX517/MAX519 Reference Inputs
The MAX517 and MAX519 can be used for multiplying
applications. The reference accepts a 0V to V
volt-
DD
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
1
0
1
0
0
0
SDA
START
ADDRESS BYTE
(DEVICE 0)
ACK
COMMAND BYTE
ADDRESSING DAC0
ACK
OUTPUT BYTE
(FULL SCALE)
ACK
ADDRESS BYTE
(DEVICE 1)
ACK
CONDITION
DEVICE 0's
DAC0 INPUT LATCH
SET TO FULL SCALE.
REPEATED START
CONDITION
(
)
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
SDA
ACK
OUTPUT BYTE
(FULL SCALE)
ACK
COMMAND BYTE
(ADDRESSING DAC0)
STOP
CONDITION
DEVICE 1's DAC0
INPUT LATCH SET
TO FULL SCALE.
ONLY DEVICE 1's DAC0 OUTPUT LATCH SET TO FULL
SCALE. DEVICE 0's OUTPUT LATCH UNCHANGED.
(
)
(
)
Figure 13. Repeated START Conditions
12 ______________________________________________________________________________________
2 -Wire S e ria l 8 -Bit DACs w it h
Ra il-t o -Ra il Ou t p u t s
78/MAX519
1
1
or or
0 AD3 AD2 AD1AD0 0
(RST) (PD)
0 0 0 1 1 0
(a)
SDA
0
1
0
INTERRUPTED
COMMAND BYTE
ADDRESS BYTE
ACK
EARLY
MAX517/MAX518/MAX519's
START
STOP CONDITION STATE REMAINS UNCHANGED.
(
CONDITION
)
1
1
or or
0 AD3 AD2AD1AD0 0
(b)
SDA
(PD)
0 RST 1
0
1
0
0
0
0
0
0
0
1
1
1
0
0
X
X
INTERRUPTED
OUTPUT BYTE
ADDRESS BYTE
ACK
COMMAND BYTE
(POWER DOWN)
ACK
MAX517/MAX518/MAX519
POWER DOWN; INPUT LATCH
UNCHANGED IF RST = 0,
START
CONDITION
EARLY
STOP CONDITION
(
)
DAC OUTPUT(S) RESET IF RST = 1.
Figure 14. Early STOP Conditions
Table 1. Unipolar Code Table
DAC CONTENTS
ANALOG OUTPUT
R
R
R
255
+ VREF (———)
256
OUT_
11111111
2R
2R
D0
2R
D5
2R
D6
2R
D7
129
+ VREF (———)
256
10000001
10000000
01111111
128
+ VREF (———) = ——
256
V
REF
2
REF_*
GND
127
+ VREF (———)
256
SHOWN FOR ALL 1s ON DAC
*REF = V FOR THE MAX518
1
+ VREF (———)
256
00000001
00000000
DD
0V
Figure 15. DAC Simplified Circuit Diagram
age, both DC and AC signals. The voltage at each REF
input sets the full-scale output voltage for its respective
DAC. The re fe re nc e volta g e mus t b e p os itive . The
DAC’s input impedance is code dependent, with the
lowest value occurring when the input code is 55 hex or
0101 0101, and the maximum value occurring when the
input code is 00 hex. Since the REF input resistance
(RIN) is code dependent, it must be driven by a circuit
with low output impedance (no more than RIN ÷ 2000)
to maintain output linearity. The REF input capacitance
is a ls o c od e d e p e nd e nt, with the ma ximum va lue
occurring at code FF hex (typically 30pF). The output
voltage for any DAC can be represented by a digitally
Output Buffer Amplifiers
The DAC voltage outputs are internally buffered preci-
sion unity-gain followers that slew up to 1V/µs. The out-
puts can swing from 0V to V . With a 0V to 4V (or 4V
DD
to 0V) output transition, the amplifier outputs typically
settle to 1/2LSB in 6µs when loaded with 10kΩ in paral-
lel with 100pF. The buffer amplifiers are stable with any
combination of resistive loads ≥2kΩ and capacitive
loads ≤300pF.
The MAX517/MAX518/MAX519 are designed for unipo-
lar-output, single-quadrant multiplication where the out-
put voltages and the reference inputs are positive with
respect to AGND. Table 1 shows the unipolar code.
programmable voltage source as: V
= (N x V ) /
OUT
REF
256, where N is the numerical value of the DAC’s binary
input code.
______________________________________________________________________________________ 13
2 -Wire S e ria l 8 -Bit DACs w it h
Ra il-t o -Ra il Ou t p u t s
SYSTEM GND
+5V
OUT1
OUT0
0.1µF
REF0
N.C.
N.C.
N.C.
GND
V
DD
REF1
R
F
REF_
C
F
MAX517
MAX519
Figure 16. PC Board Layout for Minimizing MAX519 Crosstalk
(bottom view)
__________Ap p lic a t io n s In fo rm a t io n
P o w e r-S u p p ly Byp a s s in g a n d
Gro u n d Ma n a g e m e n t
Bypass V with a 0.1µF capacitor, located as close to
Figure 17. Reference Filter When Using V as a Reference
DD
DD
V
DD
and GND as possible. Careful PC board layout
minimizes crosstalk among DAC outputs, reference
inputs, and digital inputs. Figure 16 shows the suggest-
ed PC board layout to minimize crosstalk.
78/MAX519
+5V
When using the MAX518 (or the MAX517/MAX519 with
V
DD
as the reference), you may want to add a noise fil-
ter to the V
supply (Figure 17) or to the reference
DD
R
F
input(s) (Figure 18), especially in noisy environments.
The reference input’s bandwidth exceeds 1MHz for AC
signals, so disturbances on the reference input can
easily affect the DAC output(s).
0.1µF
C
F
V
DD
The maximum input current for a single reference input
is V /16kΩ = I
(max). In Figure 17, choose R so
REF
REF
F
that changes in the reference input current will have lit-
tle effect on the reference voltage. For example, with R
MAX518
F
= 6Ω, the maximum output error due to R is given by:
F
6Ω x I
(max) = 1.9mV or 0.1LSB
REF
In Figure 18, there is a voltage drop across R that
F
adds to the TUE. This voltage drop is due to the sum of
the reference input current (V /16kΩ maximum), sup-
REF
ply current (6mA maximum), and the amplifier output
current (V
/R
). Choose R to limit this voltage
REF LOAD F
Figure 18. V Filter When Using V as a Reference
DD
DD
drop to an acceptable value. For example, with a 10kΩ
loa d , you c a n limit the e rror d ue to R to 0.5LSB
F
(9.8mV) by selecting R so that:
F
R
= V / I ≤ 9.8mV / (5V / 16kΩ + 6mA +
R R
F F
5V / 10kΩ)
≤ 1.4Ω
F
F
R
14 ______________________________________________________________________________________
2 -Wire S e ria l 8 -Bit DACs w it h
Ra il-t o -Ra il Ou t p u t s
78/MAX519
_____P in Co n fig u ra t io n s (c o n t in u e d )
____________________Ch ip To p o g ra p h y
OUT1
(MAX518/MAX519)
TOP VIEW
OUT0
OUT0
N.C.
OUT1
REF0
N.C.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REF0
(MAX517/
MAX519)
N.C.
REF1
(MAX519)
GND
REF1
MAX519
AD3
SCL
N.C.
SDA
V
DD
GND
AD0
AD1
AD2
0. 135"
(3. 429mm)
AD3
(MAX519)
DIP/SO
V
DD
__Ord e rin g In fo rm a t io n (c o n t in u e d )
AD0
SCL
TUE
(LSB)
PART
TEMP. RANGE PIN-PACKAGE
AD2
(MAX519)
SDA
AD1
MAX517AEPA
MAX517BEPA
MAX517AESA
MAX517BESA
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
8 Plastic DIP
8 Plastic DIP
8 SO
1
1.5
1
0. 078"
(1. 981mm)
8 SO
1.5
1.5
1
TRANSISTOR COUNT: 1797
SUBSTRATE CONNECTED TO V
MAX517BMJA -55°C to +125°C 8 CERDIP**
DD
MAX518ACPA
MAX518BCPA
MAX518ACSA
MAX518BCSA
MAX518BC/D
MAX518AEPA
MAX518BEPA
MAX518AESA
MAX518BESA
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
8 Plastic DIP
8 Plastic DIP
8 SO
1.5
1
8 SO
1.5
1.5
1
Dice*
8 Plastic DIP
8 Plastic DIP
8 SO
1.5
1
8 SO
1.5
1.5
1
MAX518BMJA -55°C to +125°C 8 CERDIP**
MAX519ACPE
MAX519BCPE
MAX519ACSE
MAX519BCSE
MAX519BC/D
MAX519AEPE
MAX519BEPE
MAX519AESE
MAX519BESE
MAX519BMJE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
16 Plastic DIP
16 Plastic DIP
16 Narrow SO
16 Narrow SO
Dice*
1.5
1
1.5
1.5
1
16 Plastic DIP
16 Plastic DIP
16 Narrow SO
16 Narrow SO
1.5
1
1.5
1.5
-55°C to +125°C 16 CERDIP**
*Dice are specified at T = +25°C, DC parameters only.
A
**Contact factory for availability and processing to MIL-STD-883.
______________________________________________________________________________________ 15
2 -Wire S e ria l 8 -Bit DACs w it h
Ra il-t o -Ra il Ou t p u t s
________________________________________________________P a c k a g e In fo rm a t io n
INCHES
MILLIMETERS
DIM
E
MIN
MAX
0.200
–
MIN
–
MAX
5.08
–
A
–
E1
D
A1 0.015
A2 0.125
A3 0.055
0.38
3.18
1.40
0.41
1.14
0.20
0.13
7.62
6.10
2.54
7.62
–
0.175
0.080
0.022
0.065
0.012
0.080
0.325
0.310
–
4.45
2.03
0.56
1.65
0.30
2.03
8.26
7.87
–
A3
A2
A1
A
L
B
0.016
B1 0.045
0.008
D1 0.005
0.300
E1 0.240
0.100
eA 0.300
C
0° - 15°
E
C
e
e
B1
eA
eB
–
–
B
eB
L
–
0.400
0.150
10.16
3.81
0.115
2.92
D1
INCHES
MILLIMETERS
PKG. DIM
PINS
Plastic DIP
PLASTIC
DUAL-IN-LINE
PACKAGE
(0.300 in.)
MIN
MAX MIN
MAX
8
P
P
P
P
P
N
D
D
D
D
D
D
0.348 0.390 8.84
9.91
14
16
18
20
24
0.735 0.765 18.67 19.43
0.745 0.765 18.92 19.43
0.885 0.915 22.48 23.24
1.015 1.045 25.78 26.54
78/MAX519
1.14 1.265 28.96 32.13
21-0043A
INCHES
MILLIMETERS
DIM
MIN
MAX
0.069
0.010
0.019
0.010
0.157
MIN
1.35
0.10
0.35
0.19
3.80
MAX
1.75
0.25
0.49
0.25
4.00
A
0.053
D
A1 0.004
B
C
E
e
0.014
0.007
0.150
0°-8°
A
0.101mm
0.004in.
0.050
1.27
e
H
L
0.228
0.016
0.244
0.050
5.80
0.40
6.20
1.27
A1
C
B
L
INCHES
MILLIMETERS
DIM PINS
Narrow SO
SMALL-OUTLINE
PACKAGE
MIN MAX
MIN
MAX
5.00
8.75
8
0.189 0.197 4.80
D
D
D
E
H
14 0.337 0.344 8.55
16 0.386 0.394 9.80 10.00
21-0041A
(0.150 in.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1995 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX517BCSA+T 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| MAX517BESA+ | MAXIM | D/A Converter, 1 Func, Serial Input Loading, 6us Settling Time, PDSO8, 0.150 INCH, SO-8 | 完全替代 |
|
| MAX517BCSA+ | MAXIM | 暂无描述 | 完全替代 |
|
| MAX517ACSA+ | MAXIM | D/A Converter, 1 Func, Serial Input Loading, 6us Settling Time, PDSO8, 0.150 INCH, SO-8 | 完全替代 |
|
MAX517BCSA+T 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| MAX517BCSA-T | MAXIM | D/A Converter, 1 Func, Serial Input Loading, 6us Settling Time, PDSO8, 0.150 INCH, SO-8 | 获取价格 |
|
| MAX517BEPA | MAXIM | 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs | 获取价格 |
|
| MAX517BEPA+ | MAXIM | D/A Converter, 1 Func, Serial Input Loading, 6us Settling Time, PDIP8, 0.300 INCH, PLASTIC, DIP-8 | 获取价格 |
|
| MAX517BESA | MAXIM | 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs | 获取价格 |
|
| MAX517BESA+ | MAXIM | D/A Converter, 1 Func, Serial Input Loading, 6us Settling Time, PDSO8, 0.150 INCH, SO-8 | 获取价格 |
|
| MAX517BESA+T | MAXIM | D/A Converter, 1 Func, Serial Input Loading, 6us Settling Time, PDSO8, 0.150 INCH, SO-8 | 获取价格 |
|
| MAX517BESA-T | MAXIM | D/A Converter, 1 Func, Serial Input Loading, 6us Settling Time, PDSO8, 0.150 INCH, SO-8 | 获取价格 |
|
| MAX517BMJA | MAXIM | 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs | 获取价格 |
|
| MAX517R00D | VISHAY | MAX517R00D 5 PPM | 获取价格 |
|
| MAX518 | MAXIM | 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs | 获取价格 |
|
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