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5675RPQB

更新时间：2025-05-02 01:58:08

品牌：MAXWELL

描述：14-BIT, 400MSPS DIGITAL-TO-ANOALOG CONVERTER

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5675RPQB 概述

14-BIT, 400MSPS DIGITAL-TO-ANOALOG CONVERTER 14位， 400MSPS数字 - ANOALOG变换器数模转换器

5675RPQB 规格参数

生命周期：	Contact Manufacturer	零件包装代码：	QFP
包装说明：	RAD-PAK, QFP-48	针数：	48
Reach Compliance Code：	unknown	ECCN代码：	3A001.A.2.C
HTS代码：	8542.39.00.01	风险等级：	5.64
Is Samacsys：	N	最大模拟输出电压：	3.75 V
最小模拟输出电压：	2.15 V	转换器类型：	D/A CONVERTER
输入位码：	BINARY	输入格式：	PARALLEL, WORD
JESD-30 代码：	S-XQFP-F48	最大线性误差 (EL)：	0.0244%
位数：	14	功能数量：	1
端子数量：	48	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	UNSPECIFIED
封装代码：	QFF	封装等效代码：	QFL48(UNSPEC)
封装形状：	SQUARE	封装形式：	FLATPACK
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	3.7846 mm	标称安定时间 (tstl)：	0.005 µs
子类别：	Other Converters	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子形式：	FLAT
端子节距：	0.635 mm	端子位置：	QUAD
Base Number Matches：	1

5675RPQB 数据手册

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5675

14-BIT, 400MSPS

DIGITAL-TO-ANOALOG CONVERTER

Functional Block Diagram

FEATURES:

DESCRIPTION:

• 400-MSPS Update Rate

Maxwell Technologies 5675 is a 14-bit resolution high-

speed digital to analog converter. The 5675 is designed

for high-speed digital data transmission in wired and

wireless communication systems. The 5675 has exce-

lent spurios free dynamic range (SFDR) at high interme-

diate frequencies.

• LVDS-Compatable Input Interface

• Differential Scalable Current Outputs: 2mA to 20mA

• On-Chip 1.2-V Reference

• Single 3.3-V Supply Operation

• Power Dissipation: 820 mW at f_CLK= 400MHz,

f_O= 70MHz

The 5675 operates from a single-supply voltage of 3.3V.

Power dissipation is 820 mW at fclk = 400 MSPS, fout =

70MHz. The 5675 provides a nominal full-scale differen-

tial current output of 20mA, supporting both single-

ended and differential applications. Theoutput can be

directly fed to the load with no additional external output

buffered required.

Maxwell Technologies' patented R^AD-PAK® packaging

technology incorporates radiation shielding in the micro-

circuit package. It eliminates the need for box shielding

while providing the required radiation shielding for a life-

time in orbit or space mission. In a GEO orbit, R^AD-PAK®

provides greater than 100 krad(Si) radiation dose toler-

ance. This product is available with screening up to

Class S.

07.13.04 Rev 1X

All data sheets are subject to change without notice

(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com

14-BIT, 400MSPS DIGITAL-TO-ANALOG Converter

5675

TABLE 1. PINOUT DESCRIPTION

SYMBOL

DESCRIPTION

19, 41, 46, 47

AGND

AVDD

Analog Negative Supply Voltage (Ground)

Analog Positive Supply Voltage

Full-scale Output Current Bias

External Clock Input

20, 42, 45, 48

BIASJ

CLK

CLKC

Complementory External Clock Input

1, 3, 5, 7, 9, 13, 23

25, 27, 29, 31, 33, 35

D9(13:0)A

LVDS Positive Input, data bits 13 through 0

D13A is most significant data bit (MSB)

D0A is the least significant bit (LSB)

2, 4, 6, 8, 10, 14, 24

26, 28, 30, 32, 34, 36

D(13:0)B

LVDS Positive Input, data bits 13 through 0

D13B is most significant data bit (MSB)

D0B is the least significant bit (LSB)

16, 18

DGND

DLLOFF

DVDD

Digital Negative Supply Voltage (Ground)

High = DLL Off / Low = DLL On

Digital Positive Supply Voltage

15, 17

EXTIO

Internal reference out put or external reference input. Requires a 0.1uf decou-

pling capacitor to groind when used as reference output.

IOUT1

IOUT2

SLEEP

DAC current output. Full scale when all inputs are set to 1. Connect reference

side DAC load resistors to AVDD

DAC complimentory current output. Full scale when all inputs are set to 0.

Connect reference side DAC load resistors to AVDD

Asynchronous hardware power down input. Active high. Internally pulldown.

TABLE 2. 5675 ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

MIN

MAX

UNIT

Supply Voltage Range

-0.3

-3.6

-0.3

3.6

0.5

AV_DDto DV

Voltage between AGND and DGND

CLK, CLKC, SLEEP

-0.3 to DVDD DVDD to 0.3

-1.0 to DVDD AVDD to 0.3

-0.3 to DVDD AVDD to 0.3

Digital input D[13:0]A, D[13:0]B

IOUT1, IOUT2

EXTIO, BIASJ

Peak Input Current (any input)

Peak Total Input Current (any input)

Storage temperature range

^°C

-30

-65

150

07.13.04 Rev 1

All data sheets are subject to change without notice

14-BIT, 400MSPS DIGITAL-TO-ANALOG Converter

5675

TABLE 2. 5675 ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

MIN

MAX

UNIT

Operating Temperature range

-55

125

^°C

1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recom-

mended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect

device reliability.

TABLE 3. DELTA LIMITS

PARAMETER

VARIATION

IAVDD

±10% of specified value in Table 5

I^DVDD

TABLE 4. 5675 RECOMMENDED OPERATING CONDITIONS

P^ARAMETER

MIN

TYP

MAX

UNIT

Output Update Rate

DLL disable, DLLOFF=1

DLL enable, DLLOFF=0

100

400

MSPS

100

3.15

0.6

Analog Supply Voltage, AVDD

Digital Supply Voltage, DVDD

Input Reference Voltage, EXTIO

3.3

1.2

3.6

1.25

Full-scale output currentm IO(FS)

Output compliance range

AVDD=3.15 to 3.45V, IO(FS)=20mA

AVDD-1

0.4

AVDD+0.3

0.8

Clock Differential Input Votage, CLK-CLKC

Clock Pulse Width High, tWH

Clock Pulse Width Low, tLH

Clock Duty Cycle

1.25

1. All unused control inputs of the device must be held at high or low ensure proper device operation.

TABLE 5. 5675 DC ELECTRICAL CHARACTERISTICS

(DVDD = 3.3±10%, AVDD = 3.3±10%, T_A= -55 TO +125 ^°C, UNLESS OTHERWISE SPECIFIED)

P^ARAMETER

Resolution

TEST CONDITIONS

SYMBLE SUBGROUPS

MIN

TYP

MAX

UNIT

Bits

DC Accuracy¹

Integral Nonlinearity

D^IFFERENTIALNONLINEARITY

M^ONOTICITY

TMIN TO TMAX

INL

-4

-2

LSB

DNL

+1.5

Monotonic 12-bit Level

07.13.04 Rev 1

All data sheets are subject to change without notice

14-BIT, 400MSPS DIGITAL-TO-ANALOG Converter

5675

TABLE 5. 5675 DC ELECTRICAL CHARACTERISTICS

(DVDD = 3.3±10%, AVDD = 3.3±10%, T_A= -55 TO +125 ^°C, UNLESS OTHERWISE SPECIFIED)

P^ARAMETER

TEST CONDITIONS

SYMBLE SUBGROUPS

MIN

TYP

MAX

UNIT

ANALOG OUTPUT

OFFSET ERROR

G^AINERROR

0.02

%FSR

Without Internal Reference

With Internal Reference

-10

O^UTPUTRESISTANCE

O^UTPUTCAPACITANCE

R^EFERENCEOUTPUT

REFERENCE VOLTAGE

300

EXTIO

1.17

1.23

100

1.29

R^EFERENCEOUTPUT CURRENT

R^EFERENCEINPUT

INPUT RESISTANCE

MHz

S^MALLSIGNAL BANDWIDTH

I^NPUTCAPACITANCE

1.4

100

T^EMPERATURECOEFFICIENTS

OFFSET DRIFT

ppm of

FSR/^°C

G^AINDRIFT

Without Internal Reference

+50

ppm of

FSR/^°C

R^EFERENCEVOLTAGE DRIFT

VEXTIO

ppm of

FSR/^°C

P^OWERSUPPLY

ANALOG SUPPLY CURRENT

IAVDD

IDVDD

IAVDD

175

100

D^IGITALSUPPLY CURREN T

A^NALOGSUPPLY CURRENT

Sleep Mode

P^OWERDISSIPATION

AVdd = 3.3V, DVdd = 3.3V

AVdd = 3.15 to 3.45V

ANALOG AND DIGITAL POWER

SUPPLY REJECTION RATIO

APSRR

D^PSRR

-0.5

0.5

%FSm

WR/V

LVDS I^NTERFACE: NODE D[13:0]A; D[13:0]B

P^OSITIVE-GOING DIFFERENTIAL

INPUT VOLTAGE THRESHOLD

See LVDS min/max

threshold voltage table

VITH+

VITH-

100

N^EGATIVE-GOING DIFFERENTIAL

INPUT VOLTAGE THRESHOLD

-100

I^NTERNALTERMINATION

I^MPEDANCE

132

Ohms

I^NPUTCAPACITANCE

CMOS I^NTERFACE: NODE SLEEP

07.13.04 Rev 1

All data sheets are subject to change without notice

14-BIT, 400MSPS DIGITAL-TO-ANALOG Converter

5675

TABLE 5. 5675 DC ELECTRICAL CHARACTERISTICS

(DVDD = 3.3±10%, AVDD = 3.3±10%, T_A= -55 TO +125 ^°C, UNLESS OTHERWISE SPECIFIED)

P^ARAMETER

TEST CONDITIONS

SYMBLE SUBGROUPS

MIN

TYP

MAX

UNIT

HIGH-LEVEL INPUT VOLTAGE

L^OW-LEVEL INPUT VOLTAGE

H^IGH-LEVEL INPUT CURRENT

L^OW-LEVEL INPUT CURRENT

I^{NPUT CAPACITANCE}

VIH

VIL

IIH

3.3

0.8

-10

IIL

C^{LOCK INTERFACE}: NODE CLK, CLCKC

I^NPUTRESISTANCE

I^NPUTCAPACITANCE

I^NPUTRESISTANCE

I^NPUTCAPACITANCE

T^IMING

node CLK, CLKC

670

Ohms

Differential

1.3

Kohms

INPUT SETUP TIME

I^NPUTHOLD TIME

I^NPUTLATCH PULSE HIGH TIME

D^IGITALDELAY TIME

tSU

1.5

0.25

clk

t_h

LPH

1. Measured Differential at IOUT1 and IOUT2. 2.5Ohms to AVDD

2. Use an external buffer amplifier with high impedance input drive to drive any external load.

3. Measured at fCLK = 400 MSPS and FOUT = 70 MHz

4. Measured for 50 Ohms Rl at IOUT1 and IOUT2, f^CLK= 400 MSPS and fOUT = 70MHz

07.13.04 Rev 1

All data sheets are subject to change without notice

14-BIT, 400MSPS DIGITAL-TO-ANALOG Converter

5675

TABLE 6. 5675 AC ELECTRICAL CHARACTERISTICS

(DVDD = 3.3±10%, AVDD = 3.3±10%, T_A= -55 TO +125 ^°C, UNLESS OTHERWISE SPECIFIED)

V_CC= 3.3V ± 0.3

P^ARAMETER

TEST CONDITIONS

SYMBOL SUBGROUPS

U^NIT

MIN

TYP

MAX

ANALOG OUTPUT

OUTPUT SETTLING TIME

MID-SCALE TRANSITION

T^S(DAC) 9, 10, 11

(C^ODE8191-8192)

O^UTPUTPROPAGATION DELAY

O^UTPUTRISE TIME 10% TO 90%

O^UTPUTFALL TIME 90% TO 10%

O^UTPUTNOISE

TPD

9, 10, 11

TR(IOUT) 9, 10, 11

9, 10, 11

IOUTFS = 20MA

IOUT^FS= 2MA

9, 10, 11

pA/

2^Hz

pA/

2^Hz

AC L^INEARITY

TOTAL HARMONIC DISTORTION

tCLK = 100 MSPS,

f^OUT=20MHz, TA = 25C

THD

dBc

t^CLK= 160 MSPS,

f^OUT=41MHz, TA = 25C

t^CLK= 200 MSPS,

f^OUT=70MHz, TA = 25C

t^CLK= 400 MSPS,

f^OUT=20 MHz,

T^MINto TMAX

t^CLK= 400 MSPS,

f^OUT=70MHz, TA = 25C

t^CLK= 400 MSPS,

f^OUT=140MHz, TA = 25C

S^PURIOUSFREE DYNAMIC RANGE TO

tCLK = 100 MSPS,

f^OUT=20MHz, TA = 25C

SFDR

dBc

N^YQUIST

t^CLK= 160 MSPS,

f^OUT=41MHz, TA = 25C

t^CLK= 200 MSPS,

f^OUT=701MHz, TA = 25C

t^CLK= 400 MSPS,

f^OUT=20 MHz,

T^MINto TMAX

t^CLK= 400 MSPS,

f^OUT=70MHz, TA = 25C

t^CLK= 400 MSPS,

f^OUT=140MHz, TA = 25C

07.13.04 Rev 1

All data sheets are subject to change without notice

14-BIT, 400MSPS DIGITAL-TO-ANALOG Converter

5675

TABLE 6. 5675 AC ELECTRICAL CHARACTERISTICS

(DVDD = 3.3±10%, AVDD = 3.3±10%, T_A= -55 TO +125 ^°C, UNLESS OTHERWISE SPECIFIED)

V_CC= 3.3V ± 0.3

P^ARAMETER

TEST CONDITIONS

SYMBOL SUBGROUPS

U^NIT

dBc

MIN

TYP

MAX

SPURIOUS FREE DYNAMIC RANGE

WITHIN A WINDOW, 5-MHZ SPAN

tCLK = 100 MSPS,

f^OUT=20MHz, TA = 25C

SFDR

t^CLK= 160 MSPS,

f^OUT=41MHz, TA = 25C

t^CLK= 200 MSPS,

f^OUT=701MHz, TA = 25C

t^CLK= 400 MSPS,

f^OUT=20 MHz,

T^MINto TMAX

t^CLK= 400 MSPS,

f^OUT=70MHz, TA = 25C

t^CLK= 400 MSPS,

f^OUT=140MHz, TA = 25C

A^{DJACENT CHANNEL POWER RATIO}

WCDMA ^WITH3.84 MHZ BW,

5MH^{Z CHANNEL SPACING}

fCLK=122.8 MSPS,

IF=30.72 MHz, T^A=25C

ACPR

IMD

f^CLK=245.76 MSPS,

IF=61.44 MHz, T^A=25C

f^CLK=399.32 MSPS,

IF=153.36 MHz, T^A=25C

T^WO-TONE INTERMODULATION TO

N^YQUIST(EACH TONE AT -6 DBFS)

f^CLK=400MHx,

dBc

f^OUT1=70MHz,

f^OUT2=141MHz, Ta=25C

f^CLK=400MHx,

f^OUT1=140MHz,

f^OUT2=141MHz, Ta=25C

F^OUR-TONE INTERMODULATION, 15MH^Zf^CLK=400MHx,

SPAN, MISSING CENTER TONE

(EACH TONE AT -6 DBFS)

f^OUT1=70MHz,

f^OUT2=141MHz, Ta=25C

f^CLK=400MHx,

f^OUT1=140MHz,

f^OUT2=141MHz, Ta=25C

07.13.04 Rev 1

All data sheets are subject to change without notice

14-BIT, 400MSPS DIGITAL-TO-ANALOG Converter

5675

TABLE 7. LVDS INPUT THRESHOLDS AND LOGICAL BIT EQUIVALENT

RESULTING

DIFFERENTIAL COMMON-MODE

INPUT VOLTAGE INPUT VOLTAGE EQUIVALENT

RESULTING

LOGICAL

BIT BINARY

APPIED

VOLTAGE

COMMENT

V [V]

_A,B[MV] _COM[V]

1.25

1.15

2.4

2.3

0.1

1.15

1.25

2.3

2.4

200

-200

200

1.2

Operation with minimum differential volt-

age(+/-200mV) applied to the complimen-

tory inputs versus common mode range

1.35

2.35

0.05

1.2

-200

200

0.1

0.9

1.5

1.8

2.4

-200

600

1.5

0.9

2.4

1.8

0.6

Operation with minimum differential volt-

age(+/-600mV) applied to the complimen-

tory inputs versus common mode range

-600

600

1.2

2.1

-600

600

2.1

0.3

0.6

-600

0.3

07.13.04 Rev 1

All data sheets are subject to change without notice

14-BIT, 400MSPS DIGITAL-TO-ANALOG Converter

5675

07.13.04 Rev 1

All data sheets are subject to change without notice

14-BIT, 400MSPS DIGITAL-TO-ANALOG Converter

5675

07.13.04 Rev 1

All data sheets are subject to change without notice 10

14-BIT, 400MSPS DIGITAL-TO-ANALOG Converter

5675

07.13.04 Rev 1

All data sheets are subject to change without notice 11

14-BIT, 400MSPS DIGITAL-TO-ANALOG Converter

5675

07.13.04 Rev 1

All data sheets are subject to change without notice 12

14-BIT, 400MSPS DIGITAL-TO-ANALOG Converter

5675

Applications Schematic

07.13.04 Rev 1

All data sheets are subject to change without notice 13

14-BIT, 400MSPS DIGITAL-TO-ANALOG Converter

5675

48 PIN RAD-PAK® QUAD FLAT PACKAGE

DIMENSION

SYMBOL

CENTER LINE

MIN

NOM

MAX

.121

.008

.006

.645

.270

.135

.010

.008

.650

.275

.025

1.645

1.605

.956

.108

.0125

.149

.012

.010

.655

.280

PKG/leads

Frame

1.585

.945

1.625

.965

Note: All dimensions in inches

07.13.04 Rev 1

All data sheets are subject to change without notice 14

14-BIT, 400MSPS DIGITAL-TO-ANALOG Converter

5675

Important Notice:

These data sheets are created using the chip manufacturer’s published specifications. Maxwell Technologies verifies

functionality by testing key parameters either by 100% testing, sample testing or characterization.

The specifications presented within these data sheets represent the latest and most accurate information available to

date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no

responsibility for the use of this information.

Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems

without express written approval from Maxwell Technologies.

Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech-

nologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.

07.13.04 Rev 1

All data sheets are subject to change without notice 15

14-BIT, 400MSPS DIGITAL-TO-ANALOG Converter

5675

Product Ordering Options

Model Number

5675

Option Details

Feature

Monolithic

Screening Flow

S = Maxwell Class S

B = Maxwell Class B

I = Industrial (testing @ -55°C,

+25°C, +125°C)

E = Engineering (testing @ +25°C)

Q = Quad Flat Pack

Package

RP = R^AD-PAK® package

Radiation Feature

Digital-Analog Converter

14-Bit, 400 MSPS

Base Product

Nomenclature

07.13.04 Rev 1

All data sheets are subject to change without notice 16

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