概述
规格参数
数据手册
替代型号DAC7552IRGTTG4 概述
12 位、双路、超低毛刺脉冲、电压输出数模转换器 | RGT | 16 | -40 to 105 DA转换器 数模转换器
DAC7552IRGTTG4 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 零件包装代码： | QFN |
| 包装说明： | HVQCCN, LCC16,.12SQ,20 | 针数： | 16 |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | Factory Lead Time： | 6 weeks |
| 风险等级： | 5.39 | 最大模拟输出电压： | 5.5 V |
| 最小模拟输出电压： | 转换器类型： | D/A CONVERTER | |
| 输入位码： | BINARY | 输入格式： | SERIAL |
| JESD-30 代码： | S-PQCC-N16 | JESD-609代码： | e4 |
| 长度： | 3 mm | 最大线性误差 (EL)： | 0.0244% |
| 湿度敏感等级： | 3 | 位数： | 12 |
| 功能数量： | 1 | 端子数量： | 16 |
| 最高工作温度： | 105 °C | 最低工作温度： | -40 °C |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | HVQCCN |
| 封装等效代码： | LCC16,.12SQ,20 | 封装形状： | SQUARE |
| 封装形式： | CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE | 峰值回流温度（摄氏度）： | 260 |
| 电源： | 3/5 V | 认证状态： | Not Qualified |
| 采样速率： | 1 MHz | 座面最大高度： | 1 mm |
| 最大稳定时间： | 5 µs | 子类别： | Other Converters |
| 最大压摆率： | 0.44 mA | 标称供电电压： | 3 V |
| 表面贴装： | YES | 温度等级： | INDUSTRIAL |
| 端子面层： | Nickel/Palladium/Gold (Ni/Pd/Au) | 端子形式： | NO LEAD |
| 端子节距： | 0.5 mm | 端子位置： | QUAD |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 宽度： | 3 mm |
| Base Number Matches： | 1 |
DAC7552IRGTTG4 数据手册
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DAC7552
www.ti.com
SLAS442B–JANUARY 2005–REVISED JUNE 2005
12-BIT, DUAL, ULTRALOW GLITCH, VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
•
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•
•
2.7-V to 5.5-V Single Supply
The DAC7552 is
a 12-bit, dual-channel, volt-
age-output DAC with exceptional linearity and
monotonicity. Its proprietary architecture minimizes
undesired transients such as code-to-code glitch and
12-Bit Linearity and Monotonicity
Rail-to-Rail Voltage Output
Settling Time: 5 µs (Max)
channel-to-channel
crosstalk.
The
low-power
Ultralow Glitch Energy: 0.1 nVs
Ultralow Crosstalk: –100 dB
DAC7552 operates from a single 2.7-V to 5.5-V
supply. The DAC7552 output amplifiers can drive a
2-kΩ, 200-pF load rail-to-rail with 5-µs settling time;
the output range is set using an external voltage
reference.
Low Power: 440 µA (Max)
Per-Channel Power Down: 2 µA (Max)
Power-On Reset to Zero Scale
SPI-Compatible Serial Interface: Up to 50 MHz
Daisy-Chain Capability
The 3-wire serial interface operates at clock rates up
to 50 MHz and is compatible with SPI, QSPI,
Microwire™, and DSP interface standards. The out-
puts of all DACs may be updated simultaneously or
sequentially. The parts incorporate a power-on-reset
circuit to ensure that the DAC outputs power up to
zero volts and remain there until a valid write cycle to
the device takes place. The parts contain
power-down feature that reduces the current con-
sumption of the device to under 2 µA.
Asynchronous Hardware Clear
Simultaneous or Sequential Update
Specified Temperature Range: –40°C to 105°C
Small 3-mm × 3-mm, 16-Lead QFN Package
a
APPLICATIONS
The small size and low-power operation makes the
DAC7552 ideally suited for battery-operated portable
applications. The power consumption is typically
1.5 mW at 5 V, 0.75 mW at 3 V, and reduces to 1 µW
in power-down mode.
•
•
•
•
•
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
The DAC7552 is available in a 16-lead QFN package
and is specified over –40°C to 105°C.
FUNCTIONAL BLOCK DIAGRAM
V
DD
IOV
V
REFA
DD
V
FBA
_
+
V
OUT
A
B
Input
Register
DAC
Register
String
DAC A
SCLK
SYNC
SDIN
Interface
Logic
V
FBB
_
+
V
String
DAC B
OUT
Input
Register
DAC
Register
Power-On
Reset
Power-Down
Logic
DAC7552
SDO
GND
V
REFB
PD
CLR
DCEN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Microwire is a trademark of National Semiconductor Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
DAC7552
www.ti.com
SLAS442B–JANUARY 2005–REVISED JUNE 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA
PRODUCT PACKAGE
DAC7552IRGTT
DAC7552IRGTR
250-piece Tape and Reel
3000-piece Tape and Reel
DAC7552
16 QFN
RGT
–40°C TO 105°C
D752
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
VDD to GND
–0.3 V to 6 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD+ 0.3 V
–40°C to 105°C
–65°C to 150°C
150°C
Digital input voltage to GND
VOUT to GND
Operating temperature range
Storage temperature range
Junction temperature (TJ Max)
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2
DAC7552
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SLAS442B–JANUARY 2005–REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V, VREF = VDD, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to 105°C, unless otherwise
specified
PARAMETER
STATIC PERFORMANCE(1)
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNITS
12
±0.35
±0.08
Bits
LSB
Relative accuracy
Differential nonlinearity
Offset error
±1
±0.5
±12
Specified monotonic by design
All zeroes loaded to DAC register
LSB
mV
Zero-scale error
±12
mV
Gain error
±0.15
±0.5
%FSR
%FSR
µV/°C
ppm of FSR/°C
mV/V
Full-scale error
Zero-scale error drift
Gain temperature coefficient
PSRR
7
3
VDD = 5 V
0.75
OUTPUT CHARACTERISTICS(2)
Output voltage range
Output voltage settling time
Slew rate
0
VREF
5
V
µs
RL = 2 kΩ; 0 pF < CL < 200 pF
1.8
470
V/µs
Capacitive load stability
RL = ∞
pF
RL = 2 kΩ
1000
0.1
Digital-to-analog glitch impulse
Channel-to-channel crosstalk
1 LSB change around major carry
nV-s
dB
1-kHz full-scale sine wave,
outputs unloaded
–100
Digital feedthrough
0.1
nV-s
Output noise density (10-kHz offset fre-
quency)
120
nV/rtHz
Total harmonic distortion
FOUT = 1 kHz, FS = 1 MSPS,
BW = 20 kHz
–85
dB
DC output impedance
Short-circuit current
1
50
20
15
Ω
VDD = 5 V
VDD = 3 V
mA
Power-up time
Coming out of power-down mode,
VDD = 5 V
µs
Coming out of power-down mode,
VDD = 3 V
15
REFERENCE INPUT
VREF Input range
0
VDD
V
Reference input impedance
VREFA and VREFB shorted together
50
kΩ
VREFA = VREFB = VDD = 5 V,
VREFA and VREFB shorted together
100
250
123
Reference current
µA
VREFA = VREFB = VDD = 3 V,
60
VREFA and VREFB shorted together
LOGIC INPUTS(2)
Input current
±1
µA
V
VIN_L, Input low voltage
VIN_H, Input high voltage
Pin capacitance
IOVDD ≥ 2.7 V
IOVDD ≥ 2.7 V
0.3 IOVDD
0.7 IOVDD
V
3
pF
(1) Linearity tested using a reduced code range of 30 to 4065; output unloaded.
(2) Specified by design and characterization, not production tested. For 1.8 V < IOVDD < 2.7 V, It is recommended that
VIH = IOVDD, VIL = GND.
3
DAC7552
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SLAS442B–JANUARY 2005–REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS (continued)
VDD = 2.7 V to 5.5 V, VREF = VDD, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to 105°C, unless otherwise
specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
(3)
VDD,, IOVDD
2.7
5.5
V
IDD(normal operation)
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
IDD (all power-down modes)
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
POWER EFFICIENCY
IOUT/IDD
DAC active and excluding load current
VIH = IOVDD and VIL = GND
300
250
440
400
µA
µA
0.2
2
2
VIH = IOVDD and VIL = GND
ILOAD = 2 mA, VDD = 5 V
0.05
93%
(3) IOVDD operates down to 1.8 V with slightly degraded timing, as long as VIH = IOVDD and VIL = GND.
4
DAC7552
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SLAS442B–JANUARY 2005–REVISED JUNE 2005
TIMING CHARACTERISTICS(1)(2)
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications –40°C to 105°C, unless otherwise specified
PARAMETER
TEST CONDITIONS
VDD = 2.7 V to 3.6 V
MIN
20
20
10
10
10
10
4
TYP
MAX
UNITS
(3)
t1
t2
t3
t4
t5
t6
t7
t8
t9
SCLK cycle time
ns
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
SCLK HIGH time
SCLK LOW time
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYNC falling edge to SCLK falling edge setup
time
4
5
Data setup time
5
4.5
4.5
0
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC HIGH time
SCLK falling edge to SDO valid
CLR pulse width low
0
20
20
10
10
10
10
t10
(1) All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See Serial Write Operation timing diagram Figure 1.
(3) Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.
t
1
SCLK
t
2
t
8
t
3
t
7
t
4
SYNC
SDIN
t
t
6
5
D15
D14
D13
D11
D1
D0
D15
D12
D0
Input Word n
Input Word n+1
D14
t
9
SDO
CLR
D0
D15
Input Word n
Undefined
t
10
Figure 1. Serial Write Operation
5
DAC7552
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SLAS442B–JANUARY 2005–REVISED JUNE 2005
PIN DESCRIPTION
RGT PACKAGE
(TOP VIEW)
16 15 14 13
1
2
3
4
12
11
10
9
SCLK
SYNC
V
A
OUT
V
DD
IOV
GND
DD
SDO
V
OUT
B
5
6
7
8
Terminal Functions
TERMINAL
DESCRIPTION
NO.
1
NAME
VOUT
A
Analog output voltage from DAC A
Analog voltage supply input
Ground
2
VDD
3
GND
VOUT
4
B
Analog output voltage from DAC B
5
VFBB
VREFB
PD
DAC B amplifier sense input. (For voltage output operation, connect to VOUTB externally.)
6
Positive reference voltage input for DAC B
7
Power-down
8
DCEN
SDO
Daisy-chain enable
9
Serial data output
10
11
IOVDD
SYNC
I/O voltage supply input. (For single supply operation, connect to VDD externally.)
Frame synchronization input. The falling edge of the SYNC pulse indicates the start of a serial data frame shifted out
to the DAC7552
12
13
14
SCLK
SDIN
CLR
Serial clock input
Serial data input
Asynchronous input to clear the DAC registers. When CLR is low, the DAC registers are set to 000H and the output
voltage to 0 V.
15
16
VREFA
VFBA
Positive reference voltage input for DAC A
DAC A amplifier sense input. (For voltage output operation, connect to VOUTA externally.)
6
DAC7552
www.ti.com
SLAS442B–JANUARY 2005–REVISED JUNE 2005
TYPICAL CHARACTERISTICS
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs
DIFFERENTIAL LINEARITY ERROR
vs
DIGITAL INPUT CODE
DIGITAL INPUT CODE
1
0.5
0
1
Channel A
V
= 4.096 V
V
= 5 V
DD
Channel B
V
= 4.096 V
V
= 5 V
DD
REF
REF
0.5
0
−0.5
−0.5
−1
−1
0.5
0.5
0.25
0
0.25
0
−0.25
−0.5
−0.25
−0.5
0
512
1024
1536
2048
2560
3072
3584
4096
512
1024
1536
0
2048
2560
3072
3584
4096
Digital Input Code
Digital Input Code
Figure 2.
Figure 3.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs
vs
DIGITAL INPUT CODE
DIGITAL INPUT CODE
1
0.5
0
1
0.5
0
Channel A
V
= 2.5 V
V
= 2.7 V
DD
REF
Channel B
V
= 2.5 V
V
= 2.7 V
DD
REF
−0.5
−0.5
−1
−1
0.5
0.5
0.25
0
0.25
0
−0.25
−0.5
−0.25
−0.5
0
512
1024
1536
2048
2560
3072
3584
4096
0
512
1024
1536
2048
2560
3072
3584
4096
Digital Input Code
Digital Input Code
Figure 4.
Figure 5.
7
DAC7552
www.ti.com
SLAS442B–JANUARY 2005–REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
ZERO-SCALE ERROR
vs
FREE-AIR TEMPERATURE
ZERO-SCALE ERROR
vs
FREE-AIR TEMPERATURE
3
2
3
V
V
= 5 V,
V
V
= 2.7 V,
DD
DD
= 4.096 V
= 2.5 V
REF
REF
2
1
Channel A
1
0
Channel A
Channel B
0
Channel B
−1
−40
−1
−40
−10
20
50
80
−10
20
50
80
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 6.
Figure 7.
FULL-SCALE ERROR
vs
FREE-AIR TEMPERATURE
FULL-SCALE ERROR
vs
FREE-AIR TEMPERATURE
1
0
1
0
V
= 2.7 V,
= 2.5 V
V
= 5 V,
= 4.096 V
DD
DD
V
REF
V
REF
Channel B
Channel A
Channel B
Channel A
−1
−2
−1
−2
−40
−10
20
50
80
−40
−10
20
50
80
T − Free-Air Temperature − °C
A
T
A
− Free-Air Temperature − °C
Figure 8.
Figure 9.
8
DAC7552
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SLAS442B–JANUARY 2005–REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
SINK CURRENT AT NEGATIVE RAIL
SOURCE CURRENT AT POSITIVE RAIL
0.2
5.50
5.40
5.30
5.20
Typical for All Channels
Typical for All Channels
V
V
= 2.7 V,
= 2.5 V
DD
0.15
V
DD
= V
= 5.5 V
REF
REF
0.1
V
V
= 5.5 V,
= 4.096 V
DD
REF
0.05
DAC Loaded with 000h
DAC Loaded with FFFh
0
0
5
10
15
0
5
10
15
I
− Sink Current − mA
I
− Source Current − mA
SINK
SOURCE
Figure 10.
Figure 11.
SOURCE CURRENT AT POSITIVE RAIL
SUPPLY CURRENT
vs
DIGITAL INPUT CODE
2.7
2.6
400
350
300
250
200
150
100
Typical for All Channels
V
V
= 5.5 V,
DD
= 4.096 V
REF
V
V
= 2.7 V,
DD
= 2.5 V
V
DD
= V
= 2.7 V
REF
REF
2.5
2.4
50
0
DAC Loaded with FFFh
5
All Channels Powered, No Load
0
10
15
0
512 1024 1536 2048 2560 3072 3584 4096
Digital Input Code
I
− Source Current − mA
SOURCE
Figure 12.
Figure 13.
9
DAC7552
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SLAS442B–JANUARY 2005–REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
400
350
400
350
300
All DACs Powered,
No Load,
= 2.5 V
V
REF
V
V
= 5.5 V,
DD
= 4.096 V
REF
300
250
200
V
V
= 2.7 V,
DD
= 2.5 V
REF
250
200
All Channels Powered, No Load
−40 −10 20 50
2.7
3.1
3.4
3.8
4.1
4.5
4.8
5.2
5.5
80
110
T
A
− Free-Air Temperature − °C
V
DD
− Supply Volatge − V
Figure 14.
Figure 15.
SUPPLY CURRENT
vs
LOGIC INPUT VOLTAGE
HISTOGRAM OF CURRENT CONSUMPTION - 5.5 V
2000
1500
1000
500
0
1600
1200
800
T
= 255C, SCL Input
A
V
V
= 5.5 V,
DD
(All Other Inputs = GND)
= 4.096 V
REF
V
V
= 5.5 V,
DD
= 4.096 V
REF
400
V
V
= 2.7 V,
= 2.5 V
DD
REF
0
253 264 275 286 297 308 319 330 341
0
1
2
3
4
5
I
− Current Consumption − mA
V
LOGIC
− Logic Input Voltage − V
DD
Figure 16.
Figure 17.
10
DAC7552
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SLAS442B–JANUARY 2005–REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
HISTOGRAM OF CURRENT CONSUMPTION - 2.7 V
TOTAL ERROR - 5 V
4
2
1500
V
V
T
= 5 V,
V
V
= 2.7 V,
DD
DD
= 4.096 V,
REF
= 2.5 V
REF
= 255C
A
Channel A Output
1000
500
0
0
Channel B Output
−2
−4
512 1024 1536 2048 2560 3072 3584 4095
Digital Input Code
0
239 249 259 269 279 289 299 309 319
I
− Current Consumption − mA
DD
Figure 18.
Figure 19.
TOTAL ERROR - 2.7 V
EXITING POWER-DOWN MODE
4
2
5
4
3
2
1
0
V
V
= 5 V,
REF
Power-Up Code 4000
DD
V
V
T
= 2.7 V,
DD
= 4.096 V,
= 2.5 V,
REF
= 255C
A
Channel A Output
0
Channel B Output
−2
−4
0
512 1024 1536 2048 2560 3072 3584 4095
Digital Input Code
t − Time − 4 ms/div
Figure 21.
Figure 20.
11
DAC7552
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SLAS442B–JANUARY 2005–REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
LARGE-SIGNAL SETTLING TIME - 5 V
LARGE-SIGNAL SETTLING TIME - 2.7 V
= 2.5 V
Output Loaded With 200 pF to GND
Code 41 to 4055
5
3
2
1
0
V
REF
V
DD
= 2.7 V,
V
= 5 V,
V
= 4.096 V
DD
REF
Output Loaded With 200 pF to GND
Code 41 to 4055
4
3
2
1
0
t − Time − 5 ms/div
t − Time − 5 ms/div
Figure 22.
Figure 23.
MIDSCALE GLITCH
WORST-CASE GLITCH
Trigger Pulse
Trigger Pulse
Time - (400 nS/Div)
Time - (400 nS/Div)
Figure 24.
Figure 25.
12
DAC7552
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SLAS442B–JANUARY 2005–REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
DIGITAL FEEDTHROUGH ERROR
CHANNEL-TO-CHANNEL CROSSTALK
FOR A FULL-SCALE SWING
Trigger Pulse
Trigger Pulse
Time - (400 nS/Div)
Time - (400 nS/Div)
Figure 26.
Figure 27.
TOTAL HARMONIC DISTORTION
vs
OUTPUT FREQUENCY
−40
−50
−60
−70
−80
−90
−100
V
= 5 V, V
= 4.096 V
DD
REF
−1 dB FSR Digital Input, Fs = 1 Msps
Measurement Bandwidth = 20 kHz
THD
2nd Harmonic
3rd Harmonic
0
1
2
3
4
5
6
7
8
9
10
Output Frequency (Tone) − kHz
Figure 28.
13
DAC7552
www.ti.com
SLAS442B–JANUARY 2005–REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
3-Wire Serial Interface
The DAC7552 digital interface is a standard 3-wire SPI/QSPI/Microwire/DSP-compatible interface.
Table 1. Serial Interface Programming
CONTROL
DB14 DB13
DATA BITS DAC(s)
DB12 DB11-DB10
FUNCTION
DB15
0
0
0
0
0
0
0
0
data
data
data
A
B
A
Single Channel Store. The input register of channel A is updated.
Single Channel Store. The input register of channel B is updated.
0
1
1
0
Single Channel Update. The input and DAC registers of channel A are
updated.
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
0
0
0
0
0
data
data
data
data
data
B
A
Single Channel Update. The input and DAC registers of channel A are
updated and the DAC register of channel B is updated with input register data.
Single Channel Update. The input and DAC registers of channel B are
updated.
B
Single Channel Update. The input and DAC registers of channel B are
updated and the DAC register of channel A is updated with input register data.
A–B
A–B
All Channel Update. The input and DAC registers of channels A and B are
updated.
All Channel DAC Update. The DAC register of channels A and B are updated
with input register data.
POWER-DOWN MODE
In power-down mode, the DAC outputs are programmed to one of three output impedances, 1 kΩ, 100 kΩ, or
floating.
Table 2. Power-Down Mode Control
EXTENDED CONTROL
DATA BITS
FUNCTION
DB15
DB14
DB13
X
DB12
DB11
DB10
DB9-DB0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
PWD Hi-Z (all channels)
X
PWD 1 kΩ (all channels)
X
PWD 100 kΩ (all channels)
X
PWD Hi-Z (all channels)
X
PWD Hi-Z (selected channel = A)
PWD 1 kΩ (selected channel = A)
PWD 100 kΩ (selected channel = A)
PWD Hi-Z (selected channel = A)
PWD Hi-Z (selected channel = B)
PWD 1 kΩ (selected channel = B)
PWD 100 kΩ (selected channel = B)
PWD Hi-Z (selected channel = B)
PWD Hi-Z (all channels)
X
X
X
X
X
X
X
X
X
PWD 1 kΩ (all channels)
X
PWD 100 kΩ (all channels)
X
PWD Hi-Z (all channels)
14
DAC7552
www.ti.com
SLAS442B–JANUARY 2005–REVISED JUNE 2005
THEORY OF OPERATION
D/A SECTION
OUTPUT BUFFER AMPLIFIERS
The architecture of the DAC7552 consists of a string
DAC followed by an output buffer amplifier. Figure 29
shows a generalized block diagram of the DAC
architecture.
The output amplifier is capable of generating
rail-to-rail voltages on its output, which gives an
output range of 0 V to VDD. It is capable of driving a
load of 2 kΩ in parallel with up to 1000 pF to GND.
The source and sink capabilities of the output ampli-
fier can be seen in the typical curves. The slew rate is
1.8 V/µs with a typical settling time of 3 µs with the
output unloaded.
V
REF
100 kW
100 kW
V
FB
50 kW
_
Ref +
V
OUT
DAC External Reference Input
+
Resistor String
DAC Register
Ref −
Two separate reference pins are provided for two
DACs, providing maximum flexibility. VREFA serves
DAC A and VREFB serves DAC B. VREFA and
VREFB can be externally shorted together for sim-
plicity.
GND
Figure 29. Typical DAC Architecture
The input coding to the DAC7552 is unsigned binary,
which gives the ideal output voltage as:
It is recommended to use a buffered reference in the
external circuit (e.g., REF3140). The input impedance
is typically 100 kΩ for each reference input pin.
VOUT = VREF × D/4096
Where D = decimal equivalent of the binary code that
is loaded to the DAC register which can range from 0
to 4095.
Amplifier Sense Input
The DAC7552 contains two amplifier feedback input
pins, VFBA and VFBB. For voltage output operation,
VFBA and VFBB must externally connect to VOUTA
and VOUTB, respectively. For better DC accuracy,
these connections should be made at load points.
The VFBA and VFBB pins are also useful for a
variety of applications, including digitally controlled
current sources. Each feedback input pin is internally
connected to the DAC amplifier's negative input
terminal through a 100-kΩ resistor; and, the ampli-
fier's negative input terminal internally connects to
ground through another 100-kΩ resistor (See Fig-
ure 29). This forms a gain-of-two, noninverting ampli-
fier configuration. Overall gain remains one because
the resistor string has a divide-by-two configuration.
The resistance seen at each VFBx pin is approxi-
mately 200 kΩ to ground.
To Output
Amplifier
V
REF
R
R
R
R
GND
Figure 30. Typical Resistor String
RESISTOR STRING
The resistor string section is shown in Figure 30. It is
simply a string of resistors, each of value R. The
digital code loaded to the DAC register determines at
which node on the string the voltage is tapped off to
be fed into the output amplifier. The voltage is tapped
off by closing one of the switches connecting the
string to the amplifier. Because it is a string of
resistors, it is specified monotonic. The DAC7552
architecture uses two separate resistor strings to
minimize channel-to-channel crosstalk.
Power-On Reset
On power up, all internal registers are cleared and all
channels are updated with zero-scale voltages. Until
valid data is written, all DAC outputs remain in this
state. This is particularly useful in applications where
it is important to know the state of the DAC outputs
while the device is powering up. In order not to turn
on ESD protection devices, VDD should be applied
before any other pin is brought high.
15
DAC7552
www.ti.com
SLAS442B–JANUARY 2005–REVISED JUNE 2005
Power Down
register, DAC register, or both are updated with shift
register input data. Bit 13 (DB13) determines whether
the data is for DAC A, DAC B, or both DACs. Bit 12
(DB12) determines either normal mode or
power-down mode (see Table 2). All channels are
updated when bits 15 and 14 (DB15 and DB14) are
high.
The DAC7552 has a flexible power-down capability
as described in Table 2. Individual channels could be
powered down separately or all channels could be
powered down simultaneously. During a power-down
condition, the user has flexibility to select the output
impedance of each channel. During power-down
operation, each channel can have either 1-kΩ,
100-kΩ, or Hi-Z output impedance to ground.
The SYNC input is a level-triggered input that acts as
a frame synchronization signal and chip enable. Data
can only be transferred into the device while SYNC is
low. To start the serial data transfer, SYNC should be
taken low, observing the minimum SYNC to SCLK
falling edge setup time, t4. After SYNC goes low,
serial data is shifted into the device's input shift
register on the falling edges of SCLK for 16 clock
pulses.
Asynchronous Clear
The DAC7552 output is asynchronously set to
zero-scale voltage immediately after the CLR pin is
brought low. The CLR signal resets all internal
registers and therefore behaves like the Power-On
Reset. The DAC7552 updates at the first rising edge
of the SYNC signal that occurs after the CLR pin is
brought back to high.
When DCEN is low, SDO pin is brought to a Hi-Z
state. The first 16 data bits that follow the falling edge
of SYNC are stored in the shift register. The rising
edge of SYNC that follows the 16th data bit updates
the DAC(s). If SYNC is brought high before the 16th
data bit, no action occurs.
IOVDD and Level Shifters
The DAC7552 can be used with different logic famil-
ies that require a wide range of supply voltages (from
1.8 V to 5.5 V). To enable this useful feature, the
IOVDD pin must be connected to the logic supply
voltage of the system. All DAC7552 digital input and
output pins are equipped with level-shifter circuits.
Level shifters at the input pins ensure that external
logic high voltages are translated to the internal logic
high voltage, with no additional power dissipation.
Similarly, the level shifter for the SDO pin translates
the internal logic high voltage (AVDD) to the external
logic high level (IOVDD). For single-supply operation,
the IOVDD pin can be tied to the AVDD pin.
When DCEN is high, data can continuously be shifted
into the shift register, enabling the daisy-chain oper-
ation. SDO pin becomes active and outputs SDIN
data with 16 clock cycle delay. A rising edge of SYNC
loads the shift register data into the DAC(s). The
loaded data consists of the last 16 data bits received
into the shift register before the rising edge of SYNC.
If daisy-chain operation is not needed, DCEN should
permanently be tied to a logic low voltage.
Daisy-Chain Operation
SERIAL INTERFACE
When DCEN pin is brought high, daisy chaining is
enabled. Serial Data Output (SDO) pin is provided to
daisy-chain multiple DAC7552 devices in a system.
The DAC7552 is controlled over a versatile 3-wire
serial interface, which operates at clock rates up to
50 MHz and is compatible with SPI, QSPI, Microwire,
and DSP interface standards.
As long as SYNC is high or DCEN is low, the SDO
pin is in a high-impedance state. When SYNC is
brought low the output of the internal shift register is
tied to the SDO pin. As long as SYNC is low and
DCEN is high, SDO duplicates SDIN signal with a
16-cycle delay. To support multiple devices in a daisy
chain, SCLK and SYNC signals are shared across all
devices, and SDO of one DAC7552 should be tied to
the SDIN of the next DAC7552. For n devices in such
a daisy chain, 16n SCLK cycles are required to shift
the entire input data stream. After 16n SCLK falling
edges are received, following a falling SYNC, the
data stream becomes complete and SYNC can be
brought high to update n devices simultaneously.
SDO operation is specified at a maximum SCLK
speed of 10 MHz.
In daisy-chain mode (DCEN = 1), the DAC7552
requires a falling SCLK edge after the rising SYNC, in
order to initialize the serial interface for the next
update.
16-Bit Word and Input Shift Register
The input shift register is 16 bits wide. DAC data is
loaded into the device as a 16-bit word under the
control of a serial clock input, SCLK, as shown in the
Figure 1 timing diagram. The 16-bit word, illustrated
in Table 1, consists of four control bits followed by 12
bits of DAC data. The data format is straight binary
with all zeroes corresponding to 0-V output and all
ones corresponding to full-scale output (VREF – 1
LSB). Data is loaded MSB first (bit 15) where the first
two bits (DB15 and DB14) determine if the input
16
DAC7552
www.ti.com
SLAS442B–JANUARY 2005–REVISED JUNE 2005
INTEGRAL AND DIFFERENTIAL LINEARITY
change the loop can generate. A DNL error less than
–1 LSB (non-monotonicity) can create loop instability.
A DNL error greater than +1 LSB implies unnecess-
arily large voltage steps and missed voltage targets.
With high DNL errors, the loop loses its stability,
resolution, and accuracy. Offering 12-bit ensured
monotonicity and ± 0.08 LSB typical DNL error, 755X
DACs are great choices for precision control loops.
The DAC7552 uses precision thin-film resistors pro-
viding exceptional linearity and monotonicity. Integral
linearity error is typically within (+/-) 0.35 LSBs, and
differential linearity error is typically within (+/-) 0.08
LSBs.
GLITCH ENERGY
Loop Speed:
The DAC7552 uses a proprietary architecture that
minimizes glitch energy. The code-to-code glitches
are so low, they are usually buried within the
wide-band noise and cannot be easily detected. The
DAC7552 glitch is typically well under 0.1 nV-s. Such
low glitch energy provides more than 10X improve-
ment over industry alternatives.
Many factors determine control loop speed. Typically,
the ADC's conversion time and the MCU's compu-
tation time are the two major factors that dominate
the time constant of the loop. DAC settling time is
rarely a dominant factor because ADC conversion
times usually exceed DAC conversion times. DAC
offset, gain, and linearity errors can slow the loop
down only during the start-up. Once the loop reaches
its steady-state operation, these errors do not affect
loop speed any further. Depending on the ringing
characteristics of the loop's transfer function, DAC
glitches can also slow the loop down. With its 1
MSPS (small-signal) maximum data update rate,
DAC7552 can support high-speed control loops.
Ultralow glitch energy of the DAC7552 significantly
improves loop stability and loop settling time.
CHANNEL-TO-CHANNEL CROSSTALK
The DAC7552 architecture is designed to minimize
channel-to-channel crosstalk. The voltage change in
one channel does not affect the voltage output in
another channel. The DC crosstalk is in the order of a
few microvolts. AC crosstalk is also less than –100
dBs. This provides orders of magnitude improvement
over certain competing architectures.
Generating Industrial Voltage Ranges:
APPLICATION INFORMATION
Waveform Generation
For control loop applications, DAC gain and offset
errors are not important parameters. This could be
exploited to lower trim and calibration costs in a
high-voltage control circuit design. Using an oper-
ational amplifier (OPA130), and a voltage reference
(REF3140), the DAC7552 can generate the wide
voltage swings required by the control loop.
Due to its exceptional linearity, low glitch, and low
crosstalk, the DAC7552 is well suited for waveform
generation (from DC to 10 kHz). The DAC7552
large-signal settling time is 5 µs, supporting an
update rate of 200 KSPS. However, the update rates
can exceed 1 MSPS if the waveform to be generated
consists of small voltage steps between consecutive
DAC updates. To obtain a high dynamic range,
REF3140 (4.096 V) or REF02 (5 V) are rec-
ommended for reference voltage generation.
V
tail
DAC7552
R1
REF3140
R2
V
REF
Generating ±5-V, ±10-V, and ± 12-V Outputs For
Precision Industrial Control
_
V
H
REF
V
OUT
V
dac
DAC7552
+
Industrial control applications can require multiple
feedback loops consisting of sensors, ADCs, MCUs,
DACs, and actuators. Loop accuracy and loop speed
are the two important parameters of such control
loops.
OPA130
Figure 31. Low-cost, Wide-swing Voltage Gener-
ator for Control Loop Applications
Loop Accuracy:
The output voltage of the configuration is given by:
In a control loop, the ADC has to be accurate. Offset,
gain, and the integral linearity errors of the DAC are
not factors in determining the accuracy of the loop.
As long as a voltage exists in the transfer curve of a
monotonic DAC, the loop can find it and settle to it.
On the other hand, DAC resolution and differential
linearity do determine the loop accuracy, because
each DAC step determines the minimum incremental
R2
R1
Din
4096
R2
R1
REFǒ ) 1Ǔ
V
+ V
* V
out
tail
(1)
Fixed R1 and R2 resistors can be used to coarsely
set the gain required in the first term of the equation.
Once R2 and R1 set the gain to include some
minimal over-range, a DAC7552 channel could be
used to set the required offset voltage. Residual
17
DAC7552
www.ti.com
SLAS442B–JANUARY 2005–REVISED JUNE 2005
errors are not an issue for loop accuracy because
offset and gain errors could be tolerated. One
DAC7552 channel can provide the Vtail voltage, while
the other DAC7552 channel can provide Vdac voltage
to help generate the high-voltage outputs.
For ±10-V operation: R1=10 kΩ, R2 = 39 kΩ, Vtail
2.56 V, VREF = 4.096 V
=
=
For ±12-V operation: R1=10 kΩ, R2 = 49 kΩ, Vtail
2.45 V, VREF = 4.096 V
For ±5-V operation: R1=10 kΩ, R2 = 15 kΩ, Vtail
=
3.33 V, VREF= 4.096 V
18
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jul-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
QFN
QFN
QFN
Drawing
DAC7552IRGT
DAC7552IRGTR
DAC7552IRGTT
PREVIEW
ACTIVE
ACTIVE
RGT
16
16
16
121
3000
250
TBD
TBD
TBD
Call TI
Call TI
RGT
CU NIPDAU Level-3-220C-168 HR
CU NIPDAU Level-3-220C-168 HR
RGT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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Copyright 2005, Texas Instruments Incorporated
DAC7552IRGTTG4 CAD模型
原理图符号
PCB 封装图
DAC7552IRGTTG4 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| DAC7552IRGTR | TI | 12-BIT, DUAL, ULTRALOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER | 功能相似 |
|
DAC7552IRGTTG4 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| DAC7553 | TI | 12-BIT, DUAL, ULTRALOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER | 获取价格 |
|
| DAC7553IRGTR | TI | 12-BIT, DUAL, ULTRALOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER | 获取价格 |
|
| DAC7553IRGTT | TI | 12-BIT, DUAL, ULTRALOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER | 获取价格 |
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| DAC7553IRGTTG4 | TI | 12 位、双路、超低毛刺脉冲、电压输出数模转换器 | RGT | 16 | -40 to 105 | 获取价格 |
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