SN74ABT374AN
更新时间：2025-05-02 02:34:38
品牌：TI
描述：OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
概述
规格参数
数据手册
替代型号SN74ABT374AN 概述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS 八路边沿触发D型触发器具有三态输出 触发器 总线驱动器/收发器
SN74ABT374AN 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 零件包装代码： | DIP |
| 包装说明： | DIP-20 | 针数： | 20 |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | Factory Lead Time： | 1 week |
| 风险等级： | 0.94 | Is Samacsys： | N |
| 控制类型： | ENABLE LOW | 计数方向： | UNIDIRECTIONAL |
| 系列： | ABT | JESD-30 代码： | R-PDIP-T20 |
| JESD-609代码： | e4 | 长度： | 24.325 mm |
| 负载电容（CL）： | 50 pF | 逻辑集成电路类型： | BUS DRIVER |
| 最大频率@ Nom-Sup： | 150000000 Hz | 最大I（ol）： | 0.064 A |
| 位数： | 8 | 功能数量： | 1 |
| 端口数量： | 2 | 端子数量： | 20 |
| 最高工作温度： | 85 °C | 最低工作温度： | -40 °C |
| 输出特性： | 3-STATE | 输出极性： | TRUE |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | DIP |
| 封装等效代码： | DIP20,.3 | 封装形状： | RECTANGULAR |
| 封装形式： | IN-LINE | 包装方法： | TUBE |
| 峰值回流温度（摄氏度）： | NOT SPECIFIED | 电源： | 5 V |
| 最大电源电流（ICC）： | 30 mA | Prop。Delay @ Nom-Sup： | 7.1 ns |
| 传播延迟（tpd）： | 7.1 ns | 认证状态： | Not Qualified |
| 座面最大高度： | 5.08 mm | 子类别： | FF/Latches |
| 最大供电电压 (Vsup)： | 5.5 V | 最小供电电压 (Vsup)： | 4.5 V |
| 标称供电电压 (Vsup)： | 5 V | 表面贴装： | NO |
| 技术： | BICMOS | 温度等级： | INDUSTRIAL |
| 端子面层： | Nickel/Palladium/Gold (Ni/Pd/Au) | 端子形式： | THROUGH-HOLE |
| 端子节距： | 2.54 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 触发器类型： | POSITIVE EDGE |
| 宽度： | 7.62 mm | Base Number Matches： | 1 |
SN74ABT374AN 数据手册
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PDF下载SN54ABT374, SN74ABT374A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS111G – FEBRUARY 1991 – REVISED JANUARY 1997
SN54ABT374 . . . J OR W PACKAGE
SN74ABT374A . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
Typical V
(Output Ground Bounce) < 1 V
8Q
8D
7D
OLP
at V
= 5 V, T = 25°C
CC
A
High-Drive Outputs (–32-mA I , 64-mA I
OH
)
OL
16 7Q
15 6Q
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
14
13
12
11
6D
5D
5Q
CLK
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Plastic (N) and Ceramic (J) DIPs, and
Ceramic Flat (W) Package
GND
SN54ABT374 . . . FK PACKAGE
(TOP VIEW)
description
3
2
1
20 19
18
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
2D
2Q
3Q
3D
4D
8D
7D
7Q
6Q
4
5
6
7
8
17
16
15
14 6D
9 10 11 12 13
The eight flip-flops of the SN54ABT374 and
SN74ABT374A are edge-triggered D-type
flip-flops. On the positive transition of the clock
(CLK) input, the Q outputs are set to the logic
levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines
without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data
can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT374 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT374A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT374, SN74ABT374A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS111G – FEBRUARY 1991 – REVISED JANUARY 1997
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
↑
H
L
L
L
H or L
X
X
X
Q
0
H
Z
†
logic symbol
1
EN
C1
OE
11
CLK
3
2
5
1D
2D
3D
4D
5D
6D
1D
1Q
2Q
3Q
4Q
5Q
6Q
4
7
6
8
9
13
14
12
15
17
18
16
19
7D
8D
7Q
8Q
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
OE
11
CLK
C1
1D
2
1Q
3
1D
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT374, SN74ABT374A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS111G – FEBRUARY 1991 – REVISED JANUARY 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABT374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABT374A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
recommended operating conditions (see Note 3)
SN54ABT374 SN74ABT374A
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
CC
0
V
CC
V
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–24
48
–32
64
5
mA
mA
ns/V
°C
OH
OL
I
∆t/∆v
Outputs enabled
5
T
–55
125
–40
85
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT374, SN74ABT374A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS111G – FEBRUARY 1991 – REVISED JANUARY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT374 SN74ABT374A
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
I
I
I
I
I
I
= –3 mA
= –3 mA
= –24 mA
= –32 mA
= 48 mA
= 64 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
V
2
2
V
= 4.5 V
= 4.5 V
CC
CC
2*
2
0.55
0.55
V
V
V
V
OL
0.55*
0.55
100
mV
µA
µA
µA
µA
µA
mA
µA
mA
µA
hys
I
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 0,
V = V or GND
I CC
±1
±1
±1
I
‡
10
‡
10
‡
10
V
O
V
O
= 2.7 V
= 0.5 V
OZH
OZL
off
‡
–10
‡
–10
‡
–10
V or V ≤ 4.5 V
±100
50
±100
50
I
O
= 5.5 V,
= 5.5 V,
V
= 5.5 V
Outputs high
50
–180
250
30
CEX
O
O
§
V
= 2.5 V
–50
–100
–180
250
30
–50
–50
–180
250
30
O
Outputs high
Outputs low
V
= 5.5 V, I = 0,
O
CC
I
CC
V = V
I
or GND
CC
Outputs disabled
250
250
250
V
= 5.5 V, One input at 3.4 V,
CC
Other inputs at V
¶
1.5
1.5
1.5
mA
∆I
CC
or GND
CC
V = 2.5 V or 0.5 V
C
C
3.5
6.5
pF
pF
i
I
V
O
= 2.5 V or 0.5 V
o
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
‡
§
¶
All typical values are at V
= 5 V.
CC
This data sheet limit may vary among suppliers.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABT374
V
T
= 5 V,
= 25°C
CC
A
UNIT
MIN
MAX
MIN
0
MAX
f
t
Clock frequency
Pulse duration
150
0
3.3
2.5
2.5
2.5
150
MHz
ns
clock
CLK high or low
Data high
3.3
2
w
t
ns
ns
Setup time before CLK↑
Hold time after CLK↑
su
h
Data low
2
t
Data high or low
2
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT374, SN74ABT374A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS111G – FEBRUARY 1991 – REVISED JANUARY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN74ABT374A
V
T
= 5 V,
= 25°C
CC
A
UNIT
MIN
MAX
MIN
0
MAX
f
t
Clock frequency
Pulse duration
150
0
3.3
1
150
MHz
ns
clock
CLK high or low
Data high
3.3
1
w
t
ns
ns
Setup time before CLK↑
Hold time after CLK↑
su
h
Data low
1.9
1.9
†
2.1
†
2.1
t
Data high or low
†
This data sheet limit may vary among suppliers.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
SN54ABT374
FROM
(INPUT)
TO
(OUTPUT)
V
CC
= 5 V,
PARAMETER
UNIT
T
= 25°C
TYP
200
4.2
A
MIN
MAX
MIN
150
2.2
3.1
1.2
2.3
2.3
1.9
MAX
f
t
t
t
t
t
t
150
1.8
2.6
0.8
1.5
1.3
1
MHz
ns
max
PLH
PHL
PZH
PZL
PHZ
PLZ
5.7
6.6
4.7
6.2
6.1
6
6.6
7.6
5.7
7.2
7.2
7
CLK
OE
Q
Q
Q
5.1
3.2
ns
ns
4.7
4.5
OE
4.5
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
SN74ABT374A
= 5 V,
FROM
(INPUT)
TO
(OUTPUT)
V
CC
A
PARAMETER
UNIT
T
= 25°C
TYP
200
4.2
MIN
MAX
MIN
150
2.2
3.1
1.2
2.7
2.5
2
MAX
f
t
t
t
t
t
t
150
2.2
3.1
1.2
2.7
2.5
2
MHz
ns
max
PLH
PHL
PZH
PZL
PHZ
PLZ
5.7
6.6
4.7
6.2
6
6.2
7.1
5.2
6.7
CLK
OE
Q
Q
Q
5.1
3.2
ns
ns
4.7
†
4.5
6.7
6.5
OE
4.5
6
†
This data sheet limit may vary among suppliers.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT374, SN74ABT374A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS111G – FEBRUARY 1991 – REVISED JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
7 V
PLH PHL
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
Open
L
PHZ PZH
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
t
PHL
PLH
PHL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
SN74ABT374AN CAD模型
原理图符号
PCB 封装图
SN74ABT374AN 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| SN74ABT374ANE4 | TI | ABT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP20, ROHS COMPLIANT, PLASTIC, DIP-20 | 类似代替 |
|
SN74ABT374AN 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| SN74ABT374ANE4 | TI | ABT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP20, ROHS COMPLIANT, PLASTIC, DIP-20 | 获取价格 |
|
| SN74ABT374ANSR | TI | Octal Edge-Triggered D-Type Flip-Flops with 3-State Outputs 20-SO -40 to 85 | 获取价格 |
|
| SN74ABT374ANSRG4 | TI | Octal Edge-Triggered D-Type Flip-Flops with 3-State Outputs 20-SO -40 to 85 | 获取价格 |
|
| SN74ABT374APW | TI | OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS | 获取价格 |
|
| SN74ABT374APW | ROCHESTER | ABT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, TSSOP-20 | 获取价格 |
|
| SN74ABT374APWLE | TI | Octal Edge-Triggered D-Type Flip-Flops with 3-State Outputs 20-TSSOP -40 to 85 | 获取价格 |
|
| SN74ABT374APWR | TI | OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS | 获取价格 |
|
| SN74ABT374APWR | ROCHESTER | ABT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, TSSOP-20 | 获取价格 |
|
| SN74ABT374APWRE4 | TI | ABT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, TSSOP-20 | 获取价格 |
|
| SN74ABT374APWRG4 | TI | Octal Edge-Triggered D-Type Flip-Flops with 3-State Outputs 20-TSSOP -40 to 85 | 获取价格 |
|
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