概述
规格参数
数据手册SN74ABT533APWR 概述
具有三态输出的八路透明 D 型锁存器 | PW | 20 | -40 to 85 锁存器 总线驱动器/收发器
SN74ABT533APWR 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 零件包装代码： | TSSOP |
| 包装说明： | TSSOP, TSSOP20,.25 | 针数： | 20 |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | Factory Lead Time： | 1 week |
| 风险等级： | 1.55 | 控制类型： | ENABLE LOW/HIGH |
| 计数方向： | UNIDIRECTIONAL | 系列： | ABT |
| JESD-30 代码： | R-PDSO-G20 | JESD-609代码： | e4 |
| 长度： | 6.5 mm | 负载电容（CL）： | 50 pF |
| 逻辑集成电路类型： | BUS DRIVER | 最大I（ol）： | 0.064 A |
| 湿度敏感等级： | 1 | 位数： | 8 |
| 功能数量： | 1 | 端口数量： | 2 |
| 端子数量： | 20 | 最高工作温度： | 85 °C |
| 最低工作温度： | -40 °C | 输出特性： | 3-STATE |
| 输出极性： | INVERTED | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | TSSOP | 封装等效代码： | TSSOP20,.25 |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH |
| 包装方法： | TR | 峰值回流温度（摄氏度）： | 260 |
| 电源： | 5 V | 最大电源电流（ICC）： | 30 mA |
| Prop。Delay @ Nom-Sup： | 6.6 ns | 传播延迟（tpd）： | 7.3 ns |
| 认证状态： | Not Qualified | 座面最大高度： | 1.2 mm |
| 子类别： | FF/Latches | 最大供电电压 (Vsup)： | 5.5 V |
| 最小供电电压 (Vsup)： | 4.5 V | 标称供电电压 (Vsup)： | 5 V |
| 表面贴装： | YES | 技术： | BICMOS |
| 温度等级： | INDUSTRIAL | 端子面层： | Nickel/Palladium/Gold (Ni/Pd/Au) |
| 端子形式： | GULL WING | 端子节距： | 0.65 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 翻译： | N/A | 宽度： | 4.4 mm |
| Base Number Matches： | 1 |
SN74ABT533APWR 数据手册
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PDF下载SN54ABT533, SN74ABT533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186A – FEBRUARY 1991 – REVISED JULY 1994
SN54ABT533 . . . J PACKAGE
SN74ABT533 . . . DB, DW, OR N PACKAGE
(TOP VIEW)
• State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
• Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
• Typical V
(Output Ground Bounce)
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
OLP
CC
< 1 V at V
= 5 V, T = 25°C
A
• High-Drive Outputs (–32-mA I
,
OH
64-mA I
)
OL
• Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, Ceramic
Chip Carriers (FK), and Plastic (N) and
Ceramic (J) DIPs
GND
description
SN54ABT533 . . . FK PACKAGE
(TOP VIEW)
The ′ABT533 are 8-bit transparent D-type latches
with 3-state outputs designed specifically for
driving highly capacitive or relatively low-
impedance loads. They are particularly suitable
for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
3
2 1 20 19
18
8D
2D
2Q
3Q
3D
4D
4
5
6
7
8
17 7D
16
7Q
When the latch-enable (LE) input is high, the
Q outputs follow the complements of the data
(D) inputs. When LE is taken low, the Q outputs
are latched at the inverse of the levels set up at the
D inputs. The ′ABT533 provides inverted data at
its outputs.
15
6Q
14
6D
9 10 11 12 13
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect the internal operations of the latches. Previously stored data can be retained or new data
can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ABT533 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54ABT533 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT533 is characterized for operation from –40°C to 85°C.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1994, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT533, SN74ABT533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186A – FEBRUARY 1991 – REVISED JULY 1994
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
L
L
H
L
X
X
Q
0
H
X
Z
†
logic symbol
logic diagram (positive logic)
1
OE
1
EN
C1
OE
11
11
LE
LE
2
5
C1
1Q
2Q
3
1D
4
2
3
1D
1
1Q
1D
1D
5
6
2D
7
2Q
3D
8
3Q
4Q
5Q
6Q
C1
1D
9
4D
13
4
7
2D
3D
12
15
16
19
5D
14
6D
17
6
9
C1
1D
3Q
4Q
5Q
6Q
7D
18
7Q
8Q
8D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
C1
1D
8
4D
5D
6D
12
15
16
C1
1D
13
14
C1
1D
C1
1D
7Q
8Q
17
18
7D
8D
19
C1
1D
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT533, SN74ABT533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186A – FEBRUARY 1991 – REVISED JULY 1994
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high state or power-off state, V . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABT533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABT533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Maximum power dissipation at T = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . 0.6 W
A
DW package . . . . . . . . . . . . . . . . . . . 1.6 W
N package . . . . . . . . . . . . . . . . . . . . . 1.3 W
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations
application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
recommended operating conditions (see Note 3)
SN54ABT533 SN74ABT533
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
CC
0
V
CC
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–24
48
–32
64
mA
mA
ns/V
°C
OH
OL
∆t /∆v
10
10
T
–55
125
–40
85
A
NOTE 3: Unused or floating inputs must be held high or low.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT533, SN74ABT533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186A – FEBRUARY 1991 – REVISED JULY 1994
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT533 SN74ABT533
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
I
I
I
I
I
I
= –3 mA
= –3 mA
= –24 mA
= –32 mA
= 48 mA
= 64 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
V
2
2
V
= 4.5 V
= 4.5 V
CC
CC
2*
2
0.55
0.55*
±1
0.55
V
OL
V
V
0.55
I
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 0,
V = V or GND
I CC
±1
±1
µA
µA
µA
µA
µA
mA
µA
mA
µA
I
‡
10
‡
10
‡
10
V
= 2.7 V
= 0.5 V
OZH
OZL
off
O
O
‡
–10
‡
–10
‡
–10
V
V or V ≤ 4.5 V
±150
50
±150
50
I
O
= 5.5 V,
= 5.5 V,
V
= 5.5 V
Outputs high
50
–180
250
30
CEX
O
O
§
V
= 2.5 V
–50
–140
1
–180
250
30
–50
–50
–180
250
30
O
Outputs high
V
CC
= 5.5 V,
or GND
CC
I
O
= 0,
I
Outputs low
24
CC
V = V
I
Outputs disabled
Outputs enabled
Outputs disabled
Control inputs
0.5
250
1.5
250
1.5
250
1.5
V
= 5.5 V,
CC
One input at 3.4 V,
Other inputs at V
¶
1.5
1.5
1.5
mA
∆I
CC
or GND
CC
V = 2.5 V or 0.5 V
1.5
1.5
1.5
C
C
3
9
pF
pF
i
I
V
O
= 2.5 V or 0.5 V
o
* On products compliant to MIL-STD-883, Class B, this parameter does not apply.
†
‡
§
¶
All typical values are at V
= 5 V.
CC
This data sheet limit may vary among suppliers.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure1)
V
T
= 5 V,
= 25°C
CC
A
SN54ABT533 SN74ABT533
UNIT
MIN
3.3
MAX
MIN
3.3
MAX
MIN
3.3
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
High or low
High or low
2.1
2.1
2.1
§
1.5
§
1.5
§
1.5
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT533, SN74ABT533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186A – FEBRUARY 1991 – REVISED JULY 1994
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
V
T
= 5 V,
= 25°C
CC
A
SN54ABT533 SN74ABT533
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.9
3.1
2.7
3.5
1.6
2.4
2.8
2
TYP
4.2
4.9
4.9
5.4
3.7
4.2
5.1
4.1
MAX
5.4
6.3
6.2
6.8
4.8
6.2
6.2
6
MIN
1.9
3.1
2.7
3.5
1.6
2.4
2.8
2
MAX
6.7
6.9
7.6
7.5
5.8
6.9
7.2
6.9
MIN
1.9
3.1
2.7
3.5
1.6
2.4
2.8
2
MAX
6.4
6.6
7.3
7.3
5.7
6.7
6.9
6.5
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
ns
ns
ns
ns
Q
Q
Q
Q
LE
OE
OE
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
2–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT533, SN74ABT533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186A – FEBRUARY 1991 – REVISED JULY 1994
PARAMETER MEASUREMENT INFORMATION
7 V
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
7 V
PLH PHL
/t
C
= 50 pF
L
t
500 Ω
PLZ PZL
/t
(see Note A)
Open
PHZ PZH
LOAD CIRCUIT FOR OUTPUTS
3 V
0 V
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Input
(see Note B)
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
S1 at 7 V
V
V
3.5 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
– 0.3 V
OL
V
OL
OL
(see Note C)
t
PHZ
t
PLH
t
t
PZH
PHL
Output
Waveform 2
S1 at Open
(see Note C)
V
OH
V
V
OH
OH
1.5 V
1.5 V
Output
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
2–6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-9584301Q2A
5962-9584301QRA
5962-9584301QSA
SN74ABT533DBLE
SN74ABT533DW
SN74ABT533DWR
SN74ABT533N
ACTIVE
ACTIVE
FK
J
20
20
20
20
20
20
20
20
20
20
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Call TI
ACTIVE
W
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
ACTIVE
SSOP
SOIC
SOIC
PDIP
LCCC
CDIP
CFP
DB
DW
DW
N
Call TI
Call TI
Call TI
SNJ54ABT533FK
SNJ54ABT533J
FK
J
1
1
1
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
ACTIVE
SNJ54ABT533W
ACTIVE
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
SN74ABT533APWR CAD模型
原理图符号
PCB 封装图
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