概述
规格参数
数据手册
替代型号SN74HCT373NE4 概述
具有三态输出的八路透明 D 型锁存器 | N | 20 | -40 to 85 总线驱动器/收发器
SN74HCT373NE4 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 零件包装代码： | DIP |
| 包装说明： | DIP-20 | 针数： | 20 |
| Reach Compliance Code： | compliant | HTS代码： | 8542.39.00.01 |
| Factory Lead Time： | 6 weeks | 风险等级： | 1.68 |
| Is Samacsys： | N | 控制类型： | ENABLE LOW |
| 计数方向： | UNIDIRECTIONAL | 系列： | HCT |
| JESD-30 代码： | R-PDIP-T20 | JESD-609代码： | e4 |
| 长度： | 25.4 mm | 负载电容（CL）： | 50 pF |
| 逻辑集成电路类型： | BUS DRIVER | 最大I（ol）： | 0.006 A |
| 位数： | 8 | 功能数量： | 1 |
| 端口数量： | 2 | 端子数量： | 20 |
| 最高工作温度： | 85 °C | 最低工作温度： | -40 °C |
| 输出特性： | 3-STATE | 输出极性： | TRUE |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | DIP |
| 封装等效代码： | DIP20,.3 | 封装形状： | RECTANGULAR |
| 封装形式： | IN-LINE | 包装方法： | TUBE |
| 峰值回流温度（摄氏度）： | NOT SPECIFIED | 电源： | 5 V |
| 最大电源电流（ICC）： | 0.08 mA | Prop。Delay @ Nom-Sup： | 44 ns |
| 传播延迟（tpd）： | 65 ns | 认证状态： | Not Qualified |
| 座面最大高度： | 5.08 mm | 子类别： | FF/Latches |
| 最大供电电压 (Vsup)： | 5.5 V | 最小供电电压 (Vsup)： | 4.5 V |
| 标称供电电压 (Vsup)： | 5 V | 表面贴装： | NO |
| 技术： | CMOS | 温度等级： | INDUSTRIAL |
| 端子面层： | Nickel/Palladium/Gold (Ni/Pd/Au) | 端子形式： | THROUGH-HOLE |
| 端子节距： | 2.54 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 宽度： | 7.62 mm |
| Base Number Matches： | 1 |
SN74HCT373NE4 数据手册
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PDF下载SN54HCT373, SN74HCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS009D – MARCH 1984 – REVISED AUGUST 2003
SN54HCT373 . . .J OR W PACKAGE
SN74HCT373 . . .DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
Operating Voltage Range of 4.5 V to 5.5 V
High-Current 3-State True Outputs Can
Drive Up To 15 LSTTL Loads
Low Power Consumption, 80-µA Max I
Typical t = 21 ns
pd
6-mA Output Drive at 5 V
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
8Q
8D
1
2
3
4
5
6
7
8
9
20
19
18
CC
17 7D
16 7Q
15 6Q
Low Input Current of 1 µA Max
Inputs Are TTL-Voltage Compatible
Eight High-Current Latches in a Single
Package
14
6D
13 5D
12 5Q
11 LE
Full Parallel Access for Loading
GND 10
description/ordering information
SN54HCT373 . . .FK PACKAGE
(TOP VIEW)
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
3
2
1
20 19
18
8D
7D
7Q
2D
2Q
3Q
3D
4D
4
5
6
7
8
17
16
The eight latches of the ’HCT373 devices are
transparent
D-type
latches.
While
the
15 6Q
14
9 10 11 12 13
latch-enable (LE) input is high, the Q outputs
follow the data (D) inputs. When LE is taken low,
the Q outputs are latched at the levels that were
set up at the D inputs.
6D
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – N
Tube of 20
Tube of 25
Reel of 2000
Reel of 2000
Reel of 2000
Tube of 70
Reel of 2000
Reel of 250
Tube of 20
Tube of 85
Tube of 55
SN74HCT373N
SN74HCT373N
SN74HCT373DW
SN74HCT373DWR
SN74HCT373NSR
SN74HCT373DBR
SN74HCT373PW
SN74HCT373PWR
SN74HCT373PWT
SNJ54HCT373J
SOIC – DW
HCT373
SOP – NS
HCT373
HT373
–40°C to 85°C
SSOP – DB
TSSOP – PW
HT373
CDIP – J
CFP – W
LCCC – FK
SNJ54HCT373J
SNJ54HCT373W
–55°C to 125°C
SNJ54HCT373W
SNJ54HCT373FK
SNJ54HCT373FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT373, SN74HCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS009D – MARCH 1984 – REVISED AUGUST 2003
description/ordering information (continued)
An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or
the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are off.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
logic diagram (positive logic)
1
OE
11
LE
C1
1D
2
1Q
3
1D
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT373, SN74HCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS009D – MARCH 1984 – REVISED AUGUST 2003
recommended operating conditions (see Note 3)
SN54HCT373
MIN NOM MAX
SN74HCT373
MIN NOM MAX
UNIT
V
V
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
V
V
= 4.5 V to 5.5 V
= 4.5 V to 5.5 V
CC
0.8
0.8
V
CC
0
0
V
V
0
0
V
V
V
CC
CC
Output voltage
V
O
CC
CC
∆t/∆v
Input transition rise/fall time
Operating free-air temperature
500
125
500
85
ns
°C
T
A
–55
–40
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HCT373 SN74HCT373
A
PARAMETER
TEST CONDITIONS
V
UNIT
V
CC
MIN
TYP
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
I
I
I
= –20 µA
= –6 mA
= 20 µA
= 6 mA
4.4 4.499
OH
OH
OL
OL
V
V = V or V
IH
4.5 V
4.5 V
OH
OL
I
IL
IL
3.98
4.3
0.001
0.17
0.1
3.7
3.84
0.1
0.26
100
0.5
8
0.1
0.4
0.1
0.33
1000
5
V
V = V or V
V
I
IH
I
I
I
V = V
I
or 0
5.5 V
5.5 V
5.5 V
1000
10
nA
µA
µA
I
CC
V
O
= V or 0
CC
0.01
OZ
CC
V = V
I
or 0,
I
O
= 0
160
80
CC
One input at 0.5 V or 2.4 V,
Other inputs at 0 or V
†
5.5 V
1.4
3
2.4
10
3
2.9
10
mA
pF
∆I
CC
CC
4.5 V
to 5.5 V
C
10
i
†
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or V
.
CC
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HCT373 SN74HCT373
A
V
UNIT
ns
CC
MIN
20
17
10
9
MAX
MIN
30
27
15
14
10
10
MAX
MIN
25
23
13
12
10
10
MAX
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
10
10
ns
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT373, SN74HCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS009D – MARCH 1984 – REVISED AUGUST 2003
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
25
SN54HCT373 SN74HCT373
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
35
32
35
32
35
32
35
32
12
11
MIN
MAX
53
48
53
48
53
48
53
48
18
16
MIN
MAX
44
40
44
40
44
40
44
40
15
14
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
D
Q
21
t
pd
ns
28
LE
OE
OE
Any Q
Any Q
Any Q
Any Q
25
26
t
t
t
ns
ns
ns
en
dis
t
23
23
22
10
9
switching characteristics over recommended operating free-air temperature range, C = 150 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
32
SN54HCT373 SN74HCT373
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
52
MIN
MAX
79
MIN
MAX
65
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
D
Q
27
47
71
59
t
pd
ns
38
52
79
65
LE
Any Q
Any Q
Any Q
36
47
71
59
33
52
79
65
t
t
ns
ns
OE
en
28
47
71
59
18
42
63
53
t
16
38
57
48
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance per latch
No load
50
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT373, SN74HCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS009D – MARCH 1984 – REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
PARAMETER
R
C
S1
S2
L
L
50 pF
or
150 pF
t
Open
Closed
Closed
Open
PZH
S1
S2
Test
Point
t
t
1 kΩ
1 kΩ
en
t
R
PZL
L
From Output
Under Test
t
t
Open
Closed
Open
PHZ
PLZ
50 pF
dis
C
L
Closed
(see Note A)
50 pF
or
150 pF
t
or t
––
Open
Open
pd
t
LOAD CIRCUIT
3 V
Reference
Input
1.3 V
3 V
0 V
High-Level
0 V
1.3 V
1.3 V
1.3 V
Pulse
t
t
h
su
3 V
0 V
t
Data
Input
w
2.7 V
2.7 V
1.3 V
0.3 V
1.3 V
0.3 V
3 V
0 V
Low-Level
Pulse
1.3 V
t
t
r
f
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
Output
Control
(Low-Level
Enabling)
3 V
0 V
3 V
0 V
Input
1.3 V
1.3 V
1.3 V
1.3 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
V
V
OH
≈V
CC
In-Phase
Output
Output
Waveform 1
(See Note B)
90%
t
1.3 V
10%
1.3 V
10%
1.3 V
1.3 V
10%
t
OL
V
OL
OH
t
r
f
f
t
t
t
PHL
90%
PLH
PZH
PHZ
Out-of-
Phase
Output
V
V
OH
V
Output
Waveform 2
(See Note B)
90%
t
90%
1.3 V
10%
1.3 V
10%
OL
≈0 V
t
r
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
PHL
.
en
.
pd
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CDIP
CFP
Drawing
5962-86867012A
5962-8686701RA
5962-8686701VRA
5962-8686701VSA
JM38510/65453BRA
JM38510/65453BSA
SN54HCT373J
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
20
20
20
20
20
20
20
1
1
None
None
None
None
None
None
None
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
J
1
W
J
1
CDIP
CFP
1
W
J
1
CDIP
SOIC
1
SN74HCT373DW
DW
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
SN74HCT373DWR
SN74HCT373N
ACTIVE
ACTIVE
SOIC
PDIP
DW
N
20
20
2000
20
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74HCT373N3
OBSOLETE
ACTIVE
PDIP
SO
N
20
20
None
Call TI
Call TI
SN74HCT373NSR
NS
2000
70
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74HCT373PW
ACTIVE
TSSOP
PW
20
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
SN74HCT373PWLE
SN74HCT373PWR
OBSOLETE TSSOP
PW
PW
20
20
None
Call TI
Call TI
ACTIVE
TSSOP
2000
250
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
SN74HCT373PWT
ACTIVE
TSSOP
PW
20
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
SNJ54HCT373FK
SNJ54HCT373J
SNJ54HCT373W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
20
20
1
1
1
None
None
None
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 2005, Texas Instruments Incorporated
SN74HCT373NE4 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| SN74HCT373PWR | TI | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS | 完全替代 |
|
| SN74HCT373DW | TI | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS | 类似代替 |
|
| SN74HCT373DWR | TI | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS | 类似代替 |
|
SN74HCT373NE4 相关器件
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| SN74HCT373NP1 | TI | IC,LATCH,SINGLE,8-BIT,HCT-CMOS,DIP,20PIN,PLASTIC | 获取价格 |
|
| SN74HCT373NSR | TI | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS | 获取价格 |
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| SN74HCT373NSRE4 | TI | Octal Transparent D-Type Latches With 3-State Outputs 20-SO -40 to 85 | 获取价格 |
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| SN74HCT373PW | TI | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS | 获取价格 |
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| SN74HCT373PWG4 | TI | Octal Transparent D-Type Latches With 3-State Outputs 20-TSSOP -40 to 85 | 获取价格 |
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| SN74HCT373PWLE | TI | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS | 获取价格 |
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| SN74HCT373PWR | TI | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS | 获取价格 |
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| SN74HCT373PWT | TI | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS | 获取价格 |
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| SN74HCT373PWTG4 | TI | Octal Transparent D-Type Latches With 3-State Outputs 20-TSSOP -40 to 85 | 获取价格 |
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