概述
规格参数
数据手册
替代型号SN74LVC16373DLR 概述
具有三态输出的 16 位透明 D 型锁存器 | DL | 48 | -40 to 85 总线驱动器/收发器
SN74LVC16373DLR 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 零件包装代码： | SSOP |
| 包装说明： | SSOP, SSOP48,.4 | 针数： | 48 |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | Factory Lead Time： | 1 week |
| 风险等级： | 0.65 | 控制类型： | ENABLE LOW/HIGH |
| 系列： | LVC/LCX/Z | JESD-30 代码： | R-PDSO-G48 |
| JESD-609代码： | e4 | 长度： | 15.88 mm |
| 负载电容（CL）： | 50 pF | 逻辑集成电路类型： | BUS DRIVER |
| 最大I（ol）： | 0.024 A | 湿度敏感等级： | 1 |
| 位数： | 8 | 功能数量： | 2 |
| 端口数量： | 2 | 端子数量： | 48 |
| 最高工作温度： | 85 °C | 最低工作温度： | -40 °C |
| 输出特性： | 3-STATE | 输出极性： | TRUE |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | SSOP |
| 封装等效代码： | SSOP48,.4 | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE, SHRINK PITCH | 包装方法： | TR |
| 峰值回流温度（摄氏度）： | 260 | 电源： | 3.3 V |
| 最大电源电流（ICC）： | 0.04 mA | Prop。Delay @ Nom-Sup： | 7 ns |
| 传播延迟（tpd）： | 9 ns | 认证状态： | Not Qualified |
| 座面最大高度： | 2.79 mm | 子类别： | FF/Latches |
| 最大供电电压 (Vsup)： | 3.6 V | 最小供电电压 (Vsup)： | 2.7 V |
| 标称供电电压 (Vsup)： | 3.3 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | INDUSTRIAL |
| 端子面层： | Nickel/Palladium/Gold (Ni/Pd/Au) | 端子形式： | GULL WING |
| 端子节距： | 0.635 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 翻译： | N/A |
| 宽度： | 7.49 mm | Base Number Matches： | 1 |
SN74LVC16373DLR 数据手册
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PDF下载SN74LVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS315B – NOVEMBER 1993 – REVISED JULY 1995
DGG OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
1LE
1D1
1D2
GND
1D3
1D4
2
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
3
= 3.3 V, T = 25°C
CC
A
4
Typical V
> 2 V at V
(Output V
Undershoot)
OHV
CC
OH
5
= 3.3 V, T = 25°C
A
6
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
7
V
V
CC
CC
8
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
9
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 16-bit transparent D-type latch is designed
for 2.7-V to 3.6-V V operation.
V
V
CC
CC
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
2D5
2D6
GND
2D7
2D8
2LE
The SN74LVC16373 is particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers. It
can be used as two 8-bit latches or one 16-bit
latch. Whenthelatch-enable(LE)inputishigh, the
Q outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the levels
set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVC16373 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS315B – NOVEMBER 1993 – REVISED JULY 1995
FUNCTION TABLE
(each 8-bit section)
INPUTS
OUTPUT
Q
LE
H
H
L
D
H
L
OE
L
H
L
L
L
X
X
Q
0
H
X
Z
†
logic symbol
logic diagram (positive logic)
1
1
1OE
1OE
1LE
2OE
2LE
1EN
C3
48
24
25
48
1LE
2EN
C4
C1
2
1Q1
47
1D1
1D
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
3D
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
1
3
5
6
To Seven Other Channels
8
9
11
12
13
14
16
17
19
20
22
23
24
25
2OE
2LE
4D
2
C1
1D
13
2Q1
36
2D1
To Seven Other Channels
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS315B – NOVEMBER 1993 – REVISED JULY 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Maximum power dissipation at T = 55°C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . 0.85 W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
A
DL package . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Formoreinformation,refertothePackageThermalConsiderationsapplicationnoteinthe1994ABTAdvancedBiCMOSTechnology
Data Book, literature number SCBD002B.
recommended operating conditions (see Note 4)
MIN
2.7
2
MAX
UNIT
V
V
V
V
V
Supply voltage
3.6
V
V
V
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
V
V
= 2.7 V to 3.6 V
= 2.7 V to 3.6 V
CC
0.8
CC
0
0
V
V
CC
Output voltage
O
CC
V
CC
V
CC
V
CC
V
CC
= 2.7 V
= 3 V
–12
–24
12
I
High-level output current
Low-level output current
mA
mA
OH
OL
= 2.7 V
= 3 V
I
24
∆t/∆V
Input transition rise or fall rate
Operating free-air temperature
0
10
ns/V
T
A
–40
85
°C
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS315B – NOVEMBER 1993 – REVISED JULY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
‡
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP
–0.2
MAX
UNIT
I
I
= –100 µA
MIN to MAX
V
OH
CC
2.2
2.7
V
= –12 mA
V
OH
OL
OH
3
2.4
2
I
I
I
I
= –24 mA
= 100 µA
= 12 mA
= 24 mA
3
OH
OL
OL
OL
MIN to MAX
0.2
0.4
V
2.7
3
V
0.55
±5
I
I
V = V
or GND
3.6
µA
µA
I
I
CC
V = 0.8 V
75
I
Data inputs
3
I(hold)
V = 2 V
–75
I
I
I
V
= V
or GND
3.6
3.6
±10
40
µA
µA
µA
pF
pF
OZ
O
CC
or GND,
V = V
I
I
= 0
CC
CC
O
I
i
One input at V
– 0.6 V,
Other inputs at V or GND
CC
3 V to 3.6 V
3.3
500
CC
CC
or GND
C
C
V = V
I
3.5
7
CC
= V or GND
CC
V
O
3.3
o
†
‡
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
All typical values are at V = 3.3 V, T = 25°C.
CC
A
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
V
= 3.3 V
CC
± 0.3 V
V
= 2.7 V
MAX
CC
UNIT
MIN
4
MAX
MIN
4
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
2
2
2
2
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
V
= 3.3 V
± 0.3 V
CC
V
= 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
CC
PARAMETER
UNIT
MIN
1.5
2
MAX
MIN
MAX
D
7
8
8
9
t
pd
Q
ns
LE
t
t
Q
Q
1.5
1.5
8
7
9
8
ns
ns
OE
OE
en
dis
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
TYP
20
4
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance per latch
C
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS315B – NOVEMBER 1993 – REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
6 V
Open
TEST
S1
S1
500 Ω
From Output
Under Test
t
Open
6 V
pd
/t
t
GND
PLZ PZL
t
/t
GND
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
2.7 V
0 V
LOAD CIRCUIT FOR OUTPUTS
1.5 V
Timing Input
Data Input
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
1.5 V
1.5 V
Input
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
Input
1.5 V
1.5 V
t
PZL
t
t
t
PHL
PLH
PHL
t
PLZ
Output
Waveform 1
S1 at 6 V
V
V
3 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
– 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
OH
1.5 V
1.5 V
Output
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
SN74LVC16373DLR CAD模型
原理图符号
PCB 封装图
SN74LVC16373DLR 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| SN74LVC16373ADL | TI | 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS | 类似代替 |
|
| SN74LVC16373ADLR | TI | 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS | 类似代替 |
|
| SN74LVC16373DL | TI | 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS | 类似代替 |
|
SN74LVC16373DLR 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| SN74LVC16373DLRG4 | TI | LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, 0.300 INCH, GREEN, PLASTIC, SSOP-48 | 获取价格 |
|
| SN74LVC16374 | TI | 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS | 获取价格 |
|
| SN74LVC16374A | TI | 16 BIT EDGE TRIGGERED D TYPE FLIP FLOP WITH 3 STATE OUTPUTS | 获取价格 |
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| SN74LVC16374ADGGR | TI | 16 BIT EDGE TRIGGERED D TYPE FLIP FLOP WITH 3 STATE OUTPUTS | 获取价格 |
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| SN74LVC16374ADGVR | TI | 16 BIT EDGE TRIGGERED D TYPE FLIP FLOP WITH 3 STATE OUTPUTS | 获取价格 |
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| SN74LVC16374ADL | TI | 16 BIT EDGE TRIGGERED D TYPE FLIP FLOP WITH 3 STATE OUTPUTS | 获取价格 |
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| SN74LVC16374ADLG4 | TI | 16 BIT EDGE TRIGGERED D TYPE FLIP FLOP WITH 3 STATE OUTPUTS | 获取价格 |
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| SN74LVC16374ADLR | TI | 16 BIT EDGE TRIGGERED D TYPE FLIP FLOP WITH 3 STATE OUTPUTS | 获取价格 |
|
| SN74LVC16374ADLRG4 | TI | 16 BIT EDGE TRIGGERED D TYPE FLIP FLOP WITH 3 STATE OUTPUTS | 获取价格 |
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| SN74LVC16374AGQLR | TI | 16 BIT EDGE TRIGGERED D TYPE FLIP FLOP WITH 3 STATE OUTPUTS | 获取价格 |
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