BUS
NOR FATEN AZIA BINTI
CONTENTS
Tittle
1. 2. 3. 4. 5. 6. 7. 8.
Definition Of Bus Buses Data bus Address Bus Control Bus Big and yellow Single bus Problems Traditional (ISA) (with cache)
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9. High Performance Bus 10. Bus Types 11. Bus Arbitration 12. Traditional (ISA) (with cache) 13. Distributed Arbitration
WHAT IS A BUS?
A communication pathway connecting two or more devices Usually broadcast Often grouped
A number of channels in one bus
e.g. 32 bit data bus is 32 separate single bit channels
BUSES
There are a number of possible interconnection systems Single and multiple BUS structures are most common
e.g. Control/Address/Data bus (PC)
e.g. Unibus (DEC-PDP)
DATA BUS
Carries data
Remember that there is no difference between data and instruction at this level
Width is a key determinant of performance
8, 16, 32, 64 bit
ADDRESS BUS
Identify the source or destination of data e.g. CPU needs to read an instruction (data) from a given location in memory Bus width determines maximum memory capacity of system
e.g. 8080 has 16 bit address bus giving 64k address space
CONTROL BUS
Control and timing information
Memory read/write signal Interrupt request
Clock signals
BIG AND YELLOW?
What do buses look like?
Parallel lines on circuit boards Ribbon cables
Strip connectors on motherboards
e.g. PCI
Sets of wires
SINGLE BUS PROBLEMS
Lots of devices on one bus leads to:
Propagation delays
Long data paths mean that co-ordination of bus use can adversely affect performance
If aggregate data transfer approaches bus capacity
Most systems use multiple buses to overcome these problems
TRADITIONAL (ISA) (WITH CACHE)
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HIGH PERFORMANCE BUS
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BUS TYPES
Dedicated
Separate data & address lines
Multiplexed
Shared lines
Address valid or data valid control line Advantage - fewer lines Disadvantages
More complex control Ultimate performance
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BUS ARBITRATION
More than one module controlling the bus
e.g. CPU and DMA controller
Only one module may control bus at one time Arbitration may be centralized or distributed
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CENTRALIZED ARBITRATION
Single hardware device controlling bus access
Bus Controller Arbiter
May be part of CPU or separate
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DISTRIBUTED ARBITRATION
There is no central controller; rather, each module contains access control logic and the modules act together to share the bus Each module may claim the bus Control logic on all modules
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THE END
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