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We would like to express our deep gratitude to Dr.Rahul Dubey, who not
only gave us this opportunity to work on this project, but also guided and
encouraged us throughout the course. He and TAs of the course, Neeraj
Chasta and Purushothaman, patiently helped us throughout the project. We
take this as opportunity to thank them and our classmates and friends for
extending their support and worked together in a friendly learning
environment. And last but not the least, we would like to thank non-teaching
lab staff who patiently helped us to understand that all kits were working
properly.

By

Subhash C
A N Manoj Kumar
Parth Goswami
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m. PROBLEM STATEMENT 4

2. ABSTRACT 4

3. INTRODUCTION 5

3.m. FLOATING POINT FORMAT USED 6

3.2. DETECTION OF SPECIAL INPUTS 6

4. FLOATING POINT ADDER/SUBTRACTOR 8

5. FLOATING POINT MULTIPLIER 9

5.m. ARCHITECTURE FOR FLOATING POINT MULTIPLICATION m

5.2. DESIGNED 4 * 4 BIT MULTIPLIER. m2

6. VERIFICATION PLAN m4

7. SIMULATION RESULTS & RTL SCHEMATICS m5

8. FLOOR PLAN OF DESIGN & MAPPING REPORT 2m

9. POWER ANALYSIS USING XPOWER ANALYZER 25

m . CONCLUSION 26

mm. FUTURE SCOPE 26

m2. REFERENCES 27

m3. APPENDIX 28

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Implement the arithmetic (addition/subtraction & multiplication) for IEEE-754

single precision floating point numbers on FPGA. Display the resultant value
on LCD screen.

?  
:

Floating point operations are hard to implement on FPGAs because of the

complexity of their algorithms. On the other hand, many scientific problems
require floating point arithmetic with high levels of accuracy in their
calculations. Therefore, we have explored FPGA implementations of addition
and multiplication for IEEE-754 single precision floating-point numbers. For
floating point multiplication, in IEEE single precision format, we have to
multiply two 24 bits. As we know that in Spartan 3E, m8 bit multiplier is
already there. The main idea is to replace the existing m8 bit multiplier with a
dedicated 24 bit multiplier designed with small 4 bit multiplier. For floating
point addition, exponent matching and shifting of 24 bit mantissa and sign
logic are coded in behavioral style. Entire our project is divided into 4 modules.
m. Designing of floating point adder/subtractor.
2. Designing of floating point multiplier.
3. Creation of combined control & data paths.
4. I/O interfacing: Interfacing of LCD for displaying the output and
tacking inputs from block RAM.
Prototypes have been implemented on Xilinx Spartan 3E.

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Image and digital signal processing applications require high floating

point calculations throughput, and nowadays FPGAs are being used for
performing these Digital Signal Processing (DSP) operations. Floating point
operations are hard to implement on FPGAs as their algorithms are quite
complex. In order to combat this performance bottleneck, FPGAs vendors
including Xilinx have introduced FPGAs with nearly 254 m8xm8 bit dedicated
multipliers. These architectures can cater the need of high speed integer
operations but are not suitable for performing floating point operations
especially multiplication. Floating point multiplication is one of the
performance bottlenecks in high speed and low power image and digital signal
processing applications. Recently, there has been significant work on analysis
of high-performance floating-point arithmetic on FPGAs. But so far no one has
addressed the issue of changing the dedicated m8xm8 multipliers in FPGAs by
an alternative implementation for improvement in floating point efficiency. It is
a well known concept that the single precision floating point multiplication
algorithm is divided into three main parts corresponding to the three parts of
the single precision format. In FPGAs, the bottleneck of any single precision
floating-point design is the 24x24 bit integer multiplier required for
multiplication of the mantissas. In order to circumvent the aforesaid problems,
we designed floating point multiplication and addition.

The designed architecture can perform both single precision floating

point addition as well as single precision floating point multiplication with a
single dedicated 24x24 bit multiplier block designed with small 4x4 bit
multipliers. The basic idea is to replace the existing m8xm8 multipliers in FPGAs
by dedicated 24x24 bit multiplier blocks which are implemented with dedicated
4x4 bit multipliers. This architecture can also be used for integer multiplication
as well.

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As mentioned above, the IEEE Standard for Binary Floating Point

Arithmetic (ANSI/IEEE Std 754-m985) will be used throughout our work. The
single precision format is shown in Figure m. Numbers in this format are
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composed of the following three fields:
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m
  : A value of ¶m
indicates that the number is negative, and a ¶

indicates a positive number.

 m 
This gives us an exponent range from
Emin = -m26 to = m27.

: The fractional part of the number.

The fractional part must not be confused with the significand, which is m plus
the fractional part. The leading m in the significand is implicit. When
performing arithmetic with this format, the implicit bit is usually made explicit.
To determine the value of a floating point number in this format we use the
following formula:

?= (-m)sign x  m x m!m"!!!!!m"

Fig m. Representation of floating point number

2?
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? In the ieee-754 single precision floating point numbers support three
special inputs

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The two infinities, + and - , represent the maximum positive and

negative real numbers, respectively, that can be represented in the floating-
point format. Infinity is always represented by a zero significand (fraction and

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integer bit) and the maximum biased exponent allowed in the specified format
(for example, 255m for the single-real format).

The signs of infinities are observed, and comparisons are possible.

Infinities are always interpreted in the affine sense; that is, ¨ is less than any
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finite number and + is greater than any finite number. Arithmetic on infinities
is always exact. Exceptions are generated only when the use of infinity as a
source operand constitutes an invalid operation.

Whereas de-normalized numbers represent an underflow condition, the

two infinity numbers represent the result of an overflow condition. Here, the
normalized result of a computation has a biased exponent greater than the
largest allowable exponent for the selected result format.

 ?

Since NaNs are non-numbers, they are not part of the real number line.
The encoding space for NaNs in the FPU floating-point formats is shown above
the ends of the real number line. This space includes any value with the
maximum allowable biased exponent and a non-zero fraction. (The sign bit is
ignored for NaNs.)

The IEEE standard defines two classes of NaNs: quiet NaNs (QNaNs) and
signaling NaNs (SNaNs). A QNaN is a NaN with the most significant fraction bit
set; an SNaN is a NaN with the most significant fraction bit clear. QNaNs are
allowed to propagate through most arithmetic operations without signaling an
exception. SNaNs generally signal an invalid-operation exception whenever they
appear as operands in arithmetic operations.

Though zero is not a special input, if one of the operands is zero, then
the result is known without performing any operation, so a zero which is
denoted by zero exponent and zero mantissa. One more reason to detect zeroes
is that it is difficult to find the result as adder may interpret it to decimal value
m after adding the hidden ¶m
to mantissa.

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Floating-point addition has mainly three parts:

m. Adding hidden ¶m
and Alignment of the mantissas to make exponents

equal.
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2. Addition of aligned mantissas.
3. Normalization and rounding the Result.

The initial mantissa is of 23-bits wide. After adding the hidden ¶m
,it is
24-bits wide.

First the exponents are compared by subtracting one from the other and
looking at the sign (MSB which is carry) of the result. To equalize the
exponents, the mantissa part of the number with lesser exponent is shifted
right d-times. where ¶d
is the absolute value difference between the exponents.

The sign of larger number is anchored. The xor of sign bits of the two
numbers decide the operation (addition/ subtraction) to be performed.

Now, as the shifting may cause loss of some bits and to prevent this to
some extent, generally the length of mantissas to be added is no longer 24-bits.
In our implementation, the mantissas to be added are 25-bits wide. The two
mantissas are added (subtracted) and the most significant 24-bits of the
absolute value of the result form the normalized mantissa for the final packed
floating point result.

Again xor of anchor-sign bit and the sign of result forms the sign bit for
the final packed floating point result.

The remaining part of result is exponent. Before normalizing the result

Value of exponent is same as the anchored exponent which is the larger of two
exponents. In normalization, the leading zeroes are detected and shifted so that
a leading one comes. Exponent also changes accordingly forming the exponent
for the final packed floating point result.

The whole process is explained clearly in the below figure.?

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??????????????????????Fig 2. Architecture for floating point adder/subtractor

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The single precision floating point algorithm is divided into three main
parts corresponding to the three parts of the single precision format. The first
part of the product which is the sign is determined by an exclusive OR function
of the two input signs. The exponent of the product which is the second part is
Calculated by adding the two input exponents. The third part which is the
significand of the product is determined by multiplying the two input
significands each with a ´m concatenated to it.
Below figure shows the architecture and flowchart of the single precision
floating point multiplier. It can be easily observed from the Figure that 24x24

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bit integer multiplier is the main performance bottleneck for high speed and
low power operations. In FPGAs, the availability of the dedicated m8xm8
multipliers instead of dedicated 24x24 bit multiply blocks further complicates
this problem.

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We proposed the idea of a combined floating point multiplier and adder

for FPGAs. In this, it is proposed to replace the existing m8xm8 bit multipliers in
FPGAs with dedicated blocks of 24x24 bit integer multipliers designed with 4x4
bit multipliers. In the designed architecture, the dedicated 24x24 bit
multiplication block is fragmented to four parallel m2xm2 bit multiplication
module, where AH, AL, BH and BL are each of m2 bits. The m2xm2
multiplication modules are implemented using small 4x4 bit multipliers. Thus,
the whole 24x24 bit multiplication operation is divided into 36 4x4 multiply
modules working in parallel. The m2 bit numbers A & B to be multiplied are
divided into 4 bits groups A3,A2,Am and B3,B2,Bm respectively. The flowchart
and the architecture for the multiplier block are shown below.

fig 3. Flowchart for floating point multiplication

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fig 4. Designed architecture for floating point multiplication


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The additional advantage of the proposed CIFM is that floating point
multiplication operation can now be performed easily in FPGA without any
resource and performance bottleneck. In the single precision floating point
multiplication, the mantissas are of 23 bits. Thus, 24x24 bit (23 bit mantissa
+m hidden bit) multiply operation is required for getting the intermediate
product. With the proposed architecture, the 24x24 bit mantissa multiplication
can now be easily performed by passing it to the dedicated 24x24 bit multiply
block, which will generate the product with its dedicated small 4x4 bit
multipliers.

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As evident from the proposed architecture, a high speed low power

dedicated 4x4 bit multiplier will significantly improve the efficiency of the
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designed architecture. Thus, a dedicated 4x4 bit multiplier efficient in terms of
area, speed and power is proposed. Figure 5 shows the architecture of the
proposed multiplier. For (4 X 4) bits, 4 partial products are generated, and are
added in parallel. Each two adjacent partial product are subdivided to 2 bit
blocks, where a 2 bit sum is generated by employing a 2-bit parallel adder
appropriately designed by choosing the combination of half adder-half adder,
Half adder - full adder (forming the blocks m,2,3,4 working in parallel).

This forms the first level of computation. The partial sums thus
generated are added again in block 5 & 6 (parallel adders), working in parallel
by appropriately choosing the combination of half adders and full adders. This
forms the second level of computation. The partial sums generated in the
second level are utilized in the third level (blocks 7 &8) to arrive at the final
product. Hence, there is a significant reduction in the power consumption
since the whole computation has been hierarchically divided to levels. The
reason for this stems from the fact that power is provided only to the level that
is involved in computation and thereby rendering the remaining two levels
switched off (by employing a control circuitry). Working in parallel significantly
improves the speed of the proposed multiplier.

The proposed architecture is highly optimized in terms of area, speed and

power. The proposed architecture is functionally verified in Verilog HDL and
synthesized in Xilinx FPGA. Designed 4 bit multiplier architecture is shown
below.

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Fig 5. Designed 4 bit optimized multiplier

The simulation results, RTL schematics of the designed architecture,

synthesis report and verilog code are shown below.

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? We chose inputs to various sub blocks such that all the logic blocks are
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ensured to function properly. All the internal signals are verified as follows.
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We gave various random inputs even without knowing what the order of
the inputs means and then analyzed the same inputs to know the expected
output and then verified using simulation as shown below.

 
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BFAE6666 -m.3625
4423m762 652.3654
C479C8 -999.m25
C25m 83m -52.258
ZERO
7FC NOT A NUMBER
7F8 +VE INFINITY
FF8 -VE INFINITY

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4
H O C45E364m
m 4422C 2E
4
Hm O C9mF2m28
m C3AD6m3C
4
H2 O 474BF446
m C4836C4m
4
H3 O BE3B4AEB
m C25m 49C

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RTL SCHEMATIC FOR TOP MODULE:

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BLACKBOX TEST-TOP ARITHMETIC MODULE:

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DATA PATH & CONTROL:

BLOCK DIAGRAM FOR DATA PATH & CONTROL

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RTL SCHEMATIC FOR DATAPATH & CONTROLLER:

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TEST FOR DATAPATH & CONTROLLER:

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VARIOUS SIGNALS ² DESCRIPTION (ADDER/SUBTRACTOR MODULE):

m.? A,B: input 32-bit single precision numbers

2.? C:output 32-bit single precision number
3.? sm,s2,s3, em,e2,e3 &fm,f2,f3: sign ,exponent and fraction parts of inputs
4.? new_fm,new_f2:aligned mantissas
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5.? de: difference between exponents
6.? fr:25-bit result of addition of mantissas
7.? fr_us: unsigned 25-bit result
8.? f_fr:normalized 24-bit fraction result
9.? er,sr:exponent and sign of result

RTL SCHEMATIC FOR ADDER MODULE: aa a

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TEST FOR ADDER MODULE:

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VARIOUS SIGNALS ² DESCRIPTION (MULTIPLIER MODULE):

m.? INm,IN2: input 32-bit single precision numbers

2.? OUT: output 32-bit single precision number
3.? SA,SB,EA,EB,MA,MB: sign ,exponent and mantissa parts of inputs
4.? PFPM: 48 bit multiplication result
5.? SPFPM: shifted result of multiplication
6.? EFPM: exponent result (output of exponent addition module)
7.? PFP: 48 bit fraction multiplication result
8.? SFP: m bit sing of final result
9.? EFP: 8 bit exponent of final result
m .?MFP: 23 bit mantissa of final result

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RTL SCHEMATIC FOR MULTIPLIER MODULE:

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TEST FOR MULTIPLICATION MODULE:

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FLOOR PLAN WITHOUT PIN CONNECTIONS:

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FLOOR PLAN WITH PIN CONNECTIONS:

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.#  ??
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======================================================================
* Final Report *
======================================================================
Final Results
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RTL Top Level Output File Name : TOPMODULE.ngr
Top Level Output File Name : TOPMODULE
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO

Design Statistics
# IOs : 38

Cell Usage:
# BELS : 3944
# GND :3
# INV : mm
# LUTm : 48
# LUT2 : 4m7
# LUT3 : 628
# LUT4 : m777
# MULT_AND : mm2
# MUXCY : 375
# MUXF5 :2 7
# MUXF6 :2
# MUXF7 :m
# VCC :3
# XORCY : 36
# RAMS :2
# RAMBm6_S36 :2
# Clock Buffers :m
# BUFGP :m
# IO Buffers : 37
# IBUF :5
# OBUF : 32
======================================================================

Device utilization summary:

Selected Device: 3s5 efg32 -5

Number of Slices: m6m6 out of 4656 34%
Number of 4 input LUTs: 288m out of 93m2 3 %
Number of IOs: 38
Number of bonded IOBs: 38 out of 232 m6%
Number of BRAMs: 2 out of 2 m %
Number of GCLKs: m out of 24 4%
=====================================================================

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TIMING REPORT
======================================================================
Clock Information:
------------------
No clock signals found in this design
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Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: m2.253ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

Timing constraint: Default path analysis

Total number of paths / destination ports: 96 / 32
-------------------------------------------------------------------------
Delay: m2.253ns (Levels of Logic = 9)
Source: cntr (PAD)
Destination: out<m6> (PAD)

Data Path: cntr to out<m6>

Gate Net
Cell: in->out fan-out Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF: I->O 59 m.m 6 m.232 cntr_IBUF (cntr_IBUF)
LUT4:I ->O 8 .6m2 .795 FPARITH/OUT<29>4m (FPARITH/N372)
LUT4:I ->O m .6m2 . FPARITH/OUT<m6>2mm(FPARITH/OUT<m6>2mm)
MUXF5:Im->O m .278 .5 9 FPARITH/OUT<m6>2m_f5(FPARITH/OUT<m6>2m)
LUT4:I ->O m .6m2 .387 FPARITH/OUT<m6>4 _SW (N666)
LUT4:I2->O m .6m2 .36 FPARITH/OUT<m6>4 (FPARITH/OUT<m6>4 )
LUT4:I3->O m .6m2 .387 FPARITH/OUT<m6>5m_SW (N668)
LUT4:I2->O m .6m2 .357 FPARITH/OUT<m6>5m(FPARITH/OUT<m6>5m)
OBUF:I->O 3.m69 out_m6_OBUF (out<m6>)
------------------------------------------------------------------------------------------------------
Total m2.253ns (8.225ns logic, 4. 28ns route) (67.m% logic, 32.9% route)

======================================================================

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We have successfully implemented arithmetic (adder/subtract &
multiplication) for IEEE single precision floating point numbers on FPGA, and
displayed the corresponding output values on LCD as well.
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As we have used a MUX to select the outputs of two computational

blocks, both adder and multiplier are active though only one of them is needed
to be active at a time. This consumes lot of dynamic power which can be
reduced by disabling one of them when not required
One more addition that can be made to design is that we can skip an
entire 4*4 adder block in multiplier when we have zeroes to add with (this
scenario is very much likely to occur in floating point operations) .

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m. www.xilinx.com
2. Himanshu Thapliyal, Hamid R. Arabnia, A.P Vinod , 
#  #
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3. Computer arithmetic: Algorithms and hardware design by Behrooz Parhami
4. Computer arithmetic algorithm by Isreal Koren
5. www.randelshofer.ch/fhw/gri/lcd-init for some part of code in lcd
interfacing.
6.a http://babbage.cs.qc.cuny.edu/IEEE-754/Decimal.html for java applets
regarding floating point conversions
7. HITACHI HD4478 _LCD data sheet.

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// MAIN MODULE FOR FLOATING POINT ARITHEMETIC //
aaa

(ADDITION/SUBTRACTION & MULTIPLICATION)
// IF CNTR == m: ADDITION/SUBTRACTION
// IF CNTR == : MULTIPLICATION
///////////////////////////////////////////////////////////

module FLOATINGPOINTARITHEMATIC(input [3m:  INm, input [3m:  IN2,

input cntr, input [m:  ZeroAdd, output [3m:  OUT);
wire [3m:  FPADD,FPMUL,OUTm;
wire [3m:  ADDZA = ZeroAdd[m ? IN2: INm;
assign OUT = ^ZeroAdd ? ADDZA : OUTm;

// INSTANTIATON OF FLOATINGPOINT ADDER MODULE

fpadder adder(.A(INm),.B(IN2),.C(FPADD));
// INSTATIATION OF FLOATINGPOINT MULTIPLICATION MODULE
FLOATINGMULTIPLICATION multiplication(.INm(INm),.IN2(IN2),.OUT(FPMUL));
// ASSIGNING THE REQUIRED VALUE TO OUTPUT VARIABLE DEPENDING
ON THE CONTROL(CNTR) VALUE
//assign OUT = cntr ? FPADD: FPMUL;
assign OUTm = cntr ? FPADD: FPMUL;

endmodule

// MODULE FOR FLOATING POINT MULTIPLICATION

module FLOATINGMULTIPLICATION(input [3m:  INm, input [3m:  IN2, output
[3m:  OUT);
// UNPACKING THE INPUT BITS AND ASSIGNING TO SOME OTHER
TEMPORARY VARIABLES
wire SA = INm [3m;
wire SB = IN2 [3m;
wire [7:  EA = INm [3 :23;
wire [7:  EB = IN2 [3 :23;
wire [23:  MA = { mbm,INm [22:  };
wire [23:  MB = { mbm,IN2 [22:  };
// DECLARATION OF WIRES
wire SFP;
wire [7:  EFPM,EFP;
wire [47:  PFPM, PFP;

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// GENERATION OF SIGN BIT USING XOR GATE

xor (SFP,SA,SB);
// INSTANTIATION OF EXPONENT ADDITION MODULE TO ADD
EXPONENTS
EXPONENTADDITION FPEXP(.A(EA),.B(EB),.E(EFPM));
// INSTANTIATIONG 24 BIT MULTIPLIER MODULE TO MULTIPLY FRACTION
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PART
MULTIPLIER24BIT FPMUL(.A(MA),.B(MB),.P(PFPM));
// SHIFTING STATEMENTS IF NECCESSARY
wire [m:  X = PFPM [47:46;
wire S = X[m ? m : ;
wire [47:  SPFPM = PFPM >> m;
assign PFP = S ? SPFPM : PFPM;
assign EFP = S ? EFPM+m : EFPM;
// OUTPUT OF 24 BIT MULTIPLIER WILL GIVE 48 BIT RESULT
// SO WE ARE TRUNCATING THE LEAST 24 BITS (THE FINAL RESULT IS
APPROXMATION)
wire [22:  MFP = PFP [45:23;
// PACKING THE RESULTS FOR GENERATING SINGLE PRECITION 32 BIT
OUTPUT
assign OUT = { SFP,EFP,MFP };
endmodule

// MODULE FOR ADDITOIN OF EXPONENTS

// NOTE THAT THE EXPONENTS ARE IN BIAS FORMAT
// SO WE NEED TO ADD THE BIASED EXPONENTS AND SUBTRACT m27 TO
GET PROPER BIAS
module EXPONENTADDITION(input [7:  A, input [7:  B, output [7:  E);
// DECLARATION OF WIRES AND ASSIGNING VALUES AT A TIME
// ADDING THE BIASED EXPONENTS AND SUBTRACTING m27 USING 2S
COMPLEMENT METHOD
wire [8:  X = A + B;
parameter Y = m bmmm m;
wire [m :  Z = X + Y;
// FINAL RESULT OF EXPONENT (IN THE BIAS FORMAT)
assign E = Z [7: ;
endmodule

// MODULE FOR 24 BIT MULTIPLIER USING m2 BIT MULTIPLIER

module MULTIPLIER24BIT(input [23:  A, input [23:  B, output [47:  P);
// DECLARATION OF WIRES AND ASSIGNING VALUES AT A TIME
// EACH 24 BIT INPUT IS DIVIDED INTO TWO m2 BIT VALUES
wire [mm:  AL = A [mm: ;
wire [mm:  AH = A [23:m2;
wire [mm:  BL = B [mm: ;

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wire [mm:  BH = B [23:m2;

wire [23:  ALBL,ALBH,AHBL,AHBH;
wire [35:  PL,PH;
// INSTANTIATION OF m2 BIT MULTIPLIERS BY PORT NAMES
MULTIPLIERm2BIT mulm(.A(AL),.B(BL),.P(ALBL));
MULTIPLIERm2BIT mul2(.A(AL),.B(BH),.P(ALBH));
aaa
MULTIPLIERm2BIT mul3(.A(AH),.B(BL),.P(AHBL));
MULTIPLIERm2BIT mul4(.A(AH),.B(BH),.P(AHBH));
// INSTANTIATION OF ADDER BLOCKS BY PORT NAMES
ADDER24IN36OUT adderm(.X(ALBL),.Y(AHBL),.W(PL));
ADDER24IN36OUT adder2(.X(ALBH),.Y(AHBH),.W(PH));
ADDER36IN48OUT adder3(.X(PL),.Y(PH),.W(P));
endmodule

// MODULE FOR ADDER INPUT BIT LENGTH IS 24 & OUTPUT BIT LENGTH
IS 36
module ADDER24IN36OUT(input [23:  X, input [23:  Y, output [35:  W);
wire [35:  XM = { m2b ,X };
wire [35:  YM = { Y,m2b };
assign W = XM + YM;
endmodule

// MODULE FOR ADDER INPUT BIT LENGTH IS 36 & OUTPUT BIT LENGTH
IS 48
module ADDER36IN48OUT(input [35:  X, input [35:  Y, output [47:  W);
wire [47:  XM = { m2b ,X };
wire [47:  YM = { Y,m2b };
assign W = XM + YM;
endmodule

// MODULE FOR m2 BIT MULTIPLIER USING 4 BIT MULTIPLIERS

module MULTIPLIERm2BIT(input [mm:  A, input [mm:  B, output [23:  P);
// DECLARATION OF WIRES AND ASSIGNING VALUES AT A TIME
// EACH m2 BIT INPUT IS DIVIDED INTO THREE 4 BIT VALUES
wire [3:  Am = A [3: ;
wire [3:  A2 = A [7:4;
wire [3:  A3 = A [mm:8;
wire [3:  Bm = B [3: ;
wire [3:  B2 = B [7:4;
wire [3:  B3 = B [mm:8;
// DECLARATION OF WIRES
wire [7:  AmBm,AmB2,AmB3;
wire [7:  A2Bm,A2B2,A2B3;
wire [7:  A3Bm,A3B2,A3B3;
wire [m5:  PL,PM,PH;

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// INSTANTIATION OF 4 BIT MULTIPLIERS BY PORT NAMES

MULTIPLIER4BIT mulm (.A(Am),.B(Bm),.P(AmBm));
MULTIPLIER4BIT mul2 (.A(Am),.B(B2),.P(AmB2));
MULTIPLIER4BIT mul3 (.A(Am),.B(B3),.P(AmB3));
MULTIPLIER4BIT mul4 (.A(A2),.B(Bm),.P(A2Bm));
MULTIPLIER4BIT mul5 (.A(A2),.B(B2),.P(A2B2));
aaa
MULTIPLIER4BIT mul6 (.A(A2),.B(B3),.P(A2B3));
MULTIPLIER4BIT mul7 (.A(A3),.B(Bm),.P(A3Bm));
MULTIPLIER4BIT mul8 (.A(A3),.B(B2),.P(A3B2));
MULTIPLIER4BIT mul9 (.A(A3),.B(B3),.P(A3B3));
// INSTANTIATION OF ADDER BLOCKS BY PORT NAMES
ADDER8INm6OUT adderm (.X(AmBm),.Y(A2Bm),.Z(A3Bm),.W(PL));
ADDER8INm6OUT adder2 (.X(AmB2),.Y(A2B2),.Z(A3B2),.W(PM));
ADDER8INm6OUT adder3 (.X(AmB3),.Y(A2B3),.Z(A3B3),.W(PH));
ADDERm6IN24OUT adder4 (.X(PL),.Y(PM),.Z(PH),.W(P));
endmodule

// MODULE FOR ADDER INPUT BIT LENGTH IS 8 & OUTPUT BIT LENGTH IS
m6
module ADDER8INm6OUT(input [7:  X, input [7:  Y, input [7:  Z, output
[m5:  W);
wire [m5:  XM = { 8b ,X };
wire [m5:  YM = { 4b ,Y,4b };
wire [m5:  ZM = { Z,8b };
assign W = XM + YM + ZM;
endmodule

// MODULE FOR ADDER INPUT BIT LENGTH IS m6 & OUTPUT BIT LENGTH
IS 24
module ADDERm6IN24OUT(input [m5:  X, input [m5:  Y, input [m5:  Z,
output [23:  W);
wire [23:  XM = { 8b ,X };
wire [23:  YM = { 4b ,Y,4b };
wire [23:  ZM = { Z,8b };
assign W = XM + YM + ZM;
endmodule

// MODULE FOR SIMPLE 4 BIT MULTIPLIER

module MULTIPLIER4BIT(input [3:  A, input [3:  B, output [7:  P);
// DECLARING THE WIRES
wire pp ,pp m,pp 2,pp 3;
wire ppm ,ppmm,ppm2,ppm3;
wire pp2 ,pp2m,pp22,pp23;
wire pp3 ,pp3m,pp32,pp33;
wire hcm,hs2,hc2,hs3,hc3,hs4,hc4,hs5,hc5,hs6,hc6,hc8,hc9;

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wire fsm,fcm,fs2,fc2,fs3,fc3,fs4,fc4,fs5,fc5,fc6,fc7;
// INSTANTIATION OF PARTIAL PRODUCTS BY ORDER
PARTIALPRODUCTS pp
(A,B,pp ,pp m,pp 2,pp 3,ppm ,ppmm,ppm2,ppm3,pp2 ,pp2m,pp22,pp23,pp3 ,
pp3m,pp32,pp33);
assign P[  = pp ;
aaa
// INSTANTIATION OF HALF ADDERS & FULL ADDERS BY PORT NAMES
// LEVEL m
HA ham (.a(pp m),.b(ppm ),.s(P[m),.c(hcm));
FA fam (.a(ppmm),.b(pp2 ),.cin(hcm),.s(fsm),.cout(fcm));
HA ha2 (.a(pp2m),.b(pp3 ),.s(hs2),.c(hc2));
HA ha3 (.a(pp3m),.b(hc2),.s(hs3),.c(hc3));
HA ha4 (.a(pp 3),.b(ppm2),.s(hs4),.c(hc4));
FA fa2 (.a(ppm3),.b(pp22),.cin(hc4),.s(fs2),.cout(fc2));
HA ha5 (.a(pp23),.b(pp32),.s(hs5),.c(hc5));
HA ha6 (.a(pp33),.b(hc5),.s(hs6),.c(hc6));
// LEVEL 2
HA ha7 (.a(pp 2),.b(fsm),.s(P[2),.c(hc7));
FA fa3 (.a(fcm),.b(hs2),.cin(hc7),.s(fs3),.cout(fc3));
FA fa4 (.a(hs3),.b(fs2),.cin(fc3),.s(fs4),.cout(fc4));
FA fa5 (.a(hc3),.b(fc2),.cin(hs5),.s(fs5),.cout(fc5));
// LEVEL 3
HA ha8 (.a(fs3),.b(hs4),.s(P[3),.c(hc8));
HA ha9 (.a(fs4),.b(hc8),.s(P[4),.c(hc9));
FA fa6 (.a(hc9),.b(fc4),.cin(fs5),.s(P[5),.cout(fc6));
FA fa7 (.a(fc6),.b(fc5),.cin(hs6),.s(P[6),.cout(fc7));
HA ham (.a(hc6),.b(fc7),.s(P[7));
endmodule

// MODULE FOR GENERATION OF PARTIAL PRODUCTS USING AND GATES

module PARTIALPRODUCTS(input [3:  x, input [3:  y, output
pp ,pp m,pp 2,pp 3,
output ppm ,ppmm,ppm2,ppm3,pp2 ,pp2m,pp22,pp23,pp3 ,pp3m,pp32,pp33);
and (pp ,x[ ,y[ ),(pp m,x[ ,y[m),(pp 2,x[ ,y[2),(pp 3,x[ ,y[3),
(ppm ,x[m,y[ ),(ppmm,x[m,y[m),(ppm2,x[m,y[2),(ppm3,x[m,y[3),
(pp2 ,x[2,y[ ),(pp2m,x[2,y[m),(pp22,x[2,y[2),(pp23,x[2,y[3),
(pp3 ,x[3,y[ ),(pp3m,x[3,y[m),(pp32,x[3,y[2),(pp33,x[3,y[3);
endmodule

// MODULE FOR HALF ADDER

module HA(input a,b, output s,c);
xor (s,a,b);
and (c,a,b);
endmodule

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// MODULE FOR FULL ADDER

module FA(input a,b,cin, output s,cout);
// DECLARING WIRES
wire sm,cm,c2;
// INSTANTIATION OF HALF ADDER MODULE BY PORT NAME
HA ham(.a(a),.b(b),.c(cm),.s(sm));
aaa
HA ha2(.a(sm),.b(cin),.c(c2),.s(s));
or (cout,cm,c2);
endmodule

// MODULE FOR FLOATINGPOINT ADDER

module fpadder(input [3m:  A,B,output reg [3m: C
);

reg [24:  fr,fr_us;

reg [8:  de;
reg [23:  new_fm,new_f2,f_fr;
reg f_sel,s,sr;
reg [7:  er;
integer I;
wire [7:  em,e2;
wire [23:  fm,f2;
wire sm,s2;
assign em=A[3 :23;
assign e2=B[3 :23;
assign fm[23=mbm;
assign f2[23=mbm;
assign fm[22: =A[22: ;
assign f2[22: =B[22: ;
assign sm=A[3m;
assign s2=B[3m;
always@(*)
begin
de=em-e2;
s=sm^s2;
f_sel=mbm;
if(de[8==mbm)
begin
de=~de+9bm;
f_sel=mb ;
end
new_fm=f_sel ? fm :f2;
new_f2=f_sel ? f2 :fm;
er=f_sel?em+8bm :e2+8bm;
new_f2=new_f2>>de;

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fr=s? new_fm-new_f2 : new_fm+new_f2;

sr=f_sel?sm^(fr[24&s):s2^(fr[24&s);
fr_us=(fr[24 & s)? ~fr+25bm:fr;
f_fr=fr_us[24:m;
I=f_fr[23;
repeat(24)
aaa
begin
if(f_fr[23==mb )
begin
f_fr=f_fr<<mbm;
er=er-8bm;
end
end
C={sr,er,f_fr[22: };

end

endmodule

?
' ?
??
' ?
? .?? 

?
?
?  .??
?
?
module CONVERSION(input [3m:  A, output [63:  COUT);
wire [3:  A8 = A [3m:28;
wire [3:  A7 = A [27:24;
wire [3:  A6 = A [23:2 ;
wire [3:  A5 = A [m9:m6;
wire [3:  A4 = A [m5:m2;
wire [3:  A3 = A [mm:8;
wire [3:  A2 = A [7:4;
wire [3:  Am = A [3: ;

wire [7:  COUTm,COUT2,COUT3,COUT4,COUT5,COUT6,COUT7,COUT8;

SUBBLOCK blockm(.IN(Am),.OUT(COUTm));
SUBBLOCK block2(.IN(A2),.OUT(COUT2));
SUBBLOCK block3(.IN(A3),.OUT(COUT3));
SUBBLOCK block4(.IN(A4),.OUT(COUT4));
SUBBLOCK block5(.IN(A5),.OUT(COUT5));
SUBBLOCK block6(.IN(A6),.OUT(COUT6));
SUBBLOCK block7(.IN(A7),.OUT(COUT7));
SUBBLOCK block8(.IN(A8),.OUT(COUT8));

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assign COUT = {
COUT8,COUT7,COUT6,COUT5,COUT4,COUT3,COUT2,COUTm };

endmodule

aa a
module SUBBLOCK(input [3:  IN, output reg [7:  OUT);
always @ (IN)
begin
case(IN)
4b : OUT <= 8b mm ;
4b m: OUT <= 8b mm m;
4b m : OUT <= 8b mm m ;
4b mm: OUT <= 8b mm mm;
4b m : OUT <= 8b mm m ;
4b m m: OUT <= 8b mm m m;
4b mm : OUT <= 8b mm mm ;
4b mmm: OUT <= 8b mm mmm;
4bm : OUT <= 8b mmm ;
4bm m: OUT <= 8b mmm m;
4bm m : OUT <= 8b m m;
4bm mm: OUT <= 8b m m ;
4bmm : OUT <= 8b m mm;
4bmm m: OUT <= 8b m m ;
4bmmm : OUT <= 8b m m m;
4bmmmm: OUT <= 8b m mm ;
default: $display("Sir, please enter the correct value...");
endcase
end
endmodule

 ?' ?
??  ?? #



module FPARITHMETICFINAL(input [3m:  INm, input [3m:  IN2,input CNTR,

output [63:  OUT);

wire [3m:  FPOUT;

wire Zm = ~(|INm);
wire Z2 = ~(|IN2);

wire Im = ~(|INm[22: ) && &INm[3 :23;

wire I2 = ~(|IN2[22: ) && &IN2[3 :23;

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wire SIm = INm[3m && Im;

wire SI2 = IN2[3m && I2;

wire NANm = &INm[3 :22;

wire NAN2 = &IN2[3 :22;

aa
a
wire SP = Zm || Z2 || Im || I2 || NANm || NAN2;

wire [63:  OUTm;

wire [m:  ZA = CNTR ? {Zm,Z2} : 2b ;

assign OUT = (NANm || NAN2) ?

64b m m m mmm m m m mmm m m m
: ((Im || I2) ?
64b m mmm m mmmm m mmmm mm m mmm mm mm mm
m mm: (((Zm || Z2) && ~CNTR) ?
64b m m m mm m m m m m m m m mmmm m m
: OUTm));

/*always @ (INm or IN2)

begin
if(NANm || NAN2)
SPOUT <=
64b m m m mmm m m m mmm m m m
;
else if(Im || I2)
SPOUT <=
64b m mmm m mmmm m mmmm mm m mmm mm mm mm
m mm;
else if((Zm || Z2) && ~CNTR)
SPOUT <=
64b mm mm mm mm mm mm mm m
m ;
end*/

//assign OUT = SP ? SPOUT: OUTm;

FLOATINGPOINTARITHEMATIC
FPARITH(.INm(INm),.IN2(IN2),.ZeroAdd(ZA),.cntr(CNTR),.OUT(FPOUT));
CONVERSION CONV(.A(FPOUT),.COUT(OUTm));

endmodule

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?
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module top (clk,in,cntr,lcd_rs, lcd_rw, lcd_e, lcd_4, lcd_5, lcd_6, lcd_7);

parameter n = 27;
aaa
parameter k = m7;
(* LOC="C9" *) input clk; // synthesis attribute PERIOD clk "m . MHz"
(*LOC="nm7"*)input cntr;
input [2:  in;
reg [n-m:  count= ;
reg lcd_busy=m; // Lumex LCM-S m6 2DTR/B
reg lcd_stb;
reg [5:  lcd_code;
reg [6:  lcd_stuff;
(* LOC="lm8" *) output reg lcd_rs;
(* LOC="lm7" *) output reg lcd_rw;
(* LOC="mm5" *) output reg lcd_7;
(* LOC="pm7" *) output reg lcd_6;
(* LOC="rm6" *) output reg lcd_5;
(* LOC="rm5" *) output reg lcd_4;
(* LOC="mm8" *) output reg lcd_e;
wire [63:  doutm;
TOPMODULE Tm(clk,cntr,in,doutm);

always @ (posedge clk) begin

count <= count + m;
case (count[k+7:k+2)
: lcd_code <= 6b m ; // function set
m: lcd_code <= 6b m ;
2: lcd_code <= 6b mm ;
3: lcd_code <= 6b ; // display on/off control
4: lcd_code <= 6b mm ;
5: lcd_code <= 6b ; // display clear
6: lcd_code <= 6b m;
7: lcd_code <= 6b ; // entry mode set
8: lcd_code <= 6b mm ;
9: lcd_code <= 6h22;
m : lcd_code <= 6h2 ;
mm: lcd_code <= {2bm ,doutm[63:6 };
m2: lcd_code <= {2bm ,doutm[59:56};
m3: lcd_code <= {2bm ,doutm[55:52};
m4: lcd_code <= {2bm ,doutm[5m:48};
m5: lcd_code <= {2bm ,doutm[47:44};
m6: lcd_code <= {2bm ,doutm[43:4 };

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m7: lcd_code <= {2bm ,doutm[39:36};

m8: lcd_code <= {2bm ,doutm[35:32};
m9: lcd_code <= {2bm ,doutm[3m:28};
2 : lcd_code <= {2bm ,doutm[27:24};
2m: lcd_code <= {2bm ,doutm[23:2 };
22: lcd_code <= {2bm ,doutm[m9:m6};
aaa
23: lcd_code <= {2bm ,doutm[m5:m2};
24: lcd_code <= {2bm ,doutm[mm:8};
25: lcd_code <= {2bm ,doutm[7:4};
26: lcd_code <= {2bm ,doutm[3: };
27: lcd_code <= 6h22;
28: lcd_code <= 6h2 ;
29: lcd_code <= 6h22;
3 : lcd_code <= 6h2 ;
3m: lcd_code <= 6h22;
32: lcd_code <= 6h2 ;
default: lcd_code <= 6b m ;
endcase
if (lcd_rw)
lcd_busy <= ;
lcd_stb <= ^count[k+m:k+  & ~lcd_rw & lcd_busy; // clkrate / 2^(k+2)
lcd_stuff <= {lcd_stb,lcd_code};
{lcd_e,lcd_rs,lcd_rw,lcd_7,lcd_6,lcd_5,lcd_4} <= lcd_stuff;
end
endmodule

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