Review: Construction of PDN

EE534 VLSI Design System Lecture 9:Chapter 7 CMOS Equivalent inverter and layout

NMOS devices in series implement a NAND function

AB A B

NMOS devices in parallel implement a NOR function

A+B A B

Review: CMOS NAND

Review: VTC is Data-Dependent

3
0.5/0.25 NMOS 0.75 /0.25 PMOS

A 0 A B 0 1 AB A B A B 1

B 0 1 0 1

F 1

M3 B

M4
2

F= A B 1 1 0 A
VGS2 = VA VDS1
D

A,B: 0 -> 1 B=1, A:0 -> 1 A=1, B:0->1

M2 M1

1
Cint

weaker PUN

S D S

B
VGS1 = VB

0 0 1 2

The threshold voltage of M2 is higher than M1 due to the body effect ()

VTn1 = VTn0 VTn2 = VTn0 + ((|2F| + Vint) - |2F|) since VSB of M2 is not zero (when VB = 0) due to the presence of Cint

Input Pattern Effects on Delay-I

Delay is dependent on the pattern of inputs
Rp A Rn A Rn B Cint B CL Rp

Delay Dependence on Input Patterns-II

The reason for difference in low to high transition is due to internal node capacitance and high to low is Due to initial state of the internal nodes.
3 2.5 2

Low to high transition

both inputs go low
- delay is 0.69 Rp/2 CL since two p-resistors are on in parallel

2-input NAND with NMOS = 0.5m/0.25 m PMOS = 0.75m/0.25 m CL = 10 fF

A=B=10
Input Data Delay (psec) 69 62 50 35 76 57

Voltage, V

one input goes low

- delay is 0.69 Rp CL

1.5 1 0.5 0 -0.5 0 100 200

A=1 0, B=1
Rp A Rn A Cint B CL Rp

Pattern A=B=01

High to low transition

both inputs go high
- delay is 0.69 2Rn CL

A=1, B=10
300 400

A=1, B=01 A= 01, B=1 A=B=10 A=1, B=10 A= 10, B=1

Adding transistors in series (without sizing) slows down the circuit

time, psec

Conclusions: Estimates of delay can be fairly Rn complex have to consider internal node B capacitances and the data patterns

CMOS gate design

Designing a CMOS gate: Find pulldown NMOS network from logic function or by inspection Find pullup PMOS network - By inspection - Using logic function - Using dual network approach Size transistors using equivalent inverter - Find worst-case pullup and pulldown paths - Size to meet rise/fall or threshold requirements

Equivalent inverter: effective width to length ratios (model I)

Parallel combination Series combination

For the NOR gate the effective width of the drivers transistors doubles. That means the effective aspect ratio is increased.

For the NAND gate the effective length of the driver transistors doubles. That means the effective aspect ratio is decreased.
.

Exercise: Design and compare two input NAND and NOR gates

Analysis of CMOS gates

Represent on transistors as resistors

Find W/L relationship between NMOS and PMOS transistors Assume K'n=2K'p

1
W R

1 1

W W

R R

Transistors in series resistances in series

Effective resistance = 2R Effective width = W
NAND gate NOR gate

Analysis of CMOS gates, cont

Represent on transistors as resistors
W W W R R R

Equivalent Inverter CMOS gates: many paths to Vcc and Gnd Multiple values for VTH, VIL, VOL, etc Different delays for each input combination Equivalent inverter Represent each gate as an inverter with appropriate device width Include only transistors which are on or switching Calculate VTH, delays, etc using inverter equations

0 0

Transistors in parallel resistances in parallel Effective resistance = R Effective width = 2W

Static CMOS Logic Characteristics For VTH, the VTH of the equivalent inverter is used (assumes all inputs are tied together) For specific input patterns, VTH will be different For VIL and VIH, only the worst case is interesting since circuits must be designed for worst-case noise margin For delays, both the maximum and minimum must be accounted for in race analysis

Equivalent Inverter: VTH

Example: NAND gate threshold VTH Three possibilities:
A & B switch together A switches alone B switches alone

What is equivalent inverter for each case?

CMOS NAND gate and its inverter equivalent

Can we estimate switching threshold of the NAND gate by using CMOS inverter expression for the switching threshold?

NAND Example
A 2-input NAND gate is driving 0.01 pF load. Estimate tPLH and tPHL assuming both inputs switching at the same time. Use the following device parameters:
Kn = 20 A/V2 Kp = 10 A/V2 VTn = |VTp| = 1.0V PMOS: W=10 m, Leff=2 m NMOS: W=10 m, Leff=1 m Driving High: PMOS in Parallel:

VT ,n + Vth ( INR) =

kp kn 1+

(VDD VT , p ) Kp Kn

If Kn=Kp, Vth=?

WP WN

WP

W/L = 10 / 2 2WP WN
VT ,n +

W/L = 10 / 2

2KP W/L = 10 / 1 Kn/2 W/L = 10 / 1

Effective W/L = (10 + 10) / 2 = 10/1

Driving Low: NMOS in Series: Effective W/L = 10 / (1+1) = 5/1

WN

Vth ( NAND) =

4k p (VDD VT , p ) kp 1+ 4K p Kn

Solution to Example

Equivalent inverter: Worse case delay design consideration

Represent complex gate as inverter for delay estimation Use worse-case delays Example: NAND gate Worse-case (slowest) pull-up: only 1 PMOS on Pull-down: both NMOS on
WP WN WN WP WP WN

KP Kn/2

CMOS NOR gate: design consideration

VT ,n + Vth ( INR) = kp 4k n 1+ (VDD VT , p ) Kp 4Kn
VT ,n + kp (VDD VT , p ) N 2 kn 1+ Kp N 2Kn

Equivalent inverter
(VDD VT , p ) Kp Kn

VT , n + Vth ( INR) =

kp kn 1+

Two input
Vth ( INR) =

One input For N inputs

Wp/2
B

KP/2 2Kn

2Wn
B

Problems with equivalent inverter method: Need to take into account load capacitance CL - Depends on number of transistors connected to output (junction capacitances) - Even transistors which are off (not included in equivalent inverter) contribute to capacitance Need to include capacitance in intermediate stack nodes. Worse-case: need to charge/discharge all nodes Body effect of stacked transistors

Transistor Sizing

Transistor sizing: an approach

If MOSFET serially connected in a current path, the overall current path resistance will be

R=

RsL1 RsL2 RsL3 + + + .. W1 W2 W3 L1 L2 L3 + + + ..) W1 W2 W3

R = Rs(

All serially connected MOSFET can be replace with a single MOSFET as

Leq Weq
NAND gate NOR gate

W1 W2 W3 + + + ... L1 L2 L3

If the MOSFET are connected in parallel combination then,

Le q Weq

1 W1 W2 W3 + + + .. L1 L2 L3

Review: Inverter layout

NAND layout

VDD + tub ties out transistors a

VDD + out

out

(Wells not shown)

out well ties b a

GND

GND

NOR gate

NOR layout

+ b a a

VDD

tub ties b out out a GND

out

4-input NAND Gate

Graph-based dual network

Draw network for PUN or PDN Circuit nodes are vertices Transistors are edges
VDD In1 In2 In1 In2 In3 In4 Out

Vdd

F F A A B gnd B

Out

In3 In4

GND
In1 In2 In3 In4

Graph-based dual network (2) To derive dual network:

Create new node in each enclosed region of graph Draw new edge intersecting each original edge Edge is controlled by inverted input

Dual Graph concept

A j B X = C (A + B) C i B A B C C

Logic Graph

X C

PUN

X B

i A

VDD j

A A

B B

A B F

GND

PDN

Stick Diagrams

CMOS gate layout

Goal: minimum area

Contains no dimensions Represents relative positions of transistors

VDD VDD

Method Minimize diffusion breaks (reduces capacitance on internal nodes) Align transistors with common gates above each other in layout (minimizes poly length) Group PMOS and NMOS transistors together
Out

Inverter

NAND2
Out

Approach:
In GND GND A B

Use Euler path method to find ordering of transistors in layout

Layout: Euler path method Goal: layout without diffusion breaks Method for finding ordering of transistors in layout Euler path Euler path path through a graph that traverses each edge only once Find common Euler path in pullup and pulldown graph This gives the ordering of inputs in the layout

Complex CMOS logic gates

Complex CMOS logic gates

Another Layout Example

Start with PDN (by inspection):

F = (C + DE ) ( A + B) F = (C + [ D + E ]) ( AB) F = (C [ D + E ]) ( AB ) F = ( AB + C [ D + E ])
A C

A B

C D E

D E

Layout: Euler path method

C E D A B F A B C D E Gnd B A C E D Vcc

Layout continued
Metal 1 / N-diff contact used for tub tie Metal 1 used for Power, Ground, and Output

Metal 2 used to wire internal nodes Need both contact and Metal1 / Metal2 to get from diff to Metal 2

1. 2. 3.

Euler path: BACED

Order transistors gates according to Euler path Connect Vcc and Gnd Make other connections according to circuit diagram

If you flip back and forth, you will see how the layout implements the stick diagram. Note the input order and the topology both match.

But does it work?

Set inputs on power-of-2 boundaries to generate entire counting pattern

11101110111000001110000011100000

You can read the truth table directly off of the output row!