Digital Signal Processor Instruction Set
Sonali chouhan
DSP Algorithms Shape DSPs
How Signal Processing is Different From Other Tasks
Very computationally demanding Requires attention to numeric fidelity High memory bandwidth requirements Streaming dataand lots of it Predictable data access patterns Execution-time locality Math-centric Real-time constraints Standards: algorithms, interfaces
General-Purpose Features
Several DSPs now include features traditionally associated with generalpurpose processors
User modes Memory management units Compiler-oriented features such as specialized addressing modes
Enable more sophisticated OSs Ease implementation of non-signalprocessing tasks Often make processors better compiler targets
DSP processors
SHARC, BlackFin, TMS320C55x, TMS320C67x, TMS320C64x 16-32 bit word size Single program Lightweight, often real-time OS Super Harvard Architecture Support Improved throughput Audio, Image and Video processing, Coding and Decoding, Cellular Base Station, Adaptive Filtering, Real Time operations
Super Harvard Architecture
Super Harvard architecture improves upon the Harvard architecture by adding an instruction cache and a dedicated I/O controller In Harvard architecture data memory bus is busier than the program memory bus
Super Harvard Architecture (Contd.)
Relocate part of the "data" to program memory (secondary data) Improves performance in case of data extensive operations (e.g., loop) Adds program cache in CPU
Stores ~32 most recent instructions
I/O port allows Direct memory access (DMA)
No CPU cycles wasted
Proprietary v/s Shared
Most DSP architectures are not shared, not licensable
One silicon vendor per architecture
In contrast, many GPPs are shared and licensable
ARM, MIPS, PowerPC, SH-x, x86
There are some shared or licensable DSP architectures
CEVA, StarCore, ZSP
Shared architectures can encourage stability, price competition, and wide third-party support But proprietary architectures
May achieve faster technological advances May have market momentum, integration advantages
SHARC instruction set
SHARC SHARC SHARC SHARC SHARC programming model. assembly language. memory organization. data operations. flow of control.
SHARC programming model
Register files:
R0-R15 (aliased as F0-F15 for floating point)
Status registers. Loop registers. Data address generator registers. Interrupt registers.
SHARC assembly language
Algebraic notation terminated by semicolon:
R1=DM(M0,I0), R2=PM(M8,I8); ! comment label: R3=R1+R2; data memory access program memory access
SHARC memory space
short word addressing 0x40000 normal word addressing 0x20000 interrupt vectors forbidden IOP registers 256
0x0
SHARC data types
32-bit IEEE single-precision floatingpoint. 40-bit IEEE extended-precision floating-point. 32-bit integers. Memory organized internally as 32bit words.
SHARC microarchitecture
Modified Harvard architecture.
Program memory can be used to store some data.
Register file connects to:
multiplier shifter; ALU.
SHARC Computation Unit
SHARC mode registers
Most important:
ASTAT: arithmetic status. STKY: sticky. MODE 1: mode 1.
Rounding and saturation
Floating-point can be:
rounded toward zero; rounded toward nearest.
ALU supports saturation arithmetic (controlled by ALUSAT bit in MODE1 reg).
Overflow results in max value, not rollover.
Multiplier
Fixed-point operations can accumulate into local MR registers or be written to register file.
Fixed-point result is 80 bits.
Floating-point results always go to register file. Status bits: negative, under/overflow, invalid, fixed-point underflow, floating-point underflow, floatingpoint invalid.
ALU/shifter status flags
ALU:
zero, overflow, negative, fixed-point carry, inputsign, floating-point invalid, last op was floating-point, compare accumulation registers, floating-point under/oveflow, fixed-point overflow, floating-point invalid
Shifter:
zero, overflow, sign
Flag operations
All ALU operations set AZ (zero), AN (negative), AV (overflow), AC (fixedpoint carry), AI (floating-point invalid) bits in ASTAT. STKY is sticky version of some ASTAT bits.
Reference
ADSP-21161 SHARC Processor H/W Reference (Rev 4.0)
