MULTIPLICATION & DIVISION ALGORITHMS
Multiplication
Some general observations
1. Multiplication involves the generation of partial products one for each digit in the multiplier.
2. Partial products are summed to produce the final product.
3. Partial products are very simple to define for binary multiplication. If the digit is a one the partial product is the multiplicand, otherwise the partial product is zero. 4. The total product is the sum of the partial products. Each successive partial product is shifted one position to the left. 5. The multiplication of two n-bit binary numbers results in a product of up to 2n bits in length.
1011 X 1101 1011 0000 1011 1011 10001111
Simplifying Multiplication
1. The processor can keep a running product rather than summing at the end. 2. For each 1 in the multiplier we can apply an add and a shift. 3. For each 0 only a shift is needed.
( Binary addition truth tables and circuit)
1. Multiplier and multiplicand are loaded into registers Q and M. 2. A third register (A) is initially set to zero. 3. A one-bit C register (initialised to zero) holds carry bits.
This Approach will not work if both or any one of the Multiplicand & Multiplier are negative. ALTERNATIVE --- BOOTH ALGORITHM
Multiplicand M unchanged
Based upon recoding the multiplier Q to a recoded value R Each digit can assume a negative as well as positive and zero values
Signed Digit ( SD) encoding
Booths algorithm called skipping over ones
String of 1s replaced by 0s For ex: 30 = 0011110 = 32 2 = 0100000 - 0000010
In the coded form = 0100010
Booths Algorithm (M x Q)
1. Multiplier and multiplicand placed in Q and M registers. are
2. A 1-bit register is placed to the right of the least significant bit (Q0) and designated Q-1. 3. Control logic scans the bits of the multiplier one at a time, but a bit AND its bit to the right are examined. If the bits are the same (1-1 or 0-0) then all bits of the A,Q, and Q-1 registers are shifted to the right 1 bit. If the two bits differ, then the multiplicand is added/subtracted depending on whether the bits are 0-1 or 1-0. Addition is followed by a right arithmetic shift.
Verify the operation of (+7) x (-3) Multiplicand M = 0111 Multiplier Q = 1101
A
0000 1001 1100
0011 0001
Q
1101 1101 1110
1110 1111
Q-1
0 0 1
1 0
M = 0111
initial A A-M shift
A A+M shift
1010 1101
1110
1111 0111
1011
0 1
1
A A-M shift
shift
Booths algorithm generally performs fewer additions and subtractions than repeated addition.
DIVISION
( Dividend/Divisor)
bits of dividend are examined from left to right until set of bits examined represents a number greater than or equal to the divisor (event) Until this 0s are placed in quotient from left to right
When the event occurs a 1 is placed in the quotient and divisor subtracted from dividend
The result referred as partial remainder Cyclic pattern followed
00001101
1011
1000011
10111 001110
1011
001111 1011
0111
000011
1011
1000011
1011 01111
1011
The divisor placed in M register Dividend placed in Q register Register A initially cleared In each step A and Q are shifted to left 1 bit M subtracted from A If divides the Partial remainder Q (LSB) gets 1 Else Q gets a 0 and M added back to A Process continues for n steps At the end Quotient in Q and remainder in A
Restoration Method
Divisor loaded into Register M Dividend loaded into register Q Initialise register A to Zero Shift A and Q left by one position
Subtract M form A, placing the result back in A If MSB of A is 1, set Q0 to Zero, add M to A (restore A) if MSB of A is Zero, set Q0 to 1 Repeat steps 4,5,6 n times where n is no of bits of divisor N bit quotient obtained from Q and remainder from A
Example: Divide 7 by 3
Dividend : 0111 Divisor : 0011 A 0000 0000 1101 Q 0111 1110 Initial Value shift left Sub M
M : 0011
1101 0011 0000 0001 1101 1110 0011 0001
1110 1110 1100 1100 1100
As MSB is 1 set Q0 =0 Add M Restore A Shift left Sub M As MSB is 1 set Q0= 0 Add M Restore A
0011 1101 0000 0000 0001 1101 1110 0011 0001
1000 1000 1001 0010
Shift left Sub M As MSB 0 set Q0 = 1
Shift left Sub M
As MSB 1set Q0 = 0 Add M Restore A Remainder = 0001
0010 0010
Result Q = 0010
Divide 9 by 3 Dividend = 1001 Divisor = 0011
M = 0011
Non-restoration Method
Eliminates the need for restoring A after the result of subtraction is negative
Divisor is loaded into M Dividend loaded into Q Initialise A to Zero
If sign of A is positive shift A & Q left by one bit and subtract M from A If sign of A is negative, shift A &Q left by one bit and add M to A
If MSB of result is 1, then Q0 is set to Zero otherwise set to one
Repeat steps 4 &5 n times At the end if sign of A is negative add M to A to get the correct remainder
7 divide by3
M 0011
A 0000 0000 1101 1101 1011 0011 1110 Q 0111 1110 1110 1100 1100 initialise shift left, as MSB is 0 Sub M as MSB 1, Q0 = 0 shift left, as MSB 1 Add M as MSB 1 Q0 = 0
1101 0011 0000 0000 0001 1101 1110 0011
1000
shift left , as MSB 1 Add M as MSB 0 set Q0 =1 shift left as MSB 0 Sub M as MSB 1 Add to adjust remainder
1000 1001 0010 0010
0001
Q = 0010 R = 0001
