Finite State Machine Design
The Finite state machine design process consists of 1. 2. 3. 4. !. Constructing an initial state machine that realizes the design. Minimizing the number of states. Encoding the states. Choosing the memory de ice to implement the state memory. "mplementing the finite state machine#s ne$t state and output functions.
"n the age of ery large scale integrated circuits% &hy should &e bother to minimize a state machine implementation' (fter all as long as the input)output beha ior of the machine is correct% it doesn#t matter ho& it is implemented. *r does it'
Advantages of minimum states
"n general% you &ill find it is &orth&hile to implement the finite state machine in as fe& states as possible. This usually reduces the number of gates and flip+flops you need for the machine implementation. For e$ample% you are gi en a finite state machine &ith 1, states% thus re-uiring fi e state flip+flops. "f you can reduce the number of states to 1. or less% you sa e a flip+flop. E en if reducing the reducing the number of states is not enough to eliminate a flip+flop% it still has ad antages. /ith fe&er states% you introduce more don#t care conditions into the ne$t+state and output functions% ma0ing their implementation simpler. 1tate reduction techni-ue also allo&s you to be less meticulous in obtaining the initial finite state machine description. "f you ha e introduced a fe& redundant states% you &ill find and eliminate them by using the state reduction techni-ue introduced ne$t.
State Minimization
1tate reduction identifies and combines states that ha e e-ui alent beha ior. T&o states ha e e-ui alent beha ior if% for all the input combinations% their outputs are the same and they change to the same or e-ui alent ne$t states. (lgorithms for state reduction begin &ith the symbolic state transition table. First &e group together states that ha e same state outputs 2Moore machine3 or transition outputs 2mealy machine3. These are potentially e-ui alent% since states cannot be e-ui alent if their outputs differ. 4e$t% &e e$amine the transitions to see if they go to the same ne$t state for e ery input combination. "f they do% the states are e-ui alent and &e can combine them into a renamed ne& state. /e then update all transitions to the ne&ly combine states. /e repeat this process until no additional states can be combined. There are t&o common methods by &hich states can be minimized. 1. 5o&+matching method. 2. Chart method.
Row Matching Method
6et#s begin our in estigation of a ro&+matching method &ith detailed e$ample. /e &ill see ho& to transform an initial state diagram for a simple se-uence detector into a minimized% e-ui alent state diagram. Four-Bit Sequence Detector: Specification and Initia state diagram! 6et#s consider a se-uence+detecting finite state machine &ith follo&ing specifications. The machine has single input 7 and output 8. The output is asserted after each four bit input se-uence if it consists of one of the binary strings 9119 or 1919. The machine returns to the reset state after each four+bit se-uence &ill assume mealy implementation. The state diagram of 4+bit se-uence detector is as sho&n belo&: 5eset
9)9
1)9
9)9
1)9
9)9
1)9
9)9
1)9
9)9
1)9
9)9
1)9
9)9
1)9
9)9
1)9
9)9
1)9 9)9
1)9
9)1
1)9
9)9
1)9
9)1
1)9 9)9 1)9
9)9 1)9
There are 1. uni-ue paths through the state diagram% one for each possible 4+bit pattern. This re-uires 1! states and 39 transitions. *nly t&o of the transitions ha e a one output% representing the accepted strings.
The state transition table for 4+bit se-uence detector is as sho&n belo&. "nput 1e-uence 5eset 9 1 99 91 19 11 999 991 919 911 199 191 119 111 ;resent 1tate 19 11 12 13 14 1! 1. 1= 1, 1> 119 111 112 113 114 4e$t state
7<9 7<1
*utput
7<9 7<1
11 13 1! 1= 1> 111 113 19 19 19 19 19 19 19 19
12 14 1. 1, 119 112 114 19 19 19 19 19 19 19 19
9 9 9 9 9 9 9 9 9 9 1 9 1 9 9
9 9 9 9 9 9 9 9 9 9 9 9 9 9 9
The abo e table contain one ro& per state% &ith multiple ne$t state and the outputs columns based on the input combinations. "t gi es the same information as a table &ith separate ro&s for each state and input combination. 4e$t &e e$amine the ro&s of the state transition table to find any &ith identical ne$t state and output alues 2hence the term ro& matching3. For this finite state machine &e can combine 119 and 112.6ets call the ne& state 119? and modify all transitions to 119 and 112.The re ised state table is as sho&n belo&. "nput 1e-uence ;resent 1tate 4e$t 1tate *utput 7<9 7<1 7<9 7<1 5eset 19 11 12 9 9 9 11 13 14 9 9 1 12 1! 1. 9 9 99 13 1= 1, 9 9 91 14 1> 119? 9 9 19 1! 111 119? 9 9 11 1. 113 114 9 9 999 1= 19 19 9 9 991 1, 19 19 9 9 919 1> 19 19 9 9 911 or 191 119? 19 19 1 9 199 111 19 19 9 9 119 113 19 19 9 9 111 114 19 19 9 9
/e continue matching ro&s until &e can no longer combine any. "n the abo e figure 1=% 1,% 1> 111% 113% and 114 all ha e the same ne$t state and the outputs. /e combine them into a renamed state 1=?. The table &ith renamed transitions% is sho&n in the figure belo&. "nput 1e-uence 5eset 9 1 99 91 19 11 4ot2911 or 1913 911 or 191 ;resent 1tate 19 11 12 13 14 1! 1. 1=? 119? 4e$t 1tate 7<9 11 13 1! 1=? 1=? 1=? 1=? 19 19 7<1 12 14 1. 1=? 119? 119? 1=? 19 19 *utput 7<9 9 9 9 9 9 9 9 9 1 7<1 9 9 9 9 9 9 9 9 9
4o& state 13 and 1. can be combined% as can 14 and 1!. /e call the combined states 13? and 14? respecti ely. The final reduced state transition table is as sho&n belo&. "nput 1e-uence 5eset 9 1 99 or 11 91 or 19 4ot2911 or 1913 911 or 191 ;resent 1tate 19 11 12 13? 14? 1=? 119? 4e$t 1tate 7<9 11 13? 14? 1=? 1=? 19 19 *utput 7<1 7<9 12 9 14? 9 13? 9 1=? 9 119? 9 19 9 19 1 7<1 9 9 9 9 9 9 9
"n the process &e ha e reduced 1! states to @ust = states. The reduced state diagram is as sho&n belo&. 5eset 9)9 1)9 9)9 9%1)9 9%1)9 9)9 9)1 1)9 1)9 9)9 1)9 1)9
"hart Method :
The implication Chart method is a more systematic approach to finding the states that can be combined into a single reduced state. Consider a #hree -Bit Sequence Detector: Aour goal is to design a binary se-uence detector that &ill output a 1 &hene er a machine has obser ed the serial se-uence 919 or 119 at the inputs. The initial table is as sho&n belo&. "nput 1e-uence 5eset 9 1 99 91 19 11 ;resent 1tate 19 11 12 13 14 1! 1. 4e$t state
7<9 7<1
*utput
7<9 7<1
11 13 1! 19 19 19 19
12 14 1. 19 19 19 19
9 9 9 9 1 9 1
9 9 9 9 9 9 9
The method operates on a data structure that enumerates all possible combinations of states ta0en t&o at a time% called an implication chart. 19 11 12 13 14 1! 1. 19 11 12 13 14 1! 1.
The chart sho&n abo e is more complicated then it needs to be. For e$ample the diagonal entries are not needed since &e do not need to compare a state &ith itself. (lso note that al the upper and the lo&er triangles of cells are symmetric. The chart cell for ro& 1i and column 1@ considers the same information as that for ro& 1@ and column 1i. Therefore% &e &or0 &ith the follo&ing reduced structure.
11 12 13 14 1! 1. 19 11 12 13 14 1!
/e &ill fill the implication chart as follo&s. 6et 7i@ be the cell &hose ro& is labeled by the state 1i and &hose column is labeled by the state 1@. "f &e &ere able to combine states 1i and 1@% it &ould imply that their ne$t state transitions for each input combination must also be e-ui alent. The cell contains the ne$t+state combinations that must be e-ui alent for the ro& and column states to be e-ui alent. "f 1i and 1@ ha e different outputs or ne$t state beha ior% an 7 is placed in the cell. This indicates that the t&o states can ne er be e-ui alent. The implication chart for three+bit se-uence detector is as sho&n belo&. 19% 11% 12% 13 and 1! ha e the same outputs and are the candidates for being combined. 1imilarly% states 14 and 1. might also be combined. (ny combination of states across the groups% such as 11 and 14% is labeled by an 7 in the chart. 1ince their outputs are different they can 4EBE5 be e-ui alent. To fill the chart entry for 2ro&3 11 and 2column3 19% &e loo0 at the ne$t transition. 19 goes to 11 on 9 and 12 on 1% &hile 11 goes to 13 and 14 respecti ely. /e &ill fill the chart in &ith 11+13% the transitions on 9 and 12+14% the transitions on 1./e call this grouping implied state pairs. The entry means that 19 and 11 cannot be e-ui alent unless 11 is e-ui alent to 13 and 12 is e-ui alent to 14.The rest of the entries are filled in similarly. (t this point the chart contain enough information to pro e that many states are 4*T ECD"B(6E4T. For e$ample &e already 0no& that 12 and 14 cannot be e-ui alent% since they ha e different output beha ior. Thus there is no &ay that 19 can be e-ui alent to 11.
"nitial Entries: 11+13 12+14 11+1! 12+14 11+19 12+19 13+1! 14+1. 13+19 14+19 1!+19 1.+19
11+19 12+19
13+19 14+19
1!+19 1.+19
19+19 19+19 19+19 19+19
19 First ;ass: 11 12 13 14 1! 1. 19
11
12
13
14
1!
13+1! 14+1.
19+19 19+19 19+19 19+19 11 12 13 14 1!
The abo e figure contains the results of first ma0ing pass. Entry 12+19 is mar0ed &ith 7 because the chart entry for the implied state pair 12+1. is already mar0ed &ith a 7. Entry 13+19 is also mar0ed% because 11+19 has @ust been mar0ed. The same is true for 1!+19.by the end of the passE the only entries not mar0ed are 12+11% 1!+13 and 1.+14. /e no& ma0e a second pass through the chart to see if &e can add any ne& mar0ings. Entry 12+11 remains unmar0ed. 4othing in the chart refuses that 13 and 1! are e-ui alent. The same is true of 14 and 1.. Continuing 13+1! and 14+1. are no& ob iously e-ui alent. They ha e identical outputs and transfer to the same ne$t state 2193 for all input combinations. 1ince no mar0ing ha e been added the algorithm stops. The unmar0ed entries represent e-ui alence bet&een the ro& and the column indices. The final reduced state table is as sho&n. "nput se-uence 5eset 9 or 1 99 or 19 91 or 11 ;resent 1tate 19 11? 13? 14? 4e$t 1tate 7<9 11? 13? 19 19 *utput 7<1 7<9 11? 9 14? 9 19 9 19 1 7<1 9 9 9 9
Reference Boo$s:
Contemporary 6ogic Fesign by 5andy G. Hatz ;rinciples of Figital Fesign by Faniel G. Ia@s0i Figital 6ogic and 1tate Machine Fesign by Fa id J. Comer Modern Figital Electronics by 5.;.Jain
