Chapter 5
Logic Design with MSI Components
and Programmable Logic Devices
J. C. Huang, 2004 Digital Logic Design 1
The complexity of a chip
Scale of integration:
SSI 1 - 10 gates
MSI 10 - 100 gates
LSI 100 - 1000 gates
VLSI > 1000 gates
J. C. Huang, 2004 Digital Logic Design 2
Specialized MSI components
adders
comparators
encoders/decoders
multiplexers/demultiplexers
J. C. Huang, 2004 Digital Logic Design 3
Half Adder
x
y sum carry
0
0
1
1
0
1
0
1
0
1
1
0
0
0
0
1
x
Sum
y
Carry
sum = xy + xy
carry = xy
J. C. Huang, 2004 Digital Logic Design 4
Full Adder
0 0
0 1
0 1
1 0
0 1
1 0
1 0
1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
c
i+1
s
i
x
i
y
i
c
i
x
i
s
i
y
i
c
i+1
c
i
J. C. Huang, 2004 Digital Logic Design 5
The Karnaugh maps for a full adder
J. C. Huang, 2004 Digital Logic Design 6
SUM and CARRY functions
SUM = x'y'c + x'yc' + xy'c' + xyc
CARRY = xy + yc + cx
J. C. Huang, 2004 Digital Logic Design 7
A realization of the binary full adder
J. C. Huang, 2004 Digital Logic Design 8
Parallel (ripple) binary adder
Designed to add two binary numbers bit by bit
J. C. Huang, 2004 Digital Logic Design 9
Parallel binary subtracter constructed by using a parallel binary adder
J. C. Huang, 2004 Digital Logic Design 10
Parallel binary adder/subtracter
J. C. Huang, 2004 Digital Logic Design 11
Carry-look-ahead adder
Problem: the time required to do addition is
proportional to the number of bits involved.
Solution: compute the carry for each stage
independently by using a carry-look-ahead
network.
J. C. Huang, 2004 Digital Logic Design 12
Carry-Look-ahead Adder
Recall that
c
i+1
= x
i
y
i
+ x
i
c
i
+ y
i
c
i
=x
i
y
i
+ (x
i
+ y
i
)c
i
Let g
i
= x
i
y
i
be the carry-generate function, and
p
i
= x
i
+ y
i
be the carry-propagate function.
Then we can write c
i+1
= g
i
+ p
i
c
i
and
c
1
= g
0
+ p
0
c
0
c
2
= g
1
+ p
1
g
0
+ p
1
p
0
c
0
c
3
= g
2
+ p
2
g
1
+ p
2
p
1
g
0
+ p
2
p
1
p
0
c
0
We see that all carry signal c
i
can be computed by a two level logic
circuit.
J. C. Huang, 2004 Digital Logic Design 13
A carry lookahead adder. (a) General organization. (b) Sigma block
J. C. Huang, 2004 Digital Logic Design 14
A 4-bit carry lookahead adder
J. C. Huang, 2004 Digital Logic Design 15
Cascade connection of 4-bit carry lookahead adders
J. C. Huang, 2004 Digital Logic Design 16
A 4-bit carry look-ahead generator
J. C. Huang, 2004 Digital Logic Design 17
A 16-bit high-speed adder
J. C. Huang, 2004 Digital Logic Design 18
Organization of a single-decade decimal adder
J. C. Huang, 2004 Digital Logic Design 19
Organization of a single-decade BCD adder
J. C. Huang, 2004 Digital Logic Design 20
A single-decade BCD adder
J. C. Huang, 2004 Digital Logic Design 21
Organization of a 1-bit comparator
J. C. Huang, 2004 Digital Logic Design 22
From the truth table (Table 5.4) on page 247 we obtained
G
i+1
= A
i
B'
i
+ A
i
G
i
+ B'
i
G
i
E
i+1
= A'
i
B'
i
E
i
+ A
i
B
i
E
i
L
i+1
= A'
i
B
i
+ B
i
L
i
+ A'
i
L
i
J. C. Huang, 2004 Digital Logic Design 23
Comparing two binary numbers A and B. (a) 1-bit comparator
network. (b) Cascade connection of 1-bit comparators.
J. C. Huang, 2004 Digital Logic Design 24
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
8x3
encoder
3x8
decoder
Main function of encoder and decoder
The purpose is to reduce the number of wires required for interconnection.
(sender) (receiver)
J. C. Huang, 2004 Digital Logic Design 25
A 2
n
-to-n-line encoder symbol
J. C. Huang, 2004 Digital Logic Design 26
An 8-to-3-line encoder
J. C. Huang, 2004 Digital Logic Design 27
Symbol for an n-to-2
n
-line decoder
J. C. Huang, 2004 Digital Logic Design 28
A 3-to-8-line decoder
(a) Logic diagram.
(b) Truth table.
(c) Symbol
J. C. Huang, 2004 Digital Logic Design 29
Decoder realization of f
1
(x
2
,x
1
,x
0
) =
m(1,2,4,5) and f
2
(x
2
,x
1
,x
0
) = m(1,5,7)
J. C. Huang, 2004 Digital Logic Design 30
Decoder realization of Boolean functions
f
1
= M(2, 7) and f
2
= M(0, 5, 7)
J. C. Huang, 2004 Digital Logic Design 31
A decoder realization of f
1
(x
2
,x
1
,x
0
) = M(0,1,3,5) and f
2
(x
2
,x
1
,x
0
) =
M(1,3,6,7) (a) Using output or-gates. (b) Using output nor-gates.
J. C. Huang, 2004 Digital Logic Design 32
A 3-to-8-line decoder using nand-gates
J. C. Huang, 2004 Digital Logic Design 33
Realization of the pair of maxterm canonical expressions
f
1
(x
2
,x
1
,x
0
) = M(0,3,5) and f
2
(x
2
,x
1
,x
0
) = M(2,3,4) with a
3-to-8-line decoder and two and-gates.
J. C. Huang, 2004 Digital Logic Design 34
Realization of the Boolean expressions f
1
(x
2
,x
1
,x
0
) =
M(0,1,3,4,7) with a 3-to-8-line decoder and two nand-gates.
J. C. Huang, 2004 Digital Logic Design 35
A decoder realization of f
1
(x
2
,x
1
,x
0
) = m(0,2,6,7) and f
2
(x
2
,x
1
,x
0
) =
m(3,5,6,7) (a) Using output and-gates. (b) Using output nand-gates.
J. C. Huang, 2004 Digital Logic Design 36
And-gate 2-to-4-line decoder with an enable input. (a) Logic
diagram. (b) Compressed truth table. (c) Symbol.
J. C. Huang, 2004 Digital Logic Design 37
Nand-gate 2-to-4-line decoder with an enable input
J. C. Huang, 2004 Digital Logic Design 38
A 4-to-16-line
decoder constructed
from 2-to-4-line
decoder
J. C. Huang, 2004 Digital Logic Design 39
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
8x1
multiplexer
1x8
demultiplexer
Main function of multiplexer and demultiplexer
The purpose is to reduce the number of wires required for interconnection
by making the signals to time-share the link.
(sender) (receiver)
S
2
S
1
S
0
S
2
S
1
S
0
control signal control signal
J. C. Huang, 2004 Digital Logic Design 40
A multiplexer/demultiplexer arrangement
for information transmission.
J. C. Huang, 2004 Digital Logic Design 41
A 4-to-1-line multiplexer
J. C. Huang, 2004 Digital Logic Design 42
Demultiplexer
J. C. Huang, 2004 Digital Logic Design 43
A 2
n
-to-1-line multiplexer symbol
J. C. Huang, 2004 Digital Logic Design 44
MUX implementation of a Boolean function
Any Boolean function of n variables can be
implemented by a multiplexer with n
control inputs in a straightforward manner.
J. C. Huang, 2004 Digital Logic Design 45
Example: f(x, y, z) = m(2, 5, 6, 7)
x y z | f(x, y, z) | =
0 0 0 | f(0, 0, 0) | 0
0 0 1 | f(0, 0, 1) | 0
0 1 0 | f(0, 1, 0) | 1
0 1 1 | f(0, 1, 1) | 0
1 0 0 | f(1, 0, 0) | 0
1 0 1 | f(1, 0, 1) | 1
1 1 0 | f(1, 1, 0) | 1
1 1 1 | f(1, 1, 1) | 1
J. C. Huang, 2004 Digital Logic Design 46
MUX implementation of a Boolean function
Even better, any Boolean function of n
variables can be implemented by a
multiplexer with n-1 control inputs as
illustrated in the following.
J. C. Huang, 2004 Digital Logic Design 47
Implementing a function of 3 variables with a 4x1 MUX: Method 1
I
0
I
1
I
2
I
3
s
1
s
0
f(x, y, z)
x y
J. C. Huang, 2004 Digital Logic Design 48
Using a multiplexer to implement a Boolean function: Method 1
Note that the output of a 4x1 multiplexer is
F(x, y, z) = x'y'I
0
+ x'yI
1
+ xy'I
2
+ xyI
3
Now, given a Boolean function
f(x, y, z) = f(0, 0, 0)x'y'z' + f(0, 1, 0)x'yz' + f(1, 0, 0)xy'z' + f(1, 1, 0)xyz'
+f(0, 0, 1)x'y'z + f(0, 1, 1)x'yz + f(1, 0, 1)xy'z + f(1, 1, 1)xyz
J. C. Huang, 2004 Digital Logic Design 49
The value for input I
0
is to be determined as follows.
if f(0, 0, 0) = and f(0, 0, 1) = then f(0, 0, 0)x'y'z' +
f(0, 0, 1)x'y'z =
and thus we should
let I
0
=
0 0 0=x'y'0 0
0 1 x'y'z z
1 0 x'y'z' z'
1 1 x'y'=x'y'1 1
The value for I
1
, I
2
, and I
3
are to be determined in a similar manner.
J. C. Huang, 2004 Digital Logic Design 50
Implementing a function of 3 variables with a 4x1 MUX: Method 2
I
0
I
1
I
2
I
3
s
1
s
0
f(x, y, z)
y z
J. C. Huang, 2004 Digital Logic Design 51
Using a multiplexer to implement a Boolean function: Method 2
Note that the output of a 4x1 multiplexer is
F(x, y, z)= I
0
y'z' + I
1
y'z + I
2
yz' + I
3
yz
Now, given a Boolean function
f(x, y, z) = f(0, 0, 0)x'y'z' + f(0, 0, 1)x'y'z + f(0, 1, 0)x'yz' + f(0, 1, 1)x'yz
+ f(1, 0, 0)xy'z' + f(1, 0, 1)xy'z + f(1, 1, 0)xyz' + f(1, 1, 1)xyz
J. C. Huang, 2004 Digital Logic Design 52
The value for input I
0
is to be determined as follows.
if f(0, 0, 0) = and f(0, 0, 1) = then f(0, 0, 0)x'y'z' +
f(1, 0, 0)xy'z' =
and thus we should
let I
0
=
0 0 0=0y'z' 0
0 1 xy'z' x
1 0 x'y'z' x'
1 1 y'z'=1y'z' 1
The value for I
1
, I
2
, and I
3
are to be determined in a similar manner.
J. C. Huang, 2004 Digital Logic Design 53
A multiplexer tree to form a
16-to-1-line multiplexer
J. C. Huang, 2004 Digital Logic Design 54
Realization of a three-variable function
using a 8-to-1-line multiplexer.
(a) Three-variable truth table.
(b) General realization.
J. C. Huang, 2004 Digital Logic Design 55
Example: realization of f(x,y,z) = m(0,2,3,5)
J. C. Huang, 2004 Digital Logic Design 56
Realizing a 3-variable Boolean function with a 4-to-1 multiplexer
J. C. Huang, 2004 Digital Logic Design 57
Realization of f(x,y,z) = m(0,2,3,5) using a 4-to-1-line multiplexer
J. C. Huang, 2004 Digital Logic Design 58
Obtaining multiplexer realizations using Karnaugh maps.
(a) Cell groupings corresponding to the data line functions.
(b) Karnaugh maps for the I
i
subfunctions.
J. C. Huang, 2004 Digital Logic Design 59
Realization of f(x,y,z) = m(0,2,3,5).
(a) Karnaugh map.
(b) I
0
, I
1
, I
2
, and I
3
submaps.
J. C. Huang, 2004 Digital Logic Design 60
Using Karnaugh maps to obtain multiplexer realizations under various
assignments to the select inputs.
(a) Applying input variables y and z to the S
1
and S
0
select lines.
(b) Applying input variables x and y to the S
0
and S
1
select lines.
J. C. Huang, 2004 Digital Logic Design 61
Alternative realizations of f(x,y,z) = m(0,2,3,5).
J. C. Huang, 2004 Digital Logic Design 62
A select line assignment and corresponding data line functions
for a multiplexer realization of a four-variable function.
J. C. Huang, 2004 Digital Logic Design 63
Realizations of f(w,x,y,z) = m(0,1,5,6,7,9,12,15).
J. C. Huang, 2004 Digital Logic Design 64
Using a four-variable Karnaugh map to obtain a Boolean
function realization with a 4-to-1-line multiplexer.
J. C. Huang, 2004 Digital Logic Design 65
Realizations of the Boolean function
f(w,x,y,z) = m(0,1,5,6,7,9,13,14).
J. C. Huang, 2004 Digital Logic Design 66
General structure of Programmable Logic
Devices (PLDs)
J. C. Huang, 2004 Digital Logic Design 67
Buffer/inverter. (a) Symbol. (b) Logic equivalent
J. C. Huang, 2004 Digital Logic Design 68
Types of PLDs
Programmable
Programmable
Fixed
Fixed
Programmable
Programmable
PROM
PLA
PAL
OR-array AND-array Device
J. C. Huang, 2004 Digital Logic Design 69
Programming by blowing fuses.
(a) Before programming.
(b) After programming.
J. C. Huang, 2004 Digital Logic Design 70
PLD notation
J. C. Huang, 2004 Digital Logic Design 71
Structure of a PROM
J. C. Huang, 2004 Digital Logic Design 72
A 2
n
m PROM.
(a) Logic diagram.
(b) Representation in PLD notation.
J. C. Huang, 2004 Digital Logic Design 73
Using a PROM for logic design. (a) Truth table. (b) PROM realization.
J. C. Huang, 2004 Digital Logic Design 74
Logic diagram of
an n p m PLA
J. C. Huang, 2004 Digital Logic Design 75
Example of combinational logic design using a PLA. (a) Maps showing the
multiple-output prime implicants. (b) Partial covering of the f
1
and f
2
maps. (c)
Maps for the multiple-output minimal sum. (d) Realization using a 3 4 2
PLA.
J. C. Huang, 2004 Digital Logic Design 76
Example of combinational logic design using a PLA. (a) Maps
showing the multiple-output prime implicants. (b) A multiple-
output minimal sum covering. (c) Alternative multiple-output
minimal sum covering. (d) Realization using a 3 4 2 PLA.
J. C. Huang, 2004 Digital Logic Design 77
Exclusive-or-gate with a programmable fuse.
(a) Circuit diagram. (b) Symbolic representation.
J. C. Huang, 2004 Digital Logic Design 78
General structure of a PLA having true
and complemented output capability
J. C. Huang, 2004 Digital Logic Design 79
Karnaugh maps for the functions f
1
(x,y,z) = m(1,2,3,7)
and f
2
(x,y,z) = m(0,1,2,6)
J. C. Huang, 2004 Digital Logic Design 80
Two realizations of f
1
(x,y,z) = m(1,2,3,7) and f
2
(x,y,z) = m(0,1,2,6).
J. C. Huang, 2004 Digital Logic Design 81
A simple four-input, three-output PAL device.
J. C. Huang, 2004 Digital Logic Design 82
An example of using a PAL device to realize two Boolean
functions. (a) Karnaugh maps. (b) Realization.
J. C. Huang, 2004 Digital Logic Design 83
A PLD programming unit
J. C. Huang, 2004 Digital Logic Design 84
A PLCC package with socket
P
r
i
n
t
e
d
c
i
r
c
u
i
t
b
o
a
r
d
J. C. Huang, 2004 Digital Logic Design 85
Limitations of PLAs and PALs
These chips are limited to fairly modest
size, typically supporting a combined
number of inputs plus outputs of not more
than 32.
Slide 3.31.1
J. C. Huang, 2004 Digital Logic Design 86
Complex Programmable Logic Devices
(CPLDs)
A CPLD comprises multiple PAL-like
blocks on a single chip with internal wiring
resources to connect the circuit blocks.
It is made to implement complex circuits
that cannot be done on a PAL or PLA.
J. C. Huang, 2004 Digital Logic Design 87
I
/
O
b
l
o
c
k
PAL-like
block
PAL-like
block
I
/
O
b
l
o
c
k
Structure of a CPLD
PAL-like
block
I
/
O
b
l
o
c
k
PAL-like
block
I
/
O
b
l
o
c
k
Interconnection wires
J. C. Huang, 2004 Digital Logic Design 88
D Q
D Q
D Q
PAL-like block (details not shown)
PAL-like block
A section of a CPLD
J. C. Huang, 2004 Digital Logic Design 89
CPLD packaging and programming
(a) CPLD in a Quad Flat Pack (QFP) package
Printed
circuit board
To computer
(b) JTAG programming
J. C. Huang, 2004 Digital Logic Design 90
A Measure of Circuit Size
A commonly used measure is the total
number of two-input NAND gates that
would be needed to build the circuit.
It is called the number of equivalent gates.
J. C. Huang, 2004 Digital Logic Design 91
Field-Programmable Gate Arrays (FPGAs)
An FPGA is a PLD that supports
implementation of large logic circuits.
It is different from others in that it does not
contain AND or OR planes. Instead, it
contains logic blocks as depicted in the next
slide.
J. C. Huang, 2004 Digital Logic Design 92
Structure of an FPGA
Logic block Interconnection switches
I/O block
I/O block
I
/
O
b
l
o
c
k
I
/
O
b
l
o
c
k
J. C. Huang, 2004 Digital Logic Design 93
Typical FPGAs
FPGAs can be used to implement logic
circuits of more than a few hundred
thousand equivalent gates in size.
The most commonly used logic block is a
lookup table (LUT) as depicted in Fig. 3.36.
Slide 3.35.1
J. C. Huang, 2004 Digital Logic Design 94
0/1
0/1
0/1
0/1
x
f
A two-input lookup table
y
J. C. Huang, 2004 Digital Logic Design 95
f
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
x
2
x
3
x
1
A three-input LUT
J. C. Huang, 2004 Digital Logic Design 96
0
1
0
0
0
1
1
1
0
0
0
1
x
1
x
2
x
2
x
3
f
1
f
2
f
1
f
2
f
x
1
x
2
x
3
f
A section
of a
programmed
FPGA
