Computer Architecture I
Lecture Notes
Dr. Ali Muhtaroğlu
Fall 2009
METU Northern Cyprus Campus
References:
Patterson&Hennessy, “Computer Organization and Design” (3rd Ed.), Kaufmann, 2007.
Stallings, “Computer Organization & Architecture” (7th Ed.), Pearson, 2006.
Mano & Kime, “Logic and Computer Design Fundamentals”, 4th Ed., Prentice Hall, 2008.
Brown & Vranesic, “Fund. Of Dig. Logic with VHDL Design” (2nd Ed.), McGraw Hill, 2005.
Dr. Patterson’s and Dr. Mary Jane Irwin’s (Penn State) Lecture notes
The Computer Components and
Program Concept
Lecture 3
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Some Terminology:
Structure and Function
• The computer is a hierarchical system, where each level of
the hierarchy can be defined by the designer in terms of a
structure and the function of components within that
structure.
• Structure is the way in which components relate to each
other
• Function is the operation of individual components as part of
the structure
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Functional View
4 computer functions:
1. Data processing
– The main purpose of a computer
2. Data storage
– Short or long term memory
3. Data movement
– Input/Output (I/O): Direct connection
– Data communications: Remote
4. Control
− Orchestrates the operation of
functional parts
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Functional View:
Basic Computer Operations
a) Data Movement b) Storage
c) Processing from/to d) Processing en route
storage between storage
and I/O
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Structural View : Top Level
Peripherals Computer
Central Main
Processing Memory
Unit
Computer
Systems
Interconnection
Input
Output
Communication
lines
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Structural View : Central Processing Unit
Control Unit: Controls the operation of the CPU and hence the computer
Arithmetic and Logic Unit (ALU): Performs the computer’s data processing functions
Registers: Provide storage internal to the CPU
CPU interconnection: Provides for communication among the control unit, ALU, and
registers
CPU
Computer Arithmetic
Registers and
I/O
Logic Unit
System CPU
Bus Internal CPU
Memory Interconnection
Control
Unit
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Structural View : Control Unit
Below is one possible structure of control unit, which is
implemented using microprogramming – details to come later.
Control Unit
CPU Sequencing
ALU Logic
Control
Internal
Unit
Bus Control Unit
Registers Registers and
Decoders
Control
Memory
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Hardwired Program Example
Logic: Timing Diagram:
IN1 IN2
clk
clk R1 R2
IN1 B
IN2 C
x y
IN3 D
x+y IN3
IN4 A
R3
R1 B
x y
R2 C
IN4 x-y
R3 D
R4 R4 A
x y R5 OUT
x-y A-((B+C)-D)
R5 • The logic constructed to solve a particular problem can be
OUT
thought of as a hardware “program”. The solution is
sometimes referred to as hardwired program.
• This example has data and clock inputs, and an output to
report the data back.
• What are the advantages and disadvantages of this solution?
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A more Generalized Solution
Logic:
IN1 IN2
clk R1 R2
0 1 0 1
SEL1 SEL2
x y
ADD:x+y A(0)/S(1)
SUB:x-y
R3
OUT
• In this particular design, control signals (SEL1, SEL2, A/S) can be sequenced to
solve a variety of problems involving addition and subtraction.
• An instruction set can be defined to allow software sequencing of the control
signals. e.g. ADDR1R2 : R3 R1+R2 ; SUBR1R3 : R3 R1-R3 … etc.
• Need hardware to interpret each instruction and generate the correct control
signals i.e. Control Unit. Also need storage for instructions, and perhaps data i.e.
Memory.
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A more Generalized Solution
Logic:
IN1 IN2
clk R1 R2
How do we do the same
SEL1 0 1
SEL2 0 1 operation with this
hardware?
x y
ADD:x+y A(0)/S(1)
SUB:x-y A-((B+C)-D)
R3
OUT
• In this particular design, control signals (SEL1, SEL2, A/S) can be sequenced to
solve a variety of problems involving addition and subtraction.
• An instruction set can be defined to allow software sequencing of the control
signals. e.g. ADDR1R2 : R3 R1+R2 ; SUBR1R3 : R3 R1-R3 … etc.
• Need hardware to interpret each instruction and generate the correct control
signals i.e. Control Unit. Also need storage for instructions, and perhaps data i.e.
Memory.
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A more Generalized Solution
Logic: Timing Diagram:
IN1 IN2 clk
clk R1 R2 IN1 B A
IN2 C D
0 1 0 1
SEL1 SEL2 SEL1
SEL2
x y
ADD:x+y A/S
A(0)/S(1)
SUB:x-y
R1 B A
R3 R2 C D
R3 OUT1 OUT2 OUT3
OUT
(B+C) (B+C)-D A-((B+C)-D)
• In this particular design, control signals (SEL1, SEL2, A/S) can be sequenced to
solve a variety of problems involving addition and subtraction.
• An instruction set can be defined to allow software sequencing of the control
signals. e.g. ADDR1R2 : R3 R1+R2 ; SUBR1R3 : R3 R1-R3 … etc.
• Need hardware to interpret each instruction and generate the correct control
signals i.e. Control Unit. Also need storage for instructions, and perhaps data i.e.
Memory.
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A more Generalized Solution
Logic: Timing Diagram:
IN1 IN2 clk
clk R1 R2 IN1 B A
IN2 C D
0 1 0 1
SEL1 SEL2 SEL1
SEL2
x y
ADD:x+y A/S
A(0)/S(1)
SUB:x-y
R1 B A
R3 R2 C D
R3 OUT1 OUT2 OUT3
OUT
(B+C) (B+C)-D A-((B+C)-D)
• In this particular design, control signals (SEL1, SEL2, A/S) can be sequenced to
solve a variety of problems involving addition and subtraction.
• An instruction set can be defined to allow software sequencing of the control
signals. e.g. ADDR1R2 : R3 R1+R2 ; SUBR1R3 : R3 R1-R3 … etc.
• Need hardware to interpret each instruction and generate the correct control
signals i.e. Control Unit. Also need storage for instructions, and perhaps data i.e.
Memory.
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What are the advantages and disadvantages of this solution? 13
Program Concept
Programming in Hardware:
Sequence of
Data arithmetic and Results
• Inflexible logic functions
Programming in software:
Instruction Instruction
codes Interpreter
• General purpose hardware can
do different tasks, given correct
control of signals.
General-purpose
• Instead of rewiring, supply a
Data arithmetic and Results
new set of control signals logic functions
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What is a program?
• A sequence of steps
• For each step, an arithmetic or logical (or simple movement)
operation is done
• For each operation, a different set of control signals is needed
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What is a program?
• A sequence of steps
• For each step, an arithmetic or logical (or simple movement)
operation is done
• For each operation, a different set of control signals is needed
Function of Control Unit
• For each operation a unique code is provided
– e.g. ADD, MOVE
• A hardware segment accepts the code and issues the control
signals
• We have a computer!
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Computer Components
• The Control Unit and the Arithmetic and Logic Unit
constitute the Central Processing Unit
• Data and instructions need to get into the system
and results out
– Input/output
• Temporary storage of code and results is needed
– Main memory
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Computer Components: Top Level View
* Assumes Isolated I/O (vs. Memory Mapped I/O)
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Instruction Cycle
• Two steps (three steps if you also count Decode):
– Fetch
– (Decode)
– Execute
• Fetch/(Decode)/Execute cycle will continue till the machine is
turned off, an error has occurred, or a HALT (or similar)
instruction has been encountered.
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Fetch Cycle
• Program Counter (PC) holds address of next instruction to fetch
• Processor fetches instruction from memory location pointed to by PC
• Increment PC
– Unless told otherwise
• Instruction loaded into Instruction Register (IR)
• Processor interprets (decodes) instruction and performs required actions
Execute Cycle
• Processor-memory
– data transfer between CPU and main memory
• Processor I/O
– Data transfer between CPU and I/O module
• Data processing
– Some arithmetic or logical operation on data
• Control
– Alteration of sequence of operations e.g. jump
• Combination of above
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Example: Hypothetical Machine
Instruction Format:
0 3 4 15
Opcode Address
Integer Format:
0 15
Magnitude
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Example: Hypothetical Machine
Instruction Format:
0 3 4 15
Opcode Address
Integer Format:
0 15
Magnitude
Internal CPU Registers: Program Counter (PC) = Address of instruction
Instruction Register (IR) = Instruction being executed
Accumulator (AC) = Temporary storage
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Example: Hypothetical Machine
Instruction Format:
0 3 4 15
Opcode Address
Integer Format:
0 15
Magnitude
Internal CPU Registers: Program Counter (PC) = Address of instruction
Instruction Register (IR) = Instruction being executed
Accumulator (AC) = Temporary storage
Partial list of opcodes: 0001 = Load AC from memory
0010 = Store AC to memory
0101 = Add to AC from memory (result goes back to AC)
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Example: Hypothetical Machine
Instruction Format:
0 3 4 15
Opcode Address
Integer Format:
0 15
Magnitude
Internal CPU Registers: Program Counter (PC) = Address of instruction
Instruction Register (IR) = Instruction being executed
Accumulator (AC) = Temporary storage
Partial list of opcodes: 0001 = Load AC from memory
0010 = Store AC to memory
0101 = Add to AC from memory (result goes back to AC)
Note: There can be 24 different opcodes
212=4096 memory words are directly accessible by the instruction.
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Example Program Execution
Micro-Operation:
Fetch 1st Instruction
Opcode List:
0001 = Load AC from
memory
0010 = Store AC to
memory
0101 = Add to AC from
memory
MAR & MBR data
transfers are not shown
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Example Program Execution
Micro-Operation:
Fetch 1st Instruction
Decode and Execute
Opcode List:
0001 = Load AC from
memory
0010 = Store AC to
memory
0101 = Add to AC from
memory
MAR & MBR data
transfers are not shown
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Example Program Execution
Micro-Operation:
Fetch 1st Instruction
Decode and Execute
Fetch 2nd Instruction
Opcode List:
0001 = Load AC from
memory
0010 = Store AC to
memory
0101 = Add to AC from
memory
MAR & MBR data
transfers are not shown
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Example Program Execution
Micro-Operation:
Fetch 1st Instruction
Decode and Execute
Fetch 2nd Instruction
Decode and Execute
Opcode List:
0001 = Load AC from
memory
0010 = Store AC to
memory
0101 = Add to AC from
memory
MAR & MBR data
transfers are not shown
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Example Program Execution
Micro-Operation:
Fetch 1st Instruction
Decode and Execute
Fetch 2nd Instruction
Decode and Execute
Fetch 3rd Instruction
Opcode List:
0001 = Load AC from
memory
0010 = Store AC to
memory
0101 = Add to AC from
memory
MAR & MBR data
transfers are not shown
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Example Program Execution
Micro-Operation:
Fetch 1st Instruction
Decode and Execute
Fetch 2nd Instruction
Decode and Execute
Fetch 3rd Instruction
Decode and Execute
Opcode List:
0001 = Load AC from
memory
0010 = Store AC to
memory
0101 = Add to AC from
memory
MAR & MBR data
transfers are not shown
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Instruction Cycle State Diagram
Processor and
Memory or I/O
Data exchange
Internal
Processor
Operations
This diagram incorporates the most flexible machine type where there may be
multiple operands in a single instructoin referencing the memory for multiple
data reads or writes.
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