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Software Assisted
Hardware Verification
About Coverify
We are a group of Verification Engineers
accepting challenges from designers
and challenging them back everyday.
Experting in modern test & verification
methodologies, when needed, we invent verification languages like Vlang.
Founded in 2010, we are a healthy mix
of young and veteran RTL & System
Level Verification professionals.
Domain Expertise
Verification Methodologies: UVM,
VMM
OVM,
EDA Expertise: PLI, VPI, VHPI, TCL, Discrete
Event Simulators, Virtual Platforms,
Coverification
Abstraction Expertise: RTL, TLM, ESL, Heterogeneous
Architecture Expertise: ARM, MIPS, Xtensa,
Xilinx, Altera, NoC
Hardware Protocols: AMBA, Wishbone, Ethernet, HDMI, SONET/SDH, Fiber Channel, Home Networking
Software Expertise: Object
Oriented
Programming, Functional Programming, Metaprogramming, Concurrent
Programming,
Generic/Generative
Programming
Language Expertise: C/C++, SystemC, SystemVerilog, Vlang, VHDL, Python, Ruby
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F you need Verification and ESL professionals with strong
hardware background as well as software expertise, we will
not let you down. You can rely on us for creating Verification Infrastructure, integrating your software stack with
hardware verification and for boosting your Verification Coverage.
Test Bench Development:
Test bench is a software and at Coverify, we keep that in mind and develop our methodologies around that objective. This primary objective
enabled us in mastering:
Heterogeneous TB Development: Modernized verification environments are complex and aspired towards reuse of components
designed at various levels of abstraction and languages of choice.
At Coverify, we master heterogeneous test bench development
where tools and languages like MATLAB, C, C++, SystemC, SystemVerilog, VHDL, Vlang etc are seamlessly integrated resulting in
a productive test bench.
System Level TB Development: Coverify is a system level verification
company and exactly understand the business of verification. We
develop complete system models (a car door behavior as an example) to provide better verifiability and use case verification on
your SoC.
Explorative TB Development: If you want to perform a design space
exploration on your ESL model or RTL we are there to develop
a verification environment which will enable exploration for you
which will result an optimized and cost eective design.
Custom Verification IP Development:
The software nature of the test bench provides pleasurable experience
of coding and without reference models, this experience will be full of
glitches. At Coverify we provide Verification IPs exactly for this reason.
Optimized, fast, abstract and excellently planned VIPs will never steal
you pleasure of coding.
Standard Reference Model Development: Starting from abstract objects down to bus functional models and expanding from modern
object orientation down to traditional, we design standard reference models according to your taste and need.
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+91-124-4086612
[email protected]
Why Coverify?
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We bring multidisciplinary expertise at
your doorstep.
Having ported the complete UVM
platform to Vlang, we understand the
strengths and pitfalls of UVM better
than others.
We have a vast set of homegrown tools
to help achieve very high verification
coverage in a short duration.
We develop your reference models in
C++. That is the best way to ensure that
your IP will not get outdated for a long
period of time.
We can help you enable concurrency in
your Verification and ESL platforms.
We deliver incredible service. When you
interact with Coverify, you are interacting with experienced developers. No
flu! No bullshit!!
We deliver awesome code, and we
do not hide our code in the obscurity of code encryption. Check our
github repository at http://github
.com/coverify
Collaborate with Coverify
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The ever widening Verification Gap and
the advent of Concurrency in software are
elephants in the drawing room that require immediate attention.
We believe the way forward is to collaborate and create open source solution.
We invite you to Fork us on Github.
http://github.com/coverify
UVM Testbench Architecture Development: We develop the UVM architecture of the testbench with a focus on the object oriented nature of each component.
System Level Model Development : System Level TB needs system
level reference models. Be it a car door, wheel, steering, mobile
channel model et.al., we are expert in modelling natural world.
The Verification & The Methodology:
Every verification concept exploited in modern SoC verification is directly derived from modern software engineering and embedded system
testing. That is the most dominant reason behind why you want your
test bench to be a software - answer is because you want to use novel
methodologies from software engineering. At Coverify we expertise this
- customizing a unique verification methodology from modern Software
Engineering, which is perfect for your product line, your expertise and
more importantly you.
Methodologies
Model Based Verification: Whether there is an explicit reference model
in your TB or not, every verification is model based. Coverify understands this methodological aspect very well and enable this using Standard Reference Model or UVM. At Coverify, we take full advantage of software nature of TB and reference models to implement dierent identified aspects of design functionalities at various levels of abstraction and use cases. These aspects are made
easily available through dierent soft access layer which allows
the verification engineer to attack the RTL barbarically.
System Level Verification: System Level verification becomes important when you are architecting your system or verifying architecture use cases. Coverify enables System Level verification methodology through heterogeneous verification environment development and environment modelling.
Design of Experiments: Design of experiment is a compulsory modern
trend in safety critical application in which to prove or to disprove
some assumption, experiments are designed and performed on
the device using system level test environment. We expertise in
design of experiments to prove or disprove certain hypotheses for
the SoC.
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Connect with Coverify
on
http://www.linkedin.com/company/coverify
http://twitter.com/coverify
+91 124 4086612
Skype ID
coverify
Address
ub
http://coverification.com
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Blog
Twitter
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http://coverify.com
Linkedin
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Website
A-238, South City I, Gurgaon, India - 122007
http://coverify.com
+91-124-4086612
[email protected]
lang
Open Source Verification Language
with UVM and MULTICORE Support
About Vlang
Moore's law is dead! Long live Amdahl's law!!
Vlang is an open source, high productivity, high
performance, multi-paradigm verification language built on top of D programming language.
Does your Verification IP Scale?
Till year 2005 (thanks to the good health of Moore's Law back then), processor speed would double every year and a half. As a result you did not
have to do anything to get a faster verification environment for your next
(bigger) chip. But since then, processors have stopped running faster.
Instead processor companies are putting more processor cores in the
servers. In another couple of years, servers running your functional regression are projected to have more than a hundred processor cores.
And if you do not change the way you verify, you will be utilizing precisely one of these hundred processors.
You want to change that? Give Vlang a try
Documentation
http://vlang.org
Development
http://github.com/coverify/vlang
http://github.com/coverify/vlang-uvm
Maintainer
Puneet Goel <[email protected]>
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Verification with Vlang
Even as the chip complexity keeps increasing, we continue to rely on
same old RTL methodology to design our chips. As a result the abstraction gap between the design and the specification is increasing exponentially.
Vlang attempts to bridge this gap by providing you a high productivity
and high performance verification environment.
SystemC
Verilog
VLANG
SystemVerilog
COVERAGE
Multicore Vlang enables concurrent programming. End user can fine-tune the number
of concurrently running threads at module
level. Vlang also enables concurrency at
a higher abstraction by allowing multiple
simulators running in parallel.
Constrained Randomization Full blown and eicient. Concurrency enabled.
UVM Compliance Word-to-word translation of
SystemVerilog UVM. More eicient and
user-friendly due to generic programming.
Object Oriented Programming Support for function/operator overloading.
Safety and Productivity Automatic Garbage Collection. Exception Handling. Unittests.
Systems Programming Allows low level access to
hardware resources. Allows embedded assembly language.
Interface with other Languages Full blown C++
interface. VHPI/VPI bindings with VHDL and
SystemVerilog.
Licensing Provided free under open source boost
license. Vlang UVM library is available under
Apache2 license.
PERFORMANCE
Vlang Features at a Glance
Higher Productivity
helps you start
early
Higher Performance
helps you cover
faster
VHDL
PRODUCTIVITY & SAFETY
TIME & EFFORT
Higher Productivity means that you take less time in building your verification infrastructure and higher performance means that your regression runs much faster.
If you have ESL as part of your SoC development flow, there are additional reasons that you should use Vlang to verify your ESL models. Vlang
supports much better integration with C++ compared to SystemVerilog.
Vlang is ABI compatible with C/C++. Vlang also allows you to call any
method (including virtual methods) on C++ objects right from Vlang
without any boilerplate code. In comparison SystemVerilog DPI interface is limited to C language. As a result any interface between SystemC
and SystemVerilog tends to be highly ineicient.
Yet another advantage is that Vlang is free and open source just like your
SystemC simulator.
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+91-124-4086612
[email protected]
Vlang Features
Feature
Vlang
SystemSystemC Remarks
Verilog
Performance Enablers
Concurrent Threads
Yes
No
No
Use -version=MULTICORE to enable
Multiple Concurrent Simulators
Yes
No
No
Native Compilation
Yes
No
Yes
Generic Library Support
Yes
No
Yes
Fastest
Slow
Fast
Incremental Compile
Yes
Partial
Yes
Pointer-less Programming
Yes
Yes
No
Automatic Garbage Collection
Yes
Yes
No
Every significant language born after year 2000
provides for a decent GC
User-friendly Containers
Yes
Yes
No
Associative arrays vs C++ std::map<>
[][] vs multi-dimensional vectors in C++
Array Bound Check
Yes
No
No
Check for Integral Overflow
Yes
No
No
builtin
library
library
Exception Handling
Yes
No
Yes
Contract-based Programming
Yes
No
No
Low level hardware/device access
Yes
No
Yes
Custom memory allocation
Yes
No
Yes
Eicient File IO
Yes
No
Yes
Parsing tools/libraries
Yes
No
Yes
Embedded Assembly Code
Yes
No
Yes
No standard library for SV
Coding Productivity
Compile Time
Huge elaboration time for SV
Runtime Safety
Support for Unittests
Vlang supports localized Unittests.
Systems Programming Features
Essential for Virtual Platforms and Coverification
SV can not parse even XML by itself
Reflections and Generative Programming
Support for Data Introspection
and Reflections
Yes
No
No
Generative and Metaprogramming Support
Yes
No
Limited
Base Class Libraries
Yes
Yes
Yes
Support for Sequences
Yes
Yes
Limited
Register Abstraction Layer
No
Yes
No
TLM1 Support
Yes
Yes
Yes
TLM2 Support
No
Yes
Yes
Transaction Randomization
Yes
Yes
Limited
Sequence Randomization
Yes
Yes
No
Coverage Support
No
Yes
No
Very useful for UVM automation
UVM Support
SystemC lacks randomize with
RAL package for Vlang is under development
TLM2 support in SystemVerilog is limited
Support for Vlang TLM2 in the works
Verification Features
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SystemC relies on external constraint libraries,
none of which is user friendly
Coverage will be available in next release of
Vlang
+91-124-4086612
[email protected]
