Finite state Machines
Synchronous Sequential Circuits
Outputs updated on clock edges depending on the past behavior and also the present value of the
inputs.
General form of a sequential circuit
Moore FSM Machines
Output determined solely by Present State.
Fully synchronous behavior. Prone to glitches.
State transition diagram has each node (state) labeled with output value.
Mealy FSM Machines
Output determined by Present State and current input.
React asynchronously to input transitions. Prone to race conditions.
State transition diagram has each arc (transition) labeled with output value.
Best performance, size and stability may be achieved by using registers on outputs of Mealy machines
creating a Mealy/Moore hybrid.
Finite-State Machine Design
1. Flipflops
Store state
The only circuit that depends on the clock
On clock edge, the current state is updated
2. Combinational circuits will do rest
Next state logic: Compute the next state
fn(concurrent state, inputs)
Output logic
Moore machine: fn(Present State), or
Mealy machine: fn(Present State, inputs)
Design Process
1.
2.
3.
4.
Obtain specifications of desired circuit
Choose starting state and derive state diagram
Create a state table from the state diagram
Minimize the number of states
It is hard to come up with a state table with the minimum number of required
states.
5. Assign state variable
Some assignments are better than others.
6. Choose flipflop types and derive next state and output expression
7. Implement the circuit
Step 1. Specification
Example: Sequence detector
Design a circuit that detects if two or more consecutive 1s appear on its input
One input, w, and one output z
All changes in the circuit occur on the positive edge of clock signal
The output z is equal to 1 if during two immediately preceding clock cycles the input was
equal to 1. Otherwise, the value of z is equal to 0
Key assumption: changes in the input, w, are synchronous with the clock
If changes are asynchronous, then additional states are required to detect input
transitions
Step2. State Diagram
Choose a starting/reset state A
Transitions occur only on clock edge: State diagram shows sequence of states in response to
inputs
We consider Reset and clock as special inputs implemented by clock and clear/preset
inputs on flipflops.
Step 3. State Table
Step 5. State Assignment
Assign numerical values to the state labels.
Define state variables
In this case, need 2 variables y1 and y2
Each state variable is implemented with a flipflop
Choose a mapping from the state label to state variable
Many such mappings
The complexity of mapping determines the result circuit complexity.
For now, choose any mapping, say
A =y2y1 = 00,
B =y2y1 = 01,
C =y2y1 = 10
The fourth value y2y1 = 11 is not needed
Step 6. Next-State and Output logic
Choose flipflop type
Most straightforward is to choose rising edge D flipflops
Apply the next state variable to the D inputs of the flipflops
Next state variables (Y1,Y2) are clocked into the flipflops on the next rising
clock edge to become the new values of the present state (y1,y2)
Derive the next state and output expressions
Dont cares for y1y2=11 can help simplify the expressions
Step 7. Implementation
One-Hot Encoding
Use as many state variable as there are states.
Only one of them may be 1 or hot at once.
Treat unused states as dont cares.
Only sometimes advantageous
Design of FSM using VHDL
Rudimentary method:
1. Use design technique previously described to design the next state logic, output logic
and flipflop circuits.
2. Use schematic diagrams or structural VHDL to describe these circuits. E.g. use
components for the flipflops etc.
3. Use CAD to simulate behavior
4. Use CAD to automatically implement the circuit in a chip, such as a PLD
5. Process blocks do not synthesize as sequential circuits by default. This behavior must
be defined explicitly.
Creating a Moore type sequence detector
Preferred style of FSM in VHDL
This first process defines a combinational logic block. The second block defines a clocked flipflop
sequential block and the last line defines another combinational logic block.
Manual state Assignment
VHDL constants may be used
Such as
Note that since STD_LOGIC has 9 different possible states, when others and else must be
used as appropriate.
Quartus II specific method
Mealy FSM using VHDL
Example: Create FSM of serial adder
Add pair of bits each from A and B and carry in from previous addition in each clock cycle.
Mealy FSM
Moore FSM
Requires more state definitions than Mealy.
State Minimization
Successor state.
If input w=0 is applied to FSM in state Si and machine moves to state Su, then Su is a 0-successor.
If input w=1 is applied to FSM in state Si and machine moves to state Sv, then Sv is a 1-successor.
Generally, for multiple inputs, successors of Si are referred to as K-successors of Si, where K is the
set of all possible combinations of the inputs.
Si and Sj are said to be equivalent if for every possible input sequence, same output sequence is
produced.
A partition consists of one or more blocks where each block comprises a subset of states that
may be equivalent, but are not equivalent to states in other blocks.
Procedure
Example
Incomplete Specified FSMs
If not all state transitions and/or outputs are specified, treat as dont cares and assume values
for state minimization.
Analysis of Synchronous Sequential Circuit
Outputs of flipflops represent present state variables
Inputs of flipflops represent next state variables
Construct state assigned table
Create state table and state diagram
Using JK flipflops in synthesis and analysis
Algorithmic State Machine charts
Flow chart containing state information and timing information
Moore FSM
Mealy FSM
General Model for Sequential Circuit
