EXOR Gate Using Concurrent Statements
VHDL CODE
library ieee;
use ieee.std_logic_1164.all;
entity xor1 is
port (a,b:in std_logic; c: out std_logic);
end xor1;
architecture xyz of xor1 is
begin
c<= a xor b;
end xyz;
RTL VIEW
COMPILATION REPORT
SIMULATION (WAVEFORM VECTOR)
4-bit EXOR Gate Using Concurrent Statements
VHDL CODE
library ieee;
use ieee.std_logic_1164.all;
entity xor1 is
port std_logic_vector(3 downto 0); y: out std_logic_vector(3 downto
0));end xor1;
architecture abc of xor1 is
begin
y<= a xor b;
end abc;
RTL VIEW
COMPILATION REPORT
SIMULATION (WAVEFORM VECTOR)
RECORDS
VHDL CODE
library ieee;
use ieee.std_logic_1164.all;
entity sum1 is
end sum1;
architecture abc of sum1 is
type data_date is record
year:integer range 1989 to 1999;
month:integer range 1 to 12;
date: integer range 1 to 31;
hour:integer range 0 to 23;
minute:integer range 0 to 59;
second:integer range 0 to 59;
end record;
signal a:data_date;
begin
a.year<=1990;
a.month<=10;
a.date<=24;
end;
FULL ADDER
VHDL CODE
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port(a,b,cin : in std_logic; sum ,cout : out std_logic);
end full_adder;
architecture abc of full_adder is
begin
sum<=a xor b xor cin;
cout<= (a and b)or(b and cin)or(a and cin);
end abc;
RTL VIEW
COMPILATION REPORT
SIMULATION (WAVEFORM VECTOR)
FULL ADDER USING STRUCTURAL STATEMENT
VHDL CODE
-- fulladder using structural modelling
library ieee;
use ieee.std_logic_1164.all;
entity fulladder_struct is
port (x,z, cin: in bit; sum1, carry1 : out bit);
end fulladder_struct;
architecture abc of fulladder_struct is
component halfadder is
port( a,b : in bit; sum, carry : out bit);
end component;
component or1 is
port(in1, in2: in bit; out1: out bit);
end component;
signal s1, s2, s3 : bit;
begin
HA1: halfadder port map(x,z, s1, s2);
HA2: halfadder port map(s1,cin, sum1, s3);
OR2 : or1 port map( s2, s3, carry1);
end abc;
entity halfadder is
port( a,b : in bit; sum, carry : out bit);
end halfadder;
architecture abc of halfadder is
begin
process(a,b)
begin
if(a='0' and b='0') then
sum <='0';
carry <='0';
elsif (a='0' and b='1') then
sum <='1';
carry <= '0';
elsif(a='1' and b='0') then
sum <='1';
carry <= '0';
elsif(a='1' and b='1') then
sum <='0';
carry <= '1';
end if;
end process;
end abc;
entity or1 is
port( in1,in2 : in bit; out1: out bit);
end or1;
architecture xyz of or1 is
begin
out1<= in1 OR in2;
end xyz;
RTL VIEW
COMPILATION REPORT
SIMULATION (WAVEFORM VECTOR)
HALF ADDER USING PROCESS STATEMENT
VHDL CODE
library ieee;
use ieee.std_logic_1164.all;
entity halfadder is
port( a,b : in std_logic; sum, carry : out std_logic);
end halfadder;
architecture abc of halfadder is
begin
process(a,b)
begin
if(a='0' and b='0') then
sum <='0';
carry <='0';
elsif (a='0' and b='1') then
sum <='1';
carry <= '0';
elsif(a='1' and b='0') then
sum <='1';
carry <= '0';
elsif(a='1' and b='1') then
sum <='0';
carry <= '1';
else
sum <= '-';
carry <='-';
end if;
end process;
end abc;
RTL VIEW
COMPILATION REPORT
SIMULATION (WAVEFORM VECTOR)
HALF ADDER USING CONCURRENT STATEMENTS
VHDL CODE
library ieee;
library ieee;
use ieee.std_logic_1164.all;
entity halfadder1 is
port( a,b : in std_logic; sum, carry : out std_logic);
end halfadder1;
architecture abc of halfadder1 is
begin
sum <=a xor b;
carry <= a and b;
end abc;
RTL VIEW
COMPILATION REPORT
SIMULATION (WAVEFORM VECTOR)
MATHEMATICAL OPERATIONS
VHDL CODE
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity maths is
port(a,b:in integer; c,d,e,f,g,h:out integer);
end maths;
architecture abc of maths is
begin
c <= a + b;
d<=a-b;
e<=a*b;
f<=a/b;
g<=a mod b;
h<=a rem b;
end abc;
RTL VIEW
COMPILATION REPORT
SIMULATION (WAVEFORM VECTOR)
4X1 MUX USING IF-ELSE LADDER
VHDL CODE
library ieee;
use ieee.std_logic_1164.all;
entity mux_4x1 is
port(a,b,c,d,gbar : in std_logic;
sel : in bit_vector (1 downto 0);
Y : out std_logic);
end mux_4x1;
architecture abc of mux_4x1 is
begin
process(a,b,c,d,gbar,sel)
begin
if gbar='0' then
if sel="00" then
y<=a;
elsif (sel="01") then
y<=b;
elsif (sel="10") then
y<=c;
else
y<=d;
end if;
else
y<='-';
end if;
end process;
end abc;
RTL VIEW
COMPILATION REPORT
SIMULATION (WAVEFORM VECTOR)
4X1 MUX USING CASE STATEMENT
VHDL CODE
--mux using case statement
library ieee;
use ieee.std_logic_1164.all;
entity mux_case is
port(a: in bit_vector(3 downto 0); en : in bit; sel: in bit_vector(1 downto 0);
b: out bit);
end mux_case;
architecture abc of mux_case is
begin
process(en, sel)
begin
if en='1' then
case sel is
when "00" => b<= a(0);
when "01" => b<= a(1);
when "10" => b<= a(2);
when "11" => b<= a(3);
end case;
else
b<='0';
end if;
end process;
end abc;
RTL VIEW
COMPILATION REPORT
SIMULATION (WAVEFORM VECTOR)
4X1 MUX USING CONDITIONAL STATEMENT
VHDL CODE
library ieee;
use ieee.std_logic_1164.all;
entity mux_conditional is
port (a,b,c,d : in std_logic ; s: in bit_vector(1 downto 0);y : out std_logic);
end mux_conditional;
architecture abc of mux_conditional is
begin
y<= a when s ="00" else
b when s ="01" else
c when s ="10" else
d ;
end abc;
RTL VIEW
COMPILATION REPORT
SIMULATION (WAVEFORM VECTOR)
4X1 MUX USING SELECT STATEMENT
VHDL CODE
library ieee;
use ieee.std_logic_1164.all;
entity mux_selected is
port (a,b,c,d : in std_logic ; s: in bit_vector(1 downto 0);y : out std_logic);
end mux_selected;
architecture abc of mux_selected is
begin
with s select
y<= a when "00" ,
b when "01" ,
c when "10" ,
d when others ;
end abc;
RTL VIEW
COMPILATION REPORT
SIMULATION (WAVEFORM VECTOR)
SHIFT OPERATIONS
VHDL CODE
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity operations is
port(a:in bit_vector(3 downto 0);p,q,r,s,t,u:out bit_vector(3 downto 0));
end operations;
architecture xyz of operations is
begin
p<= a sll 1;
q<= a srl 1;
r<= a sla 1;
s<= a sra 1;
t<= a rol 1;
u<= a ror 1;
end xyz;
RTL VIEW
COMPILATION REPORT
SIMULATION (WAVEFORM VECTOR)
SUBTRACTOR
VHDL CODE
library ieee;
use ieee.std_logic_1164.all;
entity subtractor is
port(a : in bit_vector(1 downto 0); diff , borr : out std_logic);
end subtractor;
architecture abc of subtractor is
begin
process(a)
begin
case a is
when "00"=> diff<= '0';
when "01"=> diff<= '1';
when "10"=> diff<= '1';
when "11"=> diff<= '0';
end case;
if a="01" then
borr <='1';
else
borr <='0';
end if;
end process;
end abc;
RTL VIEW
COMPILATION REPORT
SIMULATION (WAVEFORM VECTOR)
Rotation of array using for (O: n) [array size is even]
library ieee;
use ieee.std_logic_1164.all;
entity practice is
port ( a: in std_logic_vector(3 downto 0); c: out std_logic_vector(3 downto
0));
end practice;
architecture abc of practice is
signal d : std_logic_vector (1 downto 0);
signal e : std_logic_vector (1 downto 0);
begin
process(a,b)
begin
for i in 0 to 1 loop
d(i) <= a(3-i);
e(1-i) <= a(i);
end loop;
c <= d&e;
end process;
end abc;
Rotation of array using for (O: n^2
library ieee;
use ieee.std_logic_1164.all;
entity practice is
port ( a: in std_logic_vector(3 downto 0); c: out std_logic_vector(3 downto
0));
end practice;
architecture abc of practice is
begin
process(a)
variable b : std_logic;
variable d : std_logic_vector (3 downto 0);
begin
d := a;
for j in 2 downto 1 loop
b := d(3);
for i in 3 downto 1 loop
d(i) := d(i-1);
end loop;
d(0) := b;
end loop;
c <= d;
end process;
end abc;)
Rotation of array using for (O: n) [general]
library ieee;
use ieee.std_logic_1164.all;
entity practice is
port ( a: in std_logic_vector(4 downto 0); c: out std_logic_vector(4 downto
0));
end practice;
architecture abc of practice is
signal d : std_logic_vector (2 downto 0);
signal e : std_logic_vector (1 downto 0);
begin
process(a)
begin
for i in 0 to 1 loop
e(1-i) <= a(i);
end loop;
for i in 0 to 2 loop
d(i) <= a(4-i);
end loop;
end process;
c <= d&e;
end abc;
Function to make an ALU which multiplies and divides two numbers
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee. std_logic_arith.all;
entity practice is
port ( a,b: in integer; mul, div: out integer);
end practice;
architecture abc of practice is
function multiply(x,y: in integer)
return integer is
variable result: integer;
begin
result := x*y;
return result;
end multiply;
function divide(x,y: in integer)
return integer is
variable result: integer;
begin
result := x/y;
return result;
end divide;
begin
mul <= multiply(a,b);
div <= divide(a,b);
end abc;
