L5: Simple Sequential Circuits and Verilog

Acknowledgements:
Materials in this lecture are courtesy of the following sources and are used with
permission.
Nathan Ickes

Rex Min

L5: 6.111 Spring 2006

Introductory Digital Systems Laboratory

Key Points from L4 (Sequential Blocks)

Classification:
Latch: level sensitive (positive latch passes input to output on high phase, hold
value on low phase)
Register: edge-triggered (positive register samples input on rising edge)
Flip-Flop: any element that has two stable states. Quite often Flip-flop also used
denote an (edge-triggered) register

Positive
Latch

D Q

Clk

D Q

Positive
Register

Clk

Latches are used to build Registers (using the Master-Slave Configuration), but
are almost NEVER used by itself in a standard digital design flow.

Quite often, latches are inserted in the design by mistake (e.g., an error in your
Verilog code). Make sure you understand the difference between the two.

Several types of memory elements (SR, JK, T, D). We will most commonly use
the D-Register, though you should understand how the different types are built
and their functionality.

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Introductory Digital Systems Laboratory

System Timing Parameters

In

D Q

Combinational
Logic

Clk

Clk

Register Timing Parameters

Tcq : worst case rising edge
clock to q delay
Tcq, cd: contamination or
minimum delay from
clock to q
Tsu: setup time
Th: hold time
L5: 6.111 Spring 2006

D Q

Logic Timing Parameters

Tlogic : worst case delay
through the combinational
logic network
Tlogic,cd: contamination or
minimum delay
through logic network

Introductory Digital Systems Laboratory

System Timing (I): Minimum Period

CLout
In

Combinational
Logic

D Q

D Q

Clk

Clk
CLK
Th

Th

IN
Tsu

Tsu

Tcq

Tcq

FF1
Tcq,cd

Tlogic

Tcq,cd

CLout
Tl,cd

Tsu2

T > Tcq + Tlogic + Tsu

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Introductory Digital Systems Laboratory

System Timing (II): Minimum Delay

CLout
In

Combinational
Logic

D Q

D Q

Clk

Clk
CLK
Th

Th

IN
Tsu

FF1
Tcq,cd

CLout
Tl,cd

Tcq,cd + Tlogic,cd > Thold

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Introductory Digital Systems Laboratory

The Sequential always Block

Edge-triggered circuits are described using a sequential

always block
Combinational

Sequential

module combinational(a, b, sel,

out);
input a, b;
input sel;
output out;
reg out;
always @ (a or b or sel)
begin
if (sel) out = a;
else out = b;
end
endmodule

module sequential(a, b, sel,

clk, out);
input a, b;
input sel, clk;
output out;
reg out;
always @ (posedge clk)
begin
if (sel) out <= a;
else out <= b;
end
endmodule

1
D Q

out
b

0
sel

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out

0
sel

Introductory Digital Systems Laboratory

clk
6

Importance of the Sensitivity List

The use of posedge and negedge makes an always block sequential

(edge-triggered)

Unlike a combinational always block, the sensitivity list does

determine behavior for synthesis!
D Flip-flop with synchronous clear

module dff_sync_clear(d, clearb,

clock, q);
input d, clearb, clock;
output q;
reg q;
always @ (posedge clock)
begin
if (!clearb) q <= 1'b0;
else q <= d;
end
endmodule

always block entered only at

each positive clock edge

D Flip-flop with asynchronous clear

module dff_async_clear(d, clearb, clock, q);
input d, clearb, clock;
output q;
reg q;
always @ (negedge clearb or posedge clock)
begin
if (!clearb) q <= 1b0;
else q <= d;
end
endmodule

always block entered immediately

when (active-low) clearb is asserted

Note: The following is incorrect syntax: always @ (clear or negedge clock)

If one signal in the sensitivity list uses posedge/negedge, then all signals must.

Assign any signal or variable from only one always block, Be

wary of race conditions: always blocks execute in parallel
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Simulation (after Place and Route in Xilinx)

DFF with Synchronous Clear

tc-q

Clear on Clock Edge

DFF with Asynchronous Clear

Clear happens on
falling edge of clearb

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Blocking vs. Nonblocking Assignments

Verilog supports two types of assignments within always blocks, with

subtly different behaviors.

Blocking assignment: evaluation and assignment are immediate

always @ (a or b or c)
begin
1. Evaluate a | b, assign result to x
x = a | b;
2. Evaluate a^b^c, assign result to y
y = a ^ b ^ c;
z = b & ~c;
3. Evaluate b&(~c), assign result to z
end

Nonblocking assignment: all assignments deferred until all right-hand

sides have been evaluated (end of simulation timestep)
always
begin
x <=
y <=
z <=
end

@ (a or b or c)
a | b;
a ^ b ^ c;
b & ~c;

1. Evaluate a | b but defer assignment of x

2. Evaluate a^b^c but defer assignment of y
3. Evaluate b&(~c) but defer assignment of z
4. Assign x, y, and z with their new values

Sometimes, as above, both produce the same result. Sometimes, not!

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Assignment Styles for Sequential Logic

Flip-Flop Based
Digital Delay
Line

in

D Q

q1

D Q

q2

D Q

out

clk

Will nonblocking and blocking assignments both produce

the desired result?

module nonblocking(in, clk, out);

input in, clk;
output out;
reg q1, q2, out;
always @ (posedge clk)
begin
q1 <= in;
q2 <= q1;
out <= q2;
end
endmodule

L5: 6.111 Spring 2006

module blocking(in, clk, out);

input in, clk;
output out;
reg q1, q2, out;
always @ (posedge clk)
begin
q1 = in;
q2 = q1;
out = q2;
end
endmodule

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Use Nonblocking for Sequential Logic

always @ (posedge clk)
begin
q1 = in;
q2 = q1;
out = q2;
end

always @ (posedge clk)

begin
q1 <= in;
q2 <= q1;
out <= q2;
end

At each rising clock edge, q1 = in.

After that, q2 = q1 = in.
After that, out = q2 = q1 = in.
Therefore out = in.

At each rising clock edge, q1, q2, and out

simultaneously receive the old values of in,
q1, and q2.

q1
in

D Q

clk

q2
D Q

D Q

in

out

q1 q2
D Q

out

clk

Blocking assignments do not reflect the intrinsic behavior of multi-stage

sequential logic

Guideline: use nonblocking assignments for sequential

always blocks

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11

Simulation
Non-blocking Simulation

Blocking Simulation

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Use Blocking for Combinational Logic

Blocking Behavior
(Given) Initial Condition
a changes;
always block triggered

x = a & b;
y = x | c;

abc xy
110
010
010
010

11
11
01
00

a
b

module blocking(a,b,c,x,y);
input a,b,c;
output x,y;
reg x,y;
always @ (a or b or c)
begin
x = a & b;
y = x | c;
end
endmodule

Nonblocking Behavior
(Given) Initial Condition
a changes;
always block triggered

x <= a & b;
y <= x | c;
Assignment completion

abc xy
110
010
010
010
010

11
11
11
11
01

Deferred

x<=0
x<=0, y<=1

module nonblocking(a,b,c,x,y);
input a,b,c;
output x,y;
reg x,y;
always @ (a or b or c)
begin
x <= a & b;
y <= x | c;
end
endmodule

Nonblocking and blocking assignments will synthesize correctly. Will both

styles simulate correctly?

Nonblocking assignments do not reflect the intrinsic behavior of multi-stage

combinational logic

While nonblocking assignments can be hacked to simulate correctly (expand

the sensitivity list), its not elegant

Guideline: use blocking assignments for combinational always blocks

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13

The Asynchronous Ripple Counter

Count [3:0]
A simple counter architecture

uses only registers

(e.g., 74HC393 uses T-register and
negative edge-clocking)
Toggle rate fastest for the LSB

but ripple architecture leads to

large skew between outputs

Count[0]

D Q
Q

D Q
Q

Count[1]

D Q
Q

Count[2]

Count[3]

D Q
Q

Clock
D register set up to
always toggle: i.e., T
Register with T=1
Skew

Count [3]
Count [2]
Count [1]
Count [0]
Clock

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The Ripple Counter in Verilog

Single D Register with Asynchronous Clear:
module dreg_async_reset (clk, clear, d, q, qbar);
input d, clk, clear;
output q, qbar;
reg q;
always @ (posedge clk or negedge clear)
begin
if (!clear)
q <= 1'b0;
else q <= d;
end
assign qbar = ~q;
endmodule

Count [3:0]
Count[0]

Count[1]

Count[2]

D Q

D Q

D Q

D Q

Count[3]

Countbar[3]

clk

Countbar[0]

Countbar[1]

Countbar[2]

Structural Description of Four-bit Ripple Counter:

module ripple_counter (clk, count, clear);
input clk, clear;
output [3:0] count;
wire [3:0] count, countbar;
dreg_async_reset bit0(.clk(clk), .clear(clear), .d(countbar[0]),
.q(count[0]), .qbar(countbar[0]));
dreg_async_reset bit1(.clk(countbar[0]), .clear(clear), .d(countbar[1]),
.q(count[1]), .qbar(countbar[1]));
dreg_async_reset bit2(.clk(countbar[1]), .clear(clear), .d(countbar[2]),
.q(count[2]), .qbar(countbar[2]));
dreg_async_reset bit3(.clk(countbar[2]), .clear(clear), .d(countbar[3]),
.q(count[3]), .qbar(countbar[3]));
endmodule
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Simulation of Ripple Effect

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Logic for a Synchronous Counter

Count (C) will retained by a D Register

Next value of counter (N) computed by combinational logic
C3
0
0
0
0
1
1
1
1

C2
0
0
1
1
0
0
1
1

C1
0
1
0
1
0
1
0
1

N3
0
0
0
1
1
1
1
0

N2
0
1
1
0
0
1
1
0

N1
1
0
1
0
1
0
1
0

C3
N1

C1 0

N2

C1 1

C2

C2

C3
N3

C1 0

C2
C1

N1 := C1

D Q

N2 := C1 C2 + C1 C2
:= C1 xor C2

C3

C2
D Q

C3
D Q

CLK

N3 := C1 C2 C3 + C1 C3 + C2 C3
:= C1 C2 C3 + (C1 + C2 ) C3
:= (C1 C2) xor C3
From [Katz05]
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The 74163 Catalog Counter

Synchronous Load and Clear Inputs

Positive Edge Triggered FFs

Parallel Load Data from D, C, B, A

P, T Enable Inputs: both must be asserted

to enable counting

Ripple Carry Output (RCO): asserted when

counter value is 1111 (conditioned by T);
used for cascading counters

Synchronous CLR and LOAD

If CLRb = 0 then Q <= 0
Else if LOADb=0 then Q <= D
Else if P * T = 1 then Q <= Q + 1
Else Q <= Q

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7 P
10 T 163
15
2 CLK RCO
6
5
4
3

D
C
B
A

LOAD

CLR

QD
QC
QB
QA

11
12
13
14

74163 Synchronous
4-Bit Upcounter

18

Verilog Code for 163

Behavioral description of the 163 counter:

module counter(LDbar, CLRbar, P, T, CLK, D,
count, RCO);
input LDbar, CLRbar, P, T, CLK;
input [3:0] D;
output [3:0] count;
output RCO;
reg [3:0] Q;
always @ (posedge CLK) begin
if (!CLRbar) Q <= 4'b0000;
else if (!LDbar) Q <= D;
else if (P && T) Q <= Q + 1;
end

6
5
4
3

D
C
B
A

LOAD

CLR

QD
QC
QB
QA

11
12
13
14

priority logic for

control signals

assign count = Q;
assign RCO = Q[3] & Q[2] & Q[1] & Q[0] & T;
endmodule

L5: 6.111 Spring 2006

7 P
10 T 163
15
2 CLK RCO

Introductory Digital Systems Laboratory

RCO gated
by T input

19

Simulation

Notice the glitch on RCO!

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Output Transitions

Any time multiple bits

change, the counter output
needs time to settle.

Even though all flip-flops

share the same clock,
individual bits will change
at different times.

Clock skew, propagation

time variations

Can cause glitches in

combinational logic driven
by the counter

The RCO can also have a

glitch.

Figure by MIT OpenCourseWare.

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Cascading the 74163: Will this Work?

bits 0-3

VDD
T

QA QB QC QD

163

bits 4-7

CL LD

RCO

DA DB DC DD

bits 8-11
T

QA QB QC QD

163
CL LD

RCO

DA DB DC DD

QA QB QC QD

163

CL LD

RCO

DA DB DC DD

VDD
CLK

163 is enabled only if P and T are high

When first counter reaches Q = 4b1111, its RCO goes high

for one cycle

When RCO goes high, next counter is enabled (P T = 1)

So far, so good...then whats wrong?

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Incorrect Cascade for 74163

Everything is fine up to 8b11101111:
VDD

1 1 1 1
T

QA QB QC QD

163

CL LD

RCO

0 0 0 0

0 1 1 1
T

QA QB QC QD

163

CL LD

DA DB DC DD

RCO

QA QB QC QD

163

CL LD

DA DB DC DD

RCO

DA DB DC DD

VDD
CLK

Problem at 8b11110000: one of the RCOs is now stuck high for 16 cycles!
VDD

0 0 0 0
T

QA QB QC QD

163

CL LD

RCO

DA DB DC DD

0 0 0 0

1 1 1 1
T

0
P

QA QB QC QD

163
CL LD

RCO

DA DB DC DD

QA QB QC QD

163

CL LD

RCO

DA DB DC DD

VDD
CLK
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Correct Cascade for 74163

Master enable
P

RCO

T
CL LD

QA QB QC QD

DA DB DC DD

P input takes the master enable

T input takes the ripple carry

QA QB QC QD
RCO

T
CL LD

DA DB DC DD

assign RCO = Q[3] & Q[2] & Q[1] & Q[0] & T;

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Summary

Use blocking assignments for combinational

always blocks

Use non-blocking assignments for sequential

always blocks

Synchronous design methodology usually used in

digital circuits
Single

global clocks to all sequential elements

Sequential elements almost always of edge-triggered
flavor (design with latches can be tricky)

Today we saw simple examples of sequential

circuits (counters)

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