UNIT - VIII
The AVR RISC microcontrollers architecture
Introduction:
The acronym AVR has been reported to stand for Advanced Virtual RISC and also for the
chip's designers Alf-Egil Bogen and Vegard Wollan RISC who designed the basic
architecture at the Norwegian Institute of Technology.
RISC stands for Reduced Instruction Set Computer.
CPU design with a reduced instruction set as well as a simpler set of instructions (like for
example PIC and AVR)
An AVR Micro controller is Family of RISC Microcontrollers from Atmel.
There are multiple architectures
RISC (Reduced Instruction Set Computer)
CISC (Complex Instruction Set Computer)
Reduced Introduction Set Computer (RISC):
Till 1980 Trend was to build increasingly complex CPUs with complex set of instructions like
(CISC)
(RISC)
Instruction execute in single cycle
Architecture which reduces the chip complexity by
simpler processing instructions.
RISC architecture CPUs capable of executing only a very limited (simple) set of instructions.
In RISC Approach
Processors only use simple instructions that can be executed within one clock cycle. Here
the complex instruction MULT divided into three separate commands as follows
LOAD A,2:3
LOAD B,5:2
PROD A,B
STORE 2:3, A
Single Cycle Execution
Reduced Instruction Set Computers Advantages
Fast Execution of Instructions due to simple instructions for CPU.
RISC chips require fewer transistors, which makes them cheaper to design and
produce.
Emphasis on software
Single-clock, reduced instruction only
Register to register: LOAD" and "STOREare independent instructions
Spends more transistors on memory registers
AVR Microcontroller
The AVR is a Harvard architecture CPU.
Harvard Architecture
Computer architectures that used physically separate storage and signal pathways for their
instructions and data.
CPU can read both an instruction and data from memory at the same time that makes it
faster.
Von Neumann architecture
CPU can Read an instruction or data from/to the memory. Read, Write can`t occur at the
same time due to same memory and signal pathway for data and instructions.
Features of AVR Microcontrollers
A series of 8-bit RISC microcontrollers from Atmel.
All AVR microcontrollers share same instruction set and a basic CPU (Harvard)
architecture.
It has 32 8-Bit general purpose registers.
Mostly instruction Execute in Single clock cycle, which makes it faster among 8 bit
microcontrollers.
AVR was designed for efficient execution of compiled C code.
AVR is a family of 8-bit microcontrollers with a large range of variants differing in:
- Size of program-memory (flash)
- size of EEPROM memory
- number of I/O pins
- number of on-chip features such as UART and ADC
Smallest microcontroller is the ATTiny11 with 1k flash ROM, no RAM and 6 I/O pins.
Large such as the ATMEGA128 with 128k flash, 4KB RAM, 53 I/O pins and lots of onchip features.
AVR family architecture
AVR family architecture consists of
Registers
Instruction Set
I/O ports
Memory (flash & RAM & ROM)
CPU
1. Registers: Two types of registers, GERNEL purpose & SPECIAL purpose registers
a) GERNEL purpose
32 general purpose registers having storage capacity of 8-Bits Named as R0, R1, R2
to R31. Register 0 to 15 & 16 to 31 are different. They can store both Data & Addresses.
b) SPECIAL purpose: There are Three SPECIAL purpose registers
Program counter
Stack Pointer
Status Register
Pointer Register
Three 16-bit address register pairs of registers 26 to 31 have extra meaning in AVR
assembly. X (r27:r26), y (r29:r28), z (r31:r30).
Status Register (SREG) that contains
It is 8-bit long each bit has a different meaning.
I
I
T
H
S
V
N
:
:
:
:
:
:
Global Interrupt Enable/Disable Flag, SREG7
Transfer bit used by BLD and BST instructions, SREG6
Half Carry Flag, SREG5
For signed tests Instruction Set, SREG4
Two's complement overflow indicator, SREG3
Negative Flag, SREG2
Z
C
: Zero Flag, SREG1
: Carry Flag, SREG0
Stack Pointer (SP)
16-bit stack pointer (SP) holds address in data space of area to save function call
information.
AVR Register Architecture
Memory:
There are two separate memories
o Program Memory (Flask Memory)
o Data Memory
Program Memory (Flask Memory)
o 2K Bytes of flash memory
o 128 Bytes of In-System Programmable EEPROM, program memory holds
interrupt function addresses,
o 16 bit and double word (32 bit) Opcode, and static data tables
Data Memory
Used for data and is separate from the program memory.
128 Bytes of SRAM
Register reassigned the 32 Data Space addresses (00 - 1F),
I/O memory space contains 64 addresses for CPU peripheral functions such as: control
registers, Timer/Counters, A/D converters and other I/O functions. I/O memory can be
accessed directly or as the Data Space locations those of the Register File, 20 - 5F.
Stack is effectively allocated in the general data SRAM, and consequently the stack size is
only limited by the total SRAM size and the usage of the SRAM.
AVR Instruction SET
All Instructions (with a few exceptions) are 16 Bits Wide, Most Instructions are Executed in
One Clock Cycle
118 Powerful Instructions Most Single Clock Cycle Execution, All arithmetic operations are
done on registers R0 - R31. Mostly instructions take one cycle for execution.
ADD Rd,Rr
Rd: Destination (and source) registers in the Register File
Rr: Source register in the Register File
There
o
o
o
o
are four categories of Instructions in AVR Machine
Arithmetic and logic
Data Transfer Instructions
Program Control Instructions / Branch, jump
Bit manipulation or Bit Set/Test Instructions
Arithmetic and logic
Arithmetic instructions and their corresponding nemonics are given in table.
a+b
a-b
a++
a--
ADD
SUB
INC
DEC
a&b
a|b
-a
a=0
AND
OR
NEG
CLR
Data Transfer Instructions:
Data Transfer instructions and their corresponding nemonics are given in table.
reg1=reg2
MOV
reg=17
LDI
reg=mem
LDS
reg=*mem
LD
mem=reg
STS
*mem=reg
ST
periperal
IN
peripheral
OUT
heap
PUSH
heap
POP
Bit manipulation or Bit Set/Test Instructions
Bit manipulation or Bit Set/Test Instructions and their corresponding nemonics are given in
table.
a<<1
LSL
a>>1
LSR,
ROL,
(not avail. In
C)
ROR
Status bits
No op.
SEI,
CLI,
CLZ...
NOP
Program Control Instructions / Branch, jump:
The jump instruction syntax is given below
The conditional jump instruction syntax is given below
The switch/ case instruction syntax is given below
The AVR for instruction syntax is given below
