ECE 269
VLSI System Testing
Krish Chakrabarty
Delay Fault Testing (I)
ECE 269
Krish Chakrabarty
Delay Faults
Affect propagation delay of the
circuit, circuit fails at high
speeds
More important for high-speed
circuits
Gate delay fault (GDF): slow 1to-0 or 0-to-1 transition at a gate
output
Path delay fault (PDF): exists a
path from a primary input to
primary output that is slow to
propagate a 0-to-1 or 1-to-0
transition
Delay
Faults
1
1
Gate delay fault
(transition-delay fault)
0
0
1
Transition faults:
Two faults per gate; slow-to-rise and slow-to-fall.
Tests are similar to stuck-at fault tests. For example, a line is initialized to 0 and
then tested for s-a-0 fault to detect slow-to-rise transition fault.
Models spot (or gross) delay defects.
1
1
Path delay fault
0
1
Path-Delay Faults:
Two PDFs (rising and falling transitions) for each physical path.
Total number of paths is an exponential function of gates. Critical paths,
identified by static timing analysis (e.g., Primetime from Synopsys), must be
tested.
Types of GDFs
Gross GDFs (G-GDF): gate delay defect size is
greater than system clock period
DFs in all paths going through faulty gate, hence
catastrophic
Also called transition faults (TFs)
Small GDFs (S-GDF): delay defect size is smaller
than system clock period
Detectable if causes PDF in at least one path through
the gate
Other Delay Fault Models
Segment-delay fault -- A segment of an I/O path is assumed to have large delay
such that all paths containing the segment become faulty.
Transition fault -- A segment-delay fault with segment of unit length (single gate):
Two faults per gate; slow-to-rise and slow-to-fall.
Tests are similar to stuck-at fault tests. For example, a line is initialized to 0 and then tested for
Models spot (or gross) delay defects.
Line-delay fault A transition fault tested through the longest delay path. Two
faults per line or gate. Tests are dependent on modeled delays of gates.
s-a-0 fault to detect slow-to-rise transition fault.
Gate-delay fault A gate is assumed to have a delay increase of certain amount
(called fault size) while all other gates retain some nominal delays. Gate-delay
faults only of certain sizes may be detectable.
Circuit Delays
Switching or inertial delay is the interval between input change
and output change of a gate:
Depends on input capacitance, device (transistor) characteristics and output
capacitance of gate.
Also depends on input rise or fall times and states of other inputs (secondorder effects).
Approximation: fixed rise and fall delays (or min-max delay range, or single
fixed delay) for gate output.
Propagation or interconnect delay is the time a transition takes
to travel between gates:
Depends on transmission line effects (distributed R, L, C parameters, length
and loading) of routing paths.
Approximation: modeled as lumped delays for gate inputs.
Delay Test Definition
A circuit that passes delay test must produce
correct outputs when inputs are applied and
outputs observed with specified timing.
For a combinational or synchronous sequential
circuit, delay test verifies the limits of delay in
combinational logic.
Delay test problem for asynchronous circuits is
complex and not well understood.
Digital Circuit Timing
Input
Signal
changes
Synchronized
With clock
Outputs
Comb.
logic
Transient
region
Inputs
Output
Observation
instant
Clock period
time
Circuit Outputs
Each path can potentially produce one signal transition at the output.
The location of an output transition in time is determined by the delay of
the path.
Clock period
Final value
Initial value
Fast transitions
Slow transitions
time
Initial value
Final value
Event Propagation Delays
Single lumped inertial delay modeled for each gate
PI transitions assumed to occur without time skew
Path P1
1
13
P2
0
0
3
2
246
P3
5
Singly-Testable Paths
(Non-Robust Test)
The delay of a target path is tested if the test propagates a transition via
path to a path destination.
Delay test is a combinational vector-pair, V1,V2, that:
Produces a transition at path input.
Produces static sensitization -- All off-path inputs assume noncontrolling states in V2.
dont
care
V1 V2
Off-path inputs
V1 V2
Target
path
Static sensitization guarantees a test when the target path is the
only faulty path. The test is, therefore, called non-robust. It is a test
with minimal restriction. A path with no such test is a false path.
11
Robust Test
A robust test guarantees the detection of a delay fault of the
target path, irrespective of delay faults on other paths.
A robust test is a combinational vector-pair, V1, V2, that
satisfies following conditions:
Produce real events (different steady-state values for
V1 and V2) on all on-path signals.
All on-path signals must have controlling events
arriving via the target path.
A robust test is also a non-robust test.
Concept of robust test is general robust tests for other fault
models can be defined.
12
Enhanced-Scan Test
PI
Apply a transition at
the inputs (PIs/states)
of a combinational
circuit
Insert hold latch &
hold signal
Generate any arbitrary
pattern-pair
Combinational
PO
circuit
SCANOUT
CK TC
HL
SFF
HL
SFF
HOLD
SCANIN
CK TC
CK: system clock
TC: test control
HOLD: hold signal
SFF: scan flip-flop
HL: hold latch
Scan-Based Transition Delay Test
(Normal Scan)
Transition Test
SI1
Pattern pair (V1, V2)
V1 Initialization pattern
V2 Launch pattern
Capture result
SI2
SO1
01
SO2
SOn
Scan-based Transition Test
Shift-in (Initialization pattern)
Launch a transition
Capture result
SIn
Shift-out contents
Circuit Under Test
Launch-off-Shift (LOS) and launch-off-capture (LOC) are the two most widely used
transition fault test methods.
Normal-Scan Test
Apply a V1->V2 transition at the inputs
(PIs/states) of a combinational circuit
Normal full-scan circuits
V1 states serially shifted in
V2 states generated by
PI
PO
Combinational
circuit
CK TC
SCANOUT
SFF
(A) one-bit scan shift of V1
(B) apply V1 in normal mode
SFF
SCANIN
CK TC
CK: system clock
TC: test control
SFF: scan flip-flop
No additional hold latches, but pattern-pair not arbitrary
Normal-Scan Test (Launch-onShift)
combinational circuit
SCANOUT
(A) Shift in 1 bit after scan in of V1 in the following slowclock cycle (TC=0)
(B) V2 is the output of the comb. logic
CK TC
SFF
SFF
CK TC
V2 applied
V1 scan-in
Slow clock
(A) TC
(B) TC
Scan mode
Scan mode
Result latched
Generate
V2
Slow clock
period
normal
mode
SCANIN
Result scan-out
Rated
clock
period
Slow clock
normal
Scan mode
mode
Scan mode
Launch-on-Shift (LOS)
Transition launched in last shift
cycle
Scan enable must switch atspeed
Launch path is scan path more
controllable
e.g. V1 = 01000101
SCANIN
combinational circuit
IC: Initialization cycle
LC: Launch cycle
CC: Capture cycle
V2 = 10100010
CC
LC
IC
SCANOUT
CK
TC
V1 applied
V2 applied Transition
captured
Next V1
Launch-on-Capture (LOC)
Transition launched from
functional path
Scan enable does not have to
switch at-speed
Functional launch path
SCANIN
SCANOUT
combinational circuit
Less controllable
LC
IC
CC
CK
TC
V1 applied
V2 applied Transition
captured
Next V1
