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AFDX networks
By: J. Javier Gutirrez ([email protected])
Computers and Real-Time Group, University of Cantabria
ArtistDesign Workshop on Real-Time System Models for
Schedulability Analysis
Santander, 7-8 February 2011
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By: J. Javier Gutirrez
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Introduction to AFDX networks
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AFDX (Avionics Full Duplex Switched Ethernet) is a
communications network defined in the ARINC-664, Part 7
standard:
point to point full duplex Ethernet links (redundant)
special purpose switches with preconfigured routing
two main types of communication ports:
- Sampling Port: the arriving message overwrites the current
message stored in the buffer
- Queueing Port: the arriving message is appended to a FIFO queue
UDP/IP protocol is used for transmission
traffic regulation is made in transmission via Virtual Links
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Traffic regulation in AFDX
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Each virtual link (VL) is characterized by two parameters:
the largest Ethernet frame (Lmax): a value in bytes that can be
transmitted on the VL
the Bandwidth Allocation Gap (BAG):
- the minimum interval in milliseconds between Ethernet frames
transmitted on the VL
- a power of 2 value in the range [1,128]
Each virtual link has a FIFO queue for all the fragmented packets:
the same VL can be shared by several ports, tasks or partitions
- It can cause a poor schedulability of the system
there is no way to prioritize messages on a VL
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Maximum jitter
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The maximum allowed jitter on each VL at the output of the end
system should comply with both of the following formulas:
( ( 20 + Lmax i ) 8 )
i { set of VLs }
MaxJitter 40s + ------------------------------------------------------------------------N bw
MaxJitter 500s
Nbw is the speed of the Ethernet link in bits per second
40 s is the typical minimum fixed technological jitter
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Ethernet frame
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64 bytes
7 bytes
1 byte
6 bytes
Start
Destination
Preamble Frame
Delimiter Address
6 bytes
Source
Address
46 bytes
2 bytes
Type
(0x800
IP V4)
IP
Structure
20 bytes
UDP
Structure
4 bytes
AFDX Payload
1 to 17 bytes
Padding
0 to 16
SN
1
Frame
Check
Seq
12 bytes
Inter Frame Gap
8 bytes
1518 bytes
6 bytes
1 byte
Start
Destination
Preamble Frame
Delimiter Address
7 bytes
6 bytes
Source
Address
2 bytes
Type
(0x800
IP V4)
1500 bytes
IP
Structure
20 bytes
UDP
Structure
AFDX Payload
1471 bytes
4 bytes
Frame
SN
Check
1
Seq
12 bytes
Inter Frame Gap
8 bytes
Lmax should be in the interval [64,1518]
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Sub-Virtual Links
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A virtual link can be composed of a number of Sub-Virtual Links
Each Sub-VL has:
a dedicated FIFO queue
a round robin algorithm working over IP fragmented packets
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Latency in the transmission
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If fragmentation is not required and the messages are produced at
a frequency that is equal to or lower than the BAG of the VL:
MaxLatency BAG + MaxJitter + L T
LT is the technological latency in the transmission (it should be
lower than 150s).
If fragmentation is required or messages are produced in bursts,
the latency for packet p (with p-1 packets waiting in the VL FIFO
queue):
MaxLatency ( p ) p BAG + MaxJitter + L T
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AFDX switch
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Transmissions to or from the switch are made using the full
capacity of the physical link
Packets are delivered in a store and forward way:
the hardware latency of the switch should be taken into account
A new source of jitter appears in the FIFO queue where packets
should wait to be sent to the destination end system
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Latency in the reception
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Once a message is completely received, it is enqueued at the
corresponding AFDX port
it could potentially overflow
The technological latency of the end system in reception, LR,
should be lower than 150s
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Modelling
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The model is similar to the one for the analysis of tasks
We consider two types of messages:
Synchronized:
- the release times of these messages are relative to a general and
common reference of time
- an offset to represent the interval between the start of the MAF
(Major Frame) and the earliest release of the message
Non-synchronized: messages can be released at any time
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Modelling (contd)
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Different types of parameters to model AFDX communication:
message stream parameters
b
b
b
b
- Mi, pi, Npi, Ni, M i , p i , Np i , N i , Ti, i, Ji, Source(i), Li, Lib
VL parameters
- BAGj, Lmaxj, SourcePorts(VLj), DestinationPorts(VLj)
hardware parameters
- Nbw, LT, LTmin, JTech, LR, L R , L S
Ethernet frame and protocol parameters
- OEth, OProt, Nmin
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Latency Model
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SENDING END SYSTEM
RECEIVING END SYSTEM
SWITCH
CSend
LVL
AFDX API
Ethernet
Hardware
LTr
LSW
LTr
LRec
CReceive
Ethernet
Hardware
AFDX API
Physical Links
5 steps in the communication process
2 contention points: queueing in the sending end system (LVL)
and queueing in the switch (LSW)
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AFDX in MAST-2
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Processing Resources
- Network: AFDX_Link
- Network_Switch: AFDX_Switch
Scheduling Policy
- AFDX_Policy
Scheduling Parameter
- AFDX_Virtual_Link
Schedulable Resource
- Communication_Channel
Event Handler
- Message_Event_Handler: Message_Delivery, Message_Fork
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AFDX in MAST-2: Network
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AFDX in MAST-2: Scheduling Policy
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AFDX in MAST-2: Scheduling Policy
(contd)
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AFDX_Policy:
messages are scheduled through virtual links
messages are scheduled in FIFO order when they are originated
at an AFDX switch
This policy may only be assigned to a scheduler that has an
AFDX_Link as its host
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AFDX in MAST-2: Scheduling
Parameters
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AFDX in MAST-2: Schedulable
Resource
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AFDX in MAST-2: Schedulable
Resource (contd)
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DEFAULT_COMMUNICATION_CHANNEL:
used for communications through AFDX links when the
message is originated at an AFDX switch
the implicit scheduling policy is FIFO ordering for the messages
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AFDX in MAST-2: Switch
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It is capable of delivering messages arriving at an input port to one
or more output ports
The delivery operations are specified through special-purpose
message event handlers
MAST does not require to define the network topology (it is implicit
in the end-to-end-flow)
It is assumed a shared memory switch in which messages do not
need to be copied
Contention occurs when several messages need to be sent to the
same output port, in which case a queue is used at the output port
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AFDX in MAST-2: Switch (contd)
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AFDX in MAST-2:
Message_Event_Handler
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Example: sending a message through a
switch
CPU1
Message
Task1
Task1
Step:
Regular_P
Thread
Fixed_P_P
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SWITCH
M1
Step:
AFDX Link
Comm_Chan
AFDX Policy
MD1
Message_E_H:
Switch
By: J. Javier Gutirrez
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CPU2
Task2
M2
Step:
AFDX Link
Default_C_C
FIFO
Task2
Step:
Regular_P
Thread
Fixed_P_P
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