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Lecture-44 Strobed Output Mode

This is a device initiated p controlled I/O transfer. A p may be communicating other time. In the case of CPU initiated polled I/O transfer. Polling of I/O service request flags monopolizes a significant amount of a microprocessor time. This reduces system through put the total useful information processed or communicated during a specified time period therefore, it is advantageous, in term of increasing throughput as well as reducing program complexity, if an I/O device demands service directly from the microprocessor. Interrupts provide this capability essentially an interrupt is a subroutine call initiated by external hardware device and is asynchronous meaning it can be initiated at any time without reference to the system clock however, the response to an interrupt is directed or controlled by the p. A simple structure that allows a

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67 views5 pages

Lecture-44 Strobed Output Mode

This is a device initiated p controlled I/O transfer. A p may be communicating other time. In the case of CPU initiated polled I/O transfer. Polling of I/O service request flags monopolizes a significant amount of a microprocessor time. This reduces system through put the total useful information processed or communicated during a specified time period therefore, it is advantageous, in term of increasing throughput as well as reducing program complexity, if an I/O device demands service directly from the microprocessor. Interrupts provide this capability essentially an interrupt is a subroutine call initiated by external hardware device and is asynchronous meaning it can be initiated at any time without reference to the system clock however, the response to an interrupt is directed or controlled by the p. A simple structure that allows a

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Osy Osy
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Lecture-44

Strobed output mode


Fig illustrate on 8255 set up with both port A & B as mode1 output.
The mode word to set up this condition is also given in the figure.

Output control definitions:


The functions of the PORT C lines as determined by the mode are
described below.
PC7

Output buffer full PORT A when data is written into port A by the
CPU, this signal goes low to indicate that data is available at port A.
PC6

Acknowledge PORT A. When this signal goes low it indicates that an


external device has accepted the data that has written output A. This
signal going low, will result the

signal back HIGH.

PC5 INRA:
Interrupt request PORT A. This bit is set HIGH when

goes

HIGH after a data transfer an d if its interrupt enable PORT C bit


when set. This signal can used as a CPU interrupt to indicate that
been accepted by an external device. This means that the CPU can
now load the next output word into port A.
PC1

output buffer full PORT B.

PC2

Acknowledge request PORT B.

PC0 INTRB interrupt request PORT B.


The internal INTE f/f is set by PC2.

PORT C bits 4&5 are not used as control or status lines and therefore
they can be used as either input or output. Their direction is
determined by bit 3 of the control word.

The basic output timing diagram is a shown in fig. Whenever 8255 is


programmed in mode 1 (output) the INTR signal goes HIGH if internal

INTE f/f is set be the corresponding bit. If CPU interrupt is enabled, it


interrupt the

. The CPU, which has been interrupted by INTR

interrupt, writes (output) the data to port A or B; this setting the


corresponding

line to go low, indicating that data is available. It

also reset the INTR line. When the external device has read the data,
it acknowledges it by sending
causes
together with

low. The trailing edge of

to go HIGH. The empty output buffer (


high and

high)

high reinitiates the INTR (

INTR=high) and the complete process is recycled. When CPU


accepts these in the OBF the can also by the CPU. If it is high the
buffer is empty and of data can be written to 8255.

Data transfer from system 1

to another system 2 is possible

through through 8255 ports programmed in strobed mode. The two


systems, each having 8255 can be connected as shown in fig. below:

The output and input ports of the two systems, acting as data lines,
are connected. The OBF of system 1 is connected to STB of system
2. The IBF of system 2 is connected to ACK of system 1 through
inverter. The interrupt outputs are connected to any interrupt of the
system. Here, they are connected to RST7.5.
The flow charts for data transfer in this manner are given below:

The waveforms for during data transfer are shown in figure below:

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