MOSFET DEVICE PhYSICS

AND OPERATION
Rajaram Sivasubramanian
Associate Professor
ECE Department
Thiagarajar College of Engineering
Madurai-15 ([email protected])

What is Microelectronics

So How small is small in the DSM

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Revolution and Evolution in Electronics

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Happy Scaling- ongoing or Over?

Contents
Introduction
The MOS Capacitor
Interface Charge
Threshold Voltage
MOS Capacitance

Basic MOSFET Operation

Basic MOSFET Modeling
Simple Charge Control Model
The Meyer Model
Velocity Saturation Model

Capacitance Models
Comparison of Basic MOSFET Models

How Thresholding Occurs

VG < VT :

G (+)
0V S

D
0.1V

2F

p substrate NB

Surface doping
concentration

NB

Bulk concentration

xj
Junction
depth

As gate voltage increases, the E field

pushes holes down creating a widening
depletion layer and exposing negative ionic
charge to balance the positive Gate charge.

2F

NMOS
NS

2/8

kT NB
Ln
q
ni

With 2F F across dep

layer, the surface is
as negative as the
Bulk is positive, which
conveniently defines
V T.

VG > VT :
Surface reaches equi-potential (with 2F F
across dep layer) and electrons now flow in
from S to form a conducting film or
channel on the silicon surface. As VG
increases further, dep layer does not grow
wider, but balancing charge comes from a
strengthening of the channel on the
surface.

In SPICE, 2F F is PHI , typically 0.8V.

THRESHOLD AND BODY EFFECT

Before Discussing on Device Modeling

Let us figure out:

(1)Linear / Non-linear system?
(2)Linear region (of operation) / Saturation region?
(3)Large signal / Small signal ?

Then, a brief introduction to SiGe HBT technology.

Linear and Non-Linear

A linear System :
A linear system prohibits the feature of
Y = A X
That is, the output Y of a system is just related
to its input X variables with a certain relationship
of A (Amplification factor).

We neglect the singularity property of the system.

If there is no relationship existed among

the input variables, they are independent.
In mathematical expression:
Xis are independent, if only ai=0 to make

ai xi = 0

(summation)

Xjs are independent variables.

Linear (-operation) Region for a transistor :

The operation region where
the output of the transistor is
linearly proportional to its input signal.
However, the definitions of input and output
are related to the case what we investigate on.

Id
linear

saturation vgs
3
vgs2
vgs1
Vds

Id vs. Vds?
Id vs. Vgs?

Non-linear Case:
(1) Current is a function of voltage I(V) = a0+a1 V+a2 V2+()
(2) The drain current of a MOSFET :

VDS
W
I D (VGS , VDS ) n C ox VGS VT VDS

L
2

Discussion:
(1) if VDS >> 1, pinch-off, ID saturated. (not this form!)
(2) if VDS << 1 approximation further.
(3) under VDS << 1, ID vs. VGS also linear!

In general, (in an analog viewpoint)

BJT a current-to-current converter;
MOS a voltage-to-current converter.
IC

IG=0
X

IB
I

VG

ID

Large Signal or Small Signal

1 Vth = 0.0259 (V) = 26 mV

Another Viewpoint of Small signal or Linear operation:

-- by Power Compression
[Ex. LNA]
(ideal)
Pout (dBm)
(real)
Pin

Amp

Pout

Pin (dBm)

Device Modeling
It is extremely important to have a valid device modeling & simulation
design prior to the device fabrication b/c technology & design iteration
are expensive and post fabrication tuning is not a fun.
Device modeling actually describes the principal methods of representing
and analyzing devices (modern solid-state) .
The utmost purpose of any device modeling is to
Cuts Cost (economical)
Cuts development time (faster manufacturing)
Accurate designing
cutting edge concept (reduced size).
Minimize system complexities

Device Modelling Classification

Diode device Modeling

Transistor device Modeling

Semiconductor device Modeling (ICs)

Diode device Modeling

Diode Modeling: refers to the mathematical models used to approximate the

actual behavior of real diodes to enable calculations and circuit analysis.
diode's V-I curve is nonlinear (described by the Shockley diode law).
This nonlinearity complicates calculations in circuits involving diodes, so
simpler models are often required.
Diode Modeling may be categorized as
Large signal diode modeling (Non-linear): deals with any ACTIVE
components.
Shockley diode model
Diode-resistor model
Large signal diode modeling is based on either
Graphical modeling method
Piecewise linear (PWL) modeling
Mathematically idealized diode Modeling
small signal diode modeling (Linear): deals with any PASSIVE components.
Resistance, Capacitance.

Graphical modeling method

Graphical analysis is a simple way to derive
a numerical solution to the transcendental
equations describing the diode.
As with most graphical methods, it has the
advantage of easy visualization.
By plotting the V-I curves, it is possible to
obtain an approximate solution to any
arbitrary degree of accuracy.
This method plots the two current-voltage
equations on a graph and the point of
intersection of the two curves satisfies both
equations, giving the value of the current
flowing through the circuit and the voltage
across the diode.
Graphical method is often time consuming
and is impractical for complex circuits .

A transcendental function is a function that does not satisfy a polynomial equation whose coefficients
are themselves polynomials, in contrast to an algebraic function, which does satisfy such an equation.

Piecewise linear modeling

Piecewise linear (PWL) modeling takes a function

f(t) and breaks it into several linear segments.
The graph shows how a curve can be
approximated by three linear segments, forming a
three-segment PWL model.
PWL method is used to approximate the diode
characteristic curve into linear segments.
This enables us to substitute the real diode for an
ideal diode, a voltage source and a resistor.
The figure shows a real diode V-I curve being
approximated by a two segment PWL model.
Typically the sloped line segment would be chosen
tangent to the diode curve at the Q-point.
Then the slope of this line is given by the
reciprocal of the small-signal resistance of the
diode at the Q-point.

piecewise linear approximation of a curve

A piecewise linear approximation of the diode characteristic.

Mathematically idealized diode

Let us consider a mathematically idealized

diode.
In such an ideal diode, if the diode is reverse
biased, the current flowing through it is zero.
This ideal diode starts conducting at 0 V and
for any positive voltage an infinite current
flows and the diode acts like a short circuit.
The I-V characteristics of an ideal diode are
shown.

I-V characteristic of an ideal diode

Ideal diode in series with voltage source

Consider the case when we add a voltage

source in series with the diode as shown .
When forward biased, ideal diode is simply a
short circuit and when reverse biased, an open
circuit.

If the anode of the diode is connected to 0 V,

voltage at the cathode will be at Vt and the
potential at the cathode will be greater than
the potential at the anode and the diode will
be reverse biased.
In order to get the diode to conduct, voltage
at the anode will need to be taken to Vt.
This circuit approximates the cut-in voltage
present in real diodes.
The combined I-V characteristic of this circuit
is shown .

Ideal diode with a series voltage source

I-V characteristic of and ideal diode with a series voltage source

Diode with voltage source & current-limiting resistor

The last thing needed is a resistor to
limit the current, as shown with the IV characteristic.
The real diode now can be replaced
with the combined ideal diode,
voltage source and resistor and the
circuit then is modeled using just
linear elements.
If the sloped-line segment is tangent
to the real diode curve at the Q-point,
this approximate circuit has the same
small-signal circuit at the Q-point as
the real diode.

Ideal diode with a series voltage source and

resistor

I-V characteristic of an ideal diode with a series voltage source and resistor

Transistor device Modeling

Transistors are simple devices with complicated behavior.
In order to ensure the reliable operation of circuits employing
transistors, it is necessary to scientifically model the physical
phenomena observed in their operation using transistor models.
There exists a variety of different models that range in complexity
and in purpose.
Transistor models divide into two major groups:
Models for device design
Models for circuit design

Models for device design

Modern transistor has an internal structure that exploits complex
physical mechanisms.
Device design requires a detailed understanding of how device
manufacturing processes carried like Ion implantation, Impurity diffusion,
Oxide growth, Annealing, Etching affect device behavior.
Process models simulate the manufacturing steps and provide a
microscopic description of device "geometry" to the device simulator.
By "geometry" is meant not only readily identified geometrical features
such as whether the gate is planar or wrap-around, or whether the
source and drain is altered or not but also details inside the structure,
such as the doping profiles after completion of device processing.
Physical processes in the device determine its electrical behavior in a
variety of circumstances:
DC current-voltage behavior,
transient behavior (both large-signal and small-signal),
Internal variation in device response.

Models for circuit design (compact models)

Transistor models are used for almost all modern electronic design work.
Analog circuit simulators such as SPICE (Simulation Program with Integrated
Circuit Emphasis) use models to predict the behavior of a design.
LT SPICE is getting popularity too.
Most design work is related to IC designs which have a very large tool cost,
primarily for the photo masks used to create the devices, and there is a large
economic incentive to get the design working without any iterations.
Device models must include effect of various parameters on design like:
Width & length
Interdigitation
Proximity to other devices
Transient and DC current-voltage characteristics
Parasitic device capacitance
Resistance and inductance
Time delays
Temperature effects

Transistor Large signal nonlinear models

Large signal transistor models (non-linear models) fall into three
main types.
Physical models
Empirical models
Tabular models

Physical models
These are models based upon device physics, which relies on the
approximate modeling of physical phenomena within a transistor.
Parameters within these models are based upon physical properties such
as
Oxide thicknesses, Substrate doping concentrations, Carrier mobility,
etc.

Empirical models

Empirical models are based upon curve fitting, subjected to the parameter and
values which can fit describe the operation of the device (transistor).
Unlike a physical model, empirical model parameters are not based
fundamentals, they mostly depends on the fitting procedure used to find them.
Fitting procedure is key to success of these models if they are to be used to
extrapolate to designs lying outside the range of data to which the models were
originally fitted.

Empirical model of carrier scattering on

ionized impurity

Tabular models
Tabular models are based on look-up
table (LUT) form, by considering effect
of one parameter to the other.
Effect of parasitic components on
drain current
These values are indexed in reference
to their corresponding bias voltage
combinations.
Thus, model accuracy is increased by
inclusion of additional data points
within the table.
Limitation of these models is that they
work best for designs that use devices
within the table (interpolation) and are
unreliable for devices outside the table
(extrapolation).

Transistor Small-signal linear models

Small-signal or linear models are used to evaluate stability, gain,
noise and bandwidth.
A small-signal model is generated by taking derivatives of the
current-voltage curves about a bias point or Q-point.
As long as the signal is small relative to the nonlinearity of the
device, the derivatives do not vary significantly, and can be treated
as standard linear circuit elements.
Advantage of small signal models is that they can be solved
directly, while large signal nonlinear models are generally solved
iteratively, with possible convergence or stability issues.
By simplification to a linear model, the whole apparatus for solving
linear equations becomes available, for example, simultaneous
equations, determinants, and matrix theory etc.

Small-signal parameters
A transistors parameters represent its electrical properties.
Engineers employ transistor parameters in production-line testing and in
circuit design.
A group of a transistors parameters sufficient to predict circuit gain, input
impedance, and output impedance are components in its small-signal
model.
Parameters used in small-signal circuits (two ports) adopt names related to
the names of these circuits such as
Transmission parameters (T-parameters),
Hybrid-parameters (h-parameters),
Impedance parameters (z-parameters),
Admittance parameters (y-parameters), and
Scattering parameters (S-parameters).
These parameters all can be evaluated using measured scattering parameter
data.
Scattering parameters (S parameters) can be measured for a transistor at a
given bias point with a vector network analyzer.

Semiconductor device modeling

Semiconductor device modeling creates models for the behavior of the
electrical devices based on fundamental physics, such as the doping
profiles of the devices.
The intent of IC fabrication is to produce a wafer with specific
electrical & mechanical characteristics, usually in the form of
electronic circuits or chips, via some number of processing
transformations.

Why need semiconductor modeling?

semiconductor modeling is based on a computational modeling
mechanism, which is the evaluation & optimization of various
design, without resorting to costly and time-consuming trial
fabrication and measurement steps.
It may also include the creation of compact models (such as the
SPICE (Simulation Program with Integrated Circuit Emphasis)
transistor models, which try to capture the electrical behavior of
such devices but do not generally derive them from the underlying
physics.
Provides valuable insight into important physical quantities.
Shortened development cycles.
Reduced cost.
Increased quality and reliability of final products.
A important field of computational modeling related to
semiconductor manufacturing belongs to process modeling.

Semiconductor device models

Semiconductor device models can be considered in two broad
categories
Physical device models
Equivalent circuit models.
Physical device models: attempt to incorporate the physics of
device operation.
Equivalent circuit models: are based on electrical circuit analogies
representing the electrical behavior.

Physical device models

Physical device models can provide greater insight into the detailed
operation and operating conditions of semiconductor devices, but
usually based on a lengthy analysis.
Dependent on numerical techniques implemented on
computers.
Physical device models are solved using either bulk carrier transport
equations (the semiconductor equations), solutions to the
Boltzmann transport equation or quantum transport concepts.
Bulk transport solutions have satisfied most device models
Boltzmann and quantum transport solutions have provided a
strong insight into the detailed device physics.
The understanding of material properties, physical boundary
conditions (such as surface physics, contact properties and device
geometry) and device-circuit interaction are steadily improving,
allowing more intricate models to be developed.

1.1 Introduction

Simplified Model =
A vertical device +
A lateral device

1.2 The MOS Capacitor

A vertical device gives the vertical potential profile;
Gate oxide Ri = (in DC viewpoint);
The density of surface state << channel carrier.

1.2.1 Interface Charge

Flat-Band Voltage: VFB m s /q m X s E C E F /q

Work function

flat

s m qVFB
X s (E c E F )

zero bias

apply voltage = VFB

Surface potential s determines the operation regimes.

Note: potential vs. energy

(voltage)
(band diagram)
0 s 2 b

In band diagram:
positive potential
makes the band
energy level lower
at metal side.

depletion and weak inversion

s 2 b
strong inversion
s 0
accumulation
s 0
flat band

Potential Distribution

At surface :

In the bulk :

p s N a exp( s /Vth )

p(x) N a exp((x)/Vth )

n i2
ns
n po exp( s /Vth )
ps

n i2
n(x)
n po exp(xp((th )
p
(x) also satisfies the Poisson' s equation :
that is,
d 2 (x)
dx 2
where

p(x) n(x) N a

() 0.

An experimental expression of surface charges with surface potential

the surface electric field E s
Es 2

Vth s
f(
)
L Dp Vth

where the experimental function f() can be expressed as

f(u) [exp(u) u 1]

n po
Na

[exp( u) u 1]

and the debye length L Dp is

L Dp

s Vth
qN a

Q s s E s

(Gausss Law)

Surface Charges vs. Surface Potential for P-substrate

Applied Gate Voltage vs. Surface Potential

Since electric field flux continuity at the interface
s Es i Ei
Assume the insulator causes a voltage drop E i d i ,
where d i is the thickness of the dielectric layer;
(VGB E i d i VFB ) s
VGB VFB s ( s E s )/Cox

Where Cox is the insulator capacitance per unit area

and
Qs = - s E s

1.2.2 Threshold Voltage

* As VG = VT s = 2b
Which VT is called as the threshold voltage.
* Correspondingly, the induced charges
is assumed to be still less than the
depletion charges QdT.
* The equivalent electric field at the interface
becomes EsT=-QdT/s=(4qNab/s)

The threshold voltage :

4 s qN a b
VT VFB 2 b
C ox
Ci in the textbook

The threshold voltage includes body bias effect:

VT VFB 2 b

2 s qN a (2 b VB )
C ox

Threshold Voltage vs. Substrate Doping (Oxide thickness)

1.2.3 MOS Capacitance

Insulator capacitance;
Depletion capacitance;
Generation/Recombination
mechanism.
(depletion capacitance)

(free-carrier capacitance)

* Equivalent MOS Capacitance Cmos

1/Cmos = 1/Ci + 1/Cs

(in series)

where Ci and Cs are the capacitances

of the insulator and the semiconductor,
as shown below. (A = Gate Area)
Ci i

A
t ox

n po
dQs
Cso
s
Cs A

exp(

d s
Vth
Na
2f s /Vth
where
C so s

A
L Dp

s
exp( ) 1
Vth

Some important features:

Under the depletion regime, Cs = Cd;
Under the strong inversion regime,
(a) at DC / Low frequency operation:
Cmos ~ Ci, since Cs >> Ci (insulator cap.);
(b) at High frequency operation:
Cmos ~ (1/Ci + 1/Cd) -1,
since the free carriers can not
surge from the source end in time.

Typical C-V measurement:

Find the maximum
slope
according to
Fig.1.5 @ VFB.

Parameter
extraction

Parameter Extraction from C-V measurement

Gate oxide thickness, tox; (in accumulation)
Equivalent substrate doping concentration, Na;
Flat band voltage, VFB.
tox : from Cmax (either from A- or I- mode)
Na : from Cmin (from I-mode @ high frequency)
VFB : from CFB=(1/Ci+1/Cs) -1 @ V=VFB
Ex: Ci = Cmax = i A / tox.
4 s Vth N a

Na
ln
2
qd dT
ni

Solved by iteration
Or
By approximate analytical
method

Unified Charge Control Model

1.2.4 MOS Charge Control Model -- UCCM

Approximation
Subthreshold regime :
V VT
n s n o exp(
)
Vth
Above - threhold regime :
qn s Ci (V VT )

Continuous problem

Unified Charge Control Model (UCCM)

ns
qn s n o
V VT
Vth ln
Ca
no

(Byuns Equation for UCCM)

As ns = no, V=VT

where
Cd
1
Ci
(subthrehold ideality factor)
n o Vth Ca /2q
Ca ~ slightly modified from Ci

(Approximation Expression)

Therefore, in the subthreshold regime

V VT

n s n o exp
Vth
and in the strong inversion regime
1
V VT

n s 2n o ln 1 exp
Vth
2

1.3 Basic MOSFET Operation

At DC condition, the depletion region and
the neutral substrate provide isolation between
devices on the same substrate but substrate
coupling noise issue in RF circuits.
Self-aligned
Technology

Conduction
Channel
isolated by
the depletion
region

Typical Output I-V Characteristics

VSAT=VGS-VT
VDS=VSAT;
Pinch-off condition

VDS-VSAT

High-field E

1.4 Basic MOSFET Modeling:

x
y

GCA: Gradual Channel Approximation;

1-D potential profile (along the vertical direction);
valid for long-channel MOSFETs.

1.4.1 Simple Charge Control Model (SCCM)

Channel Charges
Let VGT = VGS-VT

qn s (x) Ci VGS V(x) - VT

where V(x) is the potential profile along the channel.
V(x) is derived from the MOS capacitor structure.
Drain current diffusion current drift current;
I ds Wqn s n E x (neglect the diffusion component )
W n Ci
I ds
(VGT VDS /2)VDS , for VDS VSAT VGT
L
W n Ci
2
I ds
(VGT
/2), for VDS VSAT
L

Channel Conductance gd and Transconductance gm

the channel conductance :
VGT VDS , for VDS VSAT
I d
gd
VGS
0, for VDS VSAT
VDS

and the transconductance :

VDS , for VDS VSAT
I d
gm
VDS
VGS
VGT , for VDS VSAT

where

W n Ci
L

( the transconductance parameter)

Substrate Bias Dependent Threshold Voltage:

2 s qN a (2 b VB )
VT VFB 2 b
C ox

1.4.2 The Meyer Model

Improvement : take into account the

depletion charges under the gate.

the total induced charges q s per unit area :

q s Ci VGS VFB 2 b V(x)
the depletion charges q d per unit area :
q d qN a d d 2 s qN a 2 b V(x)
Thus, the inversion charges density q i
qi qs qd
To correct (1.47) in the textbook.

(cont.)

qi = -q ns sheet charges

2ci2 (VGS VFB )

s qN a

=VT

1.4.3 Velocity Saturation Model

a) Two piece Model :
E for E E sat
(E) n
sat for E E sat

(*improvement: field-independent
mobility model included;
specially, fits for the short
channel device request.)

b) Sodini Velocity Model :

n E

(E) 1 E/2E sat

sat

for E 2E sat
for E 2E sat

c) continuous E Model :
(E)

1 E/E

m 1/m

sat

(m 2 for NMOS; m 1 for PMOS)

Substituti ng (E) into the I ds current model.

Normalized Velocity-E_Field relationship

> To include the velocity saturation model (VSM)

into the drain current model, one must change
the expression of VSAT.
> Example: In SCCM, using the two-piece model
for the drain current and the VSAT:
2
W n Ci VGT VDS VDS /2, for VDS VSAT
I ds

L
(VGT VSAT )VL , for VDS VSAT
and
2
VSAT VGT VL 1 VGT /VL 1

where

VL E SAT L LSAT / n

As VGT >> VL
Makes Ids ~ VLVGT

As VGT << VL
Makes Ids ~ (VGT)2/2

1.4.4 Capacitance Models

Large Signal : transient behavior;
Small Signal : Impedance match , AC Gain,
and frequency response;

Large Signal Behavior : Rise/Fall Times;

Stored Charges (driving capability).
Intrinsic Capacitors:
CGS, CGD, and CGB.

Ward and Dutton Capacitance Model:

> Charge conservation;
> nonreciprocal capacitance (Cij Cji)
i,j : relative terminals name
Meyer Capacitance Model:
> Charge conservation;
> reciprocal capacitance (Cij = Cji);
> intrinsic capacitances:

C GS

Q G

VGS

VGD, VGB

CGD

Q G

VGD

VGS, VGB

CGB

where
Q G the total intrinsic gate charges
depletion charges inversion charges

Q G

VGB

VGS, VGD

Meyer Capacitances under Strong Inversion

dV
in a long-channel MOSFET:
Ids W n Ci (VGT V(x))
dx

Q Gi WCi VGT V(x)dx

Let dx W n C i VGT V dV/Ids

W n Ci2

LIds
as CGS

Q G
VGS

VDS

VGT V dV 2Ci VGS VT 2 VGD VT 2

3 VGS VT VGD VT

VGD,VGB

CGD

Q G
VGD

VGS,VGB

CGB

Q G
VGB

VGS,VGD

*Note: Let VDS = VGS-VGD

CGS
CGB

2 VGT VDS
Ci 1
3 2VGT VDS

CGD

2 VGT
Ci 1
3 2VGT VDS

Meyer Capacitances in Saturation Condition

in a long-channel MOSFET:
Because
2
2 VGT VDS

C GS Ci 1
3 2VGT VDS

C GB 0

C GD

2

2
VGT

Ci 1
3 2VGT VDS

in saturation,
VGT VSAT and VDS VSAT

CGS

2
Ci
3

CGD 0
(important!!)

CGB 0

Before pinch-off (saturation)

CGS=CGD=Ci/2 (triode regime)

2/3 Ci

Meyer Capacitances in Subthreshold Condition

in a long-channel MOSFET:

C GS 0

C GD 0

C GB

Ci
1 4VGB VFB / 2

where
2 s qN a /C i body effect coefficient

1.4.5 Comparison of Basic MOSFET Models

Simple Charge Control Model
Meyers Model
Velocity Saturation Model

1.4.6 Basic Small-Signal Model

Lack of Rg and Lg effect for RF applications

1.5 Advanced MOSFET Modeling

0.13um
0.09um

0.065um

1.5.1 Modeling Approach

DIBL effect.
Leakage!

Thermionic
emission!

1.5.2 Nonideal Effects:

High-Field Effects:
Channel-Length Modulation;
Hot-Carrier Effect;
Temperature Dependence / Self-heating;
Gate bias-dependent mobility.
Short-Channel Effects:
Aspect ratio;
Drain-induced Barrier Lowering;
Gate Leakage and Effective Oxide Thickness:
Tunneling Leakage

Vertical field
dependent
mobility

DIBL Effect : Threshold voltage drop

T=85K

T=300K

1.5.3 Unified MOSFET C-V Model

* Channel Capacitance (in UCCM)

In subthreshold regime:

Ward-Dutton
Capacitance Model
Note: Cij Cji

Non-quasi-static modeling

Carrier profile (time-dependent)

t

Q.S.

Carrier profile (time-dependent)

t

N.Q.S

RF Modeling

RF Modeling - Introduction
Advances in CMOS fabrications have resulted in deep submicron
transistors with higher transit frequencies and lower noise figures
MOSFETs is attractive for high-frequency (HF) circuit design in
view of a system on-a-chip realization, where digital, mixed-signal
base-band and HF transceiver blocks would be integrated on a
single chip
other advantages offered by silicon CMOS technologies
low cost due to the volume of wafers processed and the
low power consumption feature of MOSFETs, which makes it
suitable for portable applications.

Issues

Accurate device models become crucial to correctly predict the circuit

performance
RF model with the consideration of the HF behavior of both intrinsic and
extrinsic components in MOSFETs is extremely important for achieving
accurate and predictive results in the simulation of a designed circuit
So far, most compact MOSFET models do not include the gate resistance RG.
However, the thermal noise contributed by the gate resistance should be
considered as MOS transistors approach gigahertz frequencies
the resistive and capacitive (RC) effects at the gate should be well modelled
Substrate resistance should be also considered

EQUIVALENT CIRCUIT (EC)

REPRESENTATION
OF MOS TRANSISTORS
a four terminal MOSFET can be divided into two portions:
intrinsic part : The intrinsic part is the core of the device
without including those parasitics
extrinsic part : The extrinsic part consists of all the parasitic
components

A MOSFET schematic cross section with the

parasitic components

Equivalent Circuit REPRESENTATION

OF MOS TRANSISTORS contd...
For an intrinsic device, AC small-signal currents referring to
the source of the device can be calculated by the following

where
vGSi, vDSi, and vBSi are the AC voltages at the intrinsic gate, at the
intrinsic drain, and at the intrinsic bulk (all referring to the intrinsic
source);
iGi, iDi, and iBi are thealternating currents (AC) through the
intrinsic gate, through the intrinsic drain, and through the intrinsic
bulk;
Gm, GDS, and Gmb are the transconductance, channel
conductance, and bulk transconductance of the device,
respectively

EC REPRESENTATION OF MOS
TRANSISTORS contd...
Cxyi are intrinsic capacitances between the
terminals with the following definitions

EC REPRESENTATION OF MOS
TRANSISTORS contd...

EC REPRESENTATION OF MOS
TRANSISTORS contd...
Assumptions
the components between the gate and the other
terminals can be considered as purely capacitive with
infinite resistance, so the gate current in Eq. does not
contain any conductive current component
Similarly, the components between the bulk and the
other terminals can be also considered as purely
capacitive with infinite resistance, so the bulk current in
Eq. does not contain any conductive current component
Those assumptions can usually hold for an intrinsic
MOSFET because of the very low leakage currents
through the gate to other terminals and through the bulk
to other terminals in a MOSFET

EC REPRESENTATION OF MOS
TRANSISTORS contd...
Rearranging the equation, we get

EC REPRESENTATION OF MOS
TRANSISTORS contd...
where Cm, Cmb, and Cmgb are the differences
of the transcapacitances between the drain
and the gate, between the drain and the bulk,
and between the gate and the bulk, and are

Intrinsic MOSFET

Extrinsic Capacitances
With the inclusion of those extrinsic
capacitances

Resistances in Substrate
for DC and low-frequency applications, the parasitic
resistances at the gate and substrate can be ignored
At HF, however, these parasitic resistances will
influence the device performance significantly and
they all should be modeled and included in the EC
for the device
The resistances in the substrate can be modeled by
different EC networks, such as five-resistor network,
four-resistor network proposed by Liu et al. (1997),
three-resistor network proposed by Cheng et al.
`(1998), two-resistor network by Ou et al. (1998),
and one-resistor network by Tin et al.

five-resistor network

four-resistor network

An equivalent circuit with

both intrinsic and
extrinsic components

HIGH-FREQUENCY BEHAVIOR OF MOS

TRANSISTORS AND AC SMALL-SIGNAL
MODELING
compact models for HF applications are more
difficult to develop owing to the additional
requirements of
bias dependence and geometry scaling of the
parasitic components
accurate prediction of the distortion and noise
behavior.

RF Modeling Approach
A common modeling approach for RF applications is to build
subcircuits based on the intrinsic MOSFET that has been
modeled well for analog applications The accuracy of such a
model depends on
how to establish subcircuits with the correct
understanding of the device physics in HF operation,
how to model the HF behavior of intrinsic devices and
extrinsic parasitics, and
how to extract parameters appropriately for the elements
of the subcircuit.

RF Modeling Approach condt

With added parasitic components at the gate, at the source, at
the drain, and at the substrate, these models can reasonably well
predict the HF AC small-signal characteristics of short-channel
(<0.5m) devices up to 10 GHz.
Further needed are:
improving the RF models in describing the AC characteristics
more accurately, and in
improving the prediction of noise characteristics, distortion
behavior, and non-quasi-static (NQS) behavior.

Requirements for MOSFET Modeling

for RF Applications

Like in low-frequency application, such as continuity, accuracy, and scalability of

the DC and capacitance models should be retained
The model should accurately predict bias dependence of small-signal parameters
at HF operation.
The model should correctly describe the nonlinear behavior of the devices in
order to permit accurate simulation of intermodulation distortion and high-speed
large-signal operation.
The model should correctly and accurately predict HF noise, which is important
for the design of low noise amplifiers (LNAs).
The model should include the NQS effect
The components in the developed EC model should be physics-based and
geometrically scaleable so that the model can be used in predictive and statistical
modeling for RF applications.

RF Modeling Approach condt

To achieve the above, the model for the intrinsic device should be
derived with the

normal and reverse short-channel and narrow width effects,

channel-length modulation,
drain-induced barrier lowering (DIBL),
velocity saturation, mobility degradation due to vertical electric field,
impact ionization,
band-to-band tunneling,
polysilicon depletion,
velocity overshoot,
self-heating, and channel quantization.
Also, the continuities of small-signal parameters such as
transconductance Gm, channel conductance GDS, and the intrinsic
transcapacitances must be modeled properly.

Modeling of the Intrinsic Components

The model accuracy in fittings of HF smallsignal parameters and large-signal distortion
of an RF MOSFET is basically determined by
the DC and capacitance models
the electric field need to be modeled,
the channel charge need to be modeled
the mobility need to be modeled carefully to
describe the current characteristics accurately
different physical effects can be added in the
model

Channel Charge Model

two types of charge models:
threshold-voltage (Vth)-based models - account
for the influence of some process parameters such
as oxide thickness and doping and device
parameters such as channel length and width
surface-potential (s)-based models - based on
the analysis of the surface potential that will
appear in the IV model

Mobility
Mobility is another key parameter in MOSFET modeling

MOSFET intrinsic capacitance models

categorized into two groups:

Meyer and Meyer-like capacitance models - simpler than the charge-based
models, so they are efficient and faster in computations. But they assume
that the capacitances in the intrinsic MOSFET are reciprocal
charge-based capacitance models - ensure charge conservation and
consider the nonreciprocal property of the capacitances in a MOSFET
describes capacitive effect.
Useful especially for RF applications in which the influence of
transcapacitances are critical . But usually the charge-based
capacitance models require complex equations to describe all of
the 16 capacitances in a MOSFET with four terminals

HF Behavior and Modeling of the

Extrinsic Components

modeling of parasitics are very important

following issues should be considered in developing a MOSFET model for deep
submicron RF applications:
The gate resistance should be modeled and included in the simulation.
The extrinsic source and drain resistances should be modeled as real external
resistors, instead of only a correction to the drain current with a virtual
component.
Substrate coupling in a MOSFET, that is, the contribution of substrate
resistance, needs to be modeled physically and accurately using appropriate
substrate network for the model to be used in RF applications.
A bias-dependent overlap capacitance model, which accurately describes the
parasitic capacitive contributions between the gate and the drain/source,
needs to be included

RG Modeling

RG,poly is the distributed gate electrode resistance from the polysilicon

gate material and is given by Eq. (3.22) and RG,nqs is the NQS distributed
channel resistance seen from the gate and is a function of both biases and
geometry.

RGsh is the gate sheet resistance, Wf is the channel width per finger, Lf is
the channel length, Nf is the number of fingers, and Wext is the extension
of the polysilicongate over the active region

Gm is the transconductance of the device and is a fitting parameter with

a typical value around 0.2

RG Equivalent

Modeling of source and drain

resistances

HF behavior and modeling of

substrate resistance
in RF ICs, the substrate resistance can
contribute significantly to the device behavior,
mainly output admittance

 where CSB and CDB are the total source-to-bulk and drain-tobulk capacitances,
CSB,K and CDB,K are the source-to-bulk and drain-to-bulk
capacitances of each source and drain region in the
multifinger device,
Ns and Nd are the numbers of the source and drain regions,
RSB, RDB, and RDSB are the total equivalent resistances
between the source and the substrate, between the drain and
the substrate, and between the source and the drain
underneath the channel in the substrate,
RSB,K , RDB,K, and RDSB,K are the resistances, corresponding
to each single source/drain.

High-frequency behavior and

modeling of parasitic capacitances

MODEL PARAMETER EXTRACTION

RF Measurement and De-embedding
Techniques
To extract the RF model parameters, on-chip HF
measurements are performed by using specifically
designed test structures
A de-embedding methodology has to be
developed to remove the influence of the
parasitics in the test structure from the measured
raw data in order to obtain the data for the
characteristics of the device-under-test (DUT)

Parameter Extraction
Usually, the Y - parameter analysis of the EC is adopted to
obtain the necessary equations to extract the values of some
resistive and capacitive components.
Terminal and substrate resistance are neglected
The parameters related to the DC characteristics are extracted
with the data from the DC measurements
In order to extract the AC parameters, the influence from the
intrinsic components has to be minimized.

Simplified MOSFET model :

a vertical (gate controlled) device +
a lateral (channel conduction) device

Comment

<c.f.> RF MOSFET Equivalent Circuit Model

Substrate-network + Gate resistor
for RF behavior
modeling

Modeling of Passive Devices

Resistors
Capacitors
Inductors / transformers
-- state-of-art structures
-- Models
-- Model parameter extraction
Lab. #2 : Modeling of on-chip inductors

4.1 Introduction

* Types of Passive Components

Resistors : well resistors; poly resistors;
metal resistors; high precision
(active-load resistors).
Capacitors : Junction capacitors;
MOS capacitors;
poly capacitors;
MIM capacitors.
Inductors : metal inductors (spiral, octagonal,
differential, center-tap,circular, stacked)
(active inductors).

5.2 Resistors
Functions of resistors : current limiting,
voltage division,
signal isolation.
* Diffused (Well) Resistors:

well
Sub

@ Low Frequency :
L
L
R
R sh
R sh number of squares
Wt
W
@High Frequency :
where

L
2
1
R

: the skin depth;

t/
1 e
W
0 0
f 0 0

0 : operation frequency;
0 : permeability in vacuum;

: conductivity

Sheet Resistance of Different Type Resistors:

Well resistor

1~100K/

Metal resistor

20~40m/

MOS resistor

20~50 /

Poly resistor

1~20/

20~1K/

4.2 Capacitors:

Capacitors:
C s

A
tox

On-chip Cap. Range:

from several fF to 100 pF.

where tox gate oxide thickness.

Poly-insulator-Poly (poly cap.) :

Equivalent CKT.

Junction Capacitor

C total,0 C j0 A C jsw0 P
(bottom + perimeter)

Junction Capacitor : (cont.)

C j (V )

C j0

1 V
V j0

M j0

Varactors :
1. MOS Capacitors : (no forward current)
2. Junction Capacitors : (has to be reversed bias)

Applications:
Switched Capacitor for A/D, D/As
Frequency tuning for VCO
Feedback element
DC blocking.

4.3 Inductors:
2

Inductors:

C s nWs

L 0 n 2 r 1.2 10 6 n 2

where

On-Chip Spiral:

0 r
t ox_m

Ws is the spiral line width;

t ox_m is the vertical distance between
the spiral and the underpass.

High Speed/RF Models

As circuit speed and operating frequency rise, the need for
accurate prediction of circuit performance near cut-off
frequency or under very rapid transient operation becomes
critical.
BSIM4.0.0 provides a set of accurate and efficient highspeed/RF (radio frequency) models which consist of three
modules:
charge-deficit non-quasi-static (NQS)model,
intrinsic-input resistance (IIR) model (bias-dependent gate
resistance model), and
substrate resistance network model.

Charge-Deficit Non-Quasi-Static (NQS)

Model

Charge-Deficit Non-Quasi-Static
(NQS) Model

BSIM4 uses two separate model selectors to turn on or off the charge-deficit NQS
model in transient simulation (using trnqsMod) and AC simulation (using
acnqsMod).
The AC NQS model does not require the internal NQS charge node
that is needed for the transient NQS model.
The transient and AC NQS models are developed from the same fundamental
physics: the channel/gate charge response to the external signal are relaxationtime (t) dependent and the transcapacitances and transconductances (such as Gm)
for AC analysis can therefore be expressed as functions of jwt.

Transient Model

The resistance R is determined from the RC time constant (t).

The current source icheq(t) represents the equilibrium channel charging
effect. The capacitor C is to be the value of Cfact (with a typical value of
Farad [11]) to improve simulation accuracy.
Qdef now becomes

The transit time t is equal to the product of Rii and WeffLeffCoxe, where Rii is
the intrinsic-input resistance given by where Coxeff is the effective gate
dielectric capacitance calculated from the DC model.

AC Model

Noise Model

Channel Thermal Noise

Junction Diode Models

Layout Dependent Parasitics Model

Effective Junction Perimeter and

Area

Source/Drain Diffusion Resistance

Gate electrode Resistance

simulation of devices
Rajaram Sivasubramanian
Associate Professor
ECE Department
Thiagarajar College of Engineering
Madurai-15 ([email protected])

255

Pn Junction

Mesh setup

Region and Electrodes

Doping Specification

Materials Specification

Specify Models

Solve for Initial and Save data

Solve for applied Bias

MOS Capacitor Simulation

Example I

THANK YOU