What is CMOS?
(complementary metaloxidesilicon technology)
How would we make an ideal logic gate (inverter)?
How does this work in CMOS?
How are other gates made?
What are the actual semiconductor devices?
What are the special features of CMOS, which have made it the
dominant technology for digital applications?
What are the less pleasant features of CMOS, and how are they avoided
in practice?
What for the future? Moores law and modern devices
Modern electronics is heavily based on integrated circuits (ICs), which
means that each package contains more than one active device usually
vastly more than one! Digital systems use very large scale integration
(VLSI) with millions of transistors now approaching a billion.
An ideal inverter made from switches
supply voltage
(positive, VDD)
on
Vin
low
off
Vout
high
Vin
high
Vout
low
off
on
ground voltage
(negative, VSS)
We need two types of controlled switch to implement this inverter:
the lower switch turns on when the input (control) voltage is high
(relatively positive, close to VDD)
the upper switch turns on when the input (control) voltage is low
(relatively negative, close to VSS)
CMOS switches MOSFETs
There are two types of transistors that act as switches in CMOS technology,
hence the name complementary. They conduct between source and drain
or turn on under opposite conditions. (Well explore MOSFETs shortly.)
n-channel MOSFET
drain
gate
p-channel MOSFET
circle for
inversion
drain
gate
source
source
The transistor turns on when the
voltage on the gate becomes more
positive than a critical value
(threshold voltage).
The transistor turns on when the
voltage on the gate becomes more
negative than a critical value
(threshold voltage).
Symbol for gate is plain.
Note the circle on the gate!
Ideal for lower switch.
Ideal for upper switch.
Basic CMOS inverter
supply voltage
(positive, VDD)
p-MOSFET
turned on
on
Vin
low
Vout
high
Vin
low
Vout
high
off
n-MOSFET
turned off
ground voltage
(negative, VSS)
Remember:
n-MOSFET turns on when gate voltage is high, so it is off here
p-MOSFET turns on when gate voltage is low, so it is on here
In the opposite case Vin is high, the n-MOSFET turns on and the
p-MOSFET turns off pulling Vout low, just as we expect for an inverter.
A simple CMOS inverter needs only two transistors!
NAND gate
The basic CMOS gates are the inverter, NAND and NOR.
VDD
P2
P1
Vout
Vin1
N1
Vin2
N2
VDD
Vin1
P1
Vin2
P2
Vout
N1
VSS
NAND
N2
VSS
NOR
You should be able to work out how these operate from the analogy with
switches. AND is made from NAND + inverter and so on. NAND is more
common because it works better than NOR for technical reasons.
The MOSFET
(metaloxidesilicon field-effect transistor)
source (S)
channel
(where current
may flow from
source to drain)
gate (G) metal
drain (D)
gate oxide
silicon dioxide (silica)
silicon substrate insulator
G
symbol:
S
Crucial feature: the gate, oxide and silicon form a capacitor
gate and silicon = metal plates,
oxide = dielectric
Operation of n-MOSFET
Initially there is no charge on the capacitor, the channel is empty, there is
nothing to carry current from source to drain and the transistor is off.
When a positive voltage is applied to the gate, one plate of the
capacitor, it attracts negative charge on to the other plate, the channel in
the silicon.
This negative charge is supplied by electrons, which are mobile.
The electrons carry current along the channel from the source to the drain,
so the transistor has turned on.
Thus a positive voltage turns on a n-MOSFET. The only complication is
that the capacitor has a sort of built-in voltage so that it doesnt turn on as
soon as the voltage on the gate becomes positive. Instead it must exceed
a value called the threshold voltage.
p-MOSFETs are more complicated to explain see Electronic Devices 2.
You can make your own MOSFETs in future courses!
Crucial features of MOSFETs and CMOS
There are two properties of a MOSFET that make CMOS wonderful:
1. the input is the gate, which behaves like a capacitor, and
a capacitor draws no current in a steady state
2. they have a very high resistance when switched off
Together these mean that:
a CMOS circuit draws almost no current except when it is switching,
because of the capacitor on the input
the output voltage from a gate goes very nearly from ground to the
supply voltage because of the high resistance when switched off
Look at the inverter again to see how this happens.
CMOS inverter in a steady state
supply voltage (positive, VDD)
p-MOSFET turned on
Vin
low
Vout
high
n-MOSFET turned off
ground voltage (negative, VSS)
Consider the current that flows when the inverter rests in the 0 1 state:
no current flows into the input because it is connected to two capacitors
no current flows through the channels of the transistors because they are
in series and the n-MOSFET is turned off
Together these show that no current flows in a steady state.
It also shows that the output voltage is very nearly VDD because the nMOSFET is turned off
CMOS inverter while switching
supply voltage (positive, VDD)
p-MOSFET turning off
Vin
rising
Vout
falling
n-MOSFET turning on
ground voltage (negative, VSS)
Two currents flow when the inverter changes state:
the input voltage must charge the two capacitors presented by the gates
both transistors are turned on briefly during the middle of the transition so
a current flows from the supply to ground.
Thus a pulse of current flows whenever the inverter changes state.
In a synchronous system, this produces a (huge) pulse of current on
every clock transition.
Power dissipated in a CMOS circuit
We have seen that no current flows and therefore no power is dissipated
in a CMOS circuit in a steady state only when it changes state.
This is a huge advance over logic based on bipolar transistors (npn and
pnp), which always draw a current, even in a steady state.
It has allowed the dense integration of a huge number of devices (many
millions) the circuit would melt if they were bipolar instead of CMOS.
(Of course circuits change state rather often when clocked at several GHz
so a considerable power is dissipated in practice!)
Much current research is devoted to reducing the power even further.
What should we do about the spikes in the current when the circuit
switches?
Decoupling capacitors
If an inverter is driven
by a square wave, the
current looks like this:
Vin(t)
t
There is a spike every I(t)
time it changes state.
These spikes act as a source of noise that can affect other components in
the circuit and cause errors. In practice they are filtered out by putting a
decoupling capacitor across the supply to every integrated circuit.
Typically this is 0.01 0.1 F and is connected as close to the package as
possible. Remember to include them in any digital circuit that you design!
100 n
supply
14
Note the orientation and position
of the power and ground pins:
almost all 7400 logic chips are
like this, but not microcontrollers.
ground
Golden rules of CMOS
1. Never leave inputs floating (unconnected)
All inputs must be connected to something, even if you dont use them!
Sometimes it is important what the inputs are connected to (e.g. enable
inputs), sometimes it is unimportant (e.g. inputs of unused gates)
Use internal pullups to connect unused inputs in a
microcontroller.
Floating inputs can cause strange faults, very difficult to track down
Unused outputs should be left unconnected (they cause no problems)
2. Treat CMOS devices with care
The dielectric (oxide layer) of the gate capacitor is very thin and can be
damaged by static electricity. Luckily it is usually too humid in Glasgow
for this to be a serious problem!
3. Always remember the decoupling capacitors
What is happening to CMOS today? Moores law
Gordon Moore, co-founder of Intel, made his famous observation in 1965,
just four years after the first planar integrated circuit was discovered. He
predicted that the number of transistors per integrated circuit would double
every 18 months. He forecast that this trend would continue through 1975.
<http://www.intel.com/research/silicon/mooreslaw.htm>
Dimensions as a function of time (predicted 1996)
<http://www.research.ibm.com/0.1um/>
The latest trend strained silicon
The performance of devices can be
improved by straining them
mechanically stretching or
squeezing the silicon.
Unfortunately n and p-MOSFETs
need the opposite type of stress, so
great ingenuity is needed to apply
this in practice.
Intel claim that compression can
improve p-MOS by about 25%.
Electrons travel more quickly under a shorter gate only 90 nm long.
Other dimensions, such as the thickness of the oxide, are reduced to scale
only 1.2 nm thick. A simple memory cell can fit in an area of 1.0 m2.
Two Intel factories are tooling up for this already IBM similarly.
<http://www.intel.com/research/silicon/micron.htm>
Review exercises
How is an inverter constructed from controlled switches?
Why are two types of transistor needed to make an inverter?
How does a CMOS inverter work when the input is 1 (and the output is 0)?
Can you explain how the CMOS NAND gate works?
When does a CMOS gate draw current (and dissipate power)?
What features of CMOS have permitted todays enormous integrated
circuits?
What must you do to all CMOS inputs? and outputs?
What should be connected across the power pins of digital integrated
circuits?
What is Moores law?
