ELE654 ADDCA MINI PROJECT: (SEPT 2016)
DESIGN OF 32 BIT SINGLE CYCLE ARM MICROPROCESOR
1. PHASE 1: Design a single cycle ARM microprocessor that can support the
instructions below:(Will be considered as Lab 4)
a. Data-processing instructions:
ADD, SUB, AND, ORR
-with register and immediate Src2, but no shifts
b. Memory instructions:
LDR, STR
-with positive immediate offset
c. Branch instructions:
B
2. PHASE 2: Add more instructions and modifications to the ARM single cycle
above based on the requirements below:(Choose 5 out of 8 instructions)
a. Data-processing instructions:
i. ADC
ii. EOR
iv.BIC
v. RSB
vi. TST
vii.LSL
viii.LSR
3. Rewrite the Assembly code in order to add and test the new instructions. Change
the assembly to machine codes (binary and hex).Rewrite the file as memfile.dat
-Add the new insructions in above
4. Simulate the microprocessor with the testbench and new memfile.dat
1 2014 David Money Harris and Sarah L. Harris
REPORT FORMAT EXAMPLE
TITLE
OBJECTIVE
LITERATURE REVIEW
i.Theory on ARM microprocessor
ii.Explain the theory and function of all modules inside the ARM microprocessor
(cpu,main dec,aludec,condlogic mux etc)
Add more related literatures
Use IEEE format for citations
METHODOLOGY
i. Explain the design process for single cycle ARM microprocessor. Draw the block
diagram and connections.
2 2014 David Money Harris and Sarah L. Harris
ii.Show the changes made for each instructions: (redraw the circuits to show
changes for each instructions)
-controller and datapath circuits
-decoder and conditional logic circuits
-Main decoder circuit and Table
-ALU circuit, ALU decoder circuit and Table
-PC logic
-newly added components
iii. Show the changes made for each instructions by rewriting the System Verilog
and write new one for the new components
Add more design processes and flow charts if needed.
RESULTS AND DISCUSSIONS
i.Raw data from different simulations to be tabulated in tables
ii.Show all of the synthesized modules in the ARM microprocessor (top
module,controller,datapath..etc).Expain.
iii.Explain the results explicitly and relate to the theories.
iv.Simulation:
a. An image of imem data from the waveform simulation that confirmed the
instructions above have been correctly stored in imem.
b. An image of the simulation waveforms showing correct operation of the
processor to store data in dmem. Does it write the correct values to the
addresses?
c. The simulation waveforms should give the signal values in hexadecimal
format and should be in the following order: clk, reset, PC, Instr,
ALUResult, WriteData, MemWrite, and ReadData. While you may
print more signals during debug, do not display any other signals in the
waveform you submit. Check that the waveforms are zoomed out enough
that the grader can read your bus values. Unreadable waveforms will
receive no credit. Use several pages and multiple images as necessary.
3 2014 David Money Harris and Sarah L. Harris
v.Block diagram and gate netlist pictures.Explain.
Add more related results, graph and diagrams.
CONCLUSION
REFERENCE
Use IEEE format
APPENDIX
Source code (New System Verilog codes and testbenches) and memfile.dat
Waveforms/Diagrams/Block Diagrams that dont fit in the above section
4 2014 David Money Harris and Sarah L. Harris
5 2014 David Money Harris and Sarah L. Harris
Figure 2. Single-cycle ARM processor
Figure 3. ARM ALU
Table 2. Extended functionality: Main Decoder
ALUOp
Branch
MemW
RegW
MemtoR
eg
ALUSrc
ImmSrc
RegSrc
Type
Funct0
Funct5
Op
00
DP
Reg
00
XX
00
DP
Imm
X0
00
01
STR
10
01
01
LDR
X0
01
10
X1
10
assign {RegSrc, ImmSrc, ALUSrc, MemtoReg, RegW, MemW, Branch, ALUOp} = controls;
Table 3. Extended functionality: ALU Decoder
ALUO
p
Funct4:1
(cmd)
Funct0
(S)
Notes
ALUControl
FlagW1:
1:0
Not DP
00
00
0100
ADD
00
00
1
0010
11
SUB
01
1
0000
11
AND
10
1
1100
0
1
00
00
10
ORR
11
00
10
Cycle
rese
t
P
C
00
04
08
Instr
SUB R0,
R15, R15
E04F000F
ADD R2,
R0, #5
E2802005
ADD R3,
R0, #12
E280300C
SrcA
Src
B
Branc
h
AluResul
t
Flags3:0
[NZCV
]
CondE
x
WriteDat
a
MemWrit
e
ReadData
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Table 1. First nineteen cycles of executing armtest.asm (all in hexadecimal, except
Flags3:0 in binary).ADD MORE NEW INSTRUCTIONS TO TEST THE NEW
ARCHITECTURE
