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0% found this document useful (0 votes)
1K views324 pagesMohan Pspice Exercises
exercitii pspice de mohan
Uploaded by
Kro LineCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF or read online on Scribd
/ 324
“Developed for anid
Minnesota Power Electtonies Resédich & Baeaiten
University Station, 2811 University Avenue §.E-
P.O, Box 14503, Minneapolis, MN 55414 USA Beginner's Instruction Set for PSpice*
in Power Electronics Simulation
‘Copyright: Ned Mohan. 1993
(= PSpive is registered wademark of MicroSimn Corporation.)
‘This beginner's insttuction set shows one out of many possible ways to represent power electronic circuits in
PSpice. The examples refer to the accompanying Power Electronics Simulation package. This instruction sct is a
very small subset of the complete PSpice User's Guide which can be obtained lrom the MieroSim Corporation by
calling (714) 770-3022.
SPICE: Simutasion Program with Imegraied PSpice: A version of SPICE developed by
Circuit Emphasis (Universite of California ~ ‘MicoSim Corporation.
Rerkeley)
Objective: To perform a transiont analysis on a given power electronic circuit.
Simulation Stops:
1. Assign names 10 nodes and components sn youreieuit on paper.
w
Create an input Circuit File ( .CIR} using a text editor like Edit im MS-DOS 5.00 or tigher.
3. Execute PSpice usins the Input Circuit File ( .CIR).
4, Examine the Output List Fife ( OUT) For the printed output using & text editor.
3. Plot the raw plot data points in the Data ile ( .DAT) using PROBE included with PSpice,
Contents of the Input Circuit File (.CIR }: See the Input Circuit File EXAMPLI.CIR for Exercise |
1. Title Statement
Comment Statements (optional but desirable)
Library Statement (if necessary)
ae
Data Statements
5. Solution Control Statements
6 Output Control Statements
7. END Statement
Conventions in Input Cireuit File ( .CIR ):
‘The user has 10 give each node in the circuit a name See Exercise 1). The name can consist of eharucters or
umbers, However, one node in the eiceuit- must be groura, named 0. Other nodes can be named arbitrarily and
don't need tobe ina sequence 1,2, 3, ee.
‘The Title Statement has to be the fest line oF che input Cieuit Pie and END statement has tobe the ver last ne
All ofr statements can be in any raridom sequence. PSpice is case insensitive, that is, uppercase and lowercase
levers mean the same and therefore can both be used in any statement. The user has the option of using the
following suffix feters to indicate various power-of-ien: [for te-t5, p for Le-12, for 1e-9. a foe le-6. m tor le-
3. K for 1e3, meg for 1e6, 2 for 1€9, and tfor Lel2. Ifthe sutftx has other letes, for example in YOmez and L7OV in
Exercise 1, Hand V wili be ignored.) ‘Statements in the Input cirenit file:
1
2
3
Title Statement: — The frst line of the Input Circuit File has 10 be any text which describes the circuit.
Ivcan be very bref or it can even be a blank line.
‘Comment Statements: Marked by * in coum 1, followed by any text.
Library Statement: Subcirewits (discussed later on), for example representing & diode with an R-C
snubber,can bé putt into'a library file . If sich a subcireuit is Used, the Input Circuit File must point to that
library file. (See Exercise 3.)
LIB library file name
Data Statements: Note thatthe dircetion of cursent throug @ component is aways defined to be from
the ode tothe -node.
a Parameter Statements: See Exercise 7 where 60-Hz frequency is defined as a parameter FREQ. On
using expressions to define parameters, see Exercise 8 Parameters defined this way are passed on 10 the
subcireuits as well,
PARAM — name = {a value oran expression}
bb. Passive Components:
Resistor: Roame tnode node value
Inductor: Liname node -nade —vafue—_[ [C= initial value of current]
(See Exercise 8 orinital value of current.)
Capacitor: Comme +node -node value [4
initial value of Vortage]
(Bee Exercise 3 for the initial value of voltage.)
Coupled Inductors: Kname Lame! Laame? value of mutual coupling coetficient 1,
(See Exercise 50.)
¢ Independent Voltage and Current Sources for Transient Analysis
Yeame +node node transient specifications
Iname +node — -node transient specifications
‘Transient specifications :
‘pulse (intial voltage. peak voliage, initial delay time, rise ume, fall ime, pulse width. pulse period)
(See VPLS! and VPULS? in Exercise 46.)
sinw0, amplitude, frequency, 0,0, phase in degrees}
(See Exercise 1)
4. Dependent sources
Voltage-Controlled, Voltage Source: See EPRI in the subcircuit of Exercise 5S,
Ename node -node +eontrolling node controling node gain
Cumrent-Controlied Curent Source: See FSEC in the subsirout of Exercise 55, Note that a OV independent
soltage source VSENSE is used to measure the current.
Frame +node node name of the current-measuring voltage souree gain Nl
© Using Models built-in within PSpice: To use these models, we need two statements, One defines the
‘omponent connections and the model name associated with the specific values of the paramelers of the
builtin PSpice mouel, ‘The sevond statement defines the parameter values of the PSpice builtin model
associated with that model name.
Diode: See the subcirewit DIODE_WITH_SNUB in Appendix A. Note the difference between the name of
the diode DX , and the mode name POWER_DIODE. ‘The same model can be used for any namber
‘of diodes in she circuit
Dname trode node model_name
MODEL — model_name — D(CJO=0.0011F, RS=0.01)
‘Note that all parameters within the brackets are optional. Iz value is not specified, then the default
values are used by the program.
Voltage-Controlled Switeh: See Exercise 28. This switch is represented by a very low resistance RON in
's on-staie, when the contol voliage is greater than VON. When the contol voliage is less than
VOFF, the Switch is represented by a very high tesistance ROFF. The delault values areas follows
RONS1 chm, ROFE=1e46 ohm, VON=I V, VOFF= 0 V. Note that the current through the siviich
2a flowin either direction whet he switch is on.
Sname +node -node +controlfing node -controlfing node mode|_name
“MODEL — model_name —_ VSWITCH( RON=0.01 ) .
Note that a large resistance is intematly connected between the controlling nodes to keep them from
Noaiing. Internally, the controlling nodes are electrically isolated frora the switch noses.
h, Subeirenits: Soe Exercise 9. The use of a subcireuit requires a call fo the subeireuit. The definition
Of the subcircuit can be a part of the input Circuit File ( .CIR) Otherwise, the Input Circuit File must point
tothe library, by means of a LIB statement, where the subcireuit definition is located.
Call to a Subeireuit: The parameter values defined in the call statement are passed on to the subcircuit,
‘This way, the same subcirevit can be used with different parameter values, See Exercise 10 where the
subeircuit SCR represents two thyristors with different gate pulse instances.
Xname novel node2.node n_ subckt_name PARAMS: name I=value, name 2=value,
Subelrevit Definition: | The subsiteit can be given any node ani! component names, without
interference with the names in the calling circuit. The only exception is O which is wreated as ground
everywhere. This delinition must end with a ENDS statement.
“SUBCKT —subcktname node 1 node .noden PARAMS: name Levalue, name
vale.
‘ENDS
& Analog Controller Modeling:
21 Instantaneous Transfer Functions (algebraic relationships):
By means of VALUE: See EDIFFA in Exercise 29,
Ename +node node VALUE = {an expression}
‘By means of TABLI
‘See ECOMP in the subckt COMPHYS in Appendix AS.
Ename +node -node TABLE { expression } = point
-point description of relationship
82 Laplace Transforms: See fall in Exercise 55.
Ename tnode node LAPLACE: { expression } = { irans(ona } h, Parametric Analysis: See Exaraple 12. It requires two statements; a PARAM statement and a STEP
statement to carryout the analysis with a specified list of values of a parameter to be varied. For a linear
Variation where a stant value, a (inal value, and a linear increment value are specified in this order, see
DBRECTID.CIR on the diskewe.
PARAM parameter_to_be_varied =1
STEP PARAM parameter,to_be_varied LIST a list of values in ascending or descending onder
§ Solntion Control Statements:
4 Transient Analysis: See Exercise 3 where UIC, wich stands for Use Initial Conditions, must be used
Otherwise, a de steady state analysis will be perforined and the resulting voltages and currents will be used
as initial conditions fér the transient analysis,
TRAN printstep final_time results delay step_eeiling UIC
Note that the print_step dicttes the frequency at which the output variables are printed in the OUT file,
Both the print ouput and the raw plot points afe saved starting at results delay. ‘The minimum me step is
not under user control but the maximum time step is dictated by step_ceiling.
, Fourier Analysis: _ See Exercise 3 where the fundamental frequency must be specified. Also note how
the eurtent chrough a subeircutt component is referred.
FOUR fundamental frequency oulpu_sarables
[Nove that the Fourier analysis printed in the .OUT file is based on the values inthe last fundamentale
frequency cycle. For each harmonic h, the Fourier Component and the Phase in dcgrees are the peak
amplitude and the phase angle in the equation, for example, ih = Ih, poak sad + 6h).
6. Output Control Statements:
‘& Printed output in the .OUT File:
PRINT TRAN oviput_sarables
b. Raw Plot Points for PROBE:Sce Exercise 9. Only the variables specified on the fist are stored.
‘Otherwise, all voltages and currents are stored, possibly resulting in an extremely large .DAT file.
PROBE output, variables
7. End Statement:
END
Executing PSpice: in she directory where the PSpice program, the Input Circuit File, and the library file are
located, isse the Fllowing command:
PSPICE. name of the inpus cizenit Fike
Examine the Printed Output: The printed outpat will have the same name as the input circuit file except
for the extension of UT. This can be examined by means of any text editor, It should be done, espectalty if the
Spice con aboried due to errors.
Plotting Using PROBE:1/ th: input Circuit File contained a PROBE statement, the raw plot points are
‘Stored in a plot ile with the same name asthe inpu ciel file except for he extension of DAT, Also, the prograin
‘automatically goes iio a ploning move using PROBE. For plouing at later time, issue the following command:
PROBE. name of the plot lile
Just follow the instructions within PROBE for plotting. To obtain the list of variables available for plotting aller
having sclected ADD TRACE, press the FA key. To obtain the list of subcireunt variables available For plotting,
ress the Fa Key’ apain and sclect Shovs_ internal, subeircuit_nodcs. ae
voce cams
Hints:
Floating Nodes: There must be ade path to ground from each node. Otherwise, an ervor message in OUT file
will indicate Hat parscular node is floating. simple remedy isto connect a large resislance, for exainplc a le
‘ohm resistance, from that node to ground which does effect the eircuit performance,
Inductor Loops: I where is a loop involving inductors with zero resistance, an error message will be printed in
the .OUT file. Insert a small resistance anywhere inthis foop.
Convergence: In modeling of power clectronic circuits, convergence and the speed of simulation are two of the
biggest problems. Always include R-C snubbers across diodes and switches to avoid a sharp discontinuity which
results in PSpice proceeding with a very shall time step. In case of convergence problems, increase the enor
tolerance YNTOL from is default valve of 14V and ABSTOL from its default value of IpA to possibly Ia by
mean ofthe Options satement below. ITLS0 ses th total iterate lit forall poms he transient al sis 0
infinity,
Options abstol= uA iUS=0 — yntol=le-3
Floating Nodes: At each node, there must be atleast two connections, otherwise the run will abort with an error
message, A large resistance froin that node to ground will correct this problem.
Step_Ceiling in the TRAN Statement: To avoid very large time steps which result in evude plots, the user
should provide the vaiue of the maximum time step. Aw arbitrarily smail valve may result in a loag simulation
time. Power Electronics: Computer Simulation,
Analysis, and Education
Using PSpice*
Ned Mohan
- Developed for and distributed by:
Minnesota Power Electronics Research & Education
~ University Station, 2811 University Avenue S. E.
P.O. Box 14503, Minneapolis, MN 55414 USA
) © Copyright 1992 by Ned Mohan
No part of this Manuel or the associated input circuit
files may be reproduced in any form in violation of
the conditions set forth in the License agreement
~ specified on page 2 of this Manual.
*Classroom (Evaluation) version Lt
ACKNOWLEDGMENTS
I would like to thank my family for their patience, I would also like to thank Professors
William P. Robbins and Tore M. Undeland, my friends, colleagues and co-authors of the
textbook used here as a reference, for their encouragement. Tam grateful to Professor
Robbins for his contribution of Exercises 71 through 73. Dear Colleague:
‘Thank you for acquiring this educational package. Please note the following:
1. These simulations and exercises are designed solely for edincationat purposes.
‘The acquisition and use of this manual and the associated diskettes are subject
to certain additional conditions and restrictions set forth in the license
agreement and warranty on the back of this page. PLEASE REVIEW THIS
AGREEMENT CAREFULLY. By opening and using these materials, you
acknowledge and agree to be bound by the conditions in that agreement.
2. The textbook in the following material refers to the book "Power Electronics:
Converters, Applications, and Design” by Mohan, Undeland and Robbins,
published by John Wiley & Sons. ,
3. The PSpice book and software in the following material refer to the 2nd edition of
“SPICE: A Guide to Circuit Simulation & Analysis Using PSpice” by Paul W.
Tuinenga and published by Prentice Hall. The software which accompanies this,
Prentice-Hall book is the Evaluation version 5.0 of PSpice from MicroSim
Corporation of California.
4. MicroSim Corporation requires that the following notation be included:
PSpice is a registered trademark of MicroSim Corporation. All other MicroSim
product names are trademark of MicroSim Corporation. Representation of
PSpice/Design Center Screens are used by permission of and are proprietary to
MicroSim Corporation. Copyright 1992 MicroSim Corporation.
T sincerely hope that you and your students will find these simulations and exercises
valuable. I will be grateful for your suggestions for improving these exercises.
Ned Mohan
January, 1993 LICENSE AGREEMENT AND LIMITED WARRANTY
PLEASE READ THIS DOCUMENT CAREFULLY BEFORE OPENING THE
DISKETTE PACKAGE OR USING THE MANUAL. BY OPENING THE DISKETTE
PACKAGE OR USING THE MANUAL, YOU ARE AGREEING TO BE BOUND BY
THE TERMS OF THIS LICENSE.
1. Educational Site License. The enclosed manual and the input eircuit files on magnetic
diskettes, and any related documentation (collectively the *Product*) are licensed to you by
Minnesota Power Electronics Research and Education ("MPERE"), Education is the sole
objective of this Product. This license allows you to use the Product at a single educational
institution for which it is originally obtained on one or more computers and to make
duplicate copies of the Product for educational use (specifically excluding any workshop,
seminar or other short course work, which are beyond the scope of this license). You must
reproduce on any copy the MPERE copyright notice that was on the original copy of the
Product. The rights and licenses granted hereunder are nontransferable, and any attempted
transfer or other misuse of the Product shall invalidate this License.
2. Company Site License. If you are not an educational institution, the policies in section 1
shall still apply in intent ata single site within your organization.
3. Rights and Restrictions. Although the Product is copyrighted, its objective is to
promote education of power electronics. Hence, modifications and enhancements are
encouraged. However, you may not network, rent, lease, oan, sell or distribute this
Product in whole or in part, except as specifically authorized in Sections 1 and 2 of this,
License.
4, Termination. This license is effective until terminated. You may terminate this License
at any time by destroying the Product and all copies thereof. This License will terminate
immediately without notice from MPERE if you fail to comply with any provision of this
License. Upon termination you must destroy the Product and all copies thereof.
5. Limited Warranty. MPERE warrants only that the diskettes on which the circuit input
files are recorded are readable under normal use for a period of 30 days from the date of
purchase. MPERE's entire liability and your exclusive remedy will be replacement of any
diskette not meeting MPERE's limited warranty, and which is retued to MPERE with
copy of the receipt. You expressly acknowledge and agree that use of the Product is at
your sole risk, that the Product is provided "AS IS" and without warranty of any kind.
MPERE hereby expressly disclaims all other warranties, express or implied, INCLUDING
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE. THIS WARRANTY GIVES YOU SPECIFIC LEGAL
RIGHTS WHICH VARY FROM STATE TO STATE. SOME STATES DO NOT
ALLOW THE EXCLUSION OF IMPLIED WARRANTIES, SO THE ABOVE
EXCLUSION MAY NOT APPLY TO YOU.
6. Limitation of Liability. UNDER NO CIRCUMSTANCES, INCLUDING
NEGLIGENCE, SHALL MPERE BE LIABLE FOR ANY INCIDENTAL, SPECIAL OR
CONSEQUENTIAL DAMAGES THAT RESULT FROM THE USE OR INABILITY TO
USE THE PRODUCT, EVEN IF MPERE HAS BEEN ADVISED OF THE POSSIBILITY
OF SUCH DAMAGES. SOME STATES DO NOT ALLOW THE LIMITATION OR
EXCLUSION OF LIABILITY FOR INCIDENTAL OR CONSEQUENTIAL DAMAGES,
SO THE ABOVE LIMITATION OF EXCLUSION MAY NOT APPLY TO YOU. Inno
event shall MPERE's total liability you for all damages, losses, and causes of action
( whether in contract, tort (including negligence) or otherwise) exceed the amount paid by
you for the Produet. wee te
Ny Nene mae Fe
PREFACE
Computer simulation can greatly aid in the analysis, design and education of Power
Electronics. However, simulation of power electronics systems is made challenging by
the following factors: 1) extreme nonlinearity presented by the switches, 2) ime
constants within the system may differ by several orders of magnimde, and 3)'a lack of
models. Therefore, it is important that the objective of the computer analysis be
evaluated carefully and an appropriate simulation package be chosen.
In system level investigation, it is often adequate to represent semiconductor switches
within converters by ideal switches. ‘This is important in order to minimize the overall
simulation time. But, itis very desirable if the same simulation package has the detailed
device models 10 design snubbers and gate drives. The simulation package should also be
able to represent the controlier portion of the converter system by its functional features
in as simplified a manner as possible. Yet, it should be able to mode! the controller on a
component level if needed.
In view of the above considerations, a SPICE-based simulation package PSpice from
‘MicroSim corporation is chosen for this purpose. The classroom (Evaluation) version 5.0
of PSpice is surprising powerful. It is used for all the simulations presented in this
Manual.
In designing this educational package, the following items have been considered:
1. For the sake of modularity, commonly used components and controllers are
organized as sub-circuits and stored in a library called PWR_ELEC.LIB.
Unfortunately in more complicated circuits, this subcircuit approach is not
possible duc to the limits of the Evaluation version.
2. Except for the exercises in the Semiconductor and Gate Drives section, all other
simulations use voltage-controlled switches to represent semiconductor switches
and thyristors for two reasons: a) to stay within the limits imposed by the
Evaluation version of PSpice, and 2) to significantly reduce the simulation time.
3. When ON, the voltage-controlied switch in PSpice conducts current in either
direction. Many converters consist of switches (which conduct current only in
their forward direction) with diodes connected in anti-parallel. In order to
explicitly show the current through the switches and their anti-parallel diodes, the
unidirectional-current switch model in SUBCKT SWITCH is used. It consists of
a bi-directional-current switch in series with a diode.
4. ‘The negative controlling node of all voltage-controlled switches is assumed to be
the same as ground. This, of course, cannot be done in a real circuit but in
simulations of the type described here, it reduces the number of nodes without
affecting the system performance, Also, it should be noted that in PSpice, a
resistance of I/GMIN is internally connected between the controlling nodes to
keep them from floating.
5. It should be noted that node "0" means ground in the main circuit as well as in the
sub-circuits.
6. Diodes are represented by the diode model in PSpice with its default values
except for CJO, RS and IS. (Exercise #71 is an exception.) 7 In case of extreme nonlinearity, PSpice uses extremely small time steps and is
also prone to problems of voltage convergence. To avoid this problem of extreme.
nonlinearity such as that associated with diodes, R-C snubbers are connected
across them, The values of R and C in these snubbers are not optimized, rather
these are based on speeding up the simulation without distorting the system
voltage and current waveforms significantly.
8. Controllers are represented by their functional macro models.
9. ‘The default tolerance values in the OPTIONS statement are very Stringent and
can lead to the problem of voltage convergence. This is remedied by increasing
the tolerances.
‘These exercises ate designed for classroom demonstration, in assigning homework
problems in power electronics courses and design courses, to add a computer Inboratory
course, and for research on new circuit topologies. ‘These exercises are also valuable to
power electronics designers for self-learning and for circuit analysis as a first step in the
design process. ‘TABLE OF CONTENTS
(Execution times listed with each simulation are in (minutes : seconds), using an
'80386/80387 microprocessor and a math co-processorsct running at 20 MHz.)
Section1 Line Frequency Diode Rectifiers
Basic Concepts in Diote Rectification (0:15)
Basic Concept of Current Commutation in Rectifiers (0:19)
Iephase Rectifiers (1:08)
1 -phase Voltage-Douibler Rectifiers (0:29)
‘Mid-Point Rectifier (0:55)
Current in the Neural Wire due w power electronic toads (2:50)
Sephase Rectifiers (3:01)
Soar
Section2 Line-Frequency Phase-Controlled Converters
8. Basic Concepts in Thyristor Conventers (1:06)
9. Lphase Thyristor Rectifiers (1:17)
10. 1-Phase Half-Controlled Bridge Rectifier (1:25) ‘
11. Tephase Thryistor Inverters (1:22)
12, Basie Concepts in 3-Phase Thyristor Converters (10:38)
13. 3-phase Thytistor Rectifiers” :49)
14, 3-Phase Half-Controlled Bridge Rectifier (2:25)
15, S-phase Thyristor Inverts @:29)
Section 3 DC-to-DC Switch-Mode Converters
16. Buck (1:16)
1. Boost (1:28)
18, Buck-Boost (1:20)
19. Cak Convener (1:29)
20. 2-Quadrant Converter (0:58)
21. Fult-bridge, bipolar-voltage-switching (1:21)
22. Full-bridge, unipolar-voltage-switching (2:10)
Section4 Switch-Mode DC-to-Sinusoidal Inverters
23, PWM, bipolar-voltage-switching, I-phase (8:48)
24, PWM, unipolar-voltage-switching, I-pbase (17:19)
2S. Square-Wave,l-phase (1:01)
26, Voliage-Cancellation Control. -phase (1:19)
27. PWM Inverter, 3-phase (19:16)
28. Square-Wave inverter, 3-phase (1:49)
29. Current-Regutated Invener, 3-phase (30:48)
30. Programmed-Harmonic-Elimination Inverter, 3-phase (18:03)
231, Effect of Blanking Time in PWM Inverter (17:41)
Section 5 Resonant Converters: Zero Voliage/Current Switching
32, Basic Concepis in Resocant Converters Operating Below the Resonant Frequency (1:54)
33. Basic Concepis in Resonant Converters Operating Above the Resonant Frequency (2:02)
34._ Series-Loaded Resonant Converters, Discontinuous Conduction Made of Operation (1:28)
35. Series-Loaded Resonant de-de Converters Operating Below the Resonant Frequency (2:00)
36. Scries-Loaded Resonant dc-dc Convesters Operating Above the Resonant frequency G:17)
37. Paraltel-Loaded Resonant dc-dc Converter in Discamtinous-Conduction Mode (0:58)
38. Parallel-Loaded Resonant de-e Converter Operating Below the Resonant Frequency (0:52) 29.
a.
42,
“3.
43,
4.
48
49.
50.
51.
52.
55.
56.
57.
58.
59,
60.
61.
62.
63.
4
65
61.
8.
70.
n
2.
B.
Parallel-Loaded Resonant de-de Converter Operating Above the Resonant Frequency (1:27)
‘Current-Source, Parallel-Resonant Inverters for Induction Heating (0:44)
Basic Oscillating Circuits (0:17)
Class-E Converter (1:02)
Zero-Cutrent Switching, Quasi-Resonant Buck Converter (0:51)
Zero-Current Switching, Quasi-Resonant Boost Converter (0:25)
Basic Concepis in Zero-Voltage Switching (0:10)
‘Zero-Voltage Switching, Clamped-Voltage (Resonant Transition) Converter (1:02)
Zero-Voliage Switching, Phase-Modulated Full-Bridge Converter (2:25)
Zero-Voltage Switching, Buck de-de Converter (0:35)
Section § Switeh-Mode DC Power Supplies with Isolation
Flyback Converters (1:03)
Flyback Convesters in Parallel (1:36)
Forward Converters (3:18)
Forward Converters in Parallel (1:50)
. Full-bridge, Transformer Tsolsted Converters (5:55)
Curent-Source dc-dc Converters. (2:00)
Feedback Compensation and Response of a Forward Converter (17:34)
Feedback Compensation and Response of a Flyback Converter (1:01)
Current-Mode Control (5:49)
Ripple inthe output voltage duc to the flter-capacitor ESR (9:32)
Section 7 DC-Motor Drives
Ripple in the Armature Curent (1:21)
Position Contzol System withoutan invemnal current-control loop (0:37)
‘Speed Control System with an internal current-control loop (0:23)
Section 8 Electric Utility Applications
“Thyristor-Controlled Inductors for Stati var Control, I-phase (0:53)
‘Tuyristor-Conwolied Inductors for Static var Control, S-phase (6:17)
Switch-mode Static var Control (100:33)
High Frequency Interconnection of Photovoliaic Arrays (174:23)
1-Phase Active Filter (a Jong simulation time)
Section 9 Optimizing the Utlty Interface with Power Electronic Systems |
1-Phase, Sinusoidal-Curtent Rectification at unity power factor (25:18)
1-Phase, Sinnsoidal-Current Rectification using an ac switch (18:24)
Switeh-mode Interface for a bi-directional power flow, I-phase (29:58)
Switch-mode Intetface for a bi-directional power How, 3-phase (160:14)
Section 10 Semiconductor Devices / Gate Drives
Dicse switching characteristics (0:12)
Power MOSFET switching characteristics (0:08)
MOSFET Gate Drive (15:14)
Section 11 Snubber Design
|. Diode Snubbers. (0:17)
|. Thytistor Snubbers (2:27)
BIT Smubbers (0:07) AIO,
AIL
SUBCKT
SUBCKT
SUBCKT
SUBCKT
SUBCKT
SUBCKT
SUBCKT
SUBCKT
SUBCKT
SUBCKT
Appendix A
Library PWR_ELEC.LIB
DIODE_WITH_SNUB
‘SW_DIGDE_WITH_SNUB
SCR
SWITCH
COMPHTYS
PWM_RAMP
PWM_TRI
PWM_SIG
DLY_SIG
‘TRANS_NONIDEAL
DMODIFY 1
Exercise 1
Basic Concepts in Diode Rectification
%y
“Sth
\
+ * io
yO Road S "Rion
Nominal Values: Vg(rms) = 120 V at 60 Hz
Ls = 10 mH
Rload =52
Include an R-C snubber across the diode,
Problems
1, Execute EXAMPLI.CIR to obtain vs, YLs and VRioad waveforms.
2. Obtain vs and i waveforms. Why does the current keep on
flowing even after the input voltage has gone to zero?
3, Note that the inductor voltage has a zero average value
(averaged over the time period of repetition) under steady
state conditions.
4. Obtain the waveform for vdiode.
5. Remove the R-C snubber across the diode and rerun this case.
(See input circuit file EXAMPLIA.CIR on the accompanying
diskette.) What seems to be the Problem and why’
6.
Replace RLoad in the nominal circuit by a de voltage source vp
= 150 V. (See EXAMPLIB.CIR on the diskette.) Plot ys, vi.g,and
i*10. Observe that the current now flows only during a small
Portion of the postive half-cycle of vs. Also, the current peak
occurs when vs and vp are equal. wae
&
L
ow
PSpice Circuit Diagram:
a
Note that the diode is represented by a subcircuit DIODE_WITH_SNUB
(with an R-C snubber) stored in the library, which is described in the 7
Appendix. ,
Input Circuit File Listing: y
EXAMPLILCIR -
™ Basic Concepts in Single-Phase, Diode Rectification |
+ Power Electronics: Simulation, Analysis & Education....by N. Mohan.
LB CLIB
PARAM —-FREQ= 60.0Hz -\
xD DIODE_WITH_SNUB
10mHt
50 {
SIN(® 170V (FREQ) 000)
JTRAN SOus 20ms 0s = SOus. UIC 1
PROBE.
END
1 2
Ls 203
RLOAD 3 °
°
vs q
Typical Waveforms:
2000 {
—— Vg .
‘Lg
: 1 . ~
Os Sms
UCI MUC2,3) © UCSD
2000
en 2-1
Exercise 2
Basic Concept of Current Commutation in Rectifiers
The following exercise helps to explain current commutation process
in rectifiers.
Nominal Values: Vs(mms) = 120 V at 60 Hz
Ls =5 mH :
Io = 104
Include R-C snubbers across the diodes.
Problems
1, Execute EXAMPL2.CIR to obtain vs, vo, and 5 ig waveforms.
2. Plot vs, vLs, and the currents through the two diodes. Observe
the process of current commutation from one diode to the
other. Are the two commutations (from D1 to D2, and vice
versa) similar?
3. Obtain an analytical expression for the commutaion interval in
terms of the circuit parameters and variables. Compare its
value with the simulation results in Problem 2.
4. What will happen to the commutation intervals if the
commutation inductance Ls is reduced by one-half and Io is
doubled? What if vs is doubled? 2-2
PSpice Circuit Diagram:
Note that the diode is represented by a subcircuit DIODE_WITH_SNUB
(with an R-C snubber) stored in the library, which is described in the
Appendix.
Input Circuit File Listing: 1
EXAMPL2.CIR
* Basic Concept of Current Commatation in Rectifiers
* Computer-Aided Analysis of Power Etectronics ..using SPICE by N.Mohan.
LB PWRELECLIB
‘PARAM, FREQ = 60.0Hz
iso 2 Sait
xD 20 3 DIODE_WITH_SNUB
xD2 0 3 DIODE_WITH_SNUB
D 3 0 TOA
vs 1 © SIN(@170V (FREQ} 000)
CTRAN 50us 20ms Os Sus UIC
‘PROBE
END
Typical Waveforms:
200
om
200 —
os Sms tons 15ms 20ms
DUCIy BUCB> o LSS
Tine 3-1
Exercise 3
1-Phase Diode Bridge Rectifier
Rioad
Nominal Values: Vs(rms) = 120V at 60 Hz
Is=1mH
Rs=1mQ
Ld = Iu
Cq = 1,000 pF
Rioad = 202
Problems
1. Execute DBRECT1.CIR to obtain vs, is and vq waveforms.
2. From the results of the Fourier analysis contained in
DBRECTI.OUT, calculate the input power factor and the
displacement power factor.
3. | Make use of the Fourier analysis in DBRECT1.OUT to plot is, is1,
is3 and is5. (See DBRECT1A.CIR on the diskette.) Superimpose
the distortion current component idistortion = is - is1 on the
above plot.
4, Calculate Icap (the rms current though the filter capacitor) as a
ratio of the average load current load.
sae sung 10.
ii,
42.
13.
3-2
Plot the current and voltage associated with one of diodes, for
example, XD1, and obtain the average and the rmis vlues of the
Current as a ratio of the average load current.
Vary Ls to investigate its influence on the input displacement
power factor, the input power factor, %THD, and the peak-peak
ripple in the de voltage vq. (See DBRECT1B.CIR on the diskette.)
Vary the filter capacitor Cq to investigate its influence on the
percentage ripple in vd, input displacement power factor and
%STHD. Plot the percentage aVq (peak-to-peak)/V(average) as
a function of Cd. (See DBRECTIC.CIR on the diskette.)
Vary the load power to investigate its influence on the average
dc voltage. (See DBRECT1D.CIR on the diskette.) +
In the nominal circuit input file, remove the limit on the
maximux time step during the simulation and observe its
influence on the circuit waveforms.
Obtain the vs, is and vq waveforms during the startup
transient when the filter capacitor is initially not charged.
Obtain the peak inrush current as a ratio of the peak current in
steady state. Vary the switching instant by simply varying the
phase angle 6 of the source vs. (See DBRECT1E.CIR on the
diskette.)
Replace the de side of the diode bridge by a current source Iq =
10 A, corresponding to a very large Lg. Make Ls almost equal
to zero. Obtain Vd(average). (See DBRECTIF.CIR on the
diskette.)
Make Ls = 3mH in Problem 10 and obtain Vd(average),
displacement power factor, power factor, %THD, and the current
commutation interval.
For the following design specifications, calculate the Capacitance
and the rms current rating of the filter capcitor:
Vs = 120 V (nominal) +/- 10% at 60Hz
Pmax = 1 kW
Ls = ImH, 3-3
maximum AVd (peak-peak) < 10 V
The load can be modeled as a resistor or a current source.
PSpice CIRCUIT:
The initial voltage across Cd equals 160 V.
Input Circuit File Listing:
DBRECTI.CIR
# Single Phase, Diode-Bridge Rectifier
* Power Electronics: Simulation, Analysis & Education... by N. Mohan,
LB PWR_ELECLIB
‘PARAM FREQ = 60.0Hz
Ls 1 2 Im
RS 203 im
LD 45 Ink
RLOAD 5 6 20.0
cD 5 6 1000uF IC=160v
XDI 3004 DIODE_WITH_SNUB
XD3 o 4 DIODE_WITH_SNUB
xD2 6 = 9 DIODE WITH_SNUB
xD4 6 3 DIODE_WITH_SNUB
vs 1 0 SING 170V (FREQ) 000)
cTRAN Sus 50ms 0s Sus UIC
PROBE
FOUR 00 iS) LD) iKDLDH)
[END 3-4
Typical Waveforms:
200
Os 10ms 20ms 30ns 4oms sons
DUCT HUK5,6) © 1KLS>
Time Exercise 4
1-Phase Voltage-Doubler Rectifier
Ly 1 eitoad
rrr gt
i
s
R
‘load
2
Nominal Values: Vs(rms) = 120 V at 60 Hz
Ls =1 mH
C1 = C2 = 1,000 uF
Rload = 80 2
Problems
1. (a) Obtain vg, ig and vd waveforms.
(b) Obtain vel, ve2 and vd waveforms.
2. By means of Fourier analysis of ig, calculate its harmonic
components as a ratio of Is. Compare these to those in
Exercise 3.
3. Calculate the input displacement power factor, power factor
and the %THD in the input current.
4. Calculate Icap, the mms current through capacitor C1, as a ratio
of the average load current Ioad.
5. Calculate the percentage peak-to-peak ripple AVq in vd as a
ratio of the average Vg. How does this compare with that in
Exercise 3.
PSpice Circuit: 42
Input Circuit File Listing:
‘VDOUBLER.CIR
* Single-Phase, Voltage-Doubler Rectifier
* Power Electronics: Simulation, Analysis & Education....by N. Mohan.
PWR_ELECLIB
LB
PARAM, FREQ = 60.0Hz
Ls 1 2 Im
RLOAD 30 4 800
col 3 0 1000uF 1C=145V
eD2 o 4 1000uF 1C=180V
XDI 2 3 DIODE_WITH_SNUB
xD2 4 2 DIODE_WITH_SNUB
vs i 0 —_SIN@ 17OV {FREQ} 000)
mICLEZAS © ILLES
Time 6-1
Exercise 6
Neutral Current in a 3-Phase Distribution System due to
1-Phase Power Electronics Loads
Power Elewonics Load with a
Jat phase diode rectifier bridge
interface
Nominal Values: VLL(rms) = 208V at 60 Hz
Vphase(tms) = 120 V
Rectifier loads are the same in each phase
and identical to that in Exercise 3,
Problems
1, Obtain the neutral current iN waveform.
2. By means of Fourier analysis of in, calculate its harmonic
components as a ratio of Ig] (where Ig] = rms value of the
fundamental frequency component of the phase current).
3. Calculate IN/Is where IN is the rms value of the neutral
current and Ig is the rms value of the phase current.
4, Verify that in steady state
XY Gish)?
3,9,15,21
= 3Is3
where Ish is the h harmonic component in the phase current is. 6-2
5. Observe the effect of load unbalance on the neutral current by
removing load entirely in one of the phases.
PSpice Circuit:
ly
mm 1G, !
ot
2?
i
-
g
SNUB?
7F conn 4
|
4
y
6-3
Input Circuit File Listing:
NEUTCURR.CIR
* Neutral Current in a 3-Phase, 4-Wire Distribution System
* Power Electronics: Simulation, Analysis & Education....by N. Moban,
PARAM — FREQ = 60.0
RNEUT 100m
RMEASA 1 11 Im
RMEASB 212: Im
RMEASC 313 Im
XRECTA {1 19 I_PHASE_RECTIFIER PARAMS: IC_CAP=160V_ LOAD_RES= 20
XRECTEB = 12. 10 I_PHASE_RECTIFIER PARAMS: IC_CAP=140V_ LOAD_RES = 20
XRECTC 13. 10. 1_PHASE_RECTIFIER PARAMS: IC_CAP= 180 LOAD_RES=20
VSA 1 0 SIN@ 170 (FREQ}-0.00)
VSB 2 0 SIN@ 170 {FREQ} 00-120)
sc 30 SIN(@ 170 (FREQ) 00-240) :
JTRAN, SOus_50ms_—§ S0us_—_ UIC
PROBE —_i(RNEUT) i(RMEASA) i(RMEASB) i(RMEASC) v(1)
SUBCKT 1_PHASE_RECTIFIER 101100 PARAMS: IC_CAP=150V_ LOAD_RES=20
Ls 101 102 mH
RS 402 103 10m
LD 104105 Iult
RLOAD —— 105 106 [LOAD_RES}
cD 105.206 1000uF1C={1C_CAP}
RSNUBL 104 115 ik
RSNUB3 104 125 1k
RSNUB2 100 126 1k
RSNUB4 103. 116 Ik.
CSNUBI 115 103 0.1uF
CSNUB3 125 1000.1uF
CSNUB2 126 106 O.10F
CSNUB4 116 106 0.1uF
DI 103 104 POWER_DIODE
D3 100 104 POWER DIODE
D2 106 100 POWER_DIODE
Da 106 103 POWER_DIODE
-MODEL POWER DIODE D{RS=0.01, CJO=100pF)
.ENDS
END
NOTE:
1. In the subcircuit 1_PHASE_RECTIFIER, the snubbers across the
diodes are included explicitly (rather than using the subcircuit
DIODE_WITH_SNUB from the library) in order to stay within the
limits of the Evaluation version of PSpice. Typical Waveforms:
200
200
Os tons 20ns. 30ns 40ns, ‘50ms
UCT ML CRNEUT? FL
Exercise 7
3-Phase Diode Bridge Rectifier
— a oad
TOM
Tg Ry *
- 5
ay
- GP 4 Riad
4
- 4A 6X 2 '
~ ] Nominal Values: VLL, (tms) = 208 V at 60 Hz
Ls = 0.1 mH
- | Rioad = 16.5 9
j Problems
~ 1. (a) Obtain vab, va and ig waveforms.
\ (b) Obtain va and iq waveforms
} 2. By means of Fourier analysis of ia, calculate its harmonic
= components as a ratio of Jal.
i 3. Calculate Ia, Ia1, Idis, %THD in the input current, input
displacement power factor and the input power factor. How do
| the results compare with the 1-phase diode-bridge rectifier of
Exercise 3.
| 4. Calculate Teap (the rms curcent through the filter capacitor) as
a ratio of the average load current Hoad. Compare the results
| with that in Exercise 3. 72
Investigate the influence of Lg on the input displacement
power factor, the input power factor and the average de
voltage Vd. Suggested range of Lq: 0.1 mH to 10 mH.
Investigate the influence of Cq on the percent ripple in vg. Plot
the percentage AVd (peak-to-peak)/Vad(average) as a function
of Cg. Suggested range of Cq: 100 uF and 2,000 FE,
Investigate the influence of Cq on the input displacement
power factor and the input power factor. Suggested range of
Ca: 100 UF to 2,000 uP.
Plot the average dc voltage as a function of load. Suggested
range of Rload: 509 to 8Q.
PSpice Circuit:
Input Circuit File Listing:
DBRECT3.CIR
* Throe-Phase, Diode-Bridge Rectifier
LB
¥ Power Electonics: Simulation, Analysis & Education....by N. Mohan,
iB
PWR_ELECLI
‘PARAM. FREQ = 60.0
LSA)
SB
LSC
RSA
RSB
1 ue O.lmH
2 21 OlmH
3 31 Olmit
uo 2 im
2 2 im RSC 31032 im
~ LD 4 5 OSmtt
RD $6 Sm
RLOAD 6 7 165
~ © 6 7 S00uF 10-280
\ ?
x01 12 4 DIODE, wrm_sNuB
- XD3 2 = 4 DIODE WETH_SNUB
: xDs 32 4 DYODE_WITH_SNUB
\ xD4 7 12 DIODE_WITH_SNUB
XDS 7 2% DIODE_WITH’SNUB
-, xD2 7° 32 DIODE_WITH_SNUB
SA 10 SIN(0 170 (FREQ) 000)
VSB 2 0 SIN@ 170 (FREQ) 00-120)
- vysc 3 © SIN 170 {FREQ} 00-240)
-TRAN Sus SOms Os S0us. UIC
- ‘PROBE
Typical Waveforms
j
J ~4004 _—
os 10ns 20ms 30ms 40ms SOms
j Duct) mUC1,2) © U66,7) + iCLSAMZ
Time Exercise 8
Basic Concepts in Thyristor Converters
ist
“st
*) 6. ‘t Os
Nominal Values: V(rms) = 120 V at 60 Hz
vs1 = 170 sin(wt)
vs2 = 170 sin(wt - 180%)
Ls = 5 mH each
Ig=10A
Delay angle a = 45 degrees
Include R-C snubbers across the thyristors.
Problems
1. Execute EXAMPL3.CIR to obtain vs], is] and vq waveforms,
2. Obtain the commutation voltage (vs1 - vg2), is1 and ig 2
waveforms, Calculate the commutation interval and compare
its value with the simulation results.
3. Obtain the average value of the output voltage vq and compare
it with its analytical value.
4. Change the delay angle « t 135 degrees and obtain the voltage
vd waveform. Note that its average value now is negative,
therefore the delay angle of 135 degrees represents an
inverter mode of operation where the flow of power is from
the de side to the ac side.
5. Obtain the voltage waveform across one of the thyristors. 8-2
6. Replace the two voltage sources with series inductances by
three such branches where the voltage sources form a balanced
three-phase set. (See EXAMPL3A.CIR on the diskette.) Obtain
the dc-side voltage waveform. Note that the thyristor
connected to the highest postive phase voltage conducts,
provided a gate pulse is applied to it.
PSpice Circuit Diagram:
fg
Thyristors are represented by the subcixcuit SCR (with an R-C
snubber) stored in the library, which is described in the Appendix.
Input Circuit File Listing:
EXAMPL3.CR
* Basic Concepts in Thyristor Converters
“ Power Blectronics: Simulation, Analysis é& Education....by N. Mohan,
LB PWRELECLIB
‘PARAM PERIOD= (1/60), ‘TDEG = (14360°60)}, TISODEG= (180*TDEG)
‘PARAM ALPA=(45.0*TDEG), PULSE_WIDTH=0.5ms
Lst 1 1 smi
$2 2 21 mH IC=10A
D 3 0 104,
XxTHY1 noo3 SCR PARAMS: TDLY=(ALFA}
xTHY2 2 93 SCR PARAMS: TDL’
VSI 1 0 SINO ITV 60.000)
VS2 2 9 SIN@170V_ 6000-180)
-TRAN 50us ms Os Sus UIC.
PROBE Typical Waveforms:
200
5, y v 9,
N NY - "st
ist . Y//-
off. \ i 7
. . ow: :
~200 —— — — r —
Os ons 1Ons 15ns 20ns 25ms 30ms
DUCID MUGS) © 1LS1>85
Tine Exercise 9
1-Phase Thyristor Rectifier Bridge
at
”
Nominal values: Vg(ms) = 120 V at 60 Hz
Le] = 0.2 mH
132 = LO mii
Ld = 20 mH
Rload =5 2
delay angle a = 45°
Problems
1, (a) Obtain vs, vg and ig waveforms.
(b) Obtain vg and is waveforms.
(c) Obtain vm and is waveforms.
2. From the plots, obtain the commutation interval u and the dc-
side current at the start of the commutation.
3. By means of Fourier analysis of ig, calculate its harmonic
components as a ratio of Isi.
4. Calculate Is, %THD in the input current, the input displacement
power factor and the input power factor. 9-2
5. At the point of common coupling, obtain the following from the
voltage vm waveform:
(a) Line-notch depth p(%)
(b) Line-notch area and,
(c) voltage %THD.
6. Obtain the average de voltage Vg. Verify that
20L
Va = 0.9 Vg cosa - 8
Ig.
where first use the average value of id for Iq and then its
value at the start of the commutation interval as calculated in
Problem 2.
PSpice Circuit:
Controller:
The gate pulses to the thyristors are of 0.5 ms in
duration. These are delayed by an angle a with respect
to the zero-crossings of the input voltage vs waveform,
PSpice Input Circuit File:
THYRECTLOR
+ Single-Phase, Thyristor-Bridge Rectifier
“Loner Hlecuonics: Simulation, Analysis & Education...by N. Mohan,
LB
-PARAM, PERIOD = {1}, ALFAs 45.0, PULSE, WIDTH=0.5ms 9-3