A.S.I.

An application-specific integrated circuit (ASIC) is an integrated circuit (IC) customized for a particular use, rather than

intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC. Intermediate

between ASICs and industry standard integrated circuits, like the 7400 or the 4000 series, are application specific

standard products (ASSPs).

As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence

functionality) possible in an ASIC has grown from 5,000 gates to over 100 million. Modern ASICs often include entire 32-

bit processors, memory blocks including ROM,RAM, EEPROM, Flash and other large building blocks. Such an ASIC is

often termed a SoC (system-on-a-chip). Designers of digital ASICs use a hardware description language (HDL), such

as Verilog or VHDL, to describe the functionality of ASICs.

Field-programmable gate arrays (FPGA) are the modern-day technology for building a breadboard or prototype from

standard parts; programmable logic blocks and programmable interconnects allow the same FPGA to be used in many

different applications. For smaller designs and/or lower production volumes, FPGAs may be more cost effective than an

ASIC design even in production. The non-recurring engineering cost of an ASIC can run into the millions of dollars.

History
The initial ASICs used gate array technology. Ferranti produced perhaps the first gate-array, the ULA (Uncommitted Logic

Array), around 1980. An early successful commercial application was the ULA circuitry found in the 8-bit ZX81 and ZX

Spectrum low-end personal computers, introduced in 1981 and 1982. These were used by Sinclair Research (UK)

essentially as a low-cost I/O solution aimed at handling the computer's graphics. Some versions of ZX81/Timex Sinclair

1000 used just four chips (ULA, 2Kx8 RAM, 8Kx8 ROM, Z80A CPU) to implement an entire mass-market personal

computer with built-in BASIC interpreter.

Customization occurred by varying the metal interconnect mask. ULAs had complexities of up to a few thousand gates.

Later versions became more generalized, with different base dies customised by both metal and polysilicon layers. Some

base dies include RAM elements.

Basic Design Flow

 Concept phase: Functional objectives and architecture of a chip are developed.

 Logic design: Architecture is implemented in a register transfer level (RTL) language, then simulated to verify

that it performs the desired functions. This includes functional verification.

 Floor-planning: The RTL of the chip is assigned to gross regions of the chip, input/output (I/O) pins are assigned

and large objects (arrays, cores, etc.) are placed.

 Logic synthesis: The RTL is mapped into a gate-level netlist in the target technology of the chip.
  Design for Testability: The test structures like scan chains are inserted.

 Placement: The gates in the netlist are assigned to nonoverlapping locations on the chip.

 Logic/placement refinement: Iterative logical and placement transformations to close performance and power

constraints.

 Clock insertion: Balanced buffered clock trees are introduced into the design.

 Routing: The wires that connect the gates in the netlist are added.

 Postwiring optimization: Remaining performance, noise, and yield violations are removed.

 Design for manufacturability: The design is modified, where possible, to make it as easy as possible to produce.

 Signoff checks: Since errors are expensive, time consuming and hard to spot, extensive error checking is the

rule, making sure the mapping to logic was done correctly, and checking that the manufacturing rules were followed

faithfully.

 Tapeout and mask generation: the design data is turned into photomasks in mask data preparation.

Standard cell design

Main article: standard cell

In the mid 1980s a designer would choose an ASIC manufacturer and implement their design using the design tools

available from the manufacturer. While third party design tools were available, there was not an effective link from the

third party design tools to the layout and actual semiconductor process performance characteristics of the various ASIC

manufacturers. Most designers ended up using factory specific tools to complete the implementation of their designs. A

solution to this problem that also yielded a much higher density device was the implementation of Standard Cells. Every

ASIC manufacturer could create functional blocks with known electrical characteristics, such aspropagation delay,

capacitance and inductance, that could also be represented in third party tools. Standard Cell design is the utilization of

these functional blocks to achieve very high gate density and good electrical performance. Standard cell design fits

between Gate Array and Full Custom design in terms of both its NRE (Non-Recurring Engineering) and recurring

component cost.

By the late 1990s, logic synthesis tools became available. Such tools could compile HDL descriptions into a gate-

level netlist. This enabled a style of design called standard-cell design. Standard-cell Integrated Circuits (ICs) are

designed in the following conceptual stages, although these stages overlap significantly in practice.

These steps, implemented with a level of skill common in the industry, almost always produce a final device that correctly

implements the original design, unless flaws are later introduced by the physical fabrication process.

1. A team of design engineers starts with a non-formal understanding of the required functions for a new ASIC,

usually derived fromRequirements analysis.

2. The design team constructs a description of an ASIC to achieve these goals using an HDL. This process is

analogous to writing a computer program in a high-level language. This is usually called the RTL (Register

transfer level) design.

 3. Suitability for purpose is verified by functional verification. This may include such techniques as logic

simulation, formal verification,emulation, or creating an equivalent pure software model (see Simics, for

example). Each technique has advantages and disadvantages, and often several methods are used.

4. Logic synthesis transforms the RTL design into a large collection of lower-level constructs called standard cells.

These constructs are taken from a standard-cell library consisting of pre-characterized collections of gates

(such as 2 input nor, 2 input nand, inverters, etc.). The standard cells are typically specific to the planned

manufacturer of the ASIC. The resulting collection of standard cells, plus the needed electrical connections

between them, is called a gate-level netlist.

5. The gate-level netlist is next processed by a placement tool which places the standard cells onto a region

representing the final ASIC. It attempts to find a placement of the standard cells, subject to a variety of specified

constraints.

6. The routing tool takes the physical placement of the standard cells and uses the netlist to create the electrical

connections between them. Since the search space is large, this process will produce a “sufficient” rather than

“globally-optimal” solution. The output is a file which can be used to create a set of photomasks enabling

a semiconductor fabrication facility (commonly called a 'fab') to produce physical ICs.

7. Given the final layout, circuit extraction computes the parasitic resistances and capacitances. In the case of a

digital circuit, this will then be further mapped into delay information, from which the circuit performance can be

estimated, usually by static timing analysis. This, and other final tests such as design rule checking and power

analysis (collectively called signoff) are intended to ensure that the device will function correctly over all

extremes of the process, voltage and temperature. When this testing is complete the photomaskinformation is

released for chip fabrication.

These design steps (or flow) are also common to standard product design. The significant difference is that Standard Cell

design uses the manufacturer's cell libraries that have been used in potentially hundreds of other design implementations

and therefore are of much lower risk than full custom design. Standard Cells produce a design density that is cost

effective, and they can also integrate IP cores and SRAM (Static Random Access Memory) effectively, unlike Gate

Arrays.

Gate array design

Gate array design is a manufacturing method in which the diffused layers, i.e. transistors and other active devices, are

predefined and wafers containing such devices are held in stock prior to metallization, in other words, unconnected. The

physical design process then defines the interconnections of the final device. For most ASIC manufacturers, this consists

of from two to as many as five metal layers, each metal layer running parallel to the one below it. Non-recurring

engineering costs are much lower as photo-lithographic masks are required only for the metal layers, and production

cycles are much shorter as metallization is a comparatively quick process.

Gate array ASICs are always a compromise as mapping a given design onto what a manufacturer held as a stock wafer

never gives 100% utilization. Often difficulties in routing the interconnect require migration onto a larger array device with

consequent increase in the piece part price. These difficulties are often a result of the layout software used to develop the

interconnect.

Pure, logic-only gate array design is rarely implemented by circuit designers today, replaced almost entirely by field-

programmable devices, such as field-programmable gate arrays (FPGAs), which can be programmed by the user and

thus offer minimal tooling charges (non-recurring engineering (NRE)), marginally increased piece part cost and

comparable performance. Today gate arrays are evolving intostructured ASICs that consist of a large IP core like

a CPU, DSP unit, peripherals, standard interfaces, integrated memories SRAM, and a block of reconfigurable

uncommited logic. This shift is largely because ASIC devices are capable of integrating such large blocks of system

functionality and "system on a chip" requires far more than just logic blocks.

In their frequent usages in the field, the terms "gate array" and "semi-custom" are synonymous. Process engineers more

commonly use the term "semi-custom" while "gate-array" is more commonly used by logic (or gate-level) designers.

Full-custom design
Main article: Full custom

By contrast, full-custom ASIC design defines all the photo lithographic layers of the device. Full-custom design is used for

both ASIC design and for standard product design.

The benefits of full-custom design usually include reduced area (and therefore recurring component cost), performance

improvements, and also the ability to integrate analog components and other pre-designed (and thus fully verified)

components such as microprocessor cores that form a system-on-chip.

The disadvantages of full-custom design can include increased manufacturing and design time, increased non-recurring

engineering costs, more complexity in the computer-aided design (CAD) system and a much higher skill requirement on

the part of the design team.

However for digital-only designs, "standard-cell" cell libraries together with modern CAD systems can offer considerable

performance/cost benefits with low risk. Automated layout tools are quick and easy to use and also offer the possibility to

"hand-tweak" or manually optimise any performance-limiting aspect of the design.

Structured/platform design
Structured ASIC design (also referred to as platform ASIC design) has different meanings in different contexts. This is a

relatively new term in the industry, which is why there is some variation in its definition. However, the basic premise of a

structured/platform ASIC is that both manufacturing cycle time and design cycle time are reduced compared to cell-based

ASIC by virtue of there being pre-defined metal layers (thus reducing manufacturing time) and pre-characterization of

what is on the silicon (thus reducing design cycle time). One definition states that
In a "structured ASIC" design, the logic mask-layers of a device are predefined by the ASIC vendor (or in some cases by

a third party). Design differentiation and customization is achieved by creating custom metal layers that create custom

connections between predefined lower-layer logic elements. "Structured ASIC" technology is seen as bridging the gap

between field-programmable gate arrays and "standard-cell" ASIC designs. Because only a small number of chip layers

must be custom-produced, "structured ASIC" designs have much smaller non-recurring expenditures (NRE) than

"standard-cell" or "full-custom" chips, which require that a full mask set be produced for every design.[citation needed]

This is effectively the same definition as a gate array.

What makes a structured/platform ASIC different from a gate array is that in a gate array the predefined metal layers

serve to make manufacturing turnaround faster. In a structured/platform ASIC the predefined metallization is primarily to

reduce cost of the mask sets and is also used to make the design cycle time significantly shorter as well. For example, in

a cell-based or gate-array design the user often must design power, clock, and test structures themselves; these are

predefined in most Structured/Platform ASICs and therefore can save time and expense for the designer compared to

gate-array. Likewise, the design tools used for structured/Platform ASIC can be substantially lower cost and easier (faster)

to use than cell-based tools, because the tools do not have to perform all the functions that cell-based tools do. In some

cases, the structured/platform ASIC vendor requires that customized tools for their device (for example, custom physical

synthesis) be used, also allowing for the design to be brought into manufacturing more quickly. ChipX, Inc. eAsic,

and Triad Semiconductor are examples of vendors offering this kind of structured ASIC.

One other important aspect about structured/platform ASIC is that it allows IP that is common to certain applications or

industry segments to be "built in", rather than "designed in". By building the IP directly into the architecture the designer

can again save both time and money compared to designing IP into a cell-based ASIC.

The Altera technique of producing a structured cell ASIC where the cells are the same design as the FPGA, but the

programmable routing is replaced with fixed wire interconnect is called HardCopy.[1] These devices then do not need re-

programming and cannot be re-programmed as an FPGA.[citation needed]

The Xilinx technique of producing a customer specific FPGA, that is 30% - 70% less expensive than a standard FPGA

and where the cells are the same as the FPGA but the programmable capability is removed,[citation needed] is called EasyPath.
[1]

Cell libraries, IP-based design, hard and soft macros

Cell libraries of logical primitives are usually provided by the device manufacturer as part of the service. Although they will

incur no additional cost, their release will be covered by the terms of a non-disclosure agreement (NDA) and they will be

regarded as intellectual property by the manufacturer. Usually their physical design will be pre-defined so they could be

termed "hard macros".

What most engineers understand as "intellectual property" are IP cores, designs purchased from a third party as sub-

components of a larger ASIC. They may be provided as an HDL description (often termed a "soft macro"), or as a fully

routed design that could be printed directly onto an ASIC's mask (often termed a hard macro). Many organizations now

sell such pre-designed cores, and larger organizations may have an entire department or division to produce cores for the

rest of the organization. For example, one can purchase CPUs, ethernet, USB or telephone interfaces. Indeed, the wide
range of functions now available is a significant factor in the phenomenal increase in electronics in the late 1990s and

early 2000s; as a core takes a lot of time and investment to create, its re-use and further development cuts product cycle

times dramatically and creates better products. Additionally, organizations such as OpenCores are collecting free IP cores

paralleling theOpenSource movement in hardware.

Soft macros are often process-independent, i.e., they can be fabricated on a wide range of manufacturing processes and

different manufacturers.

Hard macros are process-limited and usually further design effort must be invested to migrate (port) to a different process

or manufacturer.

Multi-project wafers
Some manufacturers offer Multi-Project Wafers (MPW) as a method of obtaining low cost prototypes. Often called

shuttles, these MPW, containing several designs, run at regular, scheduled intervals on a "cut and go" basis, usually with

very little liability on the part of the manufacturer. The contract involves the assembly and packaging of a handful of

devices. The service usually involves the supply of a physical design data base i.e. masking information or Pattern

Generation (PG) tape. The manufacturer is often referred to as a "silicon foundry" due to the low involvement it has in the

process. See also Multi Project Chip.

ASIC suppliers
There are two different types of ASIC suppliers, IDM and fabless. An IDM supplier's ASIC product is based in large part

on proprietary technology such as design tools, IP, packaging, and usually although not necessarily the process

technology. Fabless ASIC suppliers rely almost exclusively on outside suppliers for their technology. The classification

can be confusing since several IDM's are also fabless semiconductor companies.
 GDS II

GDS II stream format, common acronym GDSII, is a database file format which is the de facto industry standard for data

exchange of integrated circuit or IC layout artwork. It is a binary fileformat representing planar geometric shapes, text

labels, and other information about the layout in hierarchical form. The data can be used to reconstruct all or part of the

artwork to be used in sharing layouts, transferring artwork between different tools, or creating photomasks.

History of the GDS II format

GDS = Graphic Database System

Initially, GDS II was designed as a format used to control integrated circuitphotomask plotting. Despite its limited set of

features and low data density, it became the industry conventional format for transfer of IC layout data between design

tools of different vendors, all of which operated with proprietary data formats.

It was originally developed by Calma for its layout design software, "Graphic Data System" ("GDS") and "GDS II". Now the

format is owned by Cadence Design Systems.

GDS II files are usually the final output product of the IC design cycle and are given to IC foundries for IC fabrication. GDS

II files were originally placed on magnetic tapes. This moment was fittingly called tape out though it is not the original root

of the term.

Objects contained in a GDS II file are grouped by assigning numeric attributes to them including "layer number",

"datatype" or "texttype". While these attributes were designed to correspond to the "layers of material" used in

manufacturing an integrated circuit, their meaning rapidly became more abstract to reflect the way that the physical

layout is designed. As of October 2004, many EDA software vendors have begun to support a new format, OASIS, which

may replace GDS II.

GDS II utilities
As the GDS II stream format is a de facto standard, it is supported by nearly all EDA software. Besides the commercial

vendors there are plenty of free GDSII utilities.[1] These free tools includes editors,[2] viewers,[3] utilities to convert the 2D

layout data into common 3D formats,[4][5] utilities to convert the binary format to a human readable ASCII format[6] and

program libraries.[7]