International Journal of Engineering and Technical Research (IJETR)
ISSN: 2321-0869 (O) 2454-4698 (P), Volume-3, Issue-11, November 2015
VLSI Implementation of Low -Complexity Reed
Solomon Decoder
G.Lakshmi Priya, A.Raghuram
transmission by channel noise. After determining errors, the
Abstract In this paper, a low complexity architecture of decoder corrects the errors in the received data.
Reed-Solomon (RS) code is developed to correct errors based on
truncated inversion less Berlekamp Massey algorithm. The Many researchers have tried to implement increasingly
arithmetic operations which are used in RS code are Galois
efficient RS decoder. They aim at offering of high speed and
Fields (GF) addition and multiplication. This paper presents: i)
RS encoder modeled using MATLAB with data encoded in the
low complexity. One such RS decoder is high speed parallel
noisy channel for functional verification. ii) RS decoder modeled RS decoder using ME architecture. ME architecture is regular
in Veri log HDL to recover the erroneous data. The Veri log systolic architecture but required cost is high due to its degree
modeled RS (255, 239) decoder has the capability of 8 computation circuit . Furthermore, to reduce hardware
symbolerrors detection and correction. The proposed decoder complexity of RS decoder the just-in-time folding Euclidean
has been designed and synthesized for the Xilinx Spartan6 series algorithm (JIT-FMEA) architecture and the recursive degree
FPGAs xc6Ix16-3. The resource consumption is about 44%, and computation less modified Euclidean (rDCME) architecture
the data processing rates over 1.3Gbit/s is realized. were proposed Recently to provide high speed and low
complexity of RS decoder using PRiBM architecture
Index Terms Berlekamp-Massey algorithm; syndrome;
proposed.
ReedSolomon codes; key equation solver;
In Section II, Reed Solomon (RS) encoder theory introduced.
I. INTRODUCTION
Section III presents the proposed architecture for the RS
Towadays, error-correcting codes are used in various digital decoder using the TiBM algorithm [6]. In Section, IV and V
systems in order to improve reliability. Out of many error simulation result and conclusions are present.
correction codes, the Reed-Solomon (RS) codes have great
power and utility, and are found in many applications from II. REED SOLOMON ENCODER
compact disc players to deep-space application. RS codes are
very effective in correcting burst errors aswell asrandom
RS encoder works by adding parity check symbols to the input
errors. The Reed-Solomon code is defined in the Galois field,
data before the data transmitted. The encoded data that consist
which contains a fmite set of element where any arithmetic
of errors are decoded to recover the error-free data. The parity
operations on elements of that set will result in an element
check symbols are added to allow the RS decoder to detect the
belonging to the same set.
locations of the corrupted data and to correct the errors arise
in the data during transmission. The number of errors can be
corrected by the RS code is depended on the number of parity
check symbols added. The transmission codeword is
systematically encoded and defmed in (1) as a function of the
transmitted message polynomial m(x), the generator
polynomial g(x) and the number of parity symbols
2t.
Fig. 1. The Structure of a RS Codeword c(x) = m(x)X2t + m(x) mod g(x)--------(1)
Every element of field, except zero, can be expressed as a Where g(x) is the generator polynomial given by
power of a primitive element, n, of the field. The non-zero 2t
field elements form a cyclic group defined based on a binary g(x) = (x+i)---------------- (2)
primitive polynomial. Let an (n, k, t) RS code defmes over i=1
GF(2m), where n is block length of m bits wide symbol, k is So generator polynomial of RS (255, 239) code is given as.
message length of the m bits wide symbol and t= [n-k]/2 is the
maximum number of error correcting capability. RS decoder g(x) = X16 + l18x15 + 52x14 + l03x13 + 3lx12 + l04x11
performs detection and correction of information (message) + l26x10 +187x9 + 232x8 +17x7 + 56x6 + l83x5
symbols in a codeword. The RS encoded data is processed to + 49x4 + l00x3 + 8lx2 + 44x + 79------ (3)
determine whether any errors have occurred during The variable a is a root of the primitive polynomial of degree
t.
G.Lakshmi Priya, Dept.Of Electronics And Communication In GF (28) the primitive polynomial is defined as x8 + X4 + x3
Engineering, Indira Institute Of Technology&Science:Markapur. + x2 + 1.
A.Raghuram, Dept.Of Electronics And Communication Engineering,
Indira Institute Of Technology&Science:Markapur
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VLSI Implementation of Low -Complexity Reed Solomon Decoder
III. REED SOLOMON DECODER are regular, but the hardware cost is high due to the required
degree computation and comparison circuit.In the RS
Let C(x) and R(x) are the transmitted codeword polynomial decoder, the KES block is the largest block compared with SC
and the received codeword polynomial, respectively. The and CSEE blocks. The number of PEs in RiBM architecture is
transmitted codeword polynomial can be corrupted by 3t+ 1 [7] and TiBM architecture is 2t+ 2 [6]. Therefore, to
channel noise during the transmission. Therefore, the reduce the area of the KES block, TiBM architecture used by
received codeword polynomial can be described as R(x) = truncating t-l PEs. So, reducing the area of KES block means
C(x) + E(x) =R n_1 x n-1 + ..... + R1x + R0 area of RS decoder can be reduce significantly. Also, as the
where E(x) is the error polynomial. more error correcting capability (t) increases, the hardware
complexity can be reduced more.
A. Syndrome Calculation Block :
The first step in the decoding received symbol is to calculate
set of syndromes Sj, OS i S2t-l to correct correctable errors.
Any nonzero value of Sj, OS i S2t -1 indicates the presence of
errors. The syndrome polynomial Sex) is defined as equation
------(4)
Sj = R(t) = R254 254t + R253253t+. .+ R1t + Ro
(i = 0,1,2, .. ,15)----------------------(5) Fig. 4. Number of PEs for (a) RiBM architecture , and
(b) TiBM architecture .
C. Chien Search Block, Forney Block and Error Correction
Block:
After getting the error locator polynomial A(X) and error
evaluator polynomial cr(x) from KES block are then fed into
the Chien search block and Forney algorithm block,
respectively. Chien search block calculates the roots of the
error locator polynomial. The Forney algorithms block which
works in parallel with the Chien search block to calculate the
magnitude of the error symbol at each error location. Let error
locator polynomial over GF (2m) is (X) = xt +t-i x t-1+...
+0.Then chien search algorithm is used to find roots of error
locator polynomial of degree t, which present inverse of error
location. In the [mal stage, Forney algorithm is used to
calculate the value of error.
The error values corresponding to error locations are
Fig. 2 .Syndrome calculation block calculated according to equation (6).For division in eq. (6),
inverse of an element of a divisor is stored in 256*8 ROM,
and it is then multiplied with an element of dividend.
------------(6)
After getting the error locations and error values, finally can
form the error polynomial E(X) and correct the received
polynomial R(X) just by adding (with XOR operation) these
two polynomials together
Fig, 3:Syndrome cell
IV. SIMULATION RESULTS
The syndrome calculation block is consisted of 16
parallelsyndrome cells as shown in Fig.2 .Syndrome cell Reed Solomon encoder and decoder are successfully
computes Si value during 255 clock cycles. modelled in MATLAB and Verilog HDL respectively. Errors
are added into the codeword through RS encoder and the error
B. KES Block : added codeword is used as input in RS decoder. We have
implemented the proposed RS (255,239) decoder using.
The key equation s(x)).(x)=a(x)modx2t is generally solved by
BerJekamp-Massey (BM) algorithm or the modified
Euclidean (ME) algorithm. The conventional ME algorithm
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International Journal of Engineering and Technical Research (IJETR)
ISSN: 2321-0869 (O) 2454-4698 (P), Volume-3, Issue-11, November 2015
Logic Utilization Used Utilization
Number of Slice 2786 out of
15
Registers 18824
4018 out of
Number of slice LUT 44%
9112
Number of fully used 2131 out of
47%
LUT-FF pairs 4440
Number of bonded
21 out of 232 9%
lOBs
Fig.5.The Structure of Reed-Solomon Decoder V. CONCLUSION
Verilog HDL and performed logic synthesis using ISEI3.1 Reed Solomon encoder and decoder are successfully
design tool with Xilinx Spartan6 series FPGAs xc6IxI6-3. modelledin MATLAB and Verilog HDL respectively. Error
Maximum frequency for this case is also found to be 162.72 detectionand correction technique is used here for
MHz. reliablecommunication over a noisy channel. The main
element in theFPGA that is highest in the demand is the
Fig.6 and Fig.7 shows simulation result and RTL view of RS LUT's. In this paperless number of LUT's is used. This
decoder respectively. represents reduction in thecost and save a lot of area. This
design will play a remarkablerole with its significant speed
and efficiency.
REFERENCES
[1] Sarwate, D.V., and Shanbhag, N.R.: 'High-speed architectures for
Reed-Solomon decoders', IEEE Trans. Very Large Scale Integr.
(VLSI) Syst.,2001, 9, (5), pp. 641-655
[2] H. Lee, "High-Speed VLSI Architecture for Parallel ReedSolomon
Decoder," IEEE Trans. on VLSI Systems, vol. II, no. 2, pp.
288-294,April. 2003.
[3] Hsu, H.Y., Wu, A.Y., and Yeo, 1.1.: 'Area-efficient VLSI design of
Reed-Solomon decoder for IOGBase-LX4 optical communication
systems' ,IEEE Trans. Circuits Syst. II, Express Briefs, 2006, 53,
(ll),pp. 1245-1249
[4] Baek, J.H., and Sunwoo, M.H.: 'Enhanced degree computation less
modified Euclid's algorithm for Reed-Solomon decoders',
Electron.Lett., 2007, 43, (3)
[5] Yuan, B., Wang, Z., Li, L., Gao, M., Sha, J., and Zhang, c.: 'Area
Fig. 6. The Simulation result of RS decoder efficient Reed-Solomon decoder design for optical communications'
,IEEE Trans. Circuits Syst. II, Express Briefs,2009, 56, (6), pp.
469-473
[6] https://books.google.co.in/books?isbn=1402083912
[7] www.indjst.org/index.php/indjst/article/view/29431
Fig. 7. The RTL view of RS decoder
TABLE I
Device Summery for RS (255,239) decoder
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