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Cp5152 Advanced Computer Architecture

This document outlines the objectives and units of study for an advanced computer architecture course. The course aims to introduce students to recent trends in computer architecture, including multiprocessor issues and different multicore architectures. It covers topics like instruction level parallelism, memory hierarchy design, cache optimization techniques, multiprocessor architectures like shared memory and interconnection networks, and various multicore designs. Students will learn how to identify limitations of parallelism exploitation and design hierarchical memory systems.

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Dennis Ebenezer Dhanaraj
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2K views1 page

Cp5152 Advanced Computer Architecture

This document outlines the objectives and units of study for an advanced computer architecture course. The course aims to introduce students to recent trends in computer architecture, including multiprocessor issues and different multicore architectures. It covers topics like instruction level parallelism, memory hierarchy design, cache optimization techniques, multiprocessor architectures like shared memory and interconnection networks, and various multicore designs. Students will learn how to identify limitations of parallelism exploitation and design hierarchical memory systems.

Uploaded by

Dennis Ebenezer Dhanaraj
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CP5152 ADVANCED COMPUTER ARCHITECTURE

OBJECTIVES:
To introduce the students to the recent trends in the field of Computer Architecture and identify
performance related parameters.
To learn the different multiprocessor issues.
To expose the different types of multicore architectures.
To understand the design of the memory hierarchy.

UNIT I FUNDAMENTALS OF COMPUTER DESIGN AND ILP 9


Fundamentals of Computer Design Measuring and Reporting Performance Instruction Level
Parallelism and its Exploitation Concepts and Challenges Exposing ILP - Advanced Branch Prediction -
Dynamic Scheduling - Hardware-Based Speculation - Exploiting ILP - Instruction Delivery and
Speculation - Limitations of ILP - Multithreading

UNIT II MEMORY HIERARCHY DESIGN 9


Introduction Optimizations of Cache Performance Memory Technology and Optimizations
Protection: Virtual Memory and Virtual Machines Design of Memory Hierarchies Case Studies.

UNIT III MULTIPROCESSOR ISSUES 9


Introduction- Centralized, Symmetric and Distributed Shared Memory Architectures Cache Coherence
Issues Performance Issues Synchronization Models of Memory Consistency Case Study-
Interconnection Networks Buses, Crossbar and Multi-stage Interconnection Networks

UNIT IV MULTICORE ARCHITECTURES 9


Homogeneous and Heterogeneous Multi-core Architectures Intel Multicore Architectures SUN CMP
architecture IBM Cell Architecture. Introduction to Warehouse-scale computers- Architectures- Physical
Infrastructure and Costs- Cloud Computing Case Study- Google Warehouse-Scale Computer.

UNIT V VECTOR, SIMD AND GPU ARCHITECTURES 9


Introduction-Vector Architecture SIMD Extensions for Multimedia Graphics Processing Units Case
Studies GPGPU Computing Detecting and Enhancing Loop Level Parallelism-Case Studies.

OUTCOMES:
Upon completion of this course, the students should be able to:
Identify the limitations of ILP.
Discuss the issues related to multiprocessing and suggest solutions
Point out the salient features of different multicore architectures and how they exploit parallelism.
Discuss the various techniques used for optimizing the cache performance
Design hierarchal memory system
Point out how data level parallelism is exploited in architectures

REFERENCES:
1. Darryl Gove, Multicore Application Programming: For Windows, Linux, and Oracle Solaris, Pearson,
2011
2. David B. Kirk, Wen-mei W. Hwu, Programming Massively Parallel Processors, Morgan Kauffman,
2010
3. David E. Culler, Jaswinder Pal Singh, Parallel computing architecture: A hardware/software approach
, Morgan Kaufmann /Elsevier Publishers, 1999
4. John L. Hennessey and David A. Patterson, Computer Architecture A Quantitative Approach,
Morgan Kaufmann / Elsevier, 5th edition, 2012.
5. Kai Hwang and Zhi.Wei Xu, Scalable Parallel Computing, Tata McGraw Hill, NewDelhi, 2003

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