By Getachew Teshome
Addis Ababa University, Department of Electrical and
Computer Engineering
Number of Instructions
Number of Operands for Each Instruction
Storage Type
Addressing Modes
Number of operands
1, 2, 3 operands
Opcode Destination Source 1 Source 2
Opcode Operand 1 Operand 2
opcode Operand 1
Opcode Destination Source 1 Source 2
Opcode what operation to perform
Source1 source of the first operand for the operation.
Source2 source of the second operand for the operation.
Destination destination for the result of the operation
ADD R1 R4 R2
Add the contents of register R4 & R2 and store the result to
register R1
High level codes are easier to write.
Machine codes give direct control to what the
processor does. But hard to write and debug.
1-1 correspondence b/n assembly and machine codes
except that mnemonic codes and labels are used in
assembly codes.
What will be the content of the Registers after
execution o f the following code segment.
ADD R1, R2, R4;
SUB R4, R1, 4; R0 0
MULT R2, R2, R4; R1 2
R2 3
R3 1
R4 10
R5 4
R6 2
R7 0
The number of bits allocated for the opcode is
determined by the number of instructions included in
the design.
How many instructions can be encoded with am m-bit
opcode?
Similarly, the number of bits for each operand is based
on the number of addressable storage locations.
Considering register mode operation only with 16
registers, how many bits are needed for each operand?
Suppose you come up with an architecture that has 40
unique operations and 32 registers. Considering only
register mode operations with three operands, what is
the width of each instruction?
If the instruction width is decided to be 32-bits, what
will be the maximum number of registers that can be
included in the design?
1. Immediate Values
Specifying constants in instructions
1. Registers
Fast and small (and useful)
2. Memory
Big and complex (and useful)
= small constant values placed in instructions
Example: i++;
addi R2, R2, #4
0101 010 010 000100
Very useful for branch instructions
Jump 100;
Register File
Small array of memory-like storage
Register access is faster than memory because register
file arrays are small and can be put right next to the
functional units in the processor.
Each register is uniquely identified with a binary
code.
Each register in the register file has a specific size
e.g. 32-bit registers
0101 010 010 011
Load and Store instructions are provisions to access
data stored in main memory.
Load copies the data at a certain memory location
to a specified register.
Ld R1, 100;
Store stores the content of a register to a specified
location in memory.
St 100, R1;
Write an assembly code for the following C++ code
fragment.
tinyint A[10]; //assume the Array A begins from address 100;
A[9]=A[5] + 4;
The target machine has an architecture with the
following 5 instructions.
ADD Rx, Ry, Rz
SUB Rx, Ry, Rz 3 operand instructions, All register direct
MULT Rx, Ry, Rz
LOAD Rx, M
STORE M, Rx
Large array of storage accessed using memory
addresses
Used to store instructions and data
Cheap but not as fast as registers
Lots of different ways to calculate the address.
Stack
Activation records: local variables, parameters, etc.
Heap data Dynamically allocated data (new or malloc() )
Static data Global data and static local data
Text Machine code instructions (and some constants)
Reserved Reserved for operating system
Direct addressing
Indirect addressing
Register indirect
Base + displacement
PC-relative
Strange addressing modes that made it into someones processor
and are interesting enough or ridiculous enough to talk about.
Like register addressing
Specify address as immediate constant
load r1, M[1500] ; r1 contents of location 1500
jump M[3000] ; fetch instructions from addr 3000
Useful for addressing locations that dont change
during execution.
Branch target addresses
Global/static variable locations
Compute the reference address by
1. Specifying an immediate address
2. Loading the value at that immediate address
3. Using that value as the reference address
load r1, M[ M[1900] ] 0
2340 1900
5555 2340
Specify which register has the reference address
Very useful for pointers
load r1, M[ r2 ]
add r2, r2, #4 register file memory
load r1, M[ r2 ]
R2 3340
6666 3340
7777 3344
Most common addressing mode today
Compute address as: reg value + immed
load r1, M [ r2 + 1000]
Good for accessing class objects/structures. Why?
register file memory
a.tot += a.val; R2 2340
5555 2340
6666 3340
a. What are the contents of register/memory after executing the following
instructions
r2 = load M[r3]
r3 = load M[r2+4] register file memory
store M[r2+8], r3
R1 0 108 100
R2 10 -1 104
R3 108 100 108
Variant on base + displacement
PC register is base, longer displacement possible since
PC is assumed implicitly
Used for branch instructions
jump [ - 8 ] ; jump back 8 memory locations
Leave it to the assembler to determine the immediate
value, why?
Write an assembly code for the following C++ code
fragment.
tinyint A[10]; //assume the Array A begins from address 100;
A[9]=A[5] + 4;
The target machine has an architecture with the
following 5 instructions.
ADD Rx, Ry, Rz
SUB Rx, Ry, Rz 3 operand instructions, All register direct
MULT Rx, Ry, Rz
LOAD Rx, M
STORE M, Rx
