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 BiCMOS Logic Gates

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 BiCMOS - Best of Both Worlds?
n CMOS circuitry exhibits very low power dissipation, but
n Bipolar logic achieves higher speed and current drive capability.

n BiCMOS achieves low standby dissipation like CMOS, but high

speed and current drive capability like TTL and ECL.

n The disadvantage of BiCMOS is fabrication complexity (up to 30

masking steps, compared to about 20 for bipolar logic or
CMOS). This translates into higher cost and longer design
cycles. $

n Notable examples of the BiCMOS technology are the Intel P6

(a.k.a. Pentium Pro) which appeared in 1996, and its successor
the P7.
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 BiCMOS Inverter
VDD
n P1 and N1 perform the logic
function.
P1 n QP and QO are low-
QP impedance output drivers.
N3
n N2 and N3 remove base
charge from the bipolar
VOUT transistors during switching.
VIN N1
QO

N2

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 BiCMOS Inverter
VDD VIN = 0.

P1
QP
N3

VOUT
VIN N1 VIN = V DD.
QO

N2

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 BiCMOS Inverter VTC
VOUT The BiCMOS inverter shown
CMOS here exhibits reduced logic
3.0
swing (VDD - 2VBEA) compared
to CMOS (VDD).
BiCMOS
Reduction of the supply
2.0 voltage will make this problem
more severe.

1.0 V DD = 3.3V
K = 40 A / V 2 VT = 1V
F = 50 VBEA = 0.7V
0.0
0.0 1.0 2.0 3.0
VIN

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 BiCMOS NAND Gate
VDD With both inputs high:

PA PB
QP
NB3

NA3

VOUT With VA high, VB low:

VB NB1

VA NA1
QO

N2

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 How Fast is BICMOS?
n For highly-capacitive off-chip
VDD
loads, fast switching is possible
due to the high current driving
P1 capability of the bipolar
QP transistors. The speed is limited
N3 by the parasitic capacitances of
the QP, which must be driven by
the P1 - N3 CMOS circuit.
VOUT n For on-chip loads presenting very
VIN N1 little capacitance, BiCMOS offers
QO no advantage if
N2 CL < C BCP
n BiCMOS integrated circuits are
really CMOS on the inside!

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 BiCMOS Applications
n Modern BiCMOS, invented by Intel, hit the market in 1992.
n Ever-increasing clock frequencies on motherboards of PCs and
workstations may require that the VLSI / ULSI chips be made in
BiCMOS. (Witness the Intel, AMD, and Cyrix P chips.)
n Central Processing Units (CPUs) of minisupercomputers can
be implemented in BiCMOS, with packing density and
dissipation advantages over ECL. (e.g., the Cray Research
Baby Cray J916 Computer)
n TTL will soldier on in motherboard SSI and MSI applications,
where BiCMOS does not boast an advantage.

n But the BiCMOS party may be over when supply

voltages drop below 1.8 V. BJTs have a fixed turn-on
voltage; MOSFET thresholds can be reduced to at least
0.3V for room temperature operation.
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 The Problem with BiCMOS
n For standard BiCMOS, the logic swing is VDD - 2VBEA.
n Supply voltages are continually being reduced, because

P C LVDD
2

n When VDD is reduced to 1.8V, standard BiCMOS will provide a

logic swing of only 0.4V; this isnt acceptable! We can provide
shunt elements which increase the voltage swing of BiCMOS,
but
n Turning off the BJTs isnt the answer! If the supply voltage is
1.8V, the BJTs can only conduct for
0.7 V VOUT 1.1V

n In this case the BJTs can not effectively boost the switching
speed.
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 Full-Rail BiCMOS Inverter w/
Resistive Shunts
VDD This BiCMOS design provides a
rail-to-rail voltage swing.
For VOUT < VBEA, N1 and R2
P1
conduct, bringing VOL all the way to
QP 0.
R1 For VBEA < VOUT < VDD - VBEA, one
VOUT or both BJTs conducts.
For VDD - VBEA < VOUT, P1 and R1
conduct, bringing VOH all the way to
VIN N1 VDD.
QO
It is not practical to fabricate this
R2 circuit with resistors, but a similar
circuit can be made using an active
shunt for QO.

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 BiCMOS Inverter w/ Active Shunt
VDD This BiCMOS design provides a
voltage swing of VDD - VBEA.
For VOUT < VBEA, N3 and N2
P1
conduct, bringing VOL all the way to
QP 0.
For VBEA < VOUT < VDD - VBEA, one
VOUT or both BJTs conducts.
N3 The base-emitter junction of QP is
not shunted, so VOH = VDD - VBEA.
VIN N1
QO
N2

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 Full Rail BiCMOS Inverter w/
Paralleled CMOS Output
VDD
The parallel CMOS
PO inverter provides rail-to-rail
operation.
P1
For VOUT < VBEA, NO
QP conducts, bringing VOL all
N3 the way to 0.
For VBEA < VOUT < VDD -
VOUT VBEA, one or both BJTs
conducts.
VIN N1 For VDD - VBEA < VOUT, PO
QO
conducts, bringing VOH all
N2 the way to VDD.

NO

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 Buffered CMOS

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 CMOS - Single Stage
VDD = 1.8V
tOX = 100 Angstroms
VT = -0.6V k P' = 80 A / V 2
2.2 m/ 0.5 m VOUT
VIN k N' = 200 A / V 2
VT = 0.6V
0.9 m/ 0.5 m CL

tP =

A=

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 CMOS - Single Stage / 50pF
VDD = 1.8V
VT = -0.6V KP =
2.2 m/ 0.5 m VOUT
VIN KN =
VT = 0.6V
0.9 m/ 0.5 m 50pF

tP =

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 CMOS - Three Stages / 50pF
VDD = 1.8V

2.2/ 0.5 11/ 0.5 55/ 0.5

VOUT
VIN

0.9/ 0.5 4.5/ 0.5 22/ 0.5 50pF

K1 = K2 = K3 =
C L1 = CL 2 = C L3 =
tP1 = tP 2 = tP3 =

tP =

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 CMOS - Six Stages / 50pF
VDD = 1.8V

2.2/ 0.5 11/ 0.5 55/ 0.5

VIN
WIRED
TO THE
0.9/ 0.5 4.5/ 0.5 22/ 0.5 NEXT
PAGE!

K1 = K2 = K3 =
C L1 = CL 2 = C L3 =
tP1 = tP 2 = tP3 =

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 CMOS - Six Stages / 50pF
VDD = 1.8V

275/ 0.5 1375/ 0.5 6875/ 0.5

VOUT

WIRED
FROM THE 110/ 0.5 550/ 0.5 2750/ 0.5 50pF
PREVIOUS
PAGE!

K4 = K5 = K6 =
CL 4 = C L5 = C L6 =
tP 4 = t P5 = tP6 =

tP =

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 GaAs Direct-Coupled FET Logic
(DCFL)

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 DCFL Inverter
DCFL gates are similar to NMOS
circuits, but are implemented with GaAs
MESFETs rather than Si MOSFETs.
VDD The advantage of DCFL is speed - it
is up to 3 times faster than CMOS.
The disadvantages of DCFL are
fabrication complexity and cost.
VOUT GaAs 75 mm wafer - $100
VIN Si 200 mm wafer - $10
Si 300 mm wafers - coming soon!
GaAs technology is less
established compared to Si
technology, and the fabrication of
enhancement type MESFETs is
difficult.

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 DCFL Inverter - Basic Operation
VIN = LOW.

VDD

NL

VOUT
VIN NO
VIN = HIGH.

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 DCFL NOR Gate
VA = VB = VOL.
VDD

NL

VOUT
VA = VDD or VB = VDD.
VA NOA VB NOB

DCFL NAND gates are not practical due to restrictions imposed on VDD, VOL,
and the enhancement device threshold voltages.

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 Buffered DCFL NOR Gate

VDD

VOUT

VA VB VA VB

The added source follower provides a low-impedance output driver for off-chip
loads.

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 DCFL Characteristics
Compare the 1999 state-of-the art for GaAs DCFL and Si CMOS:

GaAs DCFL vs. Si CMOS: 0.25 m technology

GaAs DCFL Si CMOS

propagation delay 35 ps 75 ps

dissipation 30 W (DC) 1 W / MHz

SRAM embedded in VLSI 32 kB 128 kB

GaAs exhibits higher electron mobility than Si.

Due to the GaAs electron velocity characteristic, DCFL can operate
at a reduced supply voltage without a penalty in switching speed.
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 DCFL Applications
n For a given minimum linewidth, GaAs DCFL circuitry is about 2
to 3 times faster than Si CMOS because of the difference in
electron mobilities.
n The extra speed comes at a premium, because GaAs
technology is less developed and DCFL is expensive.
n DCFL applications are at the high end, where the extra cost can
be justified. Examples are the Cray Y-MP and the Vitesse
Semiconductor GaAs microprocessor, which boasts 1.2 M
transistors [see Ira Deyhimy, Gallium Arsenide Joins the Giants, IEEE
Spectrum, pp. 33-40, February 1995].
n At the present time, the area of fastest growth for GaAs DCFL is
communications.
n A factor of three isnt much, though, when you consider the rapid
advancement of Si CMOS / BiCMOS technology.
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Introduction to
CMOS VLSI
Design

Interconnect
 Outline
Introduction
Wire Resistance
Wire Capacitance
Wire RC Delay
Crosstalk
Wire Engineering
Repeaters

Interconnect CMOS VLSI Design Slide 2

 Introduction
Chips are mostly made of wires called interconnect
In stick diagram, wires set size
Transistors are little things under the wires
Many layers of wires
Wires are as important as transistors
Speed
Power
Noise
Alternating layers run orthogonally

Interconnect CMOS VLSI Design Slide 3

 Wire Geometry
Pitch = w + s
Aspect ratio: AR = t/w
Old processes had AR << 1
Modern processes have AR 2 w s
Pack in many skinny wires
l

Interconnect CMOS VLSI Design Slide 4

 Layer Stack
AMI 0.6 mm process has 3 metal layers
Modern processes use 6-10+ metal layers
Example: Layer T (nm) W (nm) S (nm) AR

Intel 180 nm process 6 1720 860 860 2.0

1000
M1: thin, narrow (< 3l)
5 1600 800 800 2.0
High density cells 1000

M2-M4: thicker 4 1080

700
540 540 2.0

For longer wires 3 700

700
320 320 2.2

2 700 320 320 2.2

M5-M6: thickest 700
1 480 250 250 1.9
For VDD, GND, clk 800
Substrate

Interconnect CMOS VLSI Design Slide 5

 Wire Resistance
r = resistivity (W*m)

Interconnect CMOS VLSI Design Slide 6

 Wire Resistance
r = resistivity (W*m)
r l
R
t w

Interconnect CMOS VLSI Design Slide 7

 Wire Resistance
r = resistivity (W*m)
r ll
R R
t w w
R = sheet resistance (W/) w w

is a dimensionless unit(!)
Count number of squares
l

R = R * (# of squares)
l l

t t

1 Rectangular Block 4 Rectangular Blocks

R = R (L/W) W R = R (2L/2W) W
= R (L/W) W

Interconnect CMOS VLSI Design Slide 8

 Choice of Metals
Until 180 nm generation, most wires were aluminum
Modern processes often use copper
Cu atoms diffuse into silicon and damage FETs
Must be surrounded by a diffusion barrier
Metal Bulk resistivity (mW*cm)
Silver (Ag) 1.6
Copper (Cu) 1.7
Gold (Au) 2.2
Aluminum (Al) 2.8
Tungsten (W) 5.3
Molybdenum (Mo) 5.3

Interconnect CMOS VLSI Design Slide 9

 Sheet Resistance
Typical sheet resistances in 180 nm process
Layer Sheet Resistance (W/)
Diffusion (silicided) 3-10
Diffusion (no silicide) 50-200
Polysilicon (silicided) 3-10
Polysilicon (no silicide) 50-400
Metal1 0.08
Metal2 0.05
Metal3 0.05
Metal4 0.03
Metal5 0.02
Metal6 0.02

Interconnect CMOS VLSI Design Slide 10

 Contacts Resistance
Contacts and vias also have 2-20 W
Use many contacts for lower R
Many small contacts for current crowding around
periphery

Interconnect CMOS VLSI Design Slide 11

 Wire Capacitance
Wire has capacitance per unit length
To neighbors
To layers above and below
Ctotal = Ctop + Cbot + 2Cadj
s w

layer n+1

h2 Ctop

t layer n
Cadj
h1 Cbot
layer n-1

Interconnect CMOS VLSI Design Slide 12

 Capacitance Trends
Parallel plate equation: C = eA/d
Wires are not parallel plates, but obey trends
Increasing area (W, t) increases capacitance
Increasing distance (s, h) decreases capacitance
Dielectric constant
e = ke0
e0 = 8.85 x 10-14 F/cm
k = 3.9 for SiO2
Processes are starting to use low-k dielectrics
k 3 (or less) as dielectrics use air pockets

Interconnect CMOS VLSI Design Slide 13

 M2 Capacitance Data
Typical wires have ~ 0.2 fF/mm
Compare to 2 fF/mm for gate capacitance
400

350

300
M1, M3 planes
s = 320
250 s = 480
s = 640
Ctotal (aF/mm)

s=

8
200
Isolated

150 s = 320
s = 480
s = 640
100
s=

8
50

0
0 500 1000 1500 2000
w (nm)

Interconnect CMOS VLSI Design Slide 14

 Diffusion & Polysilicon
Diffusion capacitance is very high (about 2 fF/mm)
Comparable to gate capacitance
Diffusion also has high resistance
Avoid using diffusion runners for wires!
Polysilicon has lower C but high R
Use for transistor gates
Occasionally for very short wires between gates

Interconnect CMOS VLSI Design Slide 15

Lumped Element Models
Wires are a distributed system
Approximate with lumped element models
N segments
R R/N R/N R/N R/N
C C/N C/N C/N C/N

R R R/2 R/2

C C/2 C/2 C

L-model p-model T-model

3-segment p-model is accurate to 3% in simulation

L-model needs 100 segments for same accuracy!
Use single segment p-model for Elmore delay

Interconnect CMOS VLSI Design Slide 16

 Example
Metal2 wire in 180 nm process
5 mm long
0.32 mm wide
Construct a 3-segment p-model
R =
Cpermicron =

Interconnect CMOS VLSI Design Slide 17

 Example
Metal2 wire in 180 nm process
5 mm long
0.32 mm wide
Construct a 3-segment p-model
R = 0.05 W/ => R = 781 W
Cpermicron = 0.2 fF/mm => C = 1 pF

260 W 260 W 260 W

167 fF 167 fF 167 fF 167 fF 167 fF 167 fF

Interconnect CMOS VLSI Design Slide 18

 Wire RC Delay
Estimate the delay of a 10x inverter driving a 2x
inverter at the end of the 5mm wire from the
previous example.
R = 2.5 kW*mm for gates
Unit inverter: 0.36 mm nMOS, 0.72 mm pMOS

tpd =
Interconnect CMOS VLSI Design Slide 19
 Wire RC Delay
Estimate the delay of a 10x inverter driving a 2x
inverter at the end of the 5mm wire from the
previous example.
R = 2.5 kW*mm for gates
Unit inverter: 0.36 mm nMOS, 0.72 mm pMOS
781 W

690 W 500 fF 500 fF 4 fF

Driver Wire Load

tpd = 1.1 ns
Interconnect CMOS VLSI Design Slide 20
 Crosstalk
A capacitor does not like to change its voltage
instantaneously.
A wire has high capacitance to its neighbor.
When the neighbor switches from 1-> 0 or 0->1,
the wire tends to switch too.
Called capacitive coupling or crosstalk.
Crosstalk effects
Noise on nonswitching wires
Increased delay on switching wires

Interconnect CMOS VLSI Design Slide 21

 Crosstalk Delay
Assume layers above and below on average are quiet
Second terminal of capacitor can be ignored
Model as Cgnd = Ctop + Cbot
Effective Cadj depends on behavior of neighbors
Miller effect A
C
B
Cgnd adj Cgnd

B DV Ceff(A) MCF
Constant
Switching with A
Switching opposite A

Interconnect CMOS VLSI Design Slide 22

 Crosstalk Delay
Assume layers above and below on average are quiet
Second terminal of capacitor can be ignored
Model as Cgnd = Ctop + Cbot
Effective Cadj depends on behavior of neighbors
Miller effect A
C
B
Cgnd adj Cgnd

B DV Ceff(A) MCF
Constant VDD Cgnd + Cadj 1
Switching with A 0 Cgnd 0
Switching opposite A 2VDD Cgnd + 2 Cadj 2

Interconnect CMOS VLSI Design Slide 23

 Crosstalk Noise
Crosstalk causes noise on nonswitching wires
If victim is floating:
model as capacitive voltage divider
Cadj
DVvictim DVaggressor
C gnd v Cadj
Aggressor

DVaggressor
Cadj
Victim
Cgnd-v DVvictim

Interconnect CMOS VLSI Design Slide 24

 Driven Victims
Usually victim is driven by a gate that fights noise
Noise depends on relative resistances
Victim driver is in linear region, agg. in saturation
If sizes are same, Raggressor = 2-4 x Rvictim
Cadj 1
DVvictim DVaggressor Raggressor
Cgnd v Cadj 1 k
Aggressor
Cgnd-a
DVaggressor
Cadj
Rvictim

aggressor Raggressor Cgnd a Cadj

Victim
Cgnd-v DVvictim

k
victim Rvictim Cgnd v Cadj

Interconnect CMOS VLSI Design Slide 25

 Coupling Waveforms
Simulated coupling for Cadj = Cvictim
Aggressor
1.8

1.5

1.2

Victim (undriven): 50%

0.9

0.6
Victim (half size driver): 16%

Victim (equal size driver): 8%

0.3 Victim (double size driver): 4%

0
0 200 400 600 800 1000 1200 1400 1800 2000

t(ps)

Interconnect CMOS VLSI Design Slide 26

 Noise Implications
So what if we have noise?
If the noise is less than the noise margin, nothing
happens
Static CMOS logic will eventually settle to correct
output even if disturbed by large noise spikes
But glitches cause extra delay
Also cause extra power from false transitions
Dynamic logic never recovers from glitches
Memories and other sensitive circuits also can
produce the wrong answer

Interconnect CMOS VLSI Design Slide 27

 Wire Engineering
Goal: achieve delay, area, power goals with
acceptable noise
Degrees of freedom:

Interconnect CMOS VLSI Design Slide 28

 Wire Engineering
Goal: achieve delay, area, power goals with
acceptable noise
Degrees of freedom:
2.0 0.8

Width 1.8 0.7

Coupling:2Cadj / (2C adj+Cgnd)

1.6
0.6
WireSpacing
Spacing
1.4
(nm)
Delay (ns):RC/2

0.5
1.2
320
1.0 0.4 480
640
0.8 0.3
0.6
0.2
0.4
0.1
0.2
0 0
0 500 1000 1500 2000 0 500 1000 1500 2000
Pitch (nm) Pitch (nm)

Interconnect CMOS VLSI Design Slide 29

 Wire Engineering
Goal: achieve delay, area, power goals with
acceptable noise
Degrees of freedom:
2.0 0.8

Width 1.8 0.7

Coupling:2Cadj / (2C adj+Cgnd)

1.6
0.6
WireSpacing
Spacing
1.4
(nm)
Delay (ns):RC/2

0.5
1.2
320
1.0 0.4 480

Layer
640
0.8 0.3
0.6
0.2
0.4
0.1
0.2
0 0
0 500 1000 1500 2000 0 500 1000 1500 2000
Pitch (nm) Pitch (nm)

Interconnect CMOS VLSI Design Slide 30

 Wire Engineering
Goal: achieve delay, area, power goals with
acceptable noise
Degrees of freedom:
2.0 0.8

Width 1.8 0.7

Coupling:2Cadj / (2C adj+Cgnd)

1.6
0.6
WireSpacing
Spacing
1.4
(nm)
Delay (ns):RC/2

0.5
1.2
320
1.0 0.4 480

Layer
640
0.8 0.3
0.6
0.2
0.4
Shielding 0.2
0
0.1
0
0 500 1000 1500 2000 0 500 1000 1500 2000
Pitch (nm) Pitch (nm)

vdd a0 a1 gnd a2 a3 vdd vdd a0 gnd a1 vdd a2 gnd a0 b0 a1 b1 a2 b2

Interconnect CMOS VLSI Design Slide 31

 Repeaters
R and C are proportional to l
RC delay is proportional to l2
Unacceptably great for long wires

Interconnect CMOS VLSI Design Slide 32

 Repeaters
R and C are proportional to l
RC delay is proportional to l2
Unacceptably great for long wires
Break long wires into N shorter segments
Drive each one with an inverter or buffer
Wire Length: l

Driver Receiver

N Segments
Segment
l/N l/N l/N

Driver Repeater Repeater Repeater Receiver

Interconnect CMOS VLSI Design Slide 33

 Repeater Design
How many repeaters should we use?
How large should each one be?
Equivalent Circuit
Wire length l/N
Wire Capaitance Cw*l/N, Resistance Rw*l/N
Inverter width W (nMOS = W, pMOS = 2W)
Gate Capacitance C*W, Resistance R/W

Interconnect CMOS VLSI Design Slide 34

 Repeater Design
How many repeaters should we use?
How large should each one be?
Equivalent Circuit
Wire length l
Wire Capacitance Cw*l, Resistance Rw*l
Inverter width W (nMOS = W, pMOS = 2W)
Gate Capacitance C*W, Resistance R/W
RwlN

R/W
Cwl/2N Cwl/2N C'W

Interconnect CMOS VLSI Design Slide 35

 Repeater Results
Write equation for Elmore Delay
Differentiate with respect to W and N
Set equal to 0, solve

l 2 RC

N RwCw

t pd ~60-80 ps/mm
2 2 RC RwCw
l in 180 nm process
RCw
W
RwC
Interconnect CMOS VLSI Design Slide 36