SCHOOL OF ENGINEERING & TECHONOLOGY

DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGG.

NAME OF THE TEACHER: NAVDEEP PRASHAR

SUBJECT : MICROELECTRONIC CIRCUITS
COURSE CODE : EC 3230
SESSION : JAN- JUNE 2017
CLASS : 3RD YEAR, 6TH SEMESTER
 TABLE of CONTENTS

S.NO CONTENTS
1. Course Handout

2. Time Table

3. List of Registered Students

4. Assignmnet-1,2,3
5. Solution of Assignment -1,2,3

6. Question Paper Test-1

7. Solution of Test -1
9. Question Paper Test-2

10. Solution of Test -2

11. Question paper final
12 Solution of Question Paper Final
 Course Handout
Course Number : EC 3230
Course Title : Microelectronic Circuits
Instructor-in-Charge : Navdeep Prashar
1. Course Description: To introduce the concepts of VLSI Technology. To make the
students know about the various steps to fabricate an IC.
2. Scope: The scope of Microelectronics includes the design, fabrication and testing of
devices, circuits and systems using integrated (silicon) micro fabrication technologies.
Only trained people with state-of-the-art expertise can develop successful innovative
products. This subject aims at providing such knowledge, by offering a set of courses that
enables a student to both acquire broad knowledge of the field and more detailed
knowledge in a specialization area.
3. Objective: Microelectronics provides an authoritative, international and independent
forum for the critical evaluation and dissemination of research and development,
applications, processes and current practices relating to advanced packaging, micro-
circuit engineering, interconnection, semiconductor technology and systems engineering.
It represents a current, comprehensive and practical information tool.
4. Text Book: T-1: VLSI Technology by SM SZE
T-2: VLSI Technology Fabrication by Dr. B Raj and B.Singh Laxmi Publications
T-3: Silicon VLSI Technology, fundamentals, practice and modeling. By J.
Plummer, Michael D. Deal and Peter B. Griffin; ISBN: 0-13-085037-3, McGraw-
Hill,
2000.
5. Reference Book
R-1: Microelectronics by Millmen and Gagob.

Proposed
Sr. Chapter/
Number of Objective Topics to be covered
No. Section
lectures
Introduction, Evolution of Microelectronics,
Integrated Circuits, Classification Based on
Introduction Applications, Integrated Circuits (IC)
Ch-1
1. 4 VLSI Manufacturing Flow, Fabrication of Bipolar
Fabrication Junction Transistor, N-Mos Fabrication Steps,
Advantages and Disadvantages of Integrated
Circuits
 Environment Introduction , Types of Contamination,
for VLSI Problems Due to Contamination, Clean Room,
2. 4 Ch-2
Technology : Design and Construction of Clean Rooms,
Clean Rooms Wafer Cleaning Techniques
Introduction , Silicon Material Properties,
Crystalline Defects in Silicon, Single Crystal
Silicon Growth Growing for Wafer Production, Production of
3. 4 Ch-3
EGS, Crystal Growth Theory, Different
Methods of Crystal Growth, Required
Properties of Silicon Wafers.
Introduction, Principle of Epitaxial Growth,
Epitaxial Growth Model, Methods for
4. Epitaxial
3 Depositing Epitaxial Films, Molecular Beam Ch-4
Growth
Epitaxy, Applications of Epitaxy, Defects in
Epitaxial Layers.
Introduction, Thin Film Parameters, Deposition
Thin Film
5. 3 Methods, Physical Vapour Deposition (PVD), Ch-5
Deposition
Chemical Vapour Deposition (CVD).
Introduction, Oxide Growth, Oxide Formation,
Oxidation Different Steps of Oxidation Process, Rapid
6. 4 Ch-6
Thermal Processing (RTP), High Pressure
Oxidation, and Oxidation Induced Defects.
Introduction, Definition, Mathematical Analysis
7. 2 Diffusion of Diffusion, Study of Diffusivities of Some Ch-7
Common Dopants, Diffusion Systems
Introduction, Photolithography, Processes of
Photolithography, Basic Steps of
Lithography
8. 3 Photolithography, Spin Coat, E-Beam Ch-8
Lithography (EBL), X-Ray Lithography, Ion
Projection Lithography (IPL).
Introduction, Etching Parameters, Classification
9. 3 Etching of Etching Process, Types of Etchers, Ion Beam Ch-9
Milling.
Introduction, Theory of Ion Implantation, Ion
Ion Implanters, Ion Implant Trends in Process
10. 3 Ch-10
Implantation Integration, Annealing, Channeling,
Applications.
Introduction , Single Level Metallization,
Multilevel Metallization, Metallization
11. 5 Metallization Ch-11
Materials and their Properties, Methods of
Metallization, Metallization Problems
Process Introduction , Basic Device Fabrication
Integration Methods, P-N Junction Diode Fabrication,
12. 2 (Device Bipolar Junction Transistor (BJT) Fabrication, Ch-12
Fabrication) CMOS Fabrication, Problems in VLSI
Fabrication
 Introduction, Purpose of Packaging, Types of
Packaging and
13. 2 Package, Die Attachment Techniques, , Ch-13.
Assembly
Assembly Processes, Assembly Techniques.

*Details of assignments and project will be announced later.

1. Chamber Consultation Hour: To be announced afterwards / in class.
Notices: Notices and solutions will be displayed on notice board
2. Make-up Policy: Very strict: Make up for tests will be given only to genuine cases, i.e. (i)
Sickness leading to hospitalization, (ii) out-of-station for a justifiable reason with prior
intimation to /permission from the IC
3. Evaluation Scheme:

EC Evaluation Weightage Nature of

Duration Date, Time &Venue
No. Component (%) Component

1 Test I 90 min 40 CB

Closed
2 Test II 90 min 40
Book

3 Quizzes/Assignments - 20 CB/OB

End
4 3 hrs. 100 CB
Examination

Navdeep Prashar

Instructor-in-charge
 List of Registered Student

Sr. No. University Roll No. Student Name

1 BU2014UGEC001 ABHISHEK

2 BU2014UGEC002 ASHA PATHANIA

3 BU2014UGEC003 HARSHAD MARCONEY

4 BU2014UGEC004 KOMPAL SINGH

5 BU2014UGEC005 RAHUL SEN

6 BU2014UGEC006 SAKSHAM THAKUR

7 BU2014UGEC007 SAPNA

8 BU2014UGEC008 SHIVANI KATOCH

9 BU2014UGEC009 TENZIN CHEMI

10 BU2015UGECM010 Akshay

11
BU2014UGEC011 Abhijeet Singh

12
BU2014UGEC012 Arun

13
BU2015UGECL013 Reetika Thakur
 ASSIGNMENT -1 Dated-10-02-2017

Q1. What do you mean by ASIC and FPGA?

Q2. Comparison of ASIC and FPGA?

Q3. What is the difference between Embedded System and VLSI?

Q4. How FPGA is low Power?

Q5. What is the scope of VLSI in today’s ERA?

ASSIGNMENT -2 Dated-15-03-2017

Q1. Discuss the significance of Clean room in Fabrication?

Q2. Define wafer and what are steps involved in Wafer Cleaning?

Q3. What is Contamination?

Q4. Discuss the Moore’s Law and its Significance?

ASSIGNMENT -3 Dated -15-04-2017

Q1. Discuss the silicon Material Properties?

Q2. What are the defects in Silicon Crystal?

Q3. Which is more complicated when u have a 48 MHz and 500 MHz clock design?

Q4. What is Gate delay?

Q5. What is cell delay?

Q6. What does synthesis mean?

Q7. What are the different MOS layers?

 SOLUTION of ASSIGNMNETS
Answer 1.
Answer 2
Answer 3
Answer 4
 ID No:-

BAHRA UNIVERSITY, WAKNAGHAT

TEST -1
MICROELECTRONIC CIRCUITS (EC C313)
B.Tech [ECE] (VI Semester/ 3RD Year)
Max. Marks: 40
Time: 90 mins
Note: Attempt all questions

SECTION A (Objective Type Question) 5 marks

a. What do you mean by VLSI? Which technology used in fabrication of IC and Why?
b. Why NMOS technology is preferred more than PMOS technology?
c. What do you mean by Epitaxy?
d. What happens if Vds is increased over saturation?
e. How did you resolve the setup and hold problem in any circuit?

SECTION B (short type question) 20 marks

1 Explain IC manufacturing flow?

2. Describe the various steps involved in the fabrication of N-MOS?

SECTION C (comprehensive question) 15 marks

1 a. what is contamination? Give its types and what are problem arises due to contamination? (5
marks)

b. Explain Ultrasonic cleaning and rinsing and Spin Rinse Dryers processes of Wafer Cleaning
techniques? (5 marks)

c. Discuss the Di-water treatment flow used in fabrication labs? (5 Marks)

 Solution of Test -1

SECTION A

a. Very-large-scale integration (VLSI) is the process of creating integrated circuits by

combining thousands of transistors into a single chip. The fabrication of an IC using
CMOS transistors is known as CMOS Technology. CMOS transistor is nothing but an
inverter, made up of an n-MOS and p-MOS transistor connected in series.
Advantages of CMOS Technology is
Size is less
High Speed
Less Power Dissipation
b. N-channel transistors have greater switching speed when compared to PMOS transistors.
Hence, NMOS is preferred than PMOS.
c. Epitaxy means arranging atoms in single crystal fashion upon a single crystal substrate.

d. Pinch off.

e. Setup: upsize the cells

Hold: insert buffers

SECTION B
2. Fabrication steps are as follows:

Step1:

Processing is carried on single crystal silicon of high purity on which required P impurities are
introduced as crystal is grown. Such wafers are about 75 to 150 mm in diameter and 0.4 mm
thick and they are doped with say boron to impurity concentration of 10 to power 15/cm3 to 10
to the power 16 /cm3.

Step 2:

A layer of silicon di oxide (SiO2) typically 1 micrometer thick is grown all over the surface of
the wafer to protect the surface, acts as a barrier to the dopant during processing, and provide a
generally insulating substrate on to which other layers may be deposited and patterned.

Step 3:

The surface is now covered with the photo resist which is deposited onto the wafer and spun to
an even distribution of the required thickness.

Step 4:

The photo resist layer is then exposed to ultraviolet light through masking which defines those
regions into which diffusion is to take place together with transistor channels. Assume, for
example, that those areas exposed to uv radiations are polymerized (hardened), but that the areas
required for diffusion are shielded by the mask and remain unaffected.

Step 5:

These areas are subsequently readily etched away together with the underlying silicon di oxide
so that the wafer surface is exposed in the window defined by the mask.

Step 6:

The remaining photo resist is removed and a thin layer of SiO2 (0.1 micro m typical) is grown
over the entire chip surface and then poly silicon is deposited on the top of this to form the gate
structure. The polysilicon layer consists of heavily doped polysilicon deposited by chemical
vapour deposition (CVD). In the fabrication of fine pattern devices, precise control of thickness,
impurity concentration, and resistivity is necessary

Step 7:

Further photo resist coating and masking allows the poly silicon to be patterned and then the thin
oxide is removed to expose areas into which n-type impurities are to be diffused to form the
source and drain. Diffusion is achieved by heating the wafer to a high temperature and passing a
gas containing the desired n-type impurity.

Step 8:

Thick oxide (SiO2) is grown over all again and is then masked with photo resist and etched to
expose selected areas of the poly silicon gate and the drain and source areas where connections
are to be made. (Contacts cut)

SECTION C

1 a. Contamination is the presence of a minor and unwanted constituent in a material.

TYPES OF CONTAMINATION

Particle Contaminants: Semiconductor devices are sensitive to all kind of cantaminants, the
sensitivity is due to the small feature size and thinness of deposited layer on the wafer surface.
1b.
2. Di Water Treatment Flow
 ID No:-

BAHRA UNIVERSITY, WAKNAGHAT

TEST -2

MICROELECTRONIC CIRCUITS (EC C313)

B.Tech [ECE] (VI Semester/ 3RD Year)

Max. Marks: 40 Time: 90 mins

Note: Attempt all questions

PART-I (Objective Type Question) 5 marks

a. Leakage power is inversely proportional to ___.

a. Frequency b. Load Capacitance
c. Supply voltage d. Threshold Voltage

b. Pitch of the wire is ___.

a. Min width b. Min spacing
c. Min width - min spacing d. Min width + min spacing
c. What is the effect of high drive strength buffer when added in long net?
a. Delay on the net increases b. Capacitance on the net increases
c. Delay on the net decreases d. Resistance on the net increases.
d. Which is more complicated when u have a 48 MHz and 500 MHz clock design
e. What are the problems faced related to timing?
PART-II (short type question) 20 marks

1(a). Explain Epitaxial Groove Model?

(b).Explain Molecular Beam Epitaxy?

2. Explain Crystal Growth by Czocharalski Method?

PART-III (comprehensive question) 15 marks

1 Explain the principle of Chemical Vapour Deposition and also discuss Plasma Enhanced CVD?(10
Marks)

b. Compare the Evaporation and Sputtering Process of Thin Film Deposition? (5 Marks)
 Solution of TEST-2

Section A

a. Threshold Voltage
b. Min width + min spacing
c. Delay on the net decreases
d. 500 MHz; because it is more constrained (i.e. lesser clock period) than 48 MHz
design
e. Prelayout: Setup, Max transition, max capacitance
Post layout: Hold

Section B

1a.

Epitaxial Groove Model

b. Molecular Beam Epitaxy
2. Crystal Growth by Czocharalski Method

Czochralski crystal" by filling a suitable crucible with the material - here hyperpure correctly
doped Si pieces obtained by crushing the poly-Si from the Siemens process. Take care to keep
impurities out - do it in a clean room - and use hyper pure silica for your crucible.

Make sure that the inside of the machine is very clean too and that the gas flow - the gas
you introduce but also the SiO coming from the molten Si because parts of the crucible
dissolve - does not interfere with the growing crystal.

Dissolve the Si in the crucible and keep its temperature close to the melting point. Since
you cannot avoid temperature gradients in the crucible, there will be some convection in the
liquid Si. You may want to suppress this by big magnetic fields.

Insert your seed crystal, adjust the temperature to "just right", and start withdrawing the
seed crystal. For homogeneity, rotate the seed crystal and the crucible. Rotation
directions and speeds and their development during growth, are closely guarded secrets!

First pull rather fast - the diameter of the growing crystal will decrease to a few mm. This
is the "Dash process" ensuring that the crystal will be dislocation free even though the seed
crystal may contain dislocations.
Now decrease the growth rate - the crystal diameter will increase - until you have the
desired diameter and commence to grow the commercial part of your crystal at a few
mm/second.

Czochralski process is a method of crystal growth used to obtain single crystals of

semiconductors (e.g. silicon, germanium and gallium arsenide), metals (e.g. palladium,
platinum, silver, gold), salts and synthetic gemstones. The process is named after Polish
scientist Jan Czochralski, who invented the method in 1916 while investigating the
crystallization rates of metals.
The most important application may be the growth of large cylindrical ingots, or boules,
of single crystal silicon. Other semiconductors, such as gallium arsenide, can also be
grown by this method, although lower defect densities
 SECTION C

1. a. CHEMICAL VAPOUR DEPOSITION

PLASMA ENHANCED CVD
b.
 Bahra University, Waknaghat

End Term Examination, June 2013

MICROELECTRONIC CIRCUITS (EC C313)

Max. Marks: 100 Time:

3hrs.
_____________________________________________________________________________________

PART –I (Attempt all) (10x2=20)

Q1.

(a) What is the size of Silicon wafer currently used for the manufacture of IC's?

(b) What is the current commercial device feature size?

(c) Explain the application of SiO2 layer in IC fabrication

(d) Compare ion implantation process with diffusion

(e) What is the role of diffusion in IC fabrication?

(f) What are the dimensions of an IC?

(g) What is the purpose of masking in the fabrication of IC?

(h) What is CMOS Technology? Why this technology used in VLSI?

(i) Why NMOS technology is preferred more than PMOS technology.

(j) Explain Flick’s law of diffusion?

PART –II (Attempt any four) (4x10=40)

Q2. Explain design and construction of Clean room?

Q3. What is the failure rate in metal interconnects? How it can be reduced.

Q4. What is etching? Explain wet chemical etching techniques.

Q5.Explain the concept of metallization? Describe briefly the Chemical Mechanical Polarization Method.

Q6. What is Moore's Law? Explain its relevance with respect to evolution of IC technology.

Q7. Discuss different steps in preparing wafers from raw silicon.

PART-III (Attempt any two) (2x 20=40)

Q.8 Explain chemical vapour depositions techniques used for deposition of polysilicon?

Q.9 what is photolithography? Explain any two photolithography techniques?

Q.10 a. Compare Horizontal tube furnace with vertical tube furnace for oxidation?

b. Explain Liquid source and Gaseous source Diffusion system?

 Solution of Final
Q1. a. wafer sizes from 100–300 mm diameter.

b. feature size of 0.18 m with a silicon film thickness of 110 nm and internal core voltage of 1.6 V.

c. Silicon Dioxide is an excellent electrical insulator, a mask to common diffusing species, and capable of
forming a nearly perfect electrical interface with its substrate.

d. Diffusion is an isotropic process and so there is lateral diffusion whereas ion implantation is isotropic and
very directional.

Thermal diffusion usually takes place at higher temperature whereas ion implantation is a low temperature process.

We can control the exact amount of dopant in ion implantation unlike diffusion.

Thermal diffusion is non-destructive whereas ion implantation damages the crystalline structure and so needs
annealing.

Ion implantation is more expensive than diffusion.

e. Form the base and emitter in bipolar transistors

Form integrated resistors

Form the source/drain regions in MOS transistors

Dope polysilicon gates in MOS transistors

f. Dimensions of an IC are 1.65 x 1.65 mm

g. Masking is used to identify the location in which Ion-Implantation should not take place.

h. The fabrication of an IC using CMOS transistors is known as CMOS Technology. CMOS transistor is nothing
but an inverter, made up of an n-MOS and p-MOS transistor connected in series.
i. N-channel transistors have greater switching speed when compared to PMOS transistors. Hence, NMOS is
preferred than PMOS.

j. The flux density is directly proportional to the concentration gradient. Flux Density is defined as the rate of
transfer of dopant per unit area.
 PART II

Q2. Design and Construction of Clean room.

A cleanroom is a controlled environment where products are manufactured. It is a room in which the concentration
of airborne particles is controlled to specified limits. Eliminating sub-micron airborne contamination is really a
process of control. These contaminants are generated by people, process, facilities and equipment. They must be
continually removed from the air. The level to which these particles need to be removed depends upon the standards
required. The most frequently used standard is the Federal Standard 209E. The 209E is a document that establishes
standard classes of air cleanliness for airborne particulate levels in cleanrooms and clean zones. Strict rules and
procedures are followed to prevent contamination of the product.

The only way to control contamination is to control the total environment. Air flow rates and direction,
pressurization, temperature, humidity and specialized filtration all need to be tightly controlled. And the sources of
these particles need to controlled or eliminated whenever possible. There is more to a clean room than air filters.
Cleanrooms are planned and manufactured using strict protocol and methods. They are frequently found in
electronics, pharmaceutical, biopharmaceutical, medical device industries and other critical manufacturing
environments.

It only takes a quick monitor of the air in a cleanroom compared to a typical office building to see the
difference. Typical office building air contains from 500,000 to 1,000,000 particles (0.5 microns or larger) per cubic
foot of air. A Class 100 cleanroom is designed to never allow more than 100 particles (0.5 microns or larger) per
cubic foot of air. Class 1000 and Class 10,000 cleanrooms are designed to limit particles to 1000 and 10,000
respectively.

A human hair is about 75-100 microns in diameter. A particle 200 times smaller (0.5 micron) than the
human hair can cause major disaster in a cleanroom. Contamination can lead to expensive downtime and increased
production costs. In fact, the billion dollar NASA Hubble Space Telescope was damaged and did not perform as
designed because of a particle smaller than 0.5 microns.

Once a cleanroom is built it must be maintained and cleaned to the same high standards. This handbook has
been prepared to give professional cleaning staff information about how to clean the cleanroom.

EPA (High Efficiency Particulate Air Filter)- These filters are extremely important for maintaining contamination
control. They filter particles as small as 0.3 microns with a99.97% minimum particle-collective efficiency.

CLEANROOM ARCHITECTURE - Cleanrooms are designed to achieve and maintain a airflow in which
essentially the entire body of air within a confined area moves with uniform velocity along parallel flow lines. This
air flow is called laminar flow. The more restriction of air flow the more turbulence. Turbulence can cause particle
movement.

FILTRATION - In addition to the HEPA filters commonly used in cleanrooms, there are a number of other
filtration mechanisms used to remove particles from gases and liquids. These filters are essential for providing
effective contamination control.

CLEANING - Cleaning is an essential element of contamination control. Decisions need to made about the details
of cleanroom maintenance and cleaning. Applications and procedures need to be written and agreed upon by
cleanroom management and contractors (if used). There are many problems associated with cleaning. Managers
need to answer the following questions before proceeding with any cleanroom cleaning program

HUMANS IN CLEANROOMS - There are both physical and psychological concerns when humans are present in
cleanrooms. Physical behavior like fast motion and horseplay can increase contamination. Psychological concerns
like room temperature, humidity, claustrophobia, odors and workplace attitude are important. Below are several
ways people produce contamination:

1. Body Regenerative Processes-- Skin flakes, oils, perspiration and hair.

2. Behavior-- Rate of movement, sneezing and coughing.

3. Attitude-- Work habits and communication between workers.

List of Some of Equipment and Supplies Needed to Clean the Cleanroom

1. Cleaning and disinfecting solutions

2. Cleanroom mops

3. Cleanroom vacuum cleaner (if allowed)

4. Cleanroom wipers

5. Cleanroom mop bucket and wringer

List of Cleaning Tasks to be completed in the Cleanroom

Cleaning of all work surfaces in the controlled environment.

2. Vacuuming (if allowed) of the floors and work surfaces.

3. Emptying of appropriate trash and waste.

4. Cleaning of the doors, door frames and lockers in the pre-staging area and gowning

5. Mop gowning and cleanroom floors.

Air flow principles

Air flow pattern for "Turbulent Cleanroom" Air flow pattern for "Laminar Flow Cleanroom"

Cleanrooms can be very large. Entire manufacturing facilities can be contained within a cleanroom with factory
floors covering thousands of square meters. They are used extensively in semiconductor manufacturing,
biotechnology, the life sciences and other fields that are very sensitive to environmental contamination.
The air entering a cleanroom from outside is filtered to exclude dust, and the air inside is constantly recirculated
through high-efficiency particulate air (HEPA) and/or ultra-low penetration air (ULPA) filters to remove internally
generated contaminants.

Staff enter and leave through airlocks (sometimes including an air shower stage), and wear protective clothing such
as hoods, face masks, gloves, boots and coveralls.

Equipment inside the cleanroom is designed to generate minimal air contamination. Only special mops and buckets
are used. Cleanroom furniture is designed to produce a minimum of particles and to be easy to clean.

Common materials such as paper, pencils, and fabrics made from natural fibers are often excluded, and alternatives
used. Cleanrooms are not sterile (i.e., free of uncontrolled microbes);[2] only airborne particles are controlled.
Particle levels are usually tested using a particle counter.

Some cleanrooms are kept at a positive pressure so that if there are any leaks, air leaks out of the chamber instead of
unfiltered air coming in.

Some cleanroom HVAC systems control the humidity to low levels, such that extra equipment ("ionizers") is
necessary to prevent electrostatic discharge (ESD) problems.

Low-level cleanrooms may only require special shoes, with completely smooth soles that do not track in dust or dirt.
However, for safety reasons, shoe soles must not create slipping hazards. Access to a cleanroom is usually restricted
to those wearing a cleanroom suit.[3]

In cleanrooms in which the standards of air contamination are less rigorous, the entrance to the cleanroom may not
have an air shower.

Diagram Of Clean room

Q3. Failure rate of metal interconnections in semiconductor integrated circuits due to electro migration is presented.
The defects of interest are missing material that reduces the effective cross section of the conductor at the point of
the defect. Reliability measures for the conductor are computed from a given defect distribution. These defects
appreciably increase conductor failure rate during early life but have little effect on median life for line widths above
1 μm. However, for defect densities typically encountered in current semiconductor manufacturing environments a
rapid decrease in median life is predicted for conductors less than 0.30 μm wide.

Some of the common mechanisms can be mitigated by adhering to foundry design rules(Electro migration, Time
Dependent Dielectric Breakdown (TDDB), and Hot Carrier Damage).Certain fabrication steps can cause stress that
may lead to latent damage that may later reduce the useful lifetime of an ASIC. Contamination with Mobile Ions
(most commonly Sodium) will render transistor characteristics unstable and encourage early TDDB. Process
Induced Oxide Charging, caused by injection of charge into gate oxides during certain ion etching processes, will
reduce TDDB lifetime and cause some transistor degradation similar to Hot Carrier Damage. Metal Stress
Migration, which is caused by large thermal coefficient of expansion difference between metal interconnect and
inter-level dielectrics (oxides), can lead to voiding of metal lines similar to damage caused by Electro migration.
Foundries will expend great effort to control the above fabrication related failure mechanisms by designing the
fabrication process to minimize the unnecessary stresses applied to wafers and to maintain an absolutely clean
fabrication process to eliminate contamination (by Sodium and other materials.

Electro migration is the diffusion of metal atoms along the conductor in the direction of electron flow. This
directional diffusion process occurs because the momentum transfer between the electrons and the metal atoms
increases the probability that an aluminum atom will move in the direction of the electron flow. Since the mass of
the electron is very much smaller than aluminum atoms the transfer of momentum is only enough to have a
statistical effect upon the diffusion of aluminum. This diffusion process will preferentially fill metal ion vacancies
found in crystal defects, leaving a vacancy in the location from which the metal atom came. Aluminum conductors
in IC’s are comprised of a large number of small crystal domains with random crystal axis orientation. Most of the
vacancy sites lie in the interfaces between these crystal domains. As a result, the preferential diffusion paths are
along crystal boundaries where the majority of the vacancies exist. High current density in the aluminum wires will
cause the metal ion diffusion to flow along the crystal boundaries in the general direction of electron flow.
The flow of metal ions in the direction of electron flow in itself does not cause damage to the aluminum wires.
Damage only occurs when there is a metal ion flux divergence that causes metal ions to be taken from one part of a
wire and deposit them in some other location without replenishing the metal ions from a reservoir. The flux
divergence causes vacancies to coalesce in
one location to produce a void.

Q4. Etching is used in microchip fabrication to chemically remove layers from the surface of a wafer during
manufacturing. Etching is based on the removal of undesired material or layer by immersing the wafer in to a
solution which reacts with the exposed film to form by by-products.

The first etching processes used liquid-phase ("wet") etchants. The wafer can be immersed in a bath of etchant,
which must be agitated to achieve good process control. For instance, buffered hydrofluoric acid (BHF) is used
commonly to etch silicon dioxide over a silicon substrate.

Different specialized etchants can be used to characterize the surface etched.

Wet etchants are usually isotropic, which leads to large bias when etching thick films. They also require the disposal
of large amounts of toxic waste. For these reasons, they are seldom used in state-of-the-art processes. However, the
photographic developer used for photoresist resembles wet etching.

As an alternative to immersion, single wafer machines use the Bernoulli principle to employ a gas (usually, pure
nitrogen) to cushion and protect one side of the wafer while etchant is applied to the other side. It can be done to
either the front side or back side. The etch chemistry is dispensed on the top side when in the machine and the
bottom side is not affected. This etch method is particularly effective just before "backend" processing (BEOL),
where wafers are normally very much thinner after wafer back grinding, and very sensitive to thermal or mechanical
stress. Etching a thin layer of even a few micrometers will remove micro cracks produced during back grinding
resulting in the wafer having dramatically increased strength and flexibility without breaking.

Immersion wet Etching

Q5
Q6. Moore's law is the observation that over the history of computing hardware, the number of transistors on
integrated circuits doubles approximately every two years. The period often quoted as "18 months" is due to Intel
executive David House, who predicted that period for a doubling in chip performance (being a combination of the
effect of more transistors and their being faster).

The law is named after Intel co-founder Gordon E. Moore, who described the trend in his 1965 paper. [2][3][4] The
paper noted that the number of components in integrated circuits had doubled every year from the invention of the
integrated circuit in 1958 until 1965 and predicted that the trend would continue "for at least ten years". His
prediction has proven to be uncannily accurate, in part because the law is now used in the semiconductor industry to
guide long-term planning and to set targets for research and development.

The capabilities of many digital electronic devices are strongly linked to Moore's law: processing speed, memory
capacity, sensors and even the number and size of pixels in cameras. All of these are improving at (roughly)
exponential rates as well. This exponential improvement has dramatically enhanced the impact of digital electronics
in nearly every segment of the world economy. Moore's law describes a driving force of technological and social
change in the late 20th and early 21st centuries.

This trend has continued for more than half a century. Sources in 2005 expected it to continue until at least 2015 or
2020. However, the 2010 update to the International Technology Roadmap for Semiconductors has growth slowing
at the end of 2013, after which time transistor counts and densities are to double only every three years.
Q7.Several measures of digital technology are improving at exponential rates related to Moore's law, including the
size, cost, density and speed of components. Moore himself wrote only about the density of components (or
transistors) at minimum cost.

Transistors per integrated circuit. The most popular formulation is of the doubling of the number of transistors on
integrated circuits every two years. At the end of the 1970s, Moore's law became known as the limit for the number
of transistors on the most complex chips. The graph at the top shows this trend holds true today.

Density at minimum cost per transistor. This is the formulation given in Moore's 1965 paper.] It is not just about
the density of transistors that can be achieved, but about the density of transistors at which the cost per transistor is
the lowest.[23] As more transistors are put on a chip, the cost to make each transistor decreases, but the chance that
the chip will not work due to a defect increases. In 1965, Moore examined the density of transistors at which cost is
minimized, and observed that, as transistors were made smaller through advances in photolithography, this number
would increase at "a rate of roughly a factor of two per year”. Current state-of-the-art photolithography tools use
deep ultraviolet (DUV) light from excimer lasers with wavelengths of 248 and 193 nm — the dominant lithography
technology today is thus also called "excimer laser lithography"which has enabled minimum feature sizes in chip
manufacturing to shrink from 0.5 micrometer in 1990 to 45 nanometers and below in 2010. This trend is expected to
continue into this decade for even denser chips, with minimum features approaching 10 nanometers. Excimer laser
lithography has thus played a critical role in the continued advance of Moore's law for the last 20 years.

Q7.

Wafer products are measured at various stages of the process to identify defects inducted by the manufacturing
process. This is done to eliminate unsatisfactory wafer materials from the process stream and to sort the wafers into
batches of uniform thickness and at a final inspection stage. These wafers will become the basic raw material for
new integrated circuits. The following is a summary of the steps in a typical wafer manufacturing process.

Crystal Growth and Wafer Slicing Process

The first step in the wafer manufacturing process is the formation of a large, perfect silicon crystal. The crystal is
grown from a ‘seed crystal’ that is a perfect crystal. The silicon is supplied in granular powder form, then melted in
a crucible. The seed is immersed carefully into the crucible of molten silicon, then slowly withdrawn.
Step 1: Obtaining the Sand
The sand used to grow the wafers has to be a very clean and good form of silicon. For this reason not just
any sand scraped off the beach will do.
Step 2: Preparing the Molten Silicon Bath
The sand (SiO2)is taken and put into a crucible and is heated to about 1600 degrees C – just above its
melting point. The molten sand will become the source of the silicon that will be the wafer.
Step 3: Making the Ingot
A pure silicon seed crystal is now placed into the molten sand bath. This crystal will be pulled out slowly as it is
rotated. The dominant technique is known as the Czochralski (cz) method. The result is a pure silicon cylinder that is
called an ingot. This step is done to provide a good clean surface for later processing. If a layer of Silicon is grown
onto the top of the wafer using chemical methods then that layer is of a much better quality then the slightly
damaged or unclean layer of silicon in the wafer. The epitaxial layer is where the actual processing will be done.
The diameter of the silicon ingot is determined by the temperature variables as well as the rate at which the ingot is
withdrawn. When the ingot is the correct length, it is removed, and then ground to a uniform external surface and
diameter. Each of the wafers is given either a notch or a flat edge that will be used later in orienting the wafer into
the exact position for later procedures. In these two figures you can see a notch (above) and flats. Flatsin this image
are exaggerated for clarity.
Step 4: Preparing the Wafers
After the ingot is ground into the correct diameter for the wafers, the silicon ingot is sliced into very thin wafers.
This is usually done with a diamond saw.

PART-III

Q8. Chemical vapor deposition (CVD) is a chemical process used to produce high-purity, high-performance solid
materials. The process is often used in the semiconductor industry to produce thin films. In a typical CVD process,
the wafer (substrate) is exposed to one or more volatile precursors, which react and/or decompose on the substrate
surface to produce the desired deposit. Frequently, volatile by-products are also produced, which are removed by gas
flow through the reaction chamber.

Microfabrication processes widely use CVD to deposit materials in various forms, including: monocrystalline,
polycrystalline, amorphous, and epitaxial. These materials include: silicon, carbon fiber, carbon nanofibers,
filaments, carbon nanotubes, SiO2, silicon-germanium, tungsten, silicon carbide, silicon nitride, silicon oxynitride,
titanium nitride, and various high-k dielectrics. The CVD process is also used to produce synthetic diamonds.

Classified by operating pressure:

Atmospheric pressure CVD (APCVD) – CVD process at atmospheric pressure.

Low-pressure CVD (LPCVD) – CVD process at sub-atmospheric pressures.[1] Reduced pressures tend to reduce
unwanted gas-phase reactions and improve film uniformity across the wafer.

Ultrahigh vacuum CVD (UHVCVD) – CVD process at very low pressure, typically below 10 −6 Pa (~10−8 torr). Note
that in other fields, a lower division between high and ultra-high vacuum is common, often 10−7 Pa.

Atmospheric Pressure CVD

APCVD is a CVD method at normal pressure (atmospheric pressure) which is used for deposition of doped and
undoped oxides. The deposited oxide has a low density and the coverage is moderate due to a relatively low
temperature. Because of improved tools, the APCVD undergoes a renaissance. The high wafer throughput is a big
advantage of this process.

As process gases silane SiH4 (highly deluted with nitrogen N2) and oxygen O2 are used. The gases are decomposed
thermal at about 400 °C and react with each other to form the desired film.

SiH4 + O2→SiO2 + 2H2 (T = 430 °C, p = 105 °Pa)

Added ozone O3 can cause a better conformity because it improves the movability of the accumulated particles. The
oxide is porous and electrical instable and can be densified by a high temperature process.
To avoid edges which can result in difficulties at the deposition of additional layers, phosphorus silicate glass (PSG)
is used for interlayers. Therefor phosphine is added to SiH4 and O2, so that the deposited oxide contains 4 to 8 %
phosphorus. A high amount of phosphorus leads to a high increase of the flow properties, however, phosphoric acid
can be formed which corrodes aluminum (conductor paths).

Because annealing affects earlier processes (e.g. doping) only short tempering is done with powerful argon lamps
(several hundrets kW, less than 10s, T = 1100 °C) instead of annealing in longsome furnace processes.

Analog to PSG boron can be added simultaneously (boron phosphorus silicate glass, BPSG, 4 % B and 4 % P).

Low-pressure CVD (LPCVD)

In LPCVD a vacuum is used. Thin films of silicon nitride (Si3N4), silicon oxynitride (SiON), SiO2 und tungsten (W)
can be created. LPCVD processes enable a high conformity of almost 1. This is because of the low pressure of 10 to
100 Pa (atmospheric pressure = 100.000 Pa) which leads to a non-uniform movement of the particles. The particles
dispread due to collisions and cover vertical surfaces as well as horizontal ones. The conformity is supported by a
high temperature of up to 900 °C. Compared to APCVD the density and stability is very high.

The reactions for Si3N4, SiON, SiO2 and tungsten are as follows:

a) Si3N4 (850 °C): 4NH3 + 3SiH2Cl2→Si3N4 + 6HCl + 6H2

b) SiON (900 °C): NH3 + SiH2Cl2 + N2O→Si3N4 + Nebenprodukte
c) SiO2 (700 °C): SiO4C8H20→SiO2 + Nebenprodukte
d) Wolfram (400 °C): WF6 + 3H2→W + 6HF

In contrast to gaseous precursors which are used for Si3N4, SiON and tungsten, liquid tetraethyl orthosilicate is used
for SiO2. Besides there are other liquid sources like DTBS (SiH 2C8H20) or tetramethylcyclotetrasiloxane (TMTCS,
Si4O4C4H16)

A tungsten film can only be fabricated on bare silicon. Therefore silane has to be added if there is no silicon
substrate.
PECVD: Plasma Enhanced CVD

The PECVD takes place at 250 to 350 °C. Due to low temperatures the process gases can not be decomposited
thermal. With a high frequency voltage, the gas is transformed into a plasma state. The plasma is energetic and
disposes on the surface. Because metallization, such as aluminum, can not be exposed to high temperatures, the
PECVD is used for SiO2 and Si3N4 deposition on top of metal layers. Instead of SiH2Cl2 silane is used because it
decomposes at lower temperature. The conformity is not as good as in LPCVD (0.6 to 0.8), however, the deposition
rate is much higher (0.5 microns per minute).

Q8. Photolithography, , is a process used in micro fabrication to pattern parts of a thin film or the bulk of a
substrate. It uses light to transfer a geometric pattern from a photo mask to a light-sensitive chemical "photoresist",
or simply "resist," on the substrate. A series of chemical treatments then either engraves the exposure pattern into, or
enables deposition of a new material in the desired pattern upon, the material underneath the photo resist. For
example, in complex integrated circuits, a modern CMOS wafer will go through the photolithographic cycle up to 50
times.

Photolithography shares some fundamental principles with photography in that the pattern in the etching resist is
created by exposing it to light, either directly (without using a mask) or with a projected image using an optical
mask. This procedure is comparable to a high precision version of the method used to make printed circuit boards.
Subsequent stages in the process have more in common with etching than with lithographic printing. It is used
because it can create extremely small patterns (down to a few tens of nanometers in size), it affords exact control
over the shape and size of the objects it creates, and because it can create patterns over an entire surface cost-
effectively. Its main disadvantages are that it requires a flat substrate to start with, it is not very effective at creating
shapes that are not flat, and it can require extremely clean operating conditions.
Electronic Beam lithography

Electron beam lithography (often abbreviated as e-beam lithography) is the practice of emitting a beam of
electrons in a patterned fashion across a surface covered with a film (called the resist) ("exposing" the resist) and of
selectively removing either exposed or non-exposed regions of the resist ("developing"). The purpose, as with
photolithography, is to create very small structures in the resist that can subsequently be transferred to the substrate
material, often by etching. It was developed for manufacturing integrated circuits, and is also used for creating
nanotechnology architectures.

The primary advantage of electron beam lithography is that it is one of the ways to beat the diffraction limit of light
and make features in the nanometer regime. This form of maskless lithography has found wide usage in photo mask-
making used in photolithography, low-volume production of semiconductor components, and research &
development.

The key limitation of electron beam lithography is throughput, i.e., the very long time it takes to expose an entire
silicon wafer or glass substrate. A long exposure time leaves the user vulnerable to beam drift or instability that may
occur during the exposure. Also, the turn-around time for reworking or re-design is lengthened unnecessarily if the
pattern is not being changed the second time.

Ion beam lithography

Ion beam lithography is the practice of scanning a focused beam of ions in a patterned fashion across a surface in
order to create very small structures such as integrated circuits or other nanostructures.

Ion beam lithography has been found to be useful for transferring high-fidelity patterns on three-dimensional
surfaces.

Ion beam lithography offers higher resolution patterning than UV, X-ray, or electron beam lithography because
these heavier particles have more momentum. This gives the ion beam a smaller wavelength than even an e-beam
and therefore almost no diffraction. The momentum also reduces scattering in the target and in any residual gas.
There is also a reduced potential radiation effect to sensitive underlying structures compared to x-ray and e-beam
lithography.[3]

Ion beam lithography, or ion projection lithography, is similar to Electron beam lithography, but uses much heavier
charged particles, ions. In addition to diffraction being negligible, ions move in straighter paths than electrons do
both through vacuum and through matter, so there seems be a potential for very high resolution. Secondary particles
(electrons and atoms) have very short range, because of the lower speed of the ions. On the other hand, intense
sources are more difficult to make and higher acceleration voltages are needed for a given range. Due to the higher
energy loss rate, higher particle energy for a given range and the absence of significant space charge effects, shot
noise will tend to be greater.

Fast moving ions interact differently with matter than electrons do, and, due to their higher momentum, their optical
properties are different. They have much shorter range in matter and move straighter through it. At low energies, at
the end of the range, they lose more of their energy to the atomic nuclei, rather than to the atoms, so that atoms are
dislocated rather than ionized. If the ions don't defuse out of the resist, they dope it. The energy loss in matter
follows a Bragg curve and has a smaller statistical spread. They are "stiffer" optically, they require larger fields or
distances to focus or bend. The higher momentum resists space charge effects.

Collider particle accelerators have shown that it is possible to focus and steer high momentum charged particles with
very great precision.
Q9.b.

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