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Assignment 3: EE 668

This document outlines an assignment with 4 problems related to RC circuits, wire capacitance modeling, and signal delay in interconnects. Problem 1 involves calculating the time it takes for the voltage across a capacitor in an RC circuit to drop to 50% of its initial value. Problem 2 uses an Elmore time constant model to estimate this time constant. Problem 3 calculates the per-unit-length capacitance between adjacent and non-adjacent wires based on their dimensions and spacing. Problem 4 uses SPICE simulation to determine signal delay as a function of wire length, and calculates the critical wire length at which a buffer should be inserted to reduce delay.

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86 views2 pages

Assignment 3: EE 668

This document outlines an assignment with 4 problems related to RC circuits, wire capacitance modeling, and signal delay in interconnects. Problem 1 involves calculating the time it takes for the voltage across a capacitor in an RC circuit to drop to 50% of its initial value. Problem 2 uses an Elmore time constant model to estimate this time constant. Problem 3 calculates the per-unit-length capacitance between adjacent and non-adjacent wires based on their dimensions and spacing. Problem 4 uses SPICE simulation to determine signal delay as a function of wire length, and calculates the critical wire length at which a buffer should be inserted to reduce delay.

Uploaded by

Chiquita White
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Assignment 3: EE 668

Madhav P. Desai
February 11, 2011

1 Assignment
1. Consider the RC circuit shown in Figure 1. Find the time t50 at which
the voltage V2 (t) drops to 50% of its initial value.
2. Find the Elmore time-constant for the discharge of V2 (t) (in Figure 1).
From this, estimate the value of t50 and compare with the exact calculation
in the previous problem.
3. In a 180nm technology, you are using wires which are 1µ thick and 270nm
wide to transmit information. The wires are densely spaced, and the
centre-to-centre spacing of adjacent wires is 540nm.
(a) Find the per-unit-length capacitance between adjacent wires.
(b) Find the per-unit-length capacitance between two wires that have a
single wire in between them.
This gives you some idea of the effectiveness of shielding in reducing
coupling/cross-talk effects.
4. Consider a wire as described in the previous problem. Assume that its
neighbours are shield wires, and are tied to ground. The wire is made
of Aluminium and is driven by a 180nm buffer (inverter) in the TSMC
technology with λ = 90nm (as used in Assignment 1) with Wp = 20λ,
Lp = 2λ, Wn = 10λ and Ln = 2λ. The wire is terminated in an identical
receiver buffer.
(a) Assume that you are not allowed to place buffers in the wire. Using
NGSPICE, obtain a plot of the delay from the rising of the input
of the driver to the falling of the input of the receiver buffer as a
function of the wire length (from 10µ to 1cm).
(b) Suppose that you wish to place buffers (assume that each buffer is
identical to the driver) in the wire in order to reduce the signal delay.
What is the critical length at which you will insert a new buffer?

1
1Ohm 3Ohm
+
t=0 3F 1F V2(t)
−

both capacitors initially charged


to 1V
Figure 1: RC circuit

(c) Observe that if the rise/fall delay of the driver is not the same, then
the critical length for the rise delay case will be different from the
critical length for the fall delay case. In such situations, we normally
compute the critical length using the average delay.

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