Temperature Sensor Placement in Thermal
Management Systems for MPSoCs
Francesco Zanini† , David Atienza , Colin N. Jones‡ , Giovanni De Micheli†
† Laboratory of Integrated Systems (LSI), EPFL, Switzerland
Embedded Systems Laboratory (ESL), EPFL, Switzerland
‡ Automatic Control Laboratory, ETH Zurich, Switzerland
Abstract— Modern high-performance processors employ ther- II. R ELATED W ORK
mal management systems, which rely on accurate readings
Temperature management at system-level has been pre-
of on-die thermal sensors. Systematic tools for analysis and
determination of best allocation and placement of thermal sensors sented in [7]- [12]. Several groups have addressed the problem
is therefore a highly relevant problem. This paper proposes a of thermal modelling and simulation at different levels of
novel technique for determining the placement of temperature abstraction. Finite-difference time domain [14], [15] based
sensors on complex Multi-Processor Systems-on-Chips (MPSoCs) algorithms have been proposed. In [16] a thermal/power model
floorplans. The proposed method first analyzes the observability
for super-scalar architectures is presented. One problem related
of the system for all the possible sensor placement configurations.
Minimum sensors placements ensuring the observability of the to all these techniques is that they require on-line thermal
portion of the MPSoC system that is relevant to the designer profile information from the chip in order to perform the
are then compared with simulation-based data coming from frequency and voltage assignment optimization.
a wide set of benchmarks. Pareto points identifying the best A study of the thermal profile estimation problem has
configurations are than stored. According to user designer needs been analyzed in [5] and [6]. The proposed solutions are
the best configuration is selected and a specific location is assigned
to each sensor. We compared the proposed method with state-of- based on techniques trying to reduce temperature differences
the-art approaches [5], [6]. Results show a reduction up to 4.5× between thermal sensors and hot-spots by using the minimum
in the number of required sensors. number possible of sensors for a certain accuracy. The problem
with these approaches is that since hot-spots are application
dependent, there is no guarantee that all hot-spots are detected
I. I NTRODUCTION during the lifetime of the device.
In [17] the authors select the location of the sensing element
according to a gramian-based sensor strategy. In [18] the prob-
The number of functional units and cores integrated on
lem of making a system observable is solved by employing of
a chip is increasing. Examples include the Sun’s Niagara
graph theory. The problem of choosing a set of measurements
[2] and the Tilera’s 64-core architecture [3]. This increase
from a much larger set that also minimizes the estimation error
in capability of MPSoCs is leading to an increase in chip
is solved by [19] using a convex optimization based approach.
power dissipation, which in turn leads to significant increase
This last method approximately solves the problem and has no
in chip temperature. Temperature gradients and hot-spots not
guarantee that the performance gap is always small.
only affect the performance of the system, but also lead to
unreliable circuit operation and affect the life-time of the chip III. P ROPOSED M ETHOD
[4]. Meeting temperature constraints and reducing hot-spots is A. Thermal model
indeed an important and difficult challenge facing the MPSoC To model the thermal properties of the MPSoC, we use the
designers. Thus thermal management approaches have been finite element model presented in [16] and [15]. The model
proposed [7]- [12], but all these techniques require on-line is composed by two types of layers: the silicon layer and the
thermal profile information from the chip to perform frequency heat-spreading copper layer. The chip floorplan is divided into
assignment optimization. several thermal cells of cubic shape. Every single functional
In this work we focus on the thermal sensors placement unit in the floorplan can be represented by one or more thermal
problem. Our goal is to minimize the number of sensors while cells of the silicon layer. Thermal modelling is computed
maximizing the thermal profile estimation accuracy. considering the heat conductances and capacitances of the cells
We propose a novel approach for choosing a sensor con- as computed and validated in [16] and [15]. The differential
figuration based on observability analysis. This is a general equations modelling the heat flow are given by solving this
approach that can be potentially applied to any MPSoC network. Many methods and ODE solvers can be used. A
architecture. In this work, we validated the system using a survey on these methods is reported in [13].
commercial MPSoC from SUN. We compare the resulting sen- The thermal model that we want to represent is slightly
sor placement with state-of-the-art algorithms. Results show a nonlinear since coefficients are temperature-dependent (rela-
reduction up to 4.5× in the number of required sensors. tive error in the order of 0.16%) [15]. To represent the thermal
978-1-4244-5309-2/10/$26.00 ©2010 IEEE 1065
model using a linear, time invariant discrete-time system, the
solution of the differential equations modelling the heat flow
inside the MPSoC has been linearized. The rationale behind
it is described in [13], [16] and [15]. In the sequel we assume
that the k th temperature measurement is done at time tk . The
system can be represented with the equations:
x(k + 1) = Ax(k) + Bu(k) + w (1)
y(k) = Cx(k) (2)
where at time k, x(k) is the plant’s state, u(k) is its input
and y(k) is its output. The temperature value of each cell is
the state x 2n of our system. The first n entries represent
the cells composing the silicon floorplan and the remaining n
entries model the copper layer. The input of the system u p
is related to the frequencies of the cores according to [16].
The output y s of our system is the temperature observed
by the s on-chip thermal sensors placed in the silicon layer.
Matrices A, B, C and vector w describe the system and model
all geometric constraints among each entry of the state vector
and its placement on the chip floorplan. Matrix A 2n×2n
expresses the part of the temperature spreading process inside Fig. 1. Proposed method block diagram
the chip that depends only on the current temperature profile of
the cells. Matrix B 2n×p expresses the temperature increase from the measurement vector y. The observability matrix Q
due to the input. The part of the system dynamic that is not is expressed by the following equation (see [1]):
controllable by the input vector such as the heat dissipation Q = [C; CA; . . . ; CA2n−1 ] (3)
of the copper layer due to room temperature is expressed by
vector w 2n . Matrix C B s×2n , B = {0, 1}, represents If the rank of Q equals 2n, the state vector x can be
a selection matrix that models the placement of a sensor on reconstructed completely from the measurement vector y and
the silicon die. Namely ci,j is equal to 1 if thermal sensor i the input vector u.
is located inside the cell j. Since we are assuming to have The problem of selecting the right placement of thermal
distinct measurements coming from distinct sensors, C has sensors to both minimize the number of sensors and maximize
only 1 nonzero element per row. For technological reasons observability is the problem of choosing the matrix C with
thermal sensors can be placed only on the silicon layer, so the minimum number of rows that maximize the rank of the
sensors can be located only for i, j <= n. observability matrix Q. Given a determined MPSoC model,
In the model described by Equations 1 and 2, the sampling this problem depends on the location and the number of
frequency f = (tk+1 − tk )−1 is the frequency at which we are sensors inside floorplan (matrix C). The sensor sampling
assuming to sample the original continuous time system. The frequency (f ) has as well an influence on the observability
higher this frequency is, the higher the information thermal because matrices of Equations 1, 2 depend on f .
sensors are providing about the MPSoC thermal spreading C. Algorithm
process. The contribution of this paper is a methodology to
The block diagram of the proposed algorithm is presented
find sensor placements leading to Pareto points in the area
in Figure 1. The method is consists of four steps.
versus frequency plane. In the first step, experimental data of hot spots locations are
recorded during the runtime execution of the system. Data can
B. Observability and Sensor Placement
be obtained from real chip temperature measurements or from
Observability refers to the property of a system that enables simulations using tools such as Hotspot. These data will point
the reconstruction of the state variables given the inputs [1]. out in which locations an accurate monitoring is needed in
For the system identified by Equations 1 and 2, it means that order to identify the rising of potential Hotspots. It’s important
we are able to reconstruct completely the thermal profile of to notice that these data are not used to define the placement
the chip given the inputs only by looking at the measurements for the sensors. They are used in step 3 of the algorithm as
coming from the sensors, placed in locations specified by the a criterion to rank among different sensor placements having
matrix C. This means that we are assuming to have in the the same observability properties.
output vector s distinct temperature measurements coming In the second step the design space exploration is done on all
from s distinct cells. The rank of the observability matrix the possible sensor placement configurations. First the model
Q expresses the number of states that can be reconstructed of the system of Equations 1,2 is sampled using a frequency
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f that ranges from Fmin to Fmax . After that, the number of
sensors employed in the placement is varied from 1 to n. A
value of 1 means having only 1 sensor in the whole floorplan,
while a value of n means having a sensor per cell in the silicon
layer. At this stage for every value of s and f , a total of 2n
s
sensor placement configurations are generated. The possible
configurations have only one sensor per cell. This leads to
have a matrix C having one nonzero element per row and
a total of s rows. The rank of the observability matrix Q is
computed for each configuration.
The third step performs an optimization based on data
collected on both previous steps plus some additional data.
This step performs a selection of the number of all analyzed
Fig. 2. Floorplan used of the Niagara-1 multicore case study
sensor placement configurations. First, configurations that do
not allow the estimation of area of the chip that are relevant
to the designer are discarded. If a full profile estimation is
needed by the designer, then, placements leading to observ-
ability matrixes with rank less than 2n are discarded. As 100
a second criterion, configurations where sensors are placed observable states [%]
90
on experimental hot-spots locations (see step 1 of the algo-
rithm) are preferred to other ones. Remaining placements are 80
ranked according to metrics to measure the observability of
70
a system (i.e.the observability Gramian [17]- [19]). Finally
according to aforementioned metrics, Pareto point placements 60
are computed. A specific sensor placement is corresponding to
50
every Pareto point in the plane sensor number s versus sensor 500
sampling frequency f . 400 100
300 80
The last step selects the best placement according to the 200 60
40
designer defined criteria based on area occupation(related to 100 20
sensors sampling frequency [Hz] 0 number of sensors [%]
s), power consumption(related to s and f ) and sensor sampling 0
frequency (related to f ). Fig. 3. Design space exploration of the case study (step 2)
IV. R ESULTS sampling frequency, we obtain the plot of Figure 3. As it
A. Experimental Setup can be noted from the graph, for a fixed percentage of the
In our setup, we consider an architecture resembling the observable states, there are many options. The graph shows
8-core Niagara-1 (UltraSparc T1) architecture from Sun Mi- that the number of sensors can be reduced by increasing the
crosystems [2]. The power consumption of all other elements sensors sampling frequency and vice-versa. It is important to
has been chosen according to [2]. The floorplan of the Niagara- notice also that, there are many possible sensor placement
1 multicore architecture, is presented in Figure 2. Values configurations associated with any point in previous graph.
regarding thermal resistance, silicon thickness and copper At this stage, among all possible placement configurations
layer thickness have been derived from [2]. To simulate the we identify Pareto points inside the design space. Trade-
system we use the execution characteristics of tasks from a offs are between the number of sensors and their sampling
mix of different benchmarks, ranging from web-accessing to frequency. The reason is because for a given observability
playing multimedia [20]. The simulation step for the discrete target, the lower bound of thermal sensors employed depends
time integration of the RC thermal model is 200μs. on the thermal sensor sampling frequency (see Figure 3).
Pareto points are computed by connecting previous results
B. Placement Results with experimental data derived from simulations. Additional
We applied the proposed algorithm to the case study de- data are the following. According to simulations and results
scribed in the experimental setup. The overall computation from [20] and [2], in our case study, critical areas for hotspots
of the proposed algorithm on a INTEL CoreT M 2 duo lap- are the cores and the crossbar located in the central part of
top having a frequency of 2GHz (T7200) in the case of a the chip. Moreover, we are interested in monitoring 100%
modelling performed using 24 states took 3.44 minutes. After of the states of our MPSoC. In this case study, the overall
the first step, we obtain the design space exploration results Pareto points computation step takes few seconds. The graph
of all possible sensor placement configurations. By plotting identifying the resulting Pareto points in the plane sensors
the percentage of the observable states over the overall states number Vs sensors sampling frequency is shown in Figure 4.
of the MPSoC versus the number of sensors used and their
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3×. Moreover Figure 4 shows that the gain can reach 4.5× at a
sampling frequency of 500Hz. The proposed method enables
the full thermal profile estimation of the MPSoC by using
a number of sensors that is smaller than the number of the
location of potential hot-spots formation regions.
V. C ONCLUSION
We propose a methodology for determining the placement
of temperature sensors on complex MPSoC floorplans. The
proposed algorithm identifies the best configurations of sen-
sors leading to Pareto points in the design space in terms
of sensors sampling frequency versus number of required
sensors. We compared the sensor placement with state-of-the-
art algorithms such as [5] or [6] in the case of a commercial
MPSoC device. Results show that the proposed method offers
Fig. 4. Pareto points (steps 3+4) and comparison with [5],[6]. a reduction up to 4.5× in the number of required sensors.
Moreover the method constructs a maximally observable sys-
In the last step of the algorithm, we assume as possible tem for a given number of sensors.
design constraint to allow a maximum of 3 thermal sensors
ACKNOWLEDGMENT
on the MPSoC. Moreover we want to have a sensor sampling
frequency as low as possible. According to Figure 4, the This research has been partially funded by the Nano-Tera.ch
corresponding Pareto point is a 3 sensor configuration with NTF Project CMOSAIC (ref. 123618), which is financed by
a sampling frequency of 250Hz. This means that if we want the Swiss Confederation and scientifically evaluated by SNSF.
to make the system observable with only 3 sensors, we need R EFERENCES
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