Design and Simulation of Front-End Broadband RF Power

Amplifier for LTE TDD 2.3 GHz

Erwin Setiawan1, Mukmin Maulana Latin2, Basuki Rahmatul Alam3
School of Electrical Engineering and Informatics
Institute of Technology Bandung. Indonesia
1
[email protected], [email protected],
3
[email protected], [email protected]

Abstract— In this paper, the design and simulation RF cycle, i.e. the conduction angle is 360 degrees, so the
of front-end broadband RF power amplifier for LTE output signal is not distorted. To design a class A amplifier,
TDD transmission at 2.3 GHz is reported. The amplifier the transistor Q-point must be selected at the middle of DC
circuit is designed by using Cree GaN HMET load line. In theory, class A amplifier has power efficiency
CGH25120F transistor under class-A configuration of 50%. The power is dissipated as heat, so if the power
scheme. The design and simulation using harmonic efficiency is low then the larger heatsink is necessary.
balanced simulator and load-pull method results in an
amplifier with power gain of 16.166 dB with PAE of B. Load-Pull
16.778%. The RF power amplifier can produce output
power of 41.163 dBm with S11 and S22 less than 5dB in Load-Pull is a method that can be used in order to get a
30MHz bandwidth. Mixed-signal simulation has been load impedance that can produce optimal gain and power
carried-out by using QPSK modulation scheme at 150 efficiency. Load-pull is carried out using load-pull
Mbps bit rate. instrument. In ADS software, there is a tool that can
simulate the load-pull instrument.
Keywords— RF Power Amplifier, LTE TDD, Load pull, The working principle of load-pull method is by
QPSK sweeping the load impedance until the optimal gain and
power efficiency is achieved. By using ADS load-pull
I. INTRODUCTION simulation, in addition to load impedance, the input
impedance is also calculated automatically. The value of
load impedance and input impedance are necessary for
LTE (Long-Term Evolution) is a standard high speed impedance matching.
wireless communication for cell phone and data equipment
[1]. LTE technology has been evolving since 2004 when
first proposed by NTT DoCoMo in Japan. Nowadays, LTE C. Impedance Matching
service is available for commercial in Indonesia. One of
provider that offers LTE data cellular service in Indonesia is Impedance matching is a circuit that can be designed
Smartfren, based on LTE TDD. using passive components, and will be integrated to the
input and output of amplifier. The purpose of this circuit is
LTE TDD (Time Division Duplexing) is one of the LTE
to achieve 50 Ohm impedance characteristic at the input and
mode of operation where data is transmitted and received on
output port, so the minimum reflected power at input and
the same channel frequency with a short time separation [2].
output port can be achieved. The components for impedance
The uplink and downlink bandwidth allocation for TDD can
matching can be lumped or distributed components.
be configured dynamically [3].
One of the important issue when designing the
RF power amplifier is a type of amplifier that convert
impedance matching circuit is the bandwidth. The
low power RF signal to high power RF signal [4]. Output
bandwidth is related to the Q-factor by equation (1). In order
from RF power amplifier will be delivered to antenna of the
to achieve impedance matching that meets the desired
transmitter. RF power amplifier is necessary for BTS in
bandwidth, one of the passive component must touch the Q-
order to transmit RF signal that can reach the user handset.
curve [6].
There are three digital modulations that can be used on
LTE technology: QPSK, 16-QAM, and 64-QAM. The LTE
𝑓0
downlink speed is 300 Mbps for LTE cat. 5 and 150 Mbps 𝑄= (1)
𝐵𝑊
for LTE cat. 4, while the uplink speed is 75 Mbps.
III. POWER AMPLIFIER DESIGN
II. BASIC THEORIES
A. Power Amplifier Specification
A. Class A RF Power Amplifier
The first step of power amplifier design is to define its
Power amplifier can be classified into several class: A, specification. The power amplifier in this paper is designed
AB, B, C, D, E, F. Each of the class has different conduction to meet the specification of the Smartfren provider [6]. This
angle. Conduction angle states how many RF cycle is specification is shown in table 1. The amplifier is designed
occurred in active region of the transistor [5]. On class A with class A configuration.
amplifier, the transistor always in active region for the entire
 TABLE 1. POWER AMPLIFIER SPECIFICATION

Frequency 2.3 GHz

Bandwidth 30 MHz (2330-2360 MHz)
Output Power >35 dBm (~3 W)

B. Transistor Characteristic

In this design, the Cree CGH2512F transistor is used.

This transistor is a Gallium Nitride (GaN) High Electron
Mobility Transistor (HMET) which is designed for high Figure 2. Bias circuit
efficiency, high gain, and wide bandwidth, hence suitable
for WiMAX, LTE, and BWA amplifier at frequency range D. Load-Pull Method
of 2.3-2.7 GHz [7]. The characteristic of transistor such as
bias point, S-parameter, K stability factor, and MAG can be In order to obtain power amplifier that has optimal
simulated by using ADS model of this transistor. The S- power efficiency and gain, then the load impedance must be
parameter of this transistor at 2.3 GHz is shown in table 2. simulated by load-pull simulation. Schematic for this load-
pull simulation is shown in figure 3.
The first step of load-pull simulation is to enter the VGS,
TABLE 2. S-PARAMETER AT 2.3 GHZ
VDS, operating frequency, and Rload (as “Z_Load_Fund”)
which are obtained from transistor IV – characteristic. After
Frequency S11 S21 S12 S22 that, the sweeping area for the load impedance must be
0.805∡ 1.751∡ 0.012∡ 0.966∡ defined as shown in figure 4.
2.3 GHz
151.474 -54.951 -114.538 -177.467

C. Transistor Biasing

The DC characteristic curve for this transistor is

obtained from ADS simulation as shown in figure 1. The
bias point of this transistor is selected on the middle of DC
load-line (marker m1). At this point, Rload is 19.034 Ohm,
and the transistor works as class A amplifier.
After VGS and VDS is obtained from bias point, then the
next step is to design the bias circuit by using passive
components. The bias circuit for VGS and VDS is shown in
figure 2. Bias voltage for VGS is designed by a voltage
divider circuit. The value of R1 and R2 of the circuit are 8.2
kOhm and 6.2 kOhm respectively, while the supply voltage
is -5V. Bias voltage for VDS is designed by using resistor R3
(19 Ohm) with a supply voltage of 48V.
Figure 3. Load-pull analysis schematic

Figure 4. Sweeping area for the first load-pull iteration

The sweeping area for the first load-pull iteration

Figure 1. IV curve characteristic produces maximum transducer power gain of 15.364 dB.
With input power of 15 dBm, output power of 30.364 dBm
and PAE of 3.663% is obtained. From the first load-pull
iteration, the input impedance is obtained, which is
13.142+j13.881 Ohm.
 The transducer power gain and PAE that obtained from
the first load-pull iteration can be improved by change the
“Z_Source_Fund” of the load-pull instrument with the value
of input impedance complex conjugate (13.142-j13.881
Ohm) and the value of “Z_Load_Fund” to load impedance
(1.789+j1.316 Ohm). Those values are obtained from first
load-pull iteration. The sweeping area can also be reduced in
order to produce a more accurate result [8]. The second Figure 7. Output impedance matching schematic
load-pull iteration produce maximum transducer power gain
of 18.630 dB.With input power of 15 dBm, output power of
33.630 dBm and PAE of 7.512% is obtained.
From the third load-pull iteration, the value of
“Z_Source_Fund” and “Z_Load_Fund” can be changed with
the value of input impedance complex conjugate and load
impedance respectively from the second load-pull iteration.
The input power is also increased from 15 dBm to 25 dBm.
The third load-pull iteration produce maximum transducer
power gain of 18.040 dB. With input power of 25 dBm, Figure 8. Power amplifier schematic
output power of 43.040 dBm and PAE of 37.373% is
obtained. The value of load impedance is 1.447+j0.263 Ohm IV. RESULT AND ANALYSIS
and input impedance is 10.437+j18.465 Ohm. Power output
contour and PAE from the third load-pull simulation is
A. S-Parameter
shown in figure 5.
S11 and S22 was obtained from harmonic balanced
simulation from 2.0 GHz to 2.6 GHz. The result of S11 and
S22 after impedance matching is shown in figure 9.
The magnitude of |𝑆11 | 𝑎𝑛𝑑 |𝑆22 | is less than -5dB at
the frequency range of 2330 MHz – 2360 MHz, which is the
working frequency of LTE TDD transmission.

Figure 5. Power output contour and PAE

E. Impedance Matching
After input and output impedance is obtained from load- Figure 9. S11 and S22 after impedance matching
pull simulation, the next step is to match this impedance to
50. Before the impedance matching procedure is carried B. Power Gain and PAE
out, the Q-factor must be calculated first. By using equation
1 with fc = 2.3 GHz and BW = 120 MHz can produce the Q- Power gain and PAE can be simulated by using
factor of 19. “Harmonic Balance” controller in ADS with the frequency
Impedance matching in this design is carried out by of 2.3 GHz. The result shows that the amplifier can produce
using distributed elements. The procedure of the input 41.163 dBm (13.071 W) output power from 25 dBm input
impedance matching is to shift the input impedance power (0.316 W) with PAE of 16.778%. From the output
(10.437+j18.465) to 50 input, through 2-section and input power, we can calculate the power gain by using
broadband impedance matching. equation (2). The result is 16.166 dB.
The impedance matching at output port is carried out by
shifting the output impedance from 1.447+j0.263 to 50 Pout
Gp = 10 log( ) (2)
Pin
load. The input and output impedance matching circuit are
shown in figure 6 and 7 respectively. Overall schematic of
this power amplifier circuit is shown in figure 8. C. Mixed-Signal Simulation

Mixed-signal simulation is carried out in order to see

the overall performance of RF system, i.e. the RF power
amplifier is integrated with the DSP system. In this test,
mixed-signal simulation is carried out by using QPSK
modulation. The bit rate is configured to 150 MHz (LTE cat.
4). Schematic for mixed-signal simulation is shown in figure
Figure 6. Input impedance matching schematic
10. In order to compare the result before and after
amplifying, then “Spectrum Analyzer” component can be
used. Another component that must be added in order to
perform mixed-signal simulation is “Ent Out Selector” and
also in power amplifier circuit, a controller called “Envelope” Figure 12. The value of QPSK spectrum before and after
must be added at frequency of 2.3 GHz. The QPSK power power amplifying
spectrum before and after power amplifying is shown in
figure 11. V. CONCLUSION

The class A RF power amplifier for LTE TDD 2.3 GHz

has been successfully designed. The power gain of this
amplifier is 16.166 dB and the PAE is 16.778%. The S11
and S22 is < -5dB with 30 MHz bandwidth.

REFERENCE

[1] Wikipedia, “LTE (telecommunication)”, https://en.

wikipedia.org/wiki/LTE_(telecommunication)#LT
E-TDD_and_LTE-FDD, accessed May 2017.
[2] Ahmad Sidik, Maulana Yusuf Fathany, and Basuki
Rahmatul Alam, “Design of Broadband Low Noise
Figure 10. Mixed-signal simulation schematic
Amplifier (LNA) 4G LTE TDD 2.3 GHz for Modem
Application”, 2015 International Symposium on
Intelligent Signal Processing and Communication
Systems (ISPACS) November 9-12, 2015.
[3] A. Z. Yonis, M. F. L. Abdullah, and M. F. Ghanim,
“LTE-FDD and LTE-TDD for Cellular
Communications”, Progress in Electromagnetics
Research Symposium Proceedings, KL, Malaysia,
March 27-30, 2012.
[4] Wikipedia, “RF power amplifier”, https://en.
wikipedia.org/wiki/RF_power_amplifier, accessed
May 2017.
[5] Mihai Albulet, “RF Power Amplifiers”, Noble
Publishing, 2001.
[6] Syifaul Fuada, “Perancangan Broadband RF
Power Amplifier 2,3 GHz pada 4G LTE Time
Division Duplex”, JNTETI, Vol. 4, No. 3, August
2015.
[7] Cree Product Data Sheet, “CGH25120F 120 W,
2300-2700 MHz, GaN HEMT for WiMAX and
LTE”, Rev 3.1, June 2015.
Figure 11. QPSK spectrum before and after power [8] Keysight, “How to Setup and Run Load Pull
amplifying Simulations”, https://www.youtube.com/watch?
v=34N-r5rPSzU, accessed May 2017.
The value of QPSK power spectrum before and after [9] Agilent Technologies, “ADS Circuit Design
power amplifying is shown in figure 12. With input power Cookbook-2.0”
of 24.595 dBm, output power of 44.628 dBm is obtained.