COMP2611: Computer Organization

Arithmetic for Computers

COMP2611 CSE HKUST

 Major Goals 2

 Revisit addition & subtraction for 2's complement numbers

 Explain the construction of a 32-bit arithmetic logic unit (ALU)

 Show algorithms and implementations of multiplication and division

 Demonstrate floating-point arithmetic operations

COMP2611 CSE HKUST Arithmetic for Computers

 3

1. 2’s Complement Arithmetic

COMP2611 CSE HKUST Arithmetic for Computers

 Numbers 4

 Bits: the basis for binary number representation in digital computers

 We’ve learnt:
 How to represent negative numbers
 How to represent fractions and real numbers
 What is the representable range

COMP2611 CSE HKUST Arithmetic for Computers

 Signed and Unsigned Numbers 5

 Signed numbers
 negative or non-negative integers, e.g. int in C/C++
 Unsigned numbers
 non-negative integers, e.g. unsigned int in C/C++

 Operations for unsigned numbers

 Comparison:
sltu (set on less than unsigned), sltiu
 Arithmetic:
addu, subu (add/subtract unsigned)
• binary addition with overflow ignored
addiu (add unsigned sign-extended immediate)
• The 16-bit immediate is sign-extended then addition,
overflow ignored
addi (add signed immediate)
 Load:
lbu (load byte unsigned), lhu (load half unsigned)
COMP2611 CSE HKUST Arithmetic for Computers
 Signed vs. Unsigned Comparison 6

 $s0 1111 1111 1111 1111 1111 1111 1111 11112

 $s1 0000 0000 0000 0000 0000 0000 0000 00012

 What are the values in registers $t0 and $t1 in the examples below?
slt $t0, $s0, $s1 # signed comparison
$s0 = -110, $s1 = 110, $t0 = 1
sltu $t1, $s0, $s1 # unsigned comparison
$s0 = 429496729510, $s1 = 110, $t1 = 0

COMP2611 CSE HKUST Arithmetic for Computers

 Zero Extension and Sign Extension 7

 Operands in instruction may have mis-matched sizes

addi $t0, $s0, -5 # add 32-bit operands in $s0 with 16-bit
immediate value in 2’s complement
ori $t0, $s0, 0xFB32
lb $t0, 0($s0) # load a 8-bit signed number to 32-bit register
 Need conversion from n-bit binary numbers into m-bit numbers (m >
n)

 Sign extension: Fill the leftmost bits (n-th ~ (m-1)-th) with the sign
bit
2 (16 bits -> 32 bits):
0000 0000 0000 0010 -> 0000 0000 0000 0000 0000 0000 0000 0010
-2 (16 bits -> 32 bits):
1111 1111 1111 1110 -> 1111 1111 1111 1111 1111 1111 1111 1110
addi, lb
 Zero extension: Pad the leftmost bits (n-th ~ (m-1)-th) with 0
 and, or

COMP2611 CSE HKUST Arithmetic for Computers

 Confusion on Unsigned Operation 8

 add immediate unsigned addiu $t0, $s1, 0xFB32

 Zero extended? WRONG

 MIPS unsigned arithmetic operations: addu, addiu, subu,

subiu, sltu, sltiu

 The immediate fields of addiu, sltiu are sign-extended!

The MIPS32 Instruction Set states that the word ‘unsigned’ as part of
add and subtract instructions, is a misnomer. The difference between
signed and unsigned versions of commands is not a sign extension of
the operands, but controls whether a trap is executed on overflow (i.e.
add) or an overflow is ignored (i.e. addu). An immediate operand
CONST to these instructions is always sign-extended.

COMP2611 CSE HKUST Arithmetic for Computers

 Addition and Subtraction 9

 Addition
Bits are added bit by bit from right to left, with carries passed
to the next bit position to the left

 Subtraction
Subtraction uses addition
The appropriate operand is negated before being added to the
other operand

 Overflow
The result is too large to fit into a word (32 bits in MIPS)

COMP2611 CSE HKUST Arithmetic for Computers

 Examples 10

 Addition (7 + 6 = 13):

0000 0000 0000 0000 0000 0000 0000 01112 = 710

+ 0000 0000 0000 0000 0000 0000 0000 01102 = 610

= 0000 0000 0000 0000 0000 0000 0000 11012 = 1310

 Subtraction (7 - 6 = 1):

0000 0000 0000 0000 0000 0000 0000 01112 = 710

+ 1111 1111 1111 1111 1111 1111 1111 10102 = -610

= 1 0000 0000 0000 0000 0000 0000 0000 00012 = 110

COMP2611 CSE HKUST Arithmetic for Computers

 Examples 11

 Addition (1073741824 + 1073741824 = 2147483648):

0100 0000 0000 0000 0000 0000 0000 00002 = 107374182410

+ 0100 0000 0000 0000 0000 0000 0000 00002 = 107374182410

= 1000 0000 0000 0000 0000 0000 0000 00002  214748364810

In 2’s complement the MSb is a sign bit

then, it means -214748364810

COMP2611 CSE HKUST Arithmetic for Computers

Detecting Overflow 12

Addition (X + Y) Subtraction (X - Y)

 No overflow occurs when:  No overflow occurs when:

X and Y are of different signs X and Y are of the same sign

 Overflow occurs when:  Overflow occurs when:

X and Y are of the same sign X and Y are of different signs
But, X + Y is represented in a But, X - Y is represented in a
different sign different sign from X

 Overflow condition

Operation Sign Bit of X Sign Bit of Y Sign Bit of Result

X+Y 0 0 1
X+Y 1 1 0
X–Y 0 1 1
X–Y 1 0 0

COMP2611 CSE HKUST Arithmetic for Computers

 Effects of Overflow 13

MIPS detects overflow with an exception (also called an interrupt)

 Exceptions occur when unscheduled events disrupt program execution
 Some instructions are designed to cause exceptions on overflow
e.g. add, addi and sub cause exceptions on overflow
But, addu, addiu and subu do not cause exceptions on overflow;
programmers are responsible for using them correctly

When an overflow exception occurs

 Control jumps to a predefined address (code) to handle the
exception
 The interrupted address is saved to EPC for possible resumption
EPC = exception program counter; a special register
MIPS software return to the offending instruction via jump register

COMP2611 CSE HKUST Arithmetic for Computers

 14

2. Arithmetic Logic Unit

COMP2611 CSE HKUST Arithmetic for Computers

 Constructing an Arithmetic Logic Unit 15

 The arithmetic logic unit (ALU) of a computer is the hardware

component that performs:
Arithmetic operations (like addition and subtraction)
Logical operations (like AND and OR)

Processor

Control Unit
ALU
Registers
& Cache

COMP2611 CSE HKUST Arithmetic for Computers

 Constructing an Arithmetic Logic Unit (cont’d) 16

 Since a word in MIPS is 32 bits wide, we need a 32-bit ALU

 Ideally, we can build a 32-bit ALU by connecting 32 1-bit ALUs

together (each of them takes care of the operation on one bit position)

 1-bit logical unit for AND and OR:

Operation

a
0
Result
1
b

A multiplexor selects the appropriate result depending on the

operation specified

COMP2611 CSE HKUST Arithmetic for Computers

 1-Bit Full Adder 17

 An adder must have

Two inputs (bits) for the operands
A single-bit output for the sum
 Also, must have a second output to pass on the carry, called carry-out
Carry-out becomes the carry-in to the neighbouring adder
 1-bit full adder is also called a (3, 2) adder (3 inputs and 2 outputs)

CarryIn

a
(1) (1) (0) (carries)
0 1 1 1
Sum
0 1 1 0
1 (1)1 (1)0 (0)1 b

CarryOut

COMP2611 CSE HKUST Arithmetic for Computers

 Truth Table and Logic Equations for 1-Bit Adder 18

 Truth table:
Inputs Outputs
Comments
a b CarryIn CarryOut SumOut
0 0 0 0 0 0 + 0 + 0 = 002
0 0 1 0 1 0 + 0 + 1 = 012
0 1 0 0 1 0 + 1 + 0 = 012
0 1 1 1 0 0 + 1 + 1 = 102
1 0 0 0 1 1 + 0 + 0 = 012
1 0 1 1 0 1 + 0 + 1 = 102
1 1 0 1 0 1 + 1 + 0 = 102
1 1 1 1 1 1 + 1 + 1 = 112

 Logic equations:

CarryOut  (a  b  CarryIn)  (a  b  CarryIn)  (a  b  CarryIn)  (a  b  CarryIn)

 (b  CarryIn)  (a  CarryIn)  (a  b)

SumOut  (a  b  CarryIn)  (a  b  CarryIn)  (a  b  CarryIn)

 (a  b  CarryIn)

COMP2611 CSE HKUST Arithmetic for Computers

 Hardware Implementation of 1-Bit Adder 19

 CarryOut  (b  CarryIn)  (a  CarryIn)  (a  b)

CarryIn

CarryOut

 SumOut bit: (It is left as an exercise)

COMP2611 CSE HKUST Arithmetic for Computers

 1-Bit ALU (AND, OR, and Addition) 20

 3 in 1 building block
Use the Operation bits to decide what result to push out
Operation = 0, do AND
Operation
Operation = 1, do OR
CarryIn
Operation = 2, do addition

a
0

1
Result

2
b

CarryOut

COMP2611 CSE HKUST Arithmetic for Computers

 32-Bit ALU 21

 Ripple carry organization of a CarryIn Operation

32-bit ALU constructed from 32

1-bit ALUs: a0 CarryIn
Result0
ALU0
b0

A single carry out of the least CarryOut

significant bit (Result0) could

ripple all the way through the a1 CarryIn
Result1
ALU1
adders, causing a carry out b1
CarryOut
of the most significant bit
(Result31) a2 CarryIn
Result2
ALU2
There exist more efficient
b2
CarryOut

implementations (based on
the carry lookahead idea
to be explained later)
a31 CarryIn
Result31
ALU31
b31

COMP2611 CSE HKUST Arithmetic for Computers

 Subtraction 22

 Subtraction is the same as adding the negated operand

 By doing so, an adder can be used for both addition and subtraction
 A 2:1 multiplexor is used to choose between
 an operand (for addition) and
 its negative version (for subtraction)

 Shortcut for negating a 2's complement number:

 Invert each bit (to get the 1's complement representation)
 Add 1: Obtained by setting the ALU0’s carry bit to 1

COMP2611 CSE HKUST Arithmetic for Computers

 1-Bit ALU (AND, OR, Addition, and Subtraction) 23

 To execute a – b we can execute a + (-b)

 Binvert: the selector input of a multiplexor to choose between addition
and subtraction Binvert Operation
CarryIn

a
0

1
Result

b 0 2

CarryOut

 To form a 32-bit ALU, connect 32 of these 1-bit ALUs

 To negate b we must invert it and add 1 (2’s complement), so we must
Set CarryIn input of the least significant bit (ALU0) to 1 for subtraction

COMP2611 CSE HKUST Arithmetic for Computers

 Tailoring the ALU for MIPS 24

 The 32-bit ALU being designed so far can perform add, sub, and, or
operations which constitute a large portion of MIPS’ instruction set
 Two instructions not yet supported are: slt and beq

 When we need to compare Rs to Rt

 By definition of slt, if Rs < Rt
• LSb of the output is set to 1
• Otherwise, it is reset to 0
 How to implement it?
 The comparison is equivalent to testing if (Rs – Rt) < 0
 If (Rs – Rt) is smaller than 0
• MSb of the subtraction (Rs – Rt) equals to 1 (means negative)
• Otherwise, MSb of the subtraction equals to 0
 Notice that the outcome of MSb is similar to the result of slt
 Idea: copy the MSb of the subtraction result to the LSb of
slt’s output. All other bits of the output are 0
 slt can be done using two types of 1-bit ALUs

COMP2611 CSE HKUST Arithmetic for Computers

 Tailoring the ALU for MIPS 25

 How to implement it?

The comparison is equivalent to testing if (Rs – Rt) < 0
slt $t0, $s1, $s2

If Rs – Rt ≥ 0 If Rs – Rt < 0
31 30 29 28 ... 3 2 1 0 31 30 29 28 ... 3 2 1 0
$s1 ... ...

31 30 29 28 ... 3 2 1 0 31 30 29 28 ... 3 2 1 0
$s2 ... ...

31 30 29 28 ... 3 2 1 0 31 30 29 28 ... 3 2 1 0
Res 0 ...
1 ...

31 30 29 28 ... 3 2 1 0 31 30 29 28 ... 3 2 1 0
$t0 ... ...
0 1

All 0
COMP2611 CSE HKUST Arithmetic for Computers
 Tailoring the ALU for MIPS (cont’d) 26

Binvert Operation Binvert Operation

CarryIn CarryIn

a
a 0
0
1
1
Result
b 0 2
Result
1
b 0 2
Less 3
1
Set
Less 3
Overflow Overflow
detection

CarryOut

1-bit ALU for bits 0 to 30 1-bit ALU for the MSb (bit 31)

COMP2611 CSE HKUST Arithmetic for Computers

 32-Bit ALU with (add, sub, AND, OR, slt) 27

B in v e r t C a rry In O p e r a t io n

 The “set” signal is the MSb

of the result of the a0 C a rry In

subtraction, A – B b0 ALU0
Le ss
R e s u lt0

 It is passed to LSB
C a rryO u t

 Result0 will equal to this a1 C a rry In

“set” signal when operation b1
0
ALU1
Le ss
R e s u lt1

= 3 (which means slt C a rryO u t

instruction is being
executed) a2
b2
C a rry In
ALU2 R e s u lt2
0 Le ss
C a rryO u t

C a rry In

a31 C a rry In R e s u lt3 1

b31 ALU 31 S et
0 Le ss O v e r f lo w

COMP2611 CSE HKUST Arithmetic for Computers

 Tailoring the ALU for MIPS 28

 To support beq

 We need to compare Rs to Rt

 The comparison is equivalent to testing if (Rs – Rt) == 0

 If (Rs – Rt) is equal to 0
• All bits of the output are 0
• Otherwise, at least one of them is non 0

COMP2611 CSE HKUST Arithmetic for Computers

 32-Bit ALU with (add, sub, AND, OR, slt) 29

 Finally, this adds a zero Bnegate Operation

detector
 For addition and
a0 CarryIn Result0
b0 ALU0
AND/OR operations Less
CarryOut
both Bnegate and
CarryIn are 0 and for a1 CarryIn Result1
subtract, they are both b1
0
ALU1
Less
1 so we combine them CarryOut Zero

into a single line

a2 CarryIn Result2
b2 ALU2
0 Less
CarryOut

Result31
a31 CarryIn
b31 ALU31 Set
0 Less Overflow

COMP2611 CSE HKUST Arithmetic for Computers

 Universal Representation 30

 Knowing what is exactly inside a 32-bits ALU, from now on we will use
the universal symbol for a complete ALU as follows:

ALU operation
ALU Control lines Operation
a 000 AND
Zero 001 OR
ALU Result
Overflow 010 ADD
b 110 SUB
111 SLT
CarryOu t

COMP2611 CSE HKUST Arithmetic for Computers

 Carry Lookahead 31

 Using the ripple carry adder, the carry has to propagate from the LSb
to the MSb in a sequential manner, passing through all the 32 1-bit
adders one at a time. SLOW for time-critical hardware!

 Key idea behind fast carry schemes without the ripple effect:

CarryIn2  (b1  CarryIn1)  (a1  CarryIn1)  (a1  b1)

CarryIn1  (b0  CarryIn0)  (a0  CarryIn0)  (a0  b0)

Substituting the latter into the former, we have:

CarryIn2  (a1  a0  b0)  (a1  a0  CarryIn0)  (a1  b0  CarryIn0)
 (b1  a0  b0)  (b1  a0  CarryIn0)  (b1  b0  CarryIn0)
 (a1  b1)

All other CarryIn bits can also be expressed using CarryIn0, a, b

COMP2611 CSE HKUST Arithmetic for Computers

 Carry Lookahead 32

 A Bit position generates a Carry iff both inputs are 1: Gi  ai  bi

 A Bit position propagates a Carry if exactly one input is 1: Pi  ai  bi
 CarryIn at bit i+1 (or CarryOut at bit i)can be expressed as:
Ci 1  Gi  Pi  Ci
 After substitution we have (1) (1) (0)
0 1 1 1
C1  G0  P0C0 0 1 1 0
1 (1)1 (1)0 (0)1
C2  G1  P1C1  G1  G0 P1  C0 P0 P1
C3  G2  G1 P2  G0 P1 P2  C0 P0 P1 P2
C4  G3  G2 P3  G1 P2 P3  G0 P1 P2 P3  C0 P0 P1 P2 P3

 WE can build a circuit to predict all Carries at the same time and do
the additions in parallel
 Possible because electronic chips becoming cheaper and denser

COMP2611 CSE HKUST Arithmetic for Computers

 Carry Lookahead Adder 33

COMP2611 CSE HKUST Arithmetic for Computers