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Influence of Technology and
Software on Instruction Sets:
Up to the dawn of IBM 360
Krste Asanovic
Laboratory for Computer Science
Massachusetts Institute of Technology
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Importance of Technology
New technologies not only provide greater
speed, size and reliability at lower cost, but
more importantly these dictate the kinds of
structures that can be considered and thus
come to shape our whole view of what a
computer is.
Bell & Newell
Technology is the dominant
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factor in computer design
Technology
Transistors Computers
Integrated circuits
VLSI (initially)
Laser disk, CD’s
Technology
Core memories Computers
Magnetic tapes
Disks
Technology
ROMs, RAMs
VLSI Computers
Packaging
Low Power
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But Software...
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As people write programs and use computers,
our understanding of programming and program
behavior improves.
This has profound though slower impact on
computer architecture
Modern architects cannot avoid paying attention
to software and compilation issues.
Technology
Computers
Software
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The Earliest Instruction Sets
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Single Accumulator - A carry-over from the calculators.
LOAD x AC ← M[x]
STORE x M[x] ← (AC)
ADD x AC ← (AC) + M[x]
SUB x
MUL x Involved a quotient register
DIV x
SHIFT LEFT AC ← 2 × (AC)
SHIFT RIGHT
JUMP x PC ← x
JGE x if (AC) ≥ 0 then PC ← x
LOAD ADR x AC ← Extract address field(M[x])
STORE ADR x
Typically less than 2 dozen instructions!
Programming a Single Asanovic/Devadas
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Accumulator Machine
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A
Ci ← Ai + Bi, 1≤ i ≤ n
LOOP LOAD N B
JGE DONE
ADD ONE
STORE N C
F1 LOAD A
F2 ADD B
F3 STORE C
JUMP LOOP N -n
DONE HLT ONE 1
How to modify the code
addresses A, B and C ?
Self-Modifying Code
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Ci ← Ai + Bi, 1≤ i ≤ n
LOOP LOAD N
JGE DONE Each iteration involves
ADD ONE
STORE N
F1 LOAD A
total book-
F2 ADD B
-keeping
F3 STORE C
instruction
LOAD ADR F1
ADD ONE
fetches 17 14
STORE ADR F1
modify the
program
LOAD ADR F2 operand
ADD ONE
for the next
STORE ADR F2
fetches 10 8
iteration
LOAD ADR F3
ADD ONE stores 5 4
STORE ADR F3
JUMP LOOP
DONE HLT
Processor State
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The information held in the processor at the end of an
instruction to provide the processing context for the next
instruction. e.g. Program Counter, Accumulator, . . .
Programmer visible state of the processor (and memory)
plays a central role in computer organization:
Software can only manipulate programmer-visible
state and can only rely on programmer-visible state
Hardware must never let software observe state
changes other than that defined in programmers
manual (e.g., interrupts not visible to running program)
Programmer’s model of machine is a contract
between hardware and software
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Accumulator Machines
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Can describe any possible computation using
single accumulator instruction set
Hardware is very simple
Why did different instruction sets evolve?
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Computers in mid 50’s
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Hardware was expensive
Programmer’s view of the machine was inseparable
from the actual hardware implementation
Example: IBM 650 - a drum machine with 44 instructions
1. 60 1234 1009
“Load the contents of location 1234 into the
distribution; put it also into the upper accumulator;
set lower accumulator to zero; and then go to location
1009 for the next instruction.”
Good programmers optimized the placement of
instructions on the drum to reduce latency
2. “Branch on distribution digit equal to 8”
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Computers in mid 50’s (cont.)
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Stores were small (1000 words) and 10 to 50 times
slower than the processor
1. Instruction execution time was totally dominated
by the memory reference time.
More memory references per instruction
⇒ longer execution time per instruction
2. The ability to design complex control circuits to
execute an instruction was the central concern
as opposed to the speed of decoding or ALU.
3. No resident system software because there was no
place to keep it!
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Processor 6.823
Bottleneck!
Memory
Some early solutions:
fast local storage in the processor, i.e., 8-16 registers
as opposed to one accumulator
indexing capability to reduce book keeping
instructions
complex instructions to reduce instruction fetches
compact instructions, i.e., implicit address bits for
operands, to reduce fetches
Index Registers
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Tom Kilburn, Manchester University, mid 50’s
One or more specialized registers to simplify address
calculation
Modify existing instructions
LOAD x, IX AC ← M[x + (IX)]
ADD x, IX AC ← (AC) + M[x + (IX)]
Add new instructions to manipulate index registers
JZi x, IX if (IX)=0 then PC ← x
else IX ← (IX) + 1
LOADi x, IX IX ← M[x] (truncated to fit IX)
Index registers have accumulator-like characteristics
Using Index Registers Asanovic/Devadas
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C i ← Ai + B i 1≤ i ≤ n
A
LOADi -n, IX
LOOP JZi DONE, IX # Jump or increment IX
LOAD A, IX
ADD B, IX
STORE C, IX
JUMP LOOP LASTA
DONE HALT
Program does not modify itself
Efficiency has improved dramatically (ops / iter)
with index regs without index regs
instruction fetch 5 (2) 17 (14)
operand fetch 2 10 (8)
store 1 5 (4)
Costs: Instructions are 1 to 2 bits longer
Index registers with ALU-like circuitry
Complex control
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Indexing vs. Index Registers
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LOAD x, IX
Suppose instead of registers, memory locations
are used to implement index registers.
Arithmetic operations on index registers can be
performed by bringing the contents to the accumulator.
Most book keeping instructions will be avoided
but each instruction will implicitly cause several
fetches and stores.
⇒ complex control circuitry
⇒ additional memory traffic
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Operations on Index Registers
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To increment index register by k
AC ← (IX) new instruction
AC ← (AC) + k
IX ← (AC) new instruction
also the AC must be saved and restored.
It may be better to increment IX directly
INCi k, IX IX ← (IX) + k
More instructions to manipulate index register
STOREi x, IX M[x] ← (IX) (extended to fit a word)
...
IX begins to look like an accumulator
several index registers
⇒ several accumulators
⇒ General Purpose Registers
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Support for Subroutine Calls
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call F(a1,...) F:
a1
Main a2 Subroutine F
Program
call F(b1,...)
b1 return
b2
A special subroutine jump instruction
M: JSR F F ← M + 1 and
jump to F+1
Indirect Addressing and
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Subroutine Calls Subroutine
F
Caller F+1
M JSR F 6 Events:
arg Execute M S1 LOAD (F) fetch
result Execute F+1 inc F by 1 arg
M+3 Execute S1
Execute S2
Execute S3 S2 STORE(F)
Execute M+3 inc F by 1 store
result
Indirect addressing
LOAD (x) means AC ← M[M[x]]
S3 JUMP (F)
Indirect addressing almost eliminates the need to write
self-modifying code (location F still needs to be modified)
⇒ Problems with recursive procedure calls
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Recursive Procedure Calls
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and Reentrant Codes
Indirect Addressing through a register
LOAD R1, (R2)
Load register R1 with the contents of the
word whose address is contained in register R2
Memory
Registers Pure Code
PC
SP
Data
Stack
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Evolution of Addressing Modes
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1. Single accumulator, absolute address
LOAD x
2. Single accumulator, index registers
LOAD x, IX
3. Indirection
LOAD (x)
4. Multiple accumulators, index registers, indirection
LOAD R, IX, x
or LOAD R, IX, (x) the meaning?
R ← M[M[x] + IX]
or R ← M[M[x + IX]]
5. Indirect through registers
LOAD RI, (RJ)
6. The works
LOAD RI, RJ, (RK) RJ = index, RK = base address
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Variety of Instruction Formats
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Two address formats: the destination is same as
one of the operand sources
(Reg × Reg) to Reg R I ← RI + R J
(Reg × Mem) to Reg RI ← RI + M[x]
...
x could be specified directly or via a register;
effective address calculation for x could include
indexing, indirection, ...
Three operand formats: One destination and up to
two operand sources per instruction
(Reg x Reg) to Reg R I ← RJ + RK
(Reg x Mem) to Reg RI ← RJ + M[x]
...
Many different formats are possible!
Data Formats and
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Memory Addresses
Data formats:
Bytes, Half words, words and double words
Some issues
• Byte addressing
Big Endian 0 1 2 3
vs. Little Endian 3 2 1 0
• Word alignment
Suppose the memory is organized in 32-bit words.
Can a word address begin only at 0, 4, 8, .... ?
0 1 2 3 4 5 6 7
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Some Problems
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Should all addressing modes be provided for
every operand?
⇒ regular vs. irregular instruction formats
Separate instructions to manipulate
Accumulators
Index registers
Base registers
⇒ A large number of instructions
Instructions contained implicit memory references -
several contained more than one
⇒ very complex control
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Compatibility Problem at IBM
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By early 60’s, IBM had 4 incompatible lines of computers!
701 → 7094
650 → 7074
702 → 7080
1401 → 7010
Each system had its own
• Instruction set
• I/O system and Secondary Storage:
magnetic tapes, drums and disks
• assemblers, compilers, libraries,...
• market niche
business, scientific, real time, ...
⇒ IBM 360
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IBM 360 : Design Premises
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Amdahl, Blaauw and Brooks, 1964
The design must lend itself to growth and
successor machines
General method for connecting I/O devices
Total performance - answers per month rather than
bits per microsecond ⇒ programming aids
Machine must be capable of supervising itself
without manual intervention
Built-in hardware fault checking and locating aids
to reduce down time
Simple to assemble systems with redundant I/O
devices, memories etc. for fault tolerance
Some problems required floating point words larger
than 36 bits
IBM 360:
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A General-Purpose Register Machine
Processor State
16 General-Purpose 32-bit Registers
- may be used as index and base registers
- Register 0 has some special properties
4 Floating Point 64-bit Registers
A Program Status Word (PSW)
PC, Condition codes, Control flags
A 32-bit machine with 24-bit addresses
No instruction contains a 24-bit address!
Data Formats
8-bit bytes, 16-bit half-words, 32-bit words,
64-bit double-words
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IBM 360: Implementations
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Model 30 ...
Model 70
Storage 8K - 64 KB
256K - 512 KB
Datapath 8-bit
64-bit
Circuit Delay 30 nsec/level
5 nsec/level
Local Store Main Store
Transistor Registers
Control Store Read only 1µsec
Conventional circuits
IBM 360 instruction set architecture completely hid the
underlying technological differences between various
models.
With minor modifications it survives today
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IBM S/390 z900 Microprocessor
64-bit virtual addressing
first 64-bit S/390 design (original S/360 was 24-bit, and S/370 was
31-bit extension)
1.1 GHz clock rate (announced ISSCC 2001)
0.18µm CMOS, 7 layers copper wiring
770MHz systems shipped in 2000
Single-issue 7-stage CISC pipeline
Redundant datapaths
every instruction performed in two parallel datapaths and results
compared
256KB L1 I-cache, 256KB L1 D-cache on-chip
20 CPUs + 32MB L2 cache per Multi-Chip Module
Water cooled to 10oC junction temp
What makes a good
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instruction set?
Ideally, provides simple software interface yet allows
simple, fast, efficient hardware implementations
… but across 25+ year time frame
Example of difficulties:
Current machines have register files with more storage
than entire main memory of early machines!
On-chip test circuitry of current machines hundreds of
times more transistors than entire early computers!
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Full Employment for Architects
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Good news: “Ideal” instruction set changes continually
Technology allows larger CPUs over time
Technology constraints change (e.g., power is now major constraint)
Compiler technology improves over time (e.g., register allocation)
Programming style varies over time (assembly coding, HLL, object-
oriented, …)
Applications and application demands vary over time (e.g.,
multimedia processing recent change in workload)
Bad news: Software compatibility imposes huge
damping coefficient on instruction set innovation
Software investment dwarfs hardware investment
Innovate at microarchitecture level, below instruction set level, this is
what most computer architects do
New instruction set can only be justified by new large
market and technological advantage
Network processors
Multimedia processors
